Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Andreas Noever | d6cc51c | 2014-06-03 22:04:00 +0200 | [diff] [blame] | 2 | /* |
Mika Westerberg | 15c6784 | 2018-10-01 12:31:22 +0300 | [diff] [blame] | 3 | * Thunderbolt driver - bus logic (NHI independent) |
Andreas Noever | d6cc51c | 2014-06-03 22:04:00 +0200 | [diff] [blame] | 4 | * |
| 5 | * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> |
Mika Westerberg | 15c6784 | 2018-10-01 12:31:22 +0300 | [diff] [blame] | 6 | * Copyright (C) 2018, Intel Corporation |
Andreas Noever | d6cc51c | 2014-06-03 22:04:00 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef TB_H_ |
| 10 | #define TB_H_ |
| 11 | |
Mika Westerberg | e6b245c | 2017-06-06 15:25:17 +0300 | [diff] [blame] | 12 | #include <linux/nvmem-provider.h> |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 13 | #include <linux/pci.h> |
Mika Westerberg | d1ff702 | 2017-10-02 13:38:34 +0300 | [diff] [blame] | 14 | #include <linux/thunderbolt.h> |
Mika Westerberg | bfe778a | 2017-06-06 15:25:01 +0300 | [diff] [blame] | 15 | #include <linux/uuid.h> |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 16 | |
| 17 | #include "tb_regs.h" |
Andreas Noever | d6cc51c | 2014-06-03 22:04:00 +0200 | [diff] [blame] | 18 | #include "ctl.h" |
Mika Westerberg | 3e13676 | 2017-06-06 15:25:14 +0300 | [diff] [blame] | 19 | #include "dma_port.h" |
Andreas Noever | d6cc51c | 2014-06-03 22:04:00 +0200 | [diff] [blame] | 20 | |
Mika Westerberg | 719a5fe | 2020-03-05 11:37:15 +0200 | [diff] [blame] | 21 | #define NVM_MIN_SIZE SZ_32K |
| 22 | #define NVM_MAX_SIZE SZ_512K |
Mika Westerberg | 9b38303 | 2021-04-01 16:54:15 +0300 | [diff] [blame] | 23 | #define NVM_DATA_DWORDS 16 |
Mika Westerberg | 719a5fe | 2020-03-05 11:37:15 +0200 | [diff] [blame] | 24 | |
| 25 | /* Intel specific NVM offsets */ |
| 26 | #define NVM_DEVID 0x05 |
| 27 | #define NVM_VERSION 0x08 |
| 28 | #define NVM_FLASH_SIZE 0x45 |
| 29 | |
Andreas Noever | d6cc51c | 2014-06-03 22:04:00 +0200 | [diff] [blame] | 30 | /** |
Mika Westerberg | 719a5fe | 2020-03-05 11:37:15 +0200 | [diff] [blame] | 31 | * struct tb_nvm - Structure holding NVM information |
| 32 | * @dev: Owner of the NVM |
Mika Westerberg | e6b245c | 2017-06-06 15:25:17 +0300 | [diff] [blame] | 33 | * @major: Major version number of the active NVM portion |
| 34 | * @minor: Minor version number of the active NVM portion |
| 35 | * @id: Identifier used with both NVM portions |
| 36 | * @active: Active portion NVMem device |
| 37 | * @non_active: Non-active portion NVMem device |
| 38 | * @buf: Buffer where the NVM image is stored before it is written to |
| 39 | * the actual NVM flash device |
| 40 | * @buf_data_size: Number of bytes actually consumed by the new NVM |
| 41 | * image |
Mika Westerberg | 719a5fe | 2020-03-05 11:37:15 +0200 | [diff] [blame] | 42 | * @authenticating: The device is authenticating the new NVM |
Mario Limonciello | 4b794f8 | 2020-06-23 11:14:28 -0500 | [diff] [blame] | 43 | * @flushed: The image has been flushed to the storage area |
Mika Westerberg | 719a5fe | 2020-03-05 11:37:15 +0200 | [diff] [blame] | 44 | * |
| 45 | * The user of this structure needs to handle serialization of possible |
| 46 | * concurrent access. |
Mika Westerberg | e6b245c | 2017-06-06 15:25:17 +0300 | [diff] [blame] | 47 | */ |
Mika Westerberg | 719a5fe | 2020-03-05 11:37:15 +0200 | [diff] [blame] | 48 | struct tb_nvm { |
| 49 | struct device *dev; |
Mika Westerberg | e6b245c | 2017-06-06 15:25:17 +0300 | [diff] [blame] | 50 | u8 major; |
| 51 | u8 minor; |
| 52 | int id; |
| 53 | struct nvmem_device *active; |
| 54 | struct nvmem_device *non_active; |
| 55 | void *buf; |
| 56 | size_t buf_data_size; |
| 57 | bool authenticating; |
Mario Limonciello | 4b794f8 | 2020-06-23 11:14:28 -0500 | [diff] [blame] | 58 | bool flushed; |
Mika Westerberg | e6b245c | 2017-06-06 15:25:17 +0300 | [diff] [blame] | 59 | }; |
| 60 | |
Rajmohan Mani | ff3a830 | 2021-04-12 14:01:46 +0300 | [diff] [blame] | 61 | enum tb_nvm_write_ops { |
| 62 | WRITE_AND_AUTHENTICATE = 1, |
| 63 | WRITE_ONLY = 2, |
Mika Westerberg | 1cbf680 | 2021-04-12 15:25:08 +0300 | [diff] [blame] | 64 | AUTHENTICATE_ONLY = 3, |
Rajmohan Mani | ff3a830 | 2021-04-12 14:01:46 +0300 | [diff] [blame] | 65 | }; |
| 66 | |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 67 | #define TB_SWITCH_KEY_SIZE 32 |
Mika Westerberg | f0342e7 | 2018-12-30 12:14:46 +0200 | [diff] [blame] | 68 | #define TB_SWITCH_MAX_DEPTH 6 |
Mika Westerberg | b040798 | 2019-12-17 15:33:40 +0300 | [diff] [blame] | 69 | #define USB4_SWITCH_MAX_DEPTH 5 |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 70 | |
| 71 | /** |
Rajmohan Mani | cf29b9af | 2019-12-17 15:33:43 +0300 | [diff] [blame] | 72 | * enum tb_switch_tmu_rate - TMU refresh rate |
| 73 | * @TB_SWITCH_TMU_RATE_OFF: %0 (Disable Time Sync handshake) |
| 74 | * @TB_SWITCH_TMU_RATE_HIFI: %16 us time interval between successive |
| 75 | * transmission of the Delay Request TSNOS |
| 76 | * (Time Sync Notification Ordered Set) on a Link |
| 77 | * @TB_SWITCH_TMU_RATE_NORMAL: %1 ms time interval between successive |
| 78 | * transmission of the Delay Request TSNOS on |
| 79 | * a Link |
| 80 | */ |
| 81 | enum tb_switch_tmu_rate { |
| 82 | TB_SWITCH_TMU_RATE_OFF = 0, |
| 83 | TB_SWITCH_TMU_RATE_HIFI = 16, |
| 84 | TB_SWITCH_TMU_RATE_NORMAL = 1000, |
| 85 | }; |
| 86 | |
| 87 | /** |
| 88 | * struct tb_switch_tmu - Structure holding switch TMU configuration |
| 89 | * @cap: Offset to the TMU capability (%0 if not found) |
| 90 | * @has_ucap: Does the switch support uni-directional mode |
| 91 | * @rate: TMU refresh rate related to upstream switch. In case of root |
Gil Fine | a28ec0e | 2021-12-17 03:16:38 +0200 | [diff] [blame] | 92 | * switch this holds the domain rate. Reflects the HW setting. |
Rajmohan Mani | cf29b9af | 2019-12-17 15:33:43 +0300 | [diff] [blame] | 93 | * @unidirectional: Is the TMU in uni-directional or bi-directional mode |
Gil Fine | a28ec0e | 2021-12-17 03:16:38 +0200 | [diff] [blame] | 94 | * related to upstream switch. Don't care for root switch. |
| 95 | * Reflects the HW setting. |
| 96 | * @unidirectional_request: Is the new TMU mode: uni-directional or bi-directional |
| 97 | * that is requested to be set. Related to upstream switch. |
| 98 | * Don't care for root switch. |
| 99 | * @rate_request: TMU new refresh rate related to upstream switch that is |
| 100 | * requested to be set. In case of root switch, this holds |
| 101 | * the new domain rate that is requested to be set. |
Rajmohan Mani | cf29b9af | 2019-12-17 15:33:43 +0300 | [diff] [blame] | 102 | */ |
| 103 | struct tb_switch_tmu { |
| 104 | int cap; |
| 105 | bool has_ucap; |
| 106 | enum tb_switch_tmu_rate rate; |
| 107 | bool unidirectional; |
Gil Fine | a28ec0e | 2021-12-17 03:16:38 +0200 | [diff] [blame] | 108 | bool unidirectional_request; |
| 109 | enum tb_switch_tmu_rate rate_request; |
Rajmohan Mani | cf29b9af | 2019-12-17 15:33:43 +0300 | [diff] [blame] | 110 | }; |
| 111 | |
Gil Fine | 8a90e4f | 2021-12-17 03:16:39 +0200 | [diff] [blame] | 112 | enum tb_clx { |
| 113 | TB_CLX_DISABLE, |
| 114 | TB_CL0S, |
| 115 | TB_CL1, |
| 116 | TB_CL2, |
| 117 | }; |
| 118 | |
Rajmohan Mani | cf29b9af | 2019-12-17 15:33:43 +0300 | [diff] [blame] | 119 | /** |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 120 | * struct tb_switch - a thunderbolt switch |
Mika Westerberg | bfe778a | 2017-06-06 15:25:01 +0300 | [diff] [blame] | 121 | * @dev: Device for the switch |
| 122 | * @config: Switch configuration |
| 123 | * @ports: Ports in this switch |
Mika Westerberg | 3e13676 | 2017-06-06 15:25:14 +0300 | [diff] [blame] | 124 | * @dma_port: If the switch has port supporting DMA configuration based |
| 125 | * mailbox this will hold the pointer to that (%NULL |
Mika Westerberg | e6b245c | 2017-06-06 15:25:17 +0300 | [diff] [blame] | 126 | * otherwise). If set it also means the switch has |
| 127 | * upgradeable NVM. |
Rajmohan Mani | cf29b9af | 2019-12-17 15:33:43 +0300 | [diff] [blame] | 128 | * @tmu: The switch TMU configuration |
Mika Westerberg | bfe778a | 2017-06-06 15:25:01 +0300 | [diff] [blame] | 129 | * @tb: Pointer to the domain the switch belongs to |
| 130 | * @uid: Unique ID of the switch |
| 131 | * @uuid: UUID of the switch (or %NULL if not supported) |
| 132 | * @vendor: Vendor ID of the switch |
| 133 | * @device: Device ID of the switch |
Mika Westerberg | 72ee339 | 2017-06-06 15:25:05 +0300 | [diff] [blame] | 134 | * @vendor_name: Name of the vendor (or %NULL if not known) |
| 135 | * @device_name: Name of the device (or %NULL if not known) |
Mika Westerberg | 91c0c12 | 2019-03-21 19:03:00 +0200 | [diff] [blame] | 136 | * @link_speed: Speed of the link in Gb/s |
| 137 | * @link_width: Width of the link (1 or 2) |
Mika Westerberg | bbcf40b | 2020-03-04 17:09:14 +0200 | [diff] [blame] | 138 | * @link_usb4: Upstream link is USB4 |
Mika Westerberg | 2c3c419 | 2017-06-06 15:25:13 +0300 | [diff] [blame] | 139 | * @generation: Switch Thunderbolt generation |
Mika Westerberg | bfe778a | 2017-06-06 15:25:01 +0300 | [diff] [blame] | 140 | * @cap_plug_events: Offset to the plug events capability (%0 if not found) |
Gil Fine | 23ccd21 | 2021-12-17 03:16:41 +0200 | [diff] [blame] | 141 | * @cap_vsec_tmu: Offset to the TMU vendor specific capability (%0 if not found) |
Mika Westerberg | a9be558 | 2019-01-09 16:42:12 +0200 | [diff] [blame] | 142 | * @cap_lc: Offset to the link controller capability (%0 if not found) |
Gil Fine | 43f977b | 2021-12-17 03:16:43 +0200 | [diff] [blame] | 143 | * @cap_lp: Offset to the low power (CLx for TBT) capability (%0 if not found) |
Mika Westerberg | bfe778a | 2017-06-06 15:25:01 +0300 | [diff] [blame] | 144 | * @is_unplugged: The switch is going away |
| 145 | * @drom: DROM of the switch (%NULL if not found) |
Mika Westerberg | e6b245c | 2017-06-06 15:25:17 +0300 | [diff] [blame] | 146 | * @nvm: Pointer to the NVM if the switch has one (%NULL otherwise) |
| 147 | * @no_nvm_upgrade: Prevent NVM upgrade of this switch |
| 148 | * @safe_mode: The switch is in safe-mode |
Yehezkel Bernat | 14862ee | 2018-01-22 12:50:09 +0200 | [diff] [blame] | 149 | * @boot: Whether the switch was already authorized on boot or not |
Mika Westerberg | 2d8ff0b | 2018-07-25 11:48:39 +0300 | [diff] [blame] | 150 | * @rpm: The switch supports runtime PM |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 151 | * @authorized: Whether the switch is authorized by user or policy |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 152 | * @security_level: Switch supported security level |
Gil Fine | 54e4181 | 2020-06-29 20:30:52 +0300 | [diff] [blame] | 153 | * @debugfs_dir: Pointer to the debugfs structure |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 154 | * @key: Contains the key used to challenge the device or %NULL if not |
| 155 | * supported. Size of the key is %TB_SWITCH_KEY_SIZE. |
| 156 | * @connection_id: Connection ID used with ICM messaging |
| 157 | * @connection_key: Connection key used with ICM messaging |
| 158 | * @link: Root switch link this switch is connected (ICM only) |
| 159 | * @depth: Depth in the chain this switch is connected (ICM only) |
Mika Westerberg | 4f7c2e0 | 2019-05-28 18:56:20 +0300 | [diff] [blame] | 160 | * @rpm_complete: Completion used to wait for runtime resume to |
| 161 | * complete (ICM only) |
Mario Limonciello | 1cb3629 | 2020-06-23 11:14:29 -0500 | [diff] [blame] | 162 | * @quirks: Quirks used for this Thunderbolt switch |
Mika Westerberg | 56ad3ae | 2021-03-10 13:34:12 +0200 | [diff] [blame] | 163 | * @credit_allocation: Are the below buffer allocation parameters valid |
| 164 | * @max_usb3_credits: Router preferred number of buffers for USB 3.x |
| 165 | * @min_dp_aux_credits: Router preferred minimum number of buffers for DP AUX |
| 166 | * @min_dp_main_credits: Router preferred minimum number of buffers for DP MAIN |
| 167 | * @max_pcie_credits: Router preferred number of buffers for PCIe |
| 168 | * @max_dma_credits: Router preferred number of buffers for DMA/P2P |
Gil Fine | 8a90e4f | 2021-12-17 03:16:39 +0200 | [diff] [blame] | 169 | * @clx: CLx state on the upstream link of the router |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 170 | * |
| 171 | * When the switch is being added or removed to the domain (other |
Mika Westerberg | 09f11b6 | 2019-03-19 16:48:41 +0200 | [diff] [blame] | 172 | * switches) you need to have domain lock held. |
Mika Westerberg | c3963a5 | 2021-02-01 15:03:00 +0300 | [diff] [blame] | 173 | * |
| 174 | * In USB4 terminology this structure represents a router. |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 175 | */ |
| 176 | struct tb_switch { |
Mika Westerberg | bfe778a | 2017-06-06 15:25:01 +0300 | [diff] [blame] | 177 | struct device dev; |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 178 | struct tb_regs_switch_header config; |
| 179 | struct tb_port *ports; |
Mika Westerberg | 3e13676 | 2017-06-06 15:25:14 +0300 | [diff] [blame] | 180 | struct tb_dma_port *dma_port; |
Rajmohan Mani | cf29b9af | 2019-12-17 15:33:43 +0300 | [diff] [blame] | 181 | struct tb_switch_tmu tmu; |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 182 | struct tb *tb; |
Andreas Noever | c90553b | 2014-06-03 22:04:11 +0200 | [diff] [blame] | 183 | u64 uid; |
Christoph Hellwig | 7c39ffe | 2017-07-18 15:30:05 +0200 | [diff] [blame] | 184 | uuid_t *uuid; |
Mika Westerberg | bfe778a | 2017-06-06 15:25:01 +0300 | [diff] [blame] | 185 | u16 vendor; |
| 186 | u16 device; |
Mika Westerberg | 72ee339 | 2017-06-06 15:25:05 +0300 | [diff] [blame] | 187 | const char *vendor_name; |
| 188 | const char *device_name; |
Mika Westerberg | 91c0c12 | 2019-03-21 19:03:00 +0200 | [diff] [blame] | 189 | unsigned int link_speed; |
| 190 | unsigned int link_width; |
Mika Westerberg | bbcf40b | 2020-03-04 17:09:14 +0200 | [diff] [blame] | 191 | bool link_usb4; |
Mika Westerberg | 2c3c419 | 2017-06-06 15:25:13 +0300 | [diff] [blame] | 192 | unsigned int generation; |
Mika Westerberg | bfe778a | 2017-06-06 15:25:01 +0300 | [diff] [blame] | 193 | int cap_plug_events; |
Gil Fine | 23ccd21 | 2021-12-17 03:16:41 +0200 | [diff] [blame] | 194 | int cap_vsec_tmu; |
Mika Westerberg | a9be558 | 2019-01-09 16:42:12 +0200 | [diff] [blame] | 195 | int cap_lc; |
Gil Fine | 43f977b | 2021-12-17 03:16:43 +0200 | [diff] [blame] | 196 | int cap_lp; |
Mika Westerberg | bfe778a | 2017-06-06 15:25:01 +0300 | [diff] [blame] | 197 | bool is_unplugged; |
Andreas Noever | cd22e73 | 2014-06-12 23:11:46 +0200 | [diff] [blame] | 198 | u8 *drom; |
Mika Westerberg | 719a5fe | 2020-03-05 11:37:15 +0200 | [diff] [blame] | 199 | struct tb_nvm *nvm; |
Mika Westerberg | e6b245c | 2017-06-06 15:25:17 +0300 | [diff] [blame] | 200 | bool no_nvm_upgrade; |
| 201 | bool safe_mode; |
Yehezkel Bernat | 14862ee | 2018-01-22 12:50:09 +0200 | [diff] [blame] | 202 | bool boot; |
Mika Westerberg | 2d8ff0b | 2018-07-25 11:48:39 +0300 | [diff] [blame] | 203 | bool rpm; |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 204 | unsigned int authorized; |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 205 | enum tb_security_level security_level; |
Gil Fine | 54e4181 | 2020-06-29 20:30:52 +0300 | [diff] [blame] | 206 | struct dentry *debugfs_dir; |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 207 | u8 *key; |
| 208 | u8 connection_id; |
| 209 | u8 connection_key; |
| 210 | u8 link; |
| 211 | u8 depth; |
Mika Westerberg | 4f7c2e0 | 2019-05-28 18:56:20 +0300 | [diff] [blame] | 212 | struct completion rpm_complete; |
Mario Limonciello | 1cb3629 | 2020-06-23 11:14:29 -0500 | [diff] [blame] | 213 | unsigned long quirks; |
Mika Westerberg | 56ad3ae | 2021-03-10 13:34:12 +0200 | [diff] [blame] | 214 | bool credit_allocation; |
| 215 | unsigned int max_usb3_credits; |
| 216 | unsigned int min_dp_aux_credits; |
| 217 | unsigned int min_dp_main_credits; |
| 218 | unsigned int max_pcie_credits; |
| 219 | unsigned int max_dma_credits; |
Gil Fine | 8a90e4f | 2021-12-17 03:16:39 +0200 | [diff] [blame] | 220 | enum tb_clx clx; |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 221 | }; |
| 222 | |
| 223 | /** |
| 224 | * struct tb_port - a thunderbolt port, part of a tb_switch |
Mika Westerberg | d1ff702 | 2017-10-02 13:38:34 +0300 | [diff] [blame] | 225 | * @config: Cached port configuration read from registers |
| 226 | * @sw: Switch the port belongs to |
| 227 | * @remote: Remote port (%NULL if not connected) |
| 228 | * @xdomain: Remote host (%NULL if not connected) |
| 229 | * @cap_phy: Offset, zero if not found |
Rajmohan Mani | cf29b9af | 2019-12-17 15:33:43 +0300 | [diff] [blame] | 230 | * @cap_tmu: Offset of the adapter specific TMU capability (%0 if not present) |
Mika Westerberg | 56183c8 | 2017-02-19 10:39:34 +0200 | [diff] [blame] | 231 | * @cap_adap: Offset of the adapter specific capability (%0 if not present) |
Mika Westerberg | b040798 | 2019-12-17 15:33:40 +0300 | [diff] [blame] | 232 | * @cap_usb4: Offset to the USB4 port capability (%0 if not present) |
Mika Westerberg | cae5f51 | 2021-04-01 17:34:20 +0300 | [diff] [blame] | 233 | * @usb4: Pointer to the USB4 port structure (only if @cap_usb4 is != %0) |
Mika Westerberg | d1ff702 | 2017-10-02 13:38:34 +0300 | [diff] [blame] | 234 | * @port: Port number on switch |
Nikunj A. Dadhania | 8824d19 | 2020-07-21 17:05:23 +0530 | [diff] [blame] | 235 | * @disabled: Disabled by eeprom or enabled but not implemented |
Mika Westerberg | 91c0c12 | 2019-03-21 19:03:00 +0200 | [diff] [blame] | 236 | * @bonded: true if the port is bonded (two lanes combined as one) |
Mika Westerberg | d1ff702 | 2017-10-02 13:38:34 +0300 | [diff] [blame] | 237 | * @dual_link_port: If the switch is connected using two ports, points |
| 238 | * to the other port. |
| 239 | * @link_nr: Is this primary or secondary port on the dual_link. |
Mika Westerberg | 0b2863a | 2017-02-19 16:57:27 +0200 | [diff] [blame] | 240 | * @in_hopids: Currently allocated input HopIDs |
| 241 | * @out_hopids: Currently allocated output HopIDs |
Mika Westerberg | 8afe909 | 2019-03-26 15:52:30 +0300 | [diff] [blame] | 242 | * @list: Used to link ports to DP resources list |
Mika Westerberg | 56ad3ae | 2021-03-10 13:34:12 +0200 | [diff] [blame] | 243 | * @total_credits: Total number of buffers available for this port |
| 244 | * @ctl_credits: Buffers reserved for control path |
Mika Westerberg | 6ed541c | 2021-03-22 18:09:35 +0200 | [diff] [blame] | 245 | * @dma_credits: Number of credits allocated for DMA tunneling for all |
| 246 | * DMA paths through this port. |
Mika Westerberg | c3963a5 | 2021-02-01 15:03:00 +0300 | [diff] [blame] | 247 | * |
| 248 | * In USB4 terminology this structure represents an adapter (protocol or |
| 249 | * lane adapter). |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 250 | */ |
| 251 | struct tb_port { |
| 252 | struct tb_regs_port_header config; |
| 253 | struct tb_switch *sw; |
Mika Westerberg | d1ff702 | 2017-10-02 13:38:34 +0300 | [diff] [blame] | 254 | struct tb_port *remote; |
| 255 | struct tb_xdomain *xdomain; |
| 256 | int cap_phy; |
Rajmohan Mani | cf29b9af | 2019-12-17 15:33:43 +0300 | [diff] [blame] | 257 | int cap_tmu; |
Mika Westerberg | 56183c8 | 2017-02-19 10:39:34 +0200 | [diff] [blame] | 258 | int cap_adap; |
Mika Westerberg | b040798 | 2019-12-17 15:33:40 +0300 | [diff] [blame] | 259 | int cap_usb4; |
Mika Westerberg | cae5f51 | 2021-04-01 17:34:20 +0300 | [diff] [blame] | 260 | struct usb4_port *usb4; |
Mika Westerberg | d1ff702 | 2017-10-02 13:38:34 +0300 | [diff] [blame] | 261 | u8 port; |
| 262 | bool disabled; |
Mika Westerberg | 91c0c12 | 2019-03-21 19:03:00 +0200 | [diff] [blame] | 263 | bool bonded; |
Andreas Noever | cd22e73 | 2014-06-12 23:11:46 +0200 | [diff] [blame] | 264 | struct tb_port *dual_link_port; |
| 265 | u8 link_nr:1; |
Mika Westerberg | 0b2863a | 2017-02-19 16:57:27 +0200 | [diff] [blame] | 266 | struct ida in_hopids; |
| 267 | struct ida out_hopids; |
Mika Westerberg | 8afe909 | 2019-03-26 15:52:30 +0300 | [diff] [blame] | 268 | struct list_head list; |
Mika Westerberg | 56ad3ae | 2021-03-10 13:34:12 +0200 | [diff] [blame] | 269 | unsigned int total_credits; |
| 270 | unsigned int ctl_credits; |
Mika Westerberg | 6ed541c | 2021-03-22 18:09:35 +0200 | [diff] [blame] | 271 | unsigned int dma_credits; |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 272 | }; |
| 273 | |
| 274 | /** |
Mika Westerberg | cae5f51 | 2021-04-01 17:34:20 +0300 | [diff] [blame] | 275 | * struct usb4_port - USB4 port device |
| 276 | * @dev: Device for the port |
| 277 | * @port: Pointer to the lane 0 adapter |
Rajmohan Mani | ccc5cb8 | 2021-04-01 18:20:17 +0300 | [diff] [blame] | 278 | * @can_offline: Does the port have necessary platform support to moved |
| 279 | * it into offline mode and back |
Rajmohan Mani | 3fb10ea | 2021-04-01 18:42:38 +0300 | [diff] [blame] | 280 | * @offline: The port is currently in offline mode |
Mika Westerberg | cae5f51 | 2021-04-01 17:34:20 +0300 | [diff] [blame] | 281 | */ |
| 282 | struct usb4_port { |
| 283 | struct device dev; |
| 284 | struct tb_port *port; |
Rajmohan Mani | ccc5cb8 | 2021-04-01 18:20:17 +0300 | [diff] [blame] | 285 | bool can_offline; |
Rajmohan Mani | 3fb10ea | 2021-04-01 18:42:38 +0300 | [diff] [blame] | 286 | bool offline; |
Mika Westerberg | cae5f51 | 2021-04-01 17:34:20 +0300 | [diff] [blame] | 287 | }; |
| 288 | |
| 289 | /** |
Kranthi Kuntala | dacb128 | 2020-03-05 16:39:58 +0200 | [diff] [blame] | 290 | * tb_retimer: Thunderbolt retimer |
| 291 | * @dev: Device for the retimer |
| 292 | * @tb: Pointer to the domain the retimer belongs to |
| 293 | * @index: Retimer index facing the router USB4 port |
| 294 | * @vendor: Vendor ID of the retimer |
| 295 | * @device: Device ID of the retimer |
| 296 | * @port: Pointer to the lane 0 adapter |
| 297 | * @nvm: Pointer to the NVM if the retimer has one (%NULL otherwise) |
| 298 | * @auth_status: Status of last NVM authentication |
| 299 | */ |
| 300 | struct tb_retimer { |
| 301 | struct device dev; |
| 302 | struct tb *tb; |
| 303 | u8 index; |
| 304 | u32 vendor; |
| 305 | u32 device; |
| 306 | struct tb_port *port; |
| 307 | struct tb_nvm *nvm; |
| 308 | u32 auth_status; |
| 309 | }; |
| 310 | |
| 311 | /** |
Andreas Noever | 520b670 | 2014-06-03 22:04:07 +0200 | [diff] [blame] | 312 | * struct tb_path_hop - routing information for a tb_path |
Mika Westerberg | 8c7acaaf | 2017-02-19 22:11:41 +0200 | [diff] [blame] | 313 | * @in_port: Ingress port of a switch |
| 314 | * @out_port: Egress port of a switch where the packet is routed out |
| 315 | * (must be on the same switch than @in_port) |
| 316 | * @in_hop_index: HopID where the path configuration entry is placed in |
| 317 | * the path config space of @in_port. |
| 318 | * @in_counter_index: Used counter index (not used in the driver |
| 319 | * currently, %-1 to disable) |
| 320 | * @next_hop_index: HopID of the packet when it is routed out from @out_port |
Mika Westerberg | 0414bec | 2017-02-19 23:43:26 +0200 | [diff] [blame] | 321 | * @initial_credits: Number of initial flow control credits allocated for |
| 322 | * the path |
Mika Westerberg | 02c5e7c | 2020-12-10 16:07:59 +0200 | [diff] [blame] | 323 | * @nfc_credits: Number of non-flow controlled buffers allocated for the |
| 324 | * @in_port. |
Andreas Noever | 520b670 | 2014-06-03 22:04:07 +0200 | [diff] [blame] | 325 | * |
| 326 | * Hop configuration is always done on the IN port of a switch. |
| 327 | * in_port and out_port have to be on the same switch. Packets arriving on |
| 328 | * in_port with "hop" = in_hop_index will get routed to through out_port. The |
Mika Westerberg | 8c7acaaf | 2017-02-19 22:11:41 +0200 | [diff] [blame] | 329 | * next hop to take (on out_port->remote) is determined by |
| 330 | * next_hop_index. When routing packet to another switch (out->remote is |
| 331 | * set) the @next_hop_index must match the @in_hop_index of that next |
| 332 | * hop to make routing possible. |
Andreas Noever | 520b670 | 2014-06-03 22:04:07 +0200 | [diff] [blame] | 333 | * |
| 334 | * in_counter_index is the index of a counter (in TB_CFG_COUNTERS) on the in |
| 335 | * port. |
| 336 | */ |
| 337 | struct tb_path_hop { |
| 338 | struct tb_port *in_port; |
| 339 | struct tb_port *out_port; |
| 340 | int in_hop_index; |
Mika Westerberg | 8c7acaaf | 2017-02-19 22:11:41 +0200 | [diff] [blame] | 341 | int in_counter_index; |
Andreas Noever | 520b670 | 2014-06-03 22:04:07 +0200 | [diff] [blame] | 342 | int next_hop_index; |
Mika Westerberg | 0414bec | 2017-02-19 23:43:26 +0200 | [diff] [blame] | 343 | unsigned int initial_credits; |
Mika Westerberg | 02c5e7c | 2020-12-10 16:07:59 +0200 | [diff] [blame] | 344 | unsigned int nfc_credits; |
Andreas Noever | 520b670 | 2014-06-03 22:04:07 +0200 | [diff] [blame] | 345 | }; |
| 346 | |
| 347 | /** |
| 348 | * enum tb_path_port - path options mask |
Mika Westerberg | 8c7acaaf | 2017-02-19 22:11:41 +0200 | [diff] [blame] | 349 | * @TB_PATH_NONE: Do not activate on any hop on path |
| 350 | * @TB_PATH_SOURCE: Activate on the first hop (out of src) |
| 351 | * @TB_PATH_INTERNAL: Activate on the intermediate hops (not the first/last) |
| 352 | * @TB_PATH_DESTINATION: Activate on the last hop (into dst) |
| 353 | * @TB_PATH_ALL: Activate on all hops on the path |
Andreas Noever | 520b670 | 2014-06-03 22:04:07 +0200 | [diff] [blame] | 354 | */ |
| 355 | enum tb_path_port { |
| 356 | TB_PATH_NONE = 0, |
Mika Westerberg | 8c7acaaf | 2017-02-19 22:11:41 +0200 | [diff] [blame] | 357 | TB_PATH_SOURCE = 1, |
| 358 | TB_PATH_INTERNAL = 2, |
| 359 | TB_PATH_DESTINATION = 4, |
Andreas Noever | 520b670 | 2014-06-03 22:04:07 +0200 | [diff] [blame] | 360 | TB_PATH_ALL = 7, |
| 361 | }; |
| 362 | |
| 363 | /** |
| 364 | * struct tb_path - a unidirectional path between two ports |
Mika Westerberg | 8c7acaaf | 2017-02-19 22:11:41 +0200 | [diff] [blame] | 365 | * @tb: Pointer to the domain structure |
| 366 | * @name: Name of the path (used for debugging) |
Mika Westerberg | 8c7acaaf | 2017-02-19 22:11:41 +0200 | [diff] [blame] | 367 | * @ingress_shared_buffer: Shared buffering used for ingress ports on the path |
| 368 | * @egress_shared_buffer: Shared buffering used for egress ports on the path |
| 369 | * @ingress_fc_enable: Flow control for ingress ports on the path |
| 370 | * @egress_fc_enable: Flow control for egress ports on the path |
| 371 | * @priority: Priority group if the path |
| 372 | * @weight: Weight of the path inside the priority group |
| 373 | * @drop_packages: Drop packages from queue tail or head |
| 374 | * @activated: Is the path active |
Mika Westerberg | 44242d6 | 2018-09-28 16:35:32 +0300 | [diff] [blame] | 375 | * @clear_fc: Clear all flow control from the path config space entries |
| 376 | * when deactivating this path |
Mika Westerberg | 8c7acaaf | 2017-02-19 22:11:41 +0200 | [diff] [blame] | 377 | * @hops: Path hops |
| 378 | * @path_length: How many hops the path uses |
Mika Westerberg | 43bddb2 | 2021-11-14 17:20:59 +0200 | [diff] [blame] | 379 | * @alloc_hopid: Does this path consume port HopID |
Andreas Noever | 520b670 | 2014-06-03 22:04:07 +0200 | [diff] [blame] | 380 | * |
Mika Westerberg | 8c7acaaf | 2017-02-19 22:11:41 +0200 | [diff] [blame] | 381 | * A path consists of a number of hops (see &struct tb_path_hop). To |
| 382 | * establish a PCIe tunnel two paths have to be created between the two |
| 383 | * PCIe ports. |
Andreas Noever | 520b670 | 2014-06-03 22:04:07 +0200 | [diff] [blame] | 384 | */ |
| 385 | struct tb_path { |
| 386 | struct tb *tb; |
Mika Westerberg | 8c7acaaf | 2017-02-19 22:11:41 +0200 | [diff] [blame] | 387 | const char *name; |
Andreas Noever | 520b670 | 2014-06-03 22:04:07 +0200 | [diff] [blame] | 388 | enum tb_path_port ingress_shared_buffer; |
| 389 | enum tb_path_port egress_shared_buffer; |
| 390 | enum tb_path_port ingress_fc_enable; |
| 391 | enum tb_path_port egress_fc_enable; |
| 392 | |
Nathan Chancellor | 3720978 | 2019-04-24 11:34:13 -0700 | [diff] [blame] | 393 | unsigned int priority:3; |
Andreas Noever | 520b670 | 2014-06-03 22:04:07 +0200 | [diff] [blame] | 394 | int weight:4; |
| 395 | bool drop_packages; |
| 396 | bool activated; |
Mika Westerberg | 44242d6 | 2018-09-28 16:35:32 +0300 | [diff] [blame] | 397 | bool clear_fc; |
Andreas Noever | 520b670 | 2014-06-03 22:04:07 +0200 | [diff] [blame] | 398 | struct tb_path_hop *hops; |
Mika Westerberg | 8c7acaaf | 2017-02-19 22:11:41 +0200 | [diff] [blame] | 399 | int path_length; |
Mika Westerberg | 43bddb2 | 2021-11-14 17:20:59 +0200 | [diff] [blame] | 400 | bool alloc_hopid; |
Andreas Noever | 520b670 | 2014-06-03 22:04:07 +0200 | [diff] [blame] | 401 | }; |
| 402 | |
Mika Westerberg | 0b2863a | 2017-02-19 16:57:27 +0200 | [diff] [blame] | 403 | /* HopIDs 0-7 are reserved by the Thunderbolt protocol */ |
| 404 | #define TB_PATH_MIN_HOPID 8 |
Mika Westerberg | c738a79 | 2020-05-08 11:47:00 +0300 | [diff] [blame] | 405 | /* |
| 406 | * Support paths from the farthest (depth 6) router to the host and back |
| 407 | * to the same level (not necessarily to the same router). |
| 408 | */ |
| 409 | #define TB_PATH_MAX_HOPS (7 * 2) |
Mika Westerberg | 0b2863a | 2017-02-19 16:57:27 +0200 | [diff] [blame] | 410 | |
Mika Westerberg | b2911a5 | 2019-12-06 18:36:07 +0200 | [diff] [blame] | 411 | /* Possible wake types */ |
| 412 | #define TB_WAKE_ON_CONNECT BIT(0) |
| 413 | #define TB_WAKE_ON_DISCONNECT BIT(1) |
| 414 | #define TB_WAKE_ON_USB4 BIT(2) |
| 415 | #define TB_WAKE_ON_USB3 BIT(3) |
| 416 | #define TB_WAKE_ON_PCIE BIT(4) |
Mika Westerberg | 6026b70 | 2021-01-14 16:44:17 +0200 | [diff] [blame] | 417 | #define TB_WAKE_ON_DP BIT(5) |
Mika Westerberg | b2911a5 | 2019-12-06 18:36:07 +0200 | [diff] [blame] | 418 | |
Mika Westerberg | 9d3cce0 | 2017-06-06 15:25:00 +0300 | [diff] [blame] | 419 | /** |
| 420 | * struct tb_cm_ops - Connection manager specific operations vector |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 421 | * @driver_ready: Called right after control channel is started. Used by |
| 422 | * ICM to send driver ready message to the firmware. |
Mika Westerberg | 9d3cce0 | 2017-06-06 15:25:00 +0300 | [diff] [blame] | 423 | * @start: Starts the domain |
| 424 | * @stop: Stops the domain |
| 425 | * @suspend_noirq: Connection manager specific suspend_noirq |
| 426 | * @resume_noirq: Connection manager specific resume_noirq |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 427 | * @suspend: Connection manager specific suspend |
Mika Westerberg | 884e4d5 | 2020-08-31 13:05:14 +0300 | [diff] [blame] | 428 | * @freeze_noirq: Connection manager specific freeze_noirq |
| 429 | * @thaw_noirq: Connection manager specific thaw_noirq |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 430 | * @complete: Connection manager specific complete |
Mika Westerberg | 2d8ff0b | 2018-07-25 11:48:39 +0300 | [diff] [blame] | 431 | * @runtime_suspend: Connection manager specific runtime_suspend |
| 432 | * @runtime_resume: Connection manager specific runtime_resume |
Mika Westerberg | 4f7c2e0 | 2019-05-28 18:56:20 +0300 | [diff] [blame] | 433 | * @runtime_suspend_switch: Runtime suspend a switch |
| 434 | * @runtime_resume_switch: Runtime resume a switch |
Mika Westerberg | 81a54b5 | 2017-06-06 15:25:09 +0300 | [diff] [blame] | 435 | * @handle_event: Handle thunderbolt event |
Mika Westerberg | 9aaa3b8 | 2018-01-21 12:08:04 +0200 | [diff] [blame] | 436 | * @get_boot_acl: Get boot ACL list |
| 437 | * @set_boot_acl: Set boot ACL list |
Mika Westerberg | 3da88be | 2020-11-10 11:47:14 +0300 | [diff] [blame] | 438 | * @disapprove_switch: Disapprove switch (disconnect PCIe tunnel) |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 439 | * @approve_switch: Approve switch |
| 440 | * @add_switch_key: Add key to switch |
| 441 | * @challenge_switch_key: Challenge switch using key |
Mika Westerberg | e6b245c | 2017-06-06 15:25:17 +0300 | [diff] [blame] | 442 | * @disconnect_pcie_paths: Disconnects PCIe paths before NVM update |
Mika Westerberg | d1ff702 | 2017-10-02 13:38:34 +0300 | [diff] [blame] | 443 | * @approve_xdomain_paths: Approve (establish) XDomain DMA paths |
| 444 | * @disconnect_xdomain_paths: Disconnect XDomain DMA paths |
Mika Westerberg | 9490f71 | 2020-11-03 13:58:00 +0200 | [diff] [blame] | 445 | * @usb4_switch_op: Optional proxy for USB4 router operations. If set |
| 446 | * this will be called whenever USB4 router operation is |
| 447 | * performed. If this returns %-EOPNOTSUPP then the |
| 448 | * native USB4 router operation is called. |
| 449 | * @usb4_switch_nvm_authenticate_status: Optional callback that the CM |
| 450 | * implementation can be used to |
| 451 | * return status of USB4 NVM_AUTH |
| 452 | * router operation. |
Mika Westerberg | 9d3cce0 | 2017-06-06 15:25:00 +0300 | [diff] [blame] | 453 | */ |
| 454 | struct tb_cm_ops { |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 455 | int (*driver_ready)(struct tb *tb); |
Mika Westerberg | 9d3cce0 | 2017-06-06 15:25:00 +0300 | [diff] [blame] | 456 | int (*start)(struct tb *tb); |
| 457 | void (*stop)(struct tb *tb); |
| 458 | int (*suspend_noirq)(struct tb *tb); |
| 459 | int (*resume_noirq)(struct tb *tb); |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 460 | int (*suspend)(struct tb *tb); |
Mika Westerberg | 884e4d5 | 2020-08-31 13:05:14 +0300 | [diff] [blame] | 461 | int (*freeze_noirq)(struct tb *tb); |
| 462 | int (*thaw_noirq)(struct tb *tb); |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 463 | void (*complete)(struct tb *tb); |
Mika Westerberg | 2d8ff0b | 2018-07-25 11:48:39 +0300 | [diff] [blame] | 464 | int (*runtime_suspend)(struct tb *tb); |
| 465 | int (*runtime_resume)(struct tb *tb); |
Mika Westerberg | 4f7c2e0 | 2019-05-28 18:56:20 +0300 | [diff] [blame] | 466 | int (*runtime_suspend_switch)(struct tb_switch *sw); |
| 467 | int (*runtime_resume_switch)(struct tb_switch *sw); |
Mika Westerberg | 81a54b5 | 2017-06-06 15:25:09 +0300 | [diff] [blame] | 468 | void (*handle_event)(struct tb *tb, enum tb_cfg_pkg_type, |
| 469 | const void *buf, size_t size); |
Mika Westerberg | 9aaa3b8 | 2018-01-21 12:08:04 +0200 | [diff] [blame] | 470 | int (*get_boot_acl)(struct tb *tb, uuid_t *uuids, size_t nuuids); |
| 471 | int (*set_boot_acl)(struct tb *tb, const uuid_t *uuids, size_t nuuids); |
Mika Westerberg | 3da88be | 2020-11-10 11:47:14 +0300 | [diff] [blame] | 472 | int (*disapprove_switch)(struct tb *tb, struct tb_switch *sw); |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 473 | int (*approve_switch)(struct tb *tb, struct tb_switch *sw); |
| 474 | int (*add_switch_key)(struct tb *tb, struct tb_switch *sw); |
| 475 | int (*challenge_switch_key)(struct tb *tb, struct tb_switch *sw, |
| 476 | const u8 *challenge, u8 *response); |
Mika Westerberg | e6b245c | 2017-06-06 15:25:17 +0300 | [diff] [blame] | 477 | int (*disconnect_pcie_paths)(struct tb *tb); |
Mika Westerberg | 180b068 | 2021-01-08 16:25:39 +0200 | [diff] [blame] | 478 | int (*approve_xdomain_paths)(struct tb *tb, struct tb_xdomain *xd, |
| 479 | int transmit_path, int transmit_ring, |
| 480 | int receive_path, int receive_ring); |
| 481 | int (*disconnect_xdomain_paths)(struct tb *tb, struct tb_xdomain *xd, |
| 482 | int transmit_path, int transmit_ring, |
| 483 | int receive_path, int receive_ring); |
Mika Westerberg | 9490f71 | 2020-11-03 13:58:00 +0200 | [diff] [blame] | 484 | int (*usb4_switch_op)(struct tb_switch *sw, u16 opcode, u32 *metadata, |
| 485 | u8 *status, const void *tx_data, size_t tx_data_len, |
| 486 | void *rx_data, size_t rx_data_len); |
| 487 | int (*usb4_switch_nvm_authenticate_status)(struct tb_switch *sw, |
| 488 | u32 *status); |
Mika Westerberg | 9d3cce0 | 2017-06-06 15:25:00 +0300 | [diff] [blame] | 489 | }; |
Andreas Noever | 520b670 | 2014-06-03 22:04:07 +0200 | [diff] [blame] | 490 | |
Mika Westerberg | 9d3cce0 | 2017-06-06 15:25:00 +0300 | [diff] [blame] | 491 | static inline void *tb_priv(struct tb *tb) |
| 492 | { |
| 493 | return (void *)tb->privdata; |
| 494 | } |
| 495 | |
Mika Westerberg | 2d8ff0b | 2018-07-25 11:48:39 +0300 | [diff] [blame] | 496 | #define TB_AUTOSUSPEND_DELAY 15000 /* ms */ |
| 497 | |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 498 | /* helper functions & macros */ |
| 499 | |
| 500 | /** |
| 501 | * tb_upstream_port() - return the upstream port of a switch |
| 502 | * |
| 503 | * Every switch has an upstream port (for the root switch it is the NHI). |
| 504 | * |
| 505 | * During switch alloc/init tb_upstream_port()->remote may be NULL, even for |
| 506 | * non root switches (on the NHI port remote is always NULL). |
| 507 | * |
| 508 | * Return: Returns the upstream port of the switch. |
| 509 | */ |
| 510 | static inline struct tb_port *tb_upstream_port(struct tb_switch *sw) |
| 511 | { |
| 512 | return &sw->ports[sw->config.upstream_port_number]; |
| 513 | } |
| 514 | |
Mika Westerberg | dfe40ca | 2019-03-07 15:26:45 +0200 | [diff] [blame] | 515 | /** |
| 516 | * tb_is_upstream_port() - Is the port upstream facing |
| 517 | * @port: Port to check |
| 518 | * |
| 519 | * Returns true if @port is upstream facing port. In case of dual link |
| 520 | * ports both return true. |
| 521 | */ |
| 522 | static inline bool tb_is_upstream_port(const struct tb_port *port) |
| 523 | { |
| 524 | const struct tb_port *upstream_port = tb_upstream_port(port->sw); |
| 525 | return port == upstream_port || port->dual_link_port == upstream_port; |
| 526 | } |
| 527 | |
Mika Westerberg | b323a98 | 2019-03-06 19:23:38 +0200 | [diff] [blame] | 528 | static inline u64 tb_route(const struct tb_switch *sw) |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 529 | { |
| 530 | return ((u64) sw->config.route_hi) << 32 | sw->config.route_lo; |
| 531 | } |
| 532 | |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 533 | static inline struct tb_port *tb_port_at(u64 route, struct tb_switch *sw) |
| 534 | { |
| 535 | u8 port; |
| 536 | |
| 537 | port = route >> (sw->config.depth * 8); |
| 538 | if (WARN_ON(port > sw->config.max_port_number)) |
| 539 | return NULL; |
| 540 | return &sw->ports[port]; |
| 541 | } |
| 542 | |
Mika Westerberg | dfe40ca | 2019-03-07 15:26:45 +0200 | [diff] [blame] | 543 | /** |
| 544 | * tb_port_has_remote() - Does the port have switch connected downstream |
| 545 | * @port: Port to check |
| 546 | * |
| 547 | * Returns true only when the port is primary port and has remote set. |
| 548 | */ |
| 549 | static inline bool tb_port_has_remote(const struct tb_port *port) |
| 550 | { |
| 551 | if (tb_is_upstream_port(port)) |
| 552 | return false; |
| 553 | if (!port->remote) |
| 554 | return false; |
| 555 | if (port->dual_link_port && port->link_nr) |
| 556 | return false; |
| 557 | |
| 558 | return true; |
| 559 | } |
| 560 | |
Mika Westerberg | 344e064 | 2017-10-11 17:19:54 +0300 | [diff] [blame] | 561 | static inline bool tb_port_is_null(const struct tb_port *port) |
| 562 | { |
| 563 | return port && port->port && port->config.type == TB_TYPE_PORT; |
| 564 | } |
| 565 | |
Mika Westerberg | a3cfebd | 2020-07-25 10:32:46 +0300 | [diff] [blame] | 566 | static inline bool tb_port_is_nhi(const struct tb_port *port) |
| 567 | { |
| 568 | return port && port->config.type == TB_TYPE_NHI; |
| 569 | } |
| 570 | |
Mika Westerberg | 99cabbb | 2018-12-30 21:34:08 +0200 | [diff] [blame] | 571 | static inline bool tb_port_is_pcie_down(const struct tb_port *port) |
| 572 | { |
| 573 | return port && port->config.type == TB_TYPE_PCIE_DOWN; |
| 574 | } |
| 575 | |
Mika Westerberg | 0414bec | 2017-02-19 23:43:26 +0200 | [diff] [blame] | 576 | static inline bool tb_port_is_pcie_up(const struct tb_port *port) |
| 577 | { |
| 578 | return port && port->config.type == TB_TYPE_PCIE_UP; |
| 579 | } |
| 580 | |
Mika Westerberg | 4f807e4 | 2018-09-17 16:30:49 +0300 | [diff] [blame] | 581 | static inline bool tb_port_is_dpin(const struct tb_port *port) |
| 582 | { |
| 583 | return port && port->config.type == TB_TYPE_DP_HDMI_IN; |
| 584 | } |
| 585 | |
| 586 | static inline bool tb_port_is_dpout(const struct tb_port *port) |
| 587 | { |
| 588 | return port && port->config.type == TB_TYPE_DP_HDMI_OUT; |
| 589 | } |
| 590 | |
Rajmohan Mani | e6f8185 | 2019-12-17 15:33:44 +0300 | [diff] [blame] | 591 | static inline bool tb_port_is_usb3_down(const struct tb_port *port) |
| 592 | { |
| 593 | return port && port->config.type == TB_TYPE_USB3_DOWN; |
| 594 | } |
| 595 | |
| 596 | static inline bool tb_port_is_usb3_up(const struct tb_port *port) |
| 597 | { |
| 598 | return port && port->config.type == TB_TYPE_USB3_UP; |
| 599 | } |
| 600 | |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 601 | static inline int tb_sw_read(struct tb_switch *sw, void *buffer, |
| 602 | enum tb_cfg_space space, u32 offset, u32 length) |
| 603 | { |
Mika Westerberg | 4708384 | 2019-03-19 17:07:37 +0200 | [diff] [blame] | 604 | if (sw->is_unplugged) |
| 605 | return -ENODEV; |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 606 | return tb_cfg_read(sw->tb->ctl, |
| 607 | buffer, |
| 608 | tb_route(sw), |
| 609 | 0, |
| 610 | space, |
| 611 | offset, |
| 612 | length); |
| 613 | } |
| 614 | |
Mika Westerberg | 826c6a1 | 2019-07-01 18:41:51 +0300 | [diff] [blame] | 615 | static inline int tb_sw_write(struct tb_switch *sw, const void *buffer, |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 616 | enum tb_cfg_space space, u32 offset, u32 length) |
| 617 | { |
Mika Westerberg | 4708384 | 2019-03-19 17:07:37 +0200 | [diff] [blame] | 618 | if (sw->is_unplugged) |
| 619 | return -ENODEV; |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 620 | return tb_cfg_write(sw->tb->ctl, |
| 621 | buffer, |
| 622 | tb_route(sw), |
| 623 | 0, |
| 624 | space, |
| 625 | offset, |
| 626 | length); |
| 627 | } |
| 628 | |
| 629 | static inline int tb_port_read(struct tb_port *port, void *buffer, |
| 630 | enum tb_cfg_space space, u32 offset, u32 length) |
| 631 | { |
Mika Westerberg | 4708384 | 2019-03-19 17:07:37 +0200 | [diff] [blame] | 632 | if (port->sw->is_unplugged) |
| 633 | return -ENODEV; |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 634 | return tb_cfg_read(port->sw->tb->ctl, |
| 635 | buffer, |
| 636 | tb_route(port->sw), |
| 637 | port->port, |
| 638 | space, |
| 639 | offset, |
| 640 | length); |
| 641 | } |
| 642 | |
Mika Westerberg | 16a1258 | 2017-06-06 15:24:53 +0300 | [diff] [blame] | 643 | static inline int tb_port_write(struct tb_port *port, const void *buffer, |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 644 | enum tb_cfg_space space, u32 offset, u32 length) |
| 645 | { |
Mika Westerberg | 4708384 | 2019-03-19 17:07:37 +0200 | [diff] [blame] | 646 | if (port->sw->is_unplugged) |
| 647 | return -ENODEV; |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 648 | return tb_cfg_write(port->sw->tb->ctl, |
| 649 | buffer, |
| 650 | tb_route(port->sw), |
| 651 | port->port, |
| 652 | space, |
| 653 | offset, |
| 654 | length); |
| 655 | } |
| 656 | |
| 657 | #define tb_err(tb, fmt, arg...) dev_err(&(tb)->nhi->pdev->dev, fmt, ## arg) |
| 658 | #define tb_WARN(tb, fmt, arg...) dev_WARN(&(tb)->nhi->pdev->dev, fmt, ## arg) |
| 659 | #define tb_warn(tb, fmt, arg...) dev_warn(&(tb)->nhi->pdev->dev, fmt, ## arg) |
| 660 | #define tb_info(tb, fmt, arg...) dev_info(&(tb)->nhi->pdev->dev, fmt, ## arg) |
Mika Westerberg | daa5140 | 2018-10-01 12:31:19 +0300 | [diff] [blame] | 661 | #define tb_dbg(tb, fmt, arg...) dev_dbg(&(tb)->nhi->pdev->dev, fmt, ## arg) |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 662 | |
| 663 | #define __TB_SW_PRINT(level, sw, fmt, arg...) \ |
| 664 | do { \ |
Mika Westerberg | b323a98 | 2019-03-06 19:23:38 +0200 | [diff] [blame] | 665 | const struct tb_switch *__sw = (sw); \ |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 666 | level(__sw->tb, "%llx: " fmt, \ |
| 667 | tb_route(__sw), ## arg); \ |
| 668 | } while (0) |
| 669 | #define tb_sw_WARN(sw, fmt, arg...) __TB_SW_PRINT(tb_WARN, sw, fmt, ##arg) |
| 670 | #define tb_sw_warn(sw, fmt, arg...) __TB_SW_PRINT(tb_warn, sw, fmt, ##arg) |
| 671 | #define tb_sw_info(sw, fmt, arg...) __TB_SW_PRINT(tb_info, sw, fmt, ##arg) |
Mika Westerberg | daa5140 | 2018-10-01 12:31:19 +0300 | [diff] [blame] | 672 | #define tb_sw_dbg(sw, fmt, arg...) __TB_SW_PRINT(tb_dbg, sw, fmt, ##arg) |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 673 | |
| 674 | #define __TB_PORT_PRINT(level, _port, fmt, arg...) \ |
| 675 | do { \ |
Mika Westerberg | b323a98 | 2019-03-06 19:23:38 +0200 | [diff] [blame] | 676 | const struct tb_port *__port = (_port); \ |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 677 | level(__port->sw->tb, "%llx:%x: " fmt, \ |
| 678 | tb_route(__port->sw), __port->port, ## arg); \ |
| 679 | } while (0) |
| 680 | #define tb_port_WARN(port, fmt, arg...) \ |
| 681 | __TB_PORT_PRINT(tb_WARN, port, fmt, ##arg) |
| 682 | #define tb_port_warn(port, fmt, arg...) \ |
| 683 | __TB_PORT_PRINT(tb_warn, port, fmt, ##arg) |
| 684 | #define tb_port_info(port, fmt, arg...) \ |
| 685 | __TB_PORT_PRINT(tb_info, port, fmt, ##arg) |
Mika Westerberg | daa5140 | 2018-10-01 12:31:19 +0300 | [diff] [blame] | 686 | #define tb_port_dbg(port, fmt, arg...) \ |
| 687 | __TB_PORT_PRINT(tb_dbg, port, fmt, ##arg) |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 688 | |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 689 | struct tb *icm_probe(struct tb_nhi *nhi); |
Mika Westerberg | 9d3cce0 | 2017-06-06 15:25:00 +0300 | [diff] [blame] | 690 | struct tb *tb_probe(struct tb_nhi *nhi); |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 691 | |
Mika Westerberg | 9d3cce0 | 2017-06-06 15:25:00 +0300 | [diff] [blame] | 692 | extern struct device_type tb_domain_type; |
Kranthi Kuntala | dacb128 | 2020-03-05 16:39:58 +0200 | [diff] [blame] | 693 | extern struct device_type tb_retimer_type; |
Mika Westerberg | bfe778a | 2017-06-06 15:25:01 +0300 | [diff] [blame] | 694 | extern struct device_type tb_switch_type; |
Mika Westerberg | cae5f51 | 2021-04-01 17:34:20 +0300 | [diff] [blame] | 695 | extern struct device_type usb4_port_device_type; |
Mika Westerberg | 9d3cce0 | 2017-06-06 15:25:00 +0300 | [diff] [blame] | 696 | |
| 697 | int tb_domain_init(void); |
| 698 | void tb_domain_exit(void); |
Mika Westerberg | d1ff702 | 2017-10-02 13:38:34 +0300 | [diff] [blame] | 699 | int tb_xdomain_init(void); |
| 700 | void tb_xdomain_exit(void); |
Mika Westerberg | 9d3cce0 | 2017-06-06 15:25:00 +0300 | [diff] [blame] | 701 | |
Mika Westerberg | 7f0a34d | 2020-12-29 13:44:57 +0200 | [diff] [blame] | 702 | struct tb *tb_domain_alloc(struct tb_nhi *nhi, int timeout_msec, size_t privsize); |
Mika Westerberg | 9d3cce0 | 2017-06-06 15:25:00 +0300 | [diff] [blame] | 703 | int tb_domain_add(struct tb *tb); |
| 704 | void tb_domain_remove(struct tb *tb); |
| 705 | int tb_domain_suspend_noirq(struct tb *tb); |
| 706 | int tb_domain_resume_noirq(struct tb *tb); |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 707 | int tb_domain_suspend(struct tb *tb); |
Mika Westerberg | 884e4d5 | 2020-08-31 13:05:14 +0300 | [diff] [blame] | 708 | int tb_domain_freeze_noirq(struct tb *tb); |
| 709 | int tb_domain_thaw_noirq(struct tb *tb); |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 710 | void tb_domain_complete(struct tb *tb); |
Mika Westerberg | 2d8ff0b | 2018-07-25 11:48:39 +0300 | [diff] [blame] | 711 | int tb_domain_runtime_suspend(struct tb *tb); |
| 712 | int tb_domain_runtime_resume(struct tb *tb); |
Mika Westerberg | 3da88be | 2020-11-10 11:47:14 +0300 | [diff] [blame] | 713 | int tb_domain_disapprove_switch(struct tb *tb, struct tb_switch *sw); |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 714 | int tb_domain_approve_switch(struct tb *tb, struct tb_switch *sw); |
| 715 | int tb_domain_approve_switch_key(struct tb *tb, struct tb_switch *sw); |
| 716 | int tb_domain_challenge_switch_key(struct tb *tb, struct tb_switch *sw); |
Mika Westerberg | e6b245c | 2017-06-06 15:25:17 +0300 | [diff] [blame] | 717 | int tb_domain_disconnect_pcie_paths(struct tb *tb); |
Mika Westerberg | 180b068 | 2021-01-08 16:25:39 +0200 | [diff] [blame] | 718 | int tb_domain_approve_xdomain_paths(struct tb *tb, struct tb_xdomain *xd, |
| 719 | int transmit_path, int transmit_ring, |
| 720 | int receive_path, int receive_ring); |
| 721 | int tb_domain_disconnect_xdomain_paths(struct tb *tb, struct tb_xdomain *xd, |
| 722 | int transmit_path, int transmit_ring, |
| 723 | int receive_path, int receive_ring); |
Mika Westerberg | d1ff702 | 2017-10-02 13:38:34 +0300 | [diff] [blame] | 724 | int tb_domain_disconnect_all_paths(struct tb *tb); |
Mika Westerberg | 9d3cce0 | 2017-06-06 15:25:00 +0300 | [diff] [blame] | 725 | |
Mika Westerberg | 559c1e1 | 2018-10-22 14:47:01 +0300 | [diff] [blame] | 726 | static inline struct tb *tb_domain_get(struct tb *tb) |
| 727 | { |
| 728 | if (tb) |
| 729 | get_device(&tb->dev); |
| 730 | return tb; |
| 731 | } |
| 732 | |
Mika Westerberg | 9d3cce0 | 2017-06-06 15:25:00 +0300 | [diff] [blame] | 733 | static inline void tb_domain_put(struct tb *tb) |
| 734 | { |
| 735 | put_device(&tb->dev); |
| 736 | } |
Andreas Noever | d6cc51c | 2014-06-03 22:04:00 +0200 | [diff] [blame] | 737 | |
Mika Westerberg | 719a5fe | 2020-03-05 11:37:15 +0200 | [diff] [blame] | 738 | struct tb_nvm *tb_nvm_alloc(struct device *dev); |
| 739 | int tb_nvm_add_active(struct tb_nvm *nvm, size_t size, nvmem_reg_read_t reg_read); |
| 740 | int tb_nvm_write_buf(struct tb_nvm *nvm, unsigned int offset, void *val, |
| 741 | size_t bytes); |
| 742 | int tb_nvm_add_non_active(struct tb_nvm *nvm, size_t size, |
| 743 | nvmem_reg_write_t reg_write); |
| 744 | void tb_nvm_free(struct tb_nvm *nvm); |
| 745 | void tb_nvm_exit(void); |
| 746 | |
Mika Westerberg | 9b38303 | 2021-04-01 16:54:15 +0300 | [diff] [blame] | 747 | typedef int (*read_block_fn)(void *, unsigned int, void *, size_t); |
| 748 | typedef int (*write_block_fn)(void *, unsigned int, const void *, size_t); |
| 749 | |
| 750 | int tb_nvm_read_data(unsigned int address, void *buf, size_t size, |
| 751 | unsigned int retries, read_block_fn read_block, |
| 752 | void *read_block_data); |
| 753 | int tb_nvm_write_data(unsigned int address, const void *buf, size_t size, |
| 754 | unsigned int retries, write_block_fn write_next_block, |
| 755 | void *write_block_data); |
| 756 | |
Mika Westerberg | bfe778a | 2017-06-06 15:25:01 +0300 | [diff] [blame] | 757 | struct tb_switch *tb_switch_alloc(struct tb *tb, struct device *parent, |
| 758 | u64 route); |
Mika Westerberg | e6b245c | 2017-06-06 15:25:17 +0300 | [diff] [blame] | 759 | struct tb_switch *tb_switch_alloc_safe_mode(struct tb *tb, |
| 760 | struct device *parent, u64 route); |
Mika Westerberg | bfe778a | 2017-06-06 15:25:01 +0300 | [diff] [blame] | 761 | int tb_switch_configure(struct tb_switch *sw); |
| 762 | int tb_switch_add(struct tb_switch *sw); |
| 763 | void tb_switch_remove(struct tb_switch *sw); |
Mika Westerberg | 6ac6fae | 2020-06-05 14:25:02 +0300 | [diff] [blame] | 764 | void tb_switch_suspend(struct tb_switch *sw, bool runtime); |
Andreas Noever | 23dd5bb | 2014-06-03 22:04:12 +0200 | [diff] [blame] | 765 | int tb_switch_resume(struct tb_switch *sw); |
Mika Westerberg | 356b6c4 | 2019-09-19 15:25:30 +0300 | [diff] [blame] | 766 | int tb_switch_reset(struct tb_switch *sw); |
Gil Fine | 1639664 | 2021-12-17 03:16:40 +0200 | [diff] [blame] | 767 | int tb_switch_wait_for_bit(struct tb_switch *sw, u32 offset, u32 bit, |
| 768 | u32 value, int timeout_msec); |
Lukas Wunner | aae20bb | 2016-03-20 13:57:20 +0100 | [diff] [blame] | 769 | void tb_sw_set_unplugged(struct tb_switch *sw); |
Mika Westerberg | 386e5e2 | 2019-12-17 15:33:37 +0300 | [diff] [blame] | 770 | struct tb_port *tb_switch_find_port(struct tb_switch *sw, |
| 771 | enum tb_port_type type); |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 772 | struct tb_switch *tb_switch_find_by_link_depth(struct tb *tb, u8 link, |
| 773 | u8 depth); |
Christoph Hellwig | 7c39ffe | 2017-07-18 15:30:05 +0200 | [diff] [blame] | 774 | struct tb_switch *tb_switch_find_by_uuid(struct tb *tb, const uuid_t *uuid); |
Radion Mirchevsky | 8e9267b | 2017-10-04 15:24:14 +0300 | [diff] [blame] | 775 | struct tb_switch *tb_switch_find_by_route(struct tb *tb, u64 route); |
Mika Westerberg | f67cf49 | 2017-06-06 15:25:16 +0300 | [diff] [blame] | 776 | |
Mika Westerberg | b433d01 | 2019-09-30 14:07:22 +0300 | [diff] [blame] | 777 | /** |
| 778 | * tb_switch_for_each_port() - Iterate over each switch port |
| 779 | * @sw: Switch whose ports to iterate |
| 780 | * @p: Port used as iterator |
| 781 | * |
| 782 | * Iterates over each switch port skipping the control port (port %0). |
| 783 | */ |
| 784 | #define tb_switch_for_each_port(sw, p) \ |
| 785 | for ((p) = &(sw)->ports[1]; \ |
| 786 | (p) <= &(sw)->ports[(sw)->config.max_port_number]; (p)++) |
| 787 | |
Mika Westerberg | b6b0ea7 | 2017-10-04 15:19:20 +0300 | [diff] [blame] | 788 | static inline struct tb_switch *tb_switch_get(struct tb_switch *sw) |
| 789 | { |
| 790 | if (sw) |
| 791 | get_device(&sw->dev); |
| 792 | return sw; |
| 793 | } |
| 794 | |
Mika Westerberg | bfe778a | 2017-06-06 15:25:01 +0300 | [diff] [blame] | 795 | static inline void tb_switch_put(struct tb_switch *sw) |
| 796 | { |
| 797 | put_device(&sw->dev); |
| 798 | } |
| 799 | |
| 800 | static inline bool tb_is_switch(const struct device *dev) |
| 801 | { |
| 802 | return dev->type == &tb_switch_type; |
| 803 | } |
| 804 | |
| 805 | static inline struct tb_switch *tb_to_switch(struct device *dev) |
| 806 | { |
| 807 | if (tb_is_switch(dev)) |
| 808 | return container_of(dev, struct tb_switch, dev); |
| 809 | return NULL; |
| 810 | } |
| 811 | |
Mika Westerberg | 0414bec | 2017-02-19 23:43:26 +0200 | [diff] [blame] | 812 | static inline struct tb_switch *tb_switch_parent(struct tb_switch *sw) |
| 813 | { |
| 814 | return tb_to_switch(sw->dev.parent); |
| 815 | } |
| 816 | |
Mika Westerberg | 17a8f81 | 2019-10-08 16:42:47 +0300 | [diff] [blame] | 817 | static inline bool tb_switch_is_light_ridge(const struct tb_switch *sw) |
Mika Westerberg | 8b0110d | 2019-01-08 18:55:09 +0200 | [diff] [blame] | 818 | { |
Mika Westerberg | 35ee69e | 2020-07-25 10:40:47 +0300 | [diff] [blame] | 819 | return sw->config.vendor_id == PCI_VENDOR_ID_INTEL && |
| 820 | sw->config.device_id == PCI_DEVICE_ID_INTEL_LIGHT_RIDGE; |
Mika Westerberg | 8b0110d | 2019-01-08 18:55:09 +0200 | [diff] [blame] | 821 | } |
| 822 | |
Mika Westerberg | 17a8f81 | 2019-10-08 16:42:47 +0300 | [diff] [blame] | 823 | static inline bool tb_switch_is_eagle_ridge(const struct tb_switch *sw) |
Mika Westerberg | 8b0110d | 2019-01-08 18:55:09 +0200 | [diff] [blame] | 824 | { |
Mika Westerberg | 35ee69e | 2020-07-25 10:40:47 +0300 | [diff] [blame] | 825 | return sw->config.vendor_id == PCI_VENDOR_ID_INTEL && |
| 826 | sw->config.device_id == PCI_DEVICE_ID_INTEL_EAGLE_RIDGE; |
Mika Westerberg | 8b0110d | 2019-01-08 18:55:09 +0200 | [diff] [blame] | 827 | } |
| 828 | |
Mika Westerberg | 17a8f81 | 2019-10-08 16:42:47 +0300 | [diff] [blame] | 829 | static inline bool tb_switch_is_cactus_ridge(const struct tb_switch *sw) |
Mika Westerberg | 99cabbb | 2018-12-30 21:34:08 +0200 | [diff] [blame] | 830 | { |
Mika Westerberg | 35ee69e | 2020-07-25 10:40:47 +0300 | [diff] [blame] | 831 | if (sw->config.vendor_id == PCI_VENDOR_ID_INTEL) { |
| 832 | switch (sw->config.device_id) { |
| 833 | case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_2C: |
| 834 | case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C: |
| 835 | return true; |
| 836 | } |
Mika Westerberg | 99cabbb | 2018-12-30 21:34:08 +0200 | [diff] [blame] | 837 | } |
Mika Westerberg | 35ee69e | 2020-07-25 10:40:47 +0300 | [diff] [blame] | 838 | return false; |
Mika Westerberg | 99cabbb | 2018-12-30 21:34:08 +0200 | [diff] [blame] | 839 | } |
| 840 | |
Mika Westerberg | 17a8f81 | 2019-10-08 16:42:47 +0300 | [diff] [blame] | 841 | static inline bool tb_switch_is_falcon_ridge(const struct tb_switch *sw) |
Mika Westerberg | 99cabbb | 2018-12-30 21:34:08 +0200 | [diff] [blame] | 842 | { |
Mika Westerberg | 35ee69e | 2020-07-25 10:40:47 +0300 | [diff] [blame] | 843 | if (sw->config.vendor_id == PCI_VENDOR_ID_INTEL) { |
| 844 | switch (sw->config.device_id) { |
| 845 | case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE: |
| 846 | case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE: |
| 847 | return true; |
| 848 | } |
Mika Westerberg | 99cabbb | 2018-12-30 21:34:08 +0200 | [diff] [blame] | 849 | } |
Mika Westerberg | 35ee69e | 2020-07-25 10:40:47 +0300 | [diff] [blame] | 850 | return false; |
Mika Westerberg | 99cabbb | 2018-12-30 21:34:08 +0200 | [diff] [blame] | 851 | } |
| 852 | |
Mika Westerberg | 7bffd97e | 2019-03-22 15:16:53 +0200 | [diff] [blame] | 853 | static inline bool tb_switch_is_alpine_ridge(const struct tb_switch *sw) |
| 854 | { |
Mika Westerberg | 35ee69e | 2020-07-25 10:40:47 +0300 | [diff] [blame] | 855 | if (sw->config.vendor_id == PCI_VENDOR_ID_INTEL) { |
| 856 | switch (sw->config.device_id) { |
| 857 | case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE: |
| 858 | case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE: |
| 859 | case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE: |
| 860 | case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE: |
| 861 | return true; |
| 862 | } |
Mika Westerberg | 7bffd97e | 2019-03-22 15:16:53 +0200 | [diff] [blame] | 863 | } |
Mika Westerberg | 35ee69e | 2020-07-25 10:40:47 +0300 | [diff] [blame] | 864 | return false; |
Mika Westerberg | 7bffd97e | 2019-03-22 15:16:53 +0200 | [diff] [blame] | 865 | } |
| 866 | |
| 867 | static inline bool tb_switch_is_titan_ridge(const struct tb_switch *sw) |
| 868 | { |
Mika Westerberg | 35ee69e | 2020-07-25 10:40:47 +0300 | [diff] [blame] | 869 | if (sw->config.vendor_id == PCI_VENDOR_ID_INTEL) { |
| 870 | switch (sw->config.device_id) { |
| 871 | case PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE: |
| 872 | case PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE: |
| 873 | case PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE: |
| 874 | return true; |
| 875 | } |
Mika Westerberg | 7bffd97e | 2019-03-22 15:16:53 +0200 | [diff] [blame] | 876 | } |
Mika Westerberg | 35ee69e | 2020-07-25 10:40:47 +0300 | [diff] [blame] | 877 | return false; |
Mika Westerberg | 7bffd97e | 2019-03-22 15:16:53 +0200 | [diff] [blame] | 878 | } |
| 879 | |
Gil Fine | 8a90e4f | 2021-12-17 03:16:39 +0200 | [diff] [blame] | 880 | static inline bool tb_switch_is_tiger_lake(const struct tb_switch *sw) |
| 881 | { |
| 882 | if (sw->config.vendor_id == PCI_VENDOR_ID_INTEL) { |
| 883 | switch (sw->config.device_id) { |
| 884 | case PCI_DEVICE_ID_INTEL_TGL_NHI0: |
| 885 | case PCI_DEVICE_ID_INTEL_TGL_NHI1: |
| 886 | case PCI_DEVICE_ID_INTEL_TGL_H_NHI0: |
| 887 | case PCI_DEVICE_ID_INTEL_TGL_H_NHI1: |
| 888 | return true; |
| 889 | } |
| 890 | } |
| 891 | return false; |
| 892 | } |
| 893 | |
Mika Westerberg | f07a360 | 2019-06-25 15:10:01 +0300 | [diff] [blame] | 894 | /** |
Mika Westerberg | b040798 | 2019-12-17 15:33:40 +0300 | [diff] [blame] | 895 | * tb_switch_is_usb4() - Is the switch USB4 compliant |
| 896 | * @sw: Switch to check |
| 897 | * |
| 898 | * Returns true if the @sw is USB4 compliant router, false otherwise. |
| 899 | */ |
| 900 | static inline bool tb_switch_is_usb4(const struct tb_switch *sw) |
| 901 | { |
| 902 | return sw->config.thunderbolt_version == USB4_VERSION_1_0; |
| 903 | } |
| 904 | |
| 905 | /** |
Mika Westerberg | f07a360 | 2019-06-25 15:10:01 +0300 | [diff] [blame] | 906 | * tb_switch_is_icm() - Is the switch handled by ICM firmware |
| 907 | * @sw: Switch to check |
| 908 | * |
| 909 | * In case there is a need to differentiate whether ICM firmware or SW CM |
| 910 | * is handling @sw this function can be called. It is valid to call this |
| 911 | * after tb_switch_alloc() and tb_switch_configure() has been called |
| 912 | * (latter only for SW CM case). |
| 913 | */ |
| 914 | static inline bool tb_switch_is_icm(const struct tb_switch *sw) |
| 915 | { |
| 916 | return !sw->config.enabled; |
| 917 | } |
| 918 | |
Mika Westerberg | 91c0c12 | 2019-03-21 19:03:00 +0200 | [diff] [blame] | 919 | int tb_switch_lane_bonding_enable(struct tb_switch *sw); |
| 920 | void tb_switch_lane_bonding_disable(struct tb_switch *sw); |
Mika Westerberg | de46203 | 2020-04-02 14:50:52 +0300 | [diff] [blame] | 921 | int tb_switch_configure_link(struct tb_switch *sw); |
| 922 | void tb_switch_unconfigure_link(struct tb_switch *sw); |
Mika Westerberg | 91c0c12 | 2019-03-21 19:03:00 +0200 | [diff] [blame] | 923 | |
Mika Westerberg | 8afe909 | 2019-03-26 15:52:30 +0300 | [diff] [blame] | 924 | bool tb_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in); |
| 925 | int tb_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in); |
| 926 | void tb_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in); |
| 927 | |
Rajmohan Mani | cf29b9af | 2019-12-17 15:33:43 +0300 | [diff] [blame] | 928 | int tb_switch_tmu_init(struct tb_switch *sw); |
| 929 | int tb_switch_tmu_post_time(struct tb_switch *sw); |
| 930 | int tb_switch_tmu_disable(struct tb_switch *sw); |
| 931 | int tb_switch_tmu_enable(struct tb_switch *sw); |
Gil Fine | a28ec0e | 2021-12-17 03:16:38 +0200 | [diff] [blame] | 932 | void tb_switch_tmu_configure(struct tb_switch *sw, |
| 933 | enum tb_switch_tmu_rate rate, |
| 934 | bool unidirectional); |
| 935 | /** |
| 936 | * tb_switch_tmu_hifi_is_enabled() - Checks if the specified TMU mode is enabled |
| 937 | * @sw: Router whose TMU mode to check |
| 938 | * @unidirectional: If uni-directional (bi-directional otherwise) |
| 939 | * |
| 940 | * Return true if hardware TMU configuration matches the one passed in |
| 941 | * as parameter. That is HiFi and either uni-directional or bi-directional. |
| 942 | */ |
| 943 | static inline bool tb_switch_tmu_hifi_is_enabled(const struct tb_switch *sw, |
| 944 | bool unidirectional) |
Rajmohan Mani | cf29b9af | 2019-12-17 15:33:43 +0300 | [diff] [blame] | 945 | { |
| 946 | return sw->tmu.rate == TB_SWITCH_TMU_RATE_HIFI && |
Gil Fine | a28ec0e | 2021-12-17 03:16:38 +0200 | [diff] [blame] | 947 | sw->tmu.unidirectional == unidirectional; |
Rajmohan Mani | cf29b9af | 2019-12-17 15:33:43 +0300 | [diff] [blame] | 948 | } |
| 949 | |
Gil Fine | 8a90e4f | 2021-12-17 03:16:39 +0200 | [diff] [blame] | 950 | int tb_switch_enable_clx(struct tb_switch *sw, enum tb_clx clx); |
| 951 | int tb_switch_disable_clx(struct tb_switch *sw, enum tb_clx clx); |
| 952 | |
| 953 | /** |
| 954 | * tb_switch_is_clx_enabled() - Checks if the CLx is enabled |
| 955 | * @sw: Router to check the CLx state for |
| 956 | * |
| 957 | * Checks if the CLx is enabled on the router upstream link. |
| 958 | * Not applicable for a host router. |
| 959 | */ |
| 960 | static inline bool tb_switch_is_clx_enabled(const struct tb_switch *sw) |
| 961 | { |
| 962 | return sw->clx != TB_CLX_DISABLE; |
| 963 | } |
| 964 | |
| 965 | /** |
| 966 | * tb_switch_is_cl0s_enabled() - Checks if the CL0s is enabled |
| 967 | * @sw: Router to check for the CL0s |
| 968 | * |
| 969 | * Checks if the CL0s is enabled on the router upstream link. |
| 970 | * Not applicable for a host router. |
| 971 | */ |
| 972 | static inline bool tb_switch_is_cl0s_enabled(const struct tb_switch *sw) |
| 973 | { |
| 974 | return sw->clx == TB_CL0S; |
| 975 | } |
| 976 | |
Gil Fine | 43f977b | 2021-12-17 03:16:43 +0200 | [diff] [blame] | 977 | /** |
| 978 | * tb_switch_is_clx_supported() - Is CLx supported on this type of router |
| 979 | * @sw: The router to check CLx support for |
| 980 | */ |
| 981 | static inline bool tb_switch_is_clx_supported(const struct tb_switch *sw) |
| 982 | { |
| 983 | return tb_switch_is_usb4(sw) || tb_switch_is_titan_ridge(sw); |
| 984 | } |
| 985 | |
| 986 | int tb_switch_mask_clx_objections(struct tb_switch *sw); |
| 987 | |
| 988 | int tb_switch_pcie_l1_enable(struct tb_switch *sw); |
| 989 | |
Andreas Noever | 9da672a | 2014-06-03 22:04:05 +0200 | [diff] [blame] | 990 | int tb_wait_for_port(struct tb_port *port, bool wait_if_unplugged); |
Andreas Noever | 520b670 | 2014-06-03 22:04:07 +0200 | [diff] [blame] | 991 | int tb_port_add_nfc_credits(struct tb_port *port, int credits); |
| 992 | int tb_port_clear_counter(struct tb_port *port, int counter); |
Mika Westerberg | b040798 | 2019-12-17 15:33:40 +0300 | [diff] [blame] | 993 | int tb_port_unlock(struct tb_port *port); |
Mika Westerberg | 341d451 | 2020-02-21 12:11:54 +0200 | [diff] [blame] | 994 | int tb_port_enable(struct tb_port *port); |
| 995 | int tb_port_disable(struct tb_port *port); |
Mika Westerberg | 0b2863a | 2017-02-19 16:57:27 +0200 | [diff] [blame] | 996 | int tb_port_alloc_in_hopid(struct tb_port *port, int hopid, int max_hopid); |
| 997 | void tb_port_release_in_hopid(struct tb_port *port, int hopid); |
| 998 | int tb_port_alloc_out_hopid(struct tb_port *port, int hopid, int max_hopid); |
| 999 | void tb_port_release_out_hopid(struct tb_port *port, int hopid); |
Mika Westerberg | fb19fac | 2017-02-19 21:51:30 +0200 | [diff] [blame] | 1000 | struct tb_port *tb_next_port_on_path(struct tb_port *start, struct tb_port *end, |
| 1001 | struct tb_port *prev); |
Andreas Noever | 9da672a | 2014-06-03 22:04:05 +0200 | [diff] [blame] | 1002 | |
Mika Westerberg | 56ad3ae | 2021-03-10 13:34:12 +0200 | [diff] [blame] | 1003 | static inline bool tb_port_use_credit_allocation(const struct tb_port *port) |
| 1004 | { |
| 1005 | return tb_port_is_null(port) && port->sw->credit_allocation; |
| 1006 | } |
| 1007 | |
Mika Westerberg | c64c3f3 | 2020-04-29 17:07:59 +0300 | [diff] [blame] | 1008 | /** |
| 1009 | * tb_for_each_port_on_path() - Iterate over each port on path |
| 1010 | * @src: Source port |
| 1011 | * @dst: Destination port |
| 1012 | * @p: Port used as iterator |
| 1013 | * |
| 1014 | * Walks over each port on path from @src to @dst. |
| 1015 | */ |
| 1016 | #define tb_for_each_port_on_path(src, dst, p) \ |
| 1017 | for ((p) = tb_next_port_on_path((src), (dst), NULL); (p); \ |
| 1018 | (p) = tb_next_port_on_path((src), (dst), (p))) |
| 1019 | |
Mika Westerberg | 5b7b8c0 | 2020-05-08 12:41:34 +0300 | [diff] [blame] | 1020 | int tb_port_get_link_speed(struct tb_port *port); |
Isaac Hazan | 4210d50 | 2020-09-24 11:43:58 +0300 | [diff] [blame] | 1021 | int tb_port_get_link_width(struct tb_port *port); |
Isaac Hazan | 5cc0df9 | 2020-09-24 11:44:01 +0300 | [diff] [blame] | 1022 | int tb_port_state(struct tb_port *port); |
| 1023 | int tb_port_lane_bonding_enable(struct tb_port *port); |
| 1024 | void tb_port_lane_bonding_disable(struct tb_port *port); |
Mika Westerberg | e7051be | 2021-03-22 16:54:54 +0200 | [diff] [blame] | 1025 | int tb_port_wait_for_link_width(struct tb_port *port, int width, |
| 1026 | int timeout_msec); |
Mika Westerberg | 69fea37 | 2021-03-22 17:01:59 +0200 | [diff] [blame] | 1027 | int tb_port_update_credits(struct tb_port *port); |
Mika Westerberg | 5b7b8c0 | 2020-05-08 12:41:34 +0300 | [diff] [blame] | 1028 | |
Mika Westerberg | da2da04 | 2017-06-06 15:24:58 +0300 | [diff] [blame] | 1029 | int tb_switch_find_vse_cap(struct tb_switch *sw, enum tb_switch_vse_cap vsec); |
Rajmohan Mani | aa43a9d | 2019-12-17 15:33:42 +0300 | [diff] [blame] | 1030 | int tb_switch_find_cap(struct tb_switch *sw, enum tb_switch_cap cap); |
Mika Westerberg | 6de057e | 2020-06-29 20:21:07 +0300 | [diff] [blame] | 1031 | int tb_switch_next_cap(struct tb_switch *sw, unsigned int offset); |
Mika Westerberg | da2da04 | 2017-06-06 15:24:58 +0300 | [diff] [blame] | 1032 | int tb_port_find_cap(struct tb_port *port, enum tb_port_cap cap); |
Mika Westerberg | 3c8b228 | 2020-06-29 20:15:17 +0300 | [diff] [blame] | 1033 | int tb_port_next_cap(struct tb_port *port, unsigned int offset); |
Mika Westerberg | e78db6f | 2017-10-12 16:45:50 +0300 | [diff] [blame] | 1034 | bool tb_port_is_enabled(struct tb_port *port); |
Andreas Noever | e2b8785 | 2014-06-03 22:04:03 +0200 | [diff] [blame] | 1035 | |
Rajmohan Mani | e6f8185 | 2019-12-17 15:33:44 +0300 | [diff] [blame] | 1036 | bool tb_usb3_port_is_enabled(struct tb_port *port); |
| 1037 | int tb_usb3_port_enable(struct tb_port *port, bool enable); |
| 1038 | |
Mika Westerberg | 0414bec | 2017-02-19 23:43:26 +0200 | [diff] [blame] | 1039 | bool tb_pci_port_is_enabled(struct tb_port *port); |
Mika Westerberg | 93f36ad | 2017-02-19 13:48:29 +0200 | [diff] [blame] | 1040 | int tb_pci_port_enable(struct tb_port *port, bool enable); |
| 1041 | |
Mika Westerberg | 4f807e4 | 2018-09-17 16:30:49 +0300 | [diff] [blame] | 1042 | int tb_dp_port_hpd_is_active(struct tb_port *port); |
| 1043 | int tb_dp_port_hpd_clear(struct tb_port *port); |
| 1044 | int tb_dp_port_set_hops(struct tb_port *port, unsigned int video, |
| 1045 | unsigned int aux_tx, unsigned int aux_rx); |
| 1046 | bool tb_dp_port_is_enabled(struct tb_port *port); |
| 1047 | int tb_dp_port_enable(struct tb_port *port, bool enable); |
| 1048 | |
Mika Westerberg | 0414bec | 2017-02-19 23:43:26 +0200 | [diff] [blame] | 1049 | struct tb_path *tb_path_discover(struct tb_port *src, int src_hopid, |
| 1050 | struct tb_port *dst, int dst_hopid, |
Mika Westerberg | 43bddb2 | 2021-11-14 17:20:59 +0200 | [diff] [blame] | 1051 | struct tb_port **last, const char *name, |
| 1052 | bool alloc_hopid); |
Mika Westerberg | 8c7acaaf | 2017-02-19 22:11:41 +0200 | [diff] [blame] | 1053 | struct tb_path *tb_path_alloc(struct tb *tb, struct tb_port *src, int src_hopid, |
| 1054 | struct tb_port *dst, int dst_hopid, int link_nr, |
| 1055 | const char *name); |
Andreas Noever | 520b670 | 2014-06-03 22:04:07 +0200 | [diff] [blame] | 1056 | void tb_path_free(struct tb_path *path); |
| 1057 | int tb_path_activate(struct tb_path *path); |
| 1058 | void tb_path_deactivate(struct tb_path *path); |
| 1059 | bool tb_path_is_invalid(struct tb_path *path); |
Mika Westerberg | 0bd680c | 2020-03-24 14:44:13 +0200 | [diff] [blame] | 1060 | bool tb_path_port_on_path(const struct tb_path *path, |
| 1061 | const struct tb_port *port); |
Andreas Noever | 520b670 | 2014-06-03 22:04:07 +0200 | [diff] [blame] | 1062 | |
Mika Westerberg | 6ed541c | 2021-03-22 18:09:35 +0200 | [diff] [blame] | 1063 | /** |
| 1064 | * tb_path_for_each_hop() - Iterate over each hop on path |
| 1065 | * @path: Path whose hops to iterate |
| 1066 | * @hop: Hop used as iterator |
| 1067 | * |
| 1068 | * Iterates over each hop on path. |
| 1069 | */ |
| 1070 | #define tb_path_for_each_hop(path, hop) \ |
| 1071 | for ((hop) = &(path)->hops[0]; \ |
| 1072 | (hop) <= &(path)->hops[(path)->path_length - 1]; (hop)++) |
| 1073 | |
Andreas Noever | cd22e73 | 2014-06-12 23:11:46 +0200 | [diff] [blame] | 1074 | int tb_drom_read(struct tb_switch *sw); |
| 1075 | int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid); |
Andreas Noever | c90553b | 2014-06-03 22:04:11 +0200 | [diff] [blame] | 1076 | |
Mika Westerberg | a9be558 | 2019-01-09 16:42:12 +0200 | [diff] [blame] | 1077 | int tb_lc_read_uuid(struct tb_switch *sw, u32 *uuid); |
Mika Westerberg | e28178b | 2020-04-02 12:42:44 +0300 | [diff] [blame] | 1078 | int tb_lc_configure_port(struct tb_port *port); |
| 1079 | void tb_lc_unconfigure_port(struct tb_port *port); |
Mika Westerberg | 284652a | 2020-04-09 14:23:32 +0300 | [diff] [blame] | 1080 | int tb_lc_configure_xdomain(struct tb_port *port); |
| 1081 | void tb_lc_unconfigure_xdomain(struct tb_port *port); |
Mika Westerberg | fdb0887 | 2020-11-26 12:52:43 +0300 | [diff] [blame] | 1082 | int tb_lc_start_lane_initialization(struct tb_port *port); |
Gil Fine | 43f977b | 2021-12-17 03:16:43 +0200 | [diff] [blame] | 1083 | bool tb_lc_is_clx_supported(struct tb_port *port); |
Mika Westerberg | b2911a5 | 2019-12-06 18:36:07 +0200 | [diff] [blame] | 1084 | int tb_lc_set_wake(struct tb_switch *sw, unsigned int flags); |
Mika Westerberg | 5480dfc | 2019-01-09 17:25:43 +0200 | [diff] [blame] | 1085 | int tb_lc_set_sleep(struct tb_switch *sw); |
Mika Westerberg | 91c0c12 | 2019-03-21 19:03:00 +0200 | [diff] [blame] | 1086 | bool tb_lc_lane_bonding_possible(struct tb_switch *sw); |
Mika Westerberg | 8afe909 | 2019-03-26 15:52:30 +0300 | [diff] [blame] | 1087 | bool tb_lc_dp_sink_query(struct tb_switch *sw, struct tb_port *in); |
| 1088 | int tb_lc_dp_sink_alloc(struct tb_switch *sw, struct tb_port *in); |
| 1089 | int tb_lc_dp_sink_dealloc(struct tb_switch *sw, struct tb_port *in); |
Mario Limonciello | 1cb3629 | 2020-06-23 11:14:29 -0500 | [diff] [blame] | 1090 | int tb_lc_force_power(struct tb_switch *sw); |
Andreas Noever | a25c8b2 | 2014-06-03 22:04:02 +0200 | [diff] [blame] | 1091 | |
| 1092 | static inline int tb_route_length(u64 route) |
| 1093 | { |
| 1094 | return (fls64(route) + TB_ROUTE_SHIFT - 1) / TB_ROUTE_SHIFT; |
| 1095 | } |
| 1096 | |
Andreas Noever | 9da672a | 2014-06-03 22:04:05 +0200 | [diff] [blame] | 1097 | /** |
| 1098 | * tb_downstream_route() - get route to downstream switch |
| 1099 | * |
| 1100 | * Port must not be the upstream port (otherwise a loop is created). |
| 1101 | * |
| 1102 | * Return: Returns a route to the switch behind @port. |
| 1103 | */ |
| 1104 | static inline u64 tb_downstream_route(struct tb_port *port) |
| 1105 | { |
| 1106 | return tb_route(port->sw) |
| 1107 | | ((u64) port->port << (port->sw->config.depth * 8)); |
| 1108 | } |
| 1109 | |
Mika Westerberg | 5ca6768 | 2020-10-22 13:22:06 +0300 | [diff] [blame] | 1110 | bool tb_is_xdomain_enabled(void); |
Mika Westerberg | d1ff702 | 2017-10-02 13:38:34 +0300 | [diff] [blame] | 1111 | bool tb_xdomain_handle_request(struct tb *tb, enum tb_cfg_pkg_type type, |
| 1112 | const void *buf, size_t size); |
| 1113 | struct tb_xdomain *tb_xdomain_alloc(struct tb *tb, struct device *parent, |
| 1114 | u64 route, const uuid_t *local_uuid, |
| 1115 | const uuid_t *remote_uuid); |
| 1116 | void tb_xdomain_add(struct tb_xdomain *xd); |
| 1117 | void tb_xdomain_remove(struct tb_xdomain *xd); |
| 1118 | struct tb_xdomain *tb_xdomain_find_by_link_depth(struct tb *tb, u8 link, |
| 1119 | u8 depth); |
| 1120 | |
Rajmohan Mani | 3fb10ea | 2021-04-01 18:42:38 +0300 | [diff] [blame] | 1121 | int tb_retimer_scan(struct tb_port *port, bool add); |
Kranthi Kuntala | dacb128 | 2020-03-05 16:39:58 +0200 | [diff] [blame] | 1122 | void tb_retimer_remove_all(struct tb_port *port); |
| 1123 | |
| 1124 | static inline bool tb_is_retimer(const struct device *dev) |
| 1125 | { |
| 1126 | return dev->type == &tb_retimer_type; |
| 1127 | } |
| 1128 | |
| 1129 | static inline struct tb_retimer *tb_to_retimer(struct device *dev) |
| 1130 | { |
| 1131 | if (tb_is_retimer(dev)) |
| 1132 | return container_of(dev, struct tb_retimer, dev); |
| 1133 | return NULL; |
| 1134 | } |
| 1135 | |
Mika Westerberg | b040798 | 2019-12-17 15:33:40 +0300 | [diff] [blame] | 1136 | int usb4_switch_setup(struct tb_switch *sw); |
| 1137 | int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid); |
| 1138 | int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf, |
| 1139 | size_t size); |
Mika Westerberg | b040798 | 2019-12-17 15:33:40 +0300 | [diff] [blame] | 1140 | bool usb4_switch_lane_bonding_possible(struct tb_switch *sw); |
Mika Westerberg | b2911a5 | 2019-12-06 18:36:07 +0200 | [diff] [blame] | 1141 | int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags); |
Mika Westerberg | b040798 | 2019-12-17 15:33:40 +0300 | [diff] [blame] | 1142 | int usb4_switch_set_sleep(struct tb_switch *sw); |
| 1143 | int usb4_switch_nvm_sector_size(struct tb_switch *sw); |
| 1144 | int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf, |
| 1145 | size_t size); |
Mika Westerberg | 1cbf680 | 2021-04-12 15:25:08 +0300 | [diff] [blame] | 1146 | int usb4_switch_nvm_set_offset(struct tb_switch *sw, unsigned int address); |
Mika Westerberg | b040798 | 2019-12-17 15:33:40 +0300 | [diff] [blame] | 1147 | int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address, |
| 1148 | const void *buf, size_t size); |
| 1149 | int usb4_switch_nvm_authenticate(struct tb_switch *sw); |
Mika Westerberg | 661b194 | 2020-11-10 11:34:07 +0300 | [diff] [blame] | 1150 | int usb4_switch_nvm_authenticate_status(struct tb_switch *sw, u32 *status); |
Mika Westerberg | 56ad3ae | 2021-03-10 13:34:12 +0200 | [diff] [blame] | 1151 | int usb4_switch_credits_init(struct tb_switch *sw); |
Mika Westerberg | b040798 | 2019-12-17 15:33:40 +0300 | [diff] [blame] | 1152 | bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in); |
| 1153 | int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in); |
| 1154 | int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in); |
| 1155 | struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw, |
| 1156 | const struct tb_port *port); |
Rajmohan Mani | e6f8185 | 2019-12-17 15:33:44 +0300 | [diff] [blame] | 1157 | struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw, |
| 1158 | const struct tb_port *port); |
Mika Westerberg | cae5f51 | 2021-04-01 17:34:20 +0300 | [diff] [blame] | 1159 | int usb4_switch_add_ports(struct tb_switch *sw); |
| 1160 | void usb4_switch_remove_ports(struct tb_switch *sw); |
Mika Westerberg | b040798 | 2019-12-17 15:33:40 +0300 | [diff] [blame] | 1161 | |
| 1162 | int usb4_port_unlock(struct tb_port *port); |
Mika Westerberg | e28178b | 2020-04-02 12:42:44 +0300 | [diff] [blame] | 1163 | int usb4_port_configure(struct tb_port *port); |
| 1164 | void usb4_port_unconfigure(struct tb_port *port); |
Mika Westerberg | 284652a | 2020-04-09 14:23:32 +0300 | [diff] [blame] | 1165 | int usb4_port_configure_xdomain(struct tb_port *port); |
| 1166 | void usb4_port_unconfigure_xdomain(struct tb_port *port); |
Rajmohan Mani | 3406de7 | 2021-04-01 18:38:05 +0300 | [diff] [blame] | 1167 | int usb4_port_router_offline(struct tb_port *port); |
| 1168 | int usb4_port_router_online(struct tb_port *port); |
Rajmohan Mani | 02d1285 | 2020-03-05 16:33:46 +0200 | [diff] [blame] | 1169 | int usb4_port_enumerate_retimers(struct tb_port *port); |
Gil Fine | 8a90e4f | 2021-12-17 03:16:39 +0200 | [diff] [blame] | 1170 | bool usb4_port_clx_supported(struct tb_port *port); |
Rajmohan Mani | 02d1285 | 2020-03-05 16:33:46 +0200 | [diff] [blame] | 1171 | |
Rajmohan Mani | 3406de7 | 2021-04-01 18:38:05 +0300 | [diff] [blame] | 1172 | int usb4_port_retimer_set_inbound_sbtx(struct tb_port *port, u8 index); |
Rajmohan Mani | 02d1285 | 2020-03-05 16:33:46 +0200 | [diff] [blame] | 1173 | int usb4_port_retimer_read(struct tb_port *port, u8 index, u8 reg, void *buf, |
| 1174 | u8 size); |
| 1175 | int usb4_port_retimer_write(struct tb_port *port, u8 index, u8 reg, |
| 1176 | const void *buf, u8 size); |
| 1177 | int usb4_port_retimer_is_last(struct tb_port *port, u8 index); |
| 1178 | int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index); |
Rajmohan Mani | faa1c61 | 2021-04-12 15:29:16 +0300 | [diff] [blame] | 1179 | int usb4_port_retimer_nvm_set_offset(struct tb_port *port, u8 index, |
| 1180 | unsigned int address); |
Rajmohan Mani | 02d1285 | 2020-03-05 16:33:46 +0200 | [diff] [blame] | 1181 | int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index, |
| 1182 | unsigned int address, const void *buf, |
| 1183 | size_t size); |
| 1184 | int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index); |
| 1185 | int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index, |
| 1186 | u32 *status); |
| 1187 | int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index, |
| 1188 | unsigned int address, void *buf, size_t size); |
Mika Westerberg | 3b1d8d5 | 2020-02-21 23:14:41 +0200 | [diff] [blame] | 1189 | |
| 1190 | int usb4_usb3_port_max_link_rate(struct tb_port *port); |
| 1191 | int usb4_usb3_port_actual_link_rate(struct tb_port *port); |
| 1192 | int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw, |
| 1193 | int *downstream_bw); |
| 1194 | int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw, |
| 1195 | int *downstream_bw); |
| 1196 | int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw, |
| 1197 | int *downstream_bw); |
Mario Limonciello | 1cb3629 | 2020-06-23 11:14:29 -0500 | [diff] [blame] | 1198 | |
Mika Westerberg | cae5f51 | 2021-04-01 17:34:20 +0300 | [diff] [blame] | 1199 | static inline bool tb_is_usb4_port_device(const struct device *dev) |
| 1200 | { |
| 1201 | return dev->type == &usb4_port_device_type; |
| 1202 | } |
| 1203 | |
| 1204 | static inline struct usb4_port *tb_to_usb4_port_device(struct device *dev) |
| 1205 | { |
| 1206 | if (tb_is_usb4_port_device(dev)) |
| 1207 | return container_of(dev, struct usb4_port, dev); |
| 1208 | return NULL; |
| 1209 | } |
| 1210 | |
| 1211 | struct usb4_port *usb4_port_device_add(struct tb_port *port); |
| 1212 | void usb4_port_device_remove(struct usb4_port *usb4); |
Rajmohan Mani | 3fb10ea | 2021-04-01 18:42:38 +0300 | [diff] [blame] | 1213 | int usb4_port_device_resume(struct usb4_port *usb4); |
Mika Westerberg | cae5f51 | 2021-04-01 17:34:20 +0300 | [diff] [blame] | 1214 | |
Mika Westerberg | 810278d | 2020-08-26 08:58:29 +0300 | [diff] [blame] | 1215 | /* Keep link controller awake during update */ |
Mario Limonciello | 1cb3629 | 2020-06-23 11:14:29 -0500 | [diff] [blame] | 1216 | #define QUIRK_FORCE_POWER_LINK_CONTROLLER BIT(0) |
| 1217 | |
| 1218 | void tb_check_quirks(struct tb_switch *sw); |
| 1219 | |
Mika Westerberg | b2be2b0 | 2019-04-02 15:26:00 +0300 | [diff] [blame] | 1220 | #ifdef CONFIG_ACPI |
| 1221 | void tb_acpi_add_links(struct tb_nhi *nhi); |
Mika Westerberg | c6da62a | 2020-02-18 16:14:42 +0200 | [diff] [blame] | 1222 | |
| 1223 | bool tb_acpi_is_native(void); |
| 1224 | bool tb_acpi_may_tunnel_usb3(void); |
| 1225 | bool tb_acpi_may_tunnel_dp(void); |
| 1226 | bool tb_acpi_may_tunnel_pcie(void); |
| 1227 | bool tb_acpi_is_xdomain_allowed(void); |
Rajmohan Mani | ccc5cb8 | 2021-04-01 18:20:17 +0300 | [diff] [blame] | 1228 | |
| 1229 | int tb_acpi_init(void); |
| 1230 | void tb_acpi_exit(void); |
| 1231 | int tb_acpi_power_on_retimers(struct tb_port *port); |
| 1232 | int tb_acpi_power_off_retimers(struct tb_port *port); |
Mika Westerberg | b2be2b0 | 2019-04-02 15:26:00 +0300 | [diff] [blame] | 1233 | #else |
| 1234 | static inline void tb_acpi_add_links(struct tb_nhi *nhi) { } |
Mika Westerberg | c6da62a | 2020-02-18 16:14:42 +0200 | [diff] [blame] | 1235 | |
| 1236 | static inline bool tb_acpi_is_native(void) { return true; } |
| 1237 | static inline bool tb_acpi_may_tunnel_usb3(void) { return true; } |
| 1238 | static inline bool tb_acpi_may_tunnel_dp(void) { return true; } |
| 1239 | static inline bool tb_acpi_may_tunnel_pcie(void) { return true; } |
| 1240 | static inline bool tb_acpi_is_xdomain_allowed(void) { return true; } |
Rajmohan Mani | ccc5cb8 | 2021-04-01 18:20:17 +0300 | [diff] [blame] | 1241 | |
| 1242 | static inline int tb_acpi_init(void) { return 0; } |
| 1243 | static inline void tb_acpi_exit(void) { } |
| 1244 | static inline int tb_acpi_power_on_retimers(struct tb_port *port) { return 0; } |
| 1245 | static inline int tb_acpi_power_off_retimers(struct tb_port *port) { return 0; } |
Mika Westerberg | b2be2b0 | 2019-04-02 15:26:00 +0300 | [diff] [blame] | 1246 | #endif |
| 1247 | |
Gil Fine | 54e4181 | 2020-06-29 20:30:52 +0300 | [diff] [blame] | 1248 | #ifdef CONFIG_DEBUG_FS |
| 1249 | void tb_debugfs_init(void); |
| 1250 | void tb_debugfs_exit(void); |
| 1251 | void tb_switch_debugfs_init(struct tb_switch *sw); |
| 1252 | void tb_switch_debugfs_remove(struct tb_switch *sw); |
Mika Westerberg | 407ac93 | 2020-10-07 17:53:44 +0300 | [diff] [blame] | 1253 | void tb_service_debugfs_init(struct tb_service *svc); |
| 1254 | void tb_service_debugfs_remove(struct tb_service *svc); |
Gil Fine | 54e4181 | 2020-06-29 20:30:52 +0300 | [diff] [blame] | 1255 | #else |
| 1256 | static inline void tb_debugfs_init(void) { } |
| 1257 | static inline void tb_debugfs_exit(void) { } |
| 1258 | static inline void tb_switch_debugfs_init(struct tb_switch *sw) { } |
| 1259 | static inline void tb_switch_debugfs_remove(struct tb_switch *sw) { } |
Mika Westerberg | 407ac93 | 2020-10-07 17:53:44 +0300 | [diff] [blame] | 1260 | static inline void tb_service_debugfs_init(struct tb_service *svc) { } |
| 1261 | static inline void tb_service_debugfs_remove(struct tb_service *svc) { } |
Gil Fine | 54e4181 | 2020-06-29 20:30:52 +0300 | [diff] [blame] | 1262 | #endif |
| 1263 | |
Mika Westerberg | 2c6ea4e | 2020-08-24 12:46:52 +0300 | [diff] [blame] | 1264 | #ifdef CONFIG_USB4_KUNIT_TEST |
| 1265 | int tb_test_init(void); |
| 1266 | void tb_test_exit(void); |
| 1267 | #else |
| 1268 | static inline int tb_test_init(void) { return 0; } |
| 1269 | static inline void tb_test_exit(void) { } |
| 1270 | #endif |
| 1271 | |
Andreas Noever | d6cc51c | 2014-06-03 22:04:00 +0200 | [diff] [blame] | 1272 | #endif |