blob: 2d5c57e3782d187b19ab598e5df7f9b391e43e3a [file] [log] [blame]
Sandeep Singh4f567b92020-10-10 01:31:36 +05301/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * AMD MP2 PCIe communication driver
4 * Copyright 2020 Advanced Micro Devices, Inc.
5 * Authors: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
6 * Sandeep Singh <Sandeep.singh@amd.com>
7 */
8
9#ifndef PCIE_MP2_AMD_H
10#define PCIE_MP2_AMD_H
11
12#include <linux/pci.h>
Basavaraj Natikar0aad9c92021-06-18 13:48:37 +053013#include "amd_sfh_hid.h"
Sandeep Singh4f567b92020-10-10 01:31:36 +053014
15#define PCI_DEVICE_ID_AMD_MP2 0x15E4
16
17#define ENABLE_SENSOR 1
18#define DISABLE_SENSOR 2
19#define STOP_ALL_SENSORS 8
20
21/* MP2 C2P Message Registers */
22#define AMD_C2P_MSG0 0x10500
23#define AMD_C2P_MSG1 0x10504
24#define AMD_C2P_MSG2 0x10508
25
Basavaraj Natikarf2644812021-06-18 13:48:36 +053026#define AMD_C2P_MSG(regno) (0x10500 + ((regno) * 4))
27
Sandeep Singh4f567b92020-10-10 01:31:36 +053028/* MP2 P2C Message Registers */
29#define AMD_P2C_MSG3 0x1068C /* Supported Sensors info */
30
Basavaraj Natikarf2644812021-06-18 13:48:36 +053031#define V2_STATUS 0x2
32
Basavaraj Natikar24a31ea2021-06-18 13:48:38 +053033#define HPD_IDX 16
34
Sandeep Singh4f567b92020-10-10 01:31:36 +053035/* SFH Command register */
36union sfh_cmd_base {
37 u32 ul;
38 struct {
39 u32 cmd_id : 8;
40 u32 sensor_id : 8;
41 u32 period : 16;
42 } s;
Basavaraj Natikarf2644812021-06-18 13:48:36 +053043 struct {
44 u32 cmd_id : 4;
45 u32 intr_enable : 1;
46 u32 rsvd1 : 3;
47 u32 length : 7;
48 u32 mem_type : 1;
49 u32 sensor_id : 8;
50 u32 period : 8;
51 } cmd_v2;
Sandeep Singh4f567b92020-10-10 01:31:36 +053052};
53
54union sfh_cmd_param {
55 u32 ul;
56 struct {
57 u32 buf_layout : 2;
58 u32 buf_length : 6;
59 u32 rsvd : 24;
60 } s;
61};
62
63struct sfh_cmd_reg {
64 union sfh_cmd_base cmd_base;
65 union sfh_cmd_param cmd_param;
66 phys_addr_t phys_addr;
67};
68
69enum sensor_idx {
70 accel_idx = 0,
71 gyro_idx = 1,
72 mag_idx = 2,
73 als_idx = 19
74};
75
76struct amd_mp2_dev {
77 struct pci_dev *pdev;
78 struct amdtp_cl_data *cl_data;
79 void __iomem *mmio;
Basavaraj Natikarf2644812021-06-18 13:48:36 +053080 const struct amd_mp2_ops *mp2_ops;
Basavaraj Natikar0aad9c92021-06-18 13:48:37 +053081 struct amd_input_data in_data;
Basavaraj Natikarf2644812021-06-18 13:48:36 +053082 /* mp2 active control status */
83 u32 mp2_acs;
Sandeep Singh4f567b92020-10-10 01:31:36 +053084};
85
86struct amd_mp2_sensor_info {
87 u8 sensor_idx;
88 u32 period;
Arnd Bergmannde304912021-01-03 14:53:55 +010089 dma_addr_t dma_address;
Sandeep Singh4f567b92020-10-10 01:31:36 +053090};
91
Basavaraj Natikarf2644812021-06-18 13:48:36 +053092enum mem_use_type {
93 USE_DRAM,
94 USE_C2P_REG,
95};
96
Basavaraj Natikar24a31ea2021-06-18 13:48:38 +053097struct hpd_status {
98 union {
99 struct {
100 u32 human_presence_report : 4;
101 u32 human_presence_actual : 4;
102 u32 probablity : 8;
103 u32 object_distance : 16;
104 } shpd;
105 u32 val;
106 };
107};
108
Sandeep Singh4f567b92020-10-10 01:31:36 +0530109void amd_start_sensor(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info);
110void amd_stop_sensor(struct amd_mp2_dev *privdata, u16 sensor_idx);
111void amd_stop_all_sensors(struct amd_mp2_dev *privdata);
112int amd_mp2_get_sensor_num(struct amd_mp2_dev *privdata, u8 *sensor_id);
113int amd_sfh_hid_client_init(struct amd_mp2_dev *privdata);
114int amd_sfh_hid_client_deinit(struct amd_mp2_dev *privdata);
Basavaraj Natikarf2644812021-06-18 13:48:36 +0530115
116struct amd_mp2_ops {
117 void (*start)(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info);
118 void (*stop)(struct amd_mp2_dev *privdata, u16 sensor_idx);
119 void (*stop_all)(struct amd_mp2_dev *privdata);
120};
Sandeep Singh4f567b92020-10-10 01:31:36 +0530121#endif