Blame - drivers/reset/Kconfig - SHIFTPHONES/mainline/linux

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Thomas Gleixner	ec8f24b	2019-05-19 13:07:45 +0100	[diff] [blame]	1	# SPDX-License-Identifier: GPL-2.0-only
Philipp Zabel	61fc413	2012-11-19 17:23:13 +0100	[diff] [blame]	2	config ARCH_HAS_RESET_CONTROLLER
				3	bool
				4
				5	menuconfig RESET_CONTROLLER
				6	bool "Reset Controller Support"
				7	default y if ARCH_HAS_RESET_CONTROLLER
				8	help
				9	Generic Reset Controller support.
				10
				11	This framework is designed to abstract reset handling of devices
				12	via GPIOs or SoC-internal reset controller modules.
				13
				14	If unsure, say no.
Stephen Gallimore	e5d7607	2013-08-07 15:53:12 +0100	[diff] [blame]	15
Masahiro Yamada	998cd46	2016-05-03 15:29:52 +0900	[diff] [blame]	16	if RESET_CONTROLLER
				17
Thor Thayer	6270068	2017-02-22 11:10:17 -0600	[diff] [blame]	18	config RESET_A10SR
				19	tristate "Altera Arria10 System Resource Reset"
				20	depends on MFD_ALTERA_A10SR
				21	help
				22	This option enables support for the external reset functions for
				23	peripheral PHYs on the Altera Arria10 System Resource Chip.
				24
Philipp Zabel	e27b4a6	2016-07-28 15:30:08 +0200	[diff] [blame]	25	config RESET_ATH79
				26	bool "AR71xx Reset Driver" if COMPILE_TEST
				27	default ATH79
				28	help
				29	This enables the ATH79 reset controller driver that supports the
				30	AR71xx SoC reset controller.
				31
Eugeniy Paltsev	3763492	2017-09-14 17:28:42 +0300	[diff] [blame]	32	config RESET_AXS10X
				33	bool "AXS10x Reset Driver" if COMPILE_TEST
				34	default ARC_PLAT_AXS10X
				35	help
				36	This enables the reset controller driver for AXS10x.
				37
Álvaro Fernández Rojas	aac0254	2020-06-17 12:50:35 +0200	[diff] [blame]	38	config RESET_BCM6345
				39	bool "BCM6345 Reset Controller"
				40	depends on BMIPS_GENERIC \|\| COMPILE_TEST
				41	default BMIPS_GENERIC
				42	help
				43	This enables the reset controller driver for BCM6345 SoCs.
				44
Philipp Zabel	70d467e	2016-07-28 15:31:12 +0200	[diff] [blame]	45	config RESET_BERLIN
				46	bool "Berlin Reset Driver" if COMPILE_TEST
				47	default ARCH_BERLIN
				48	help
				49	This enables the reset controller driver for Marvell Berlin SoCs.
				50
Florian Fainelli	77750bc	2019-01-23 14:54:36 -0800	[diff] [blame]	51	config RESET_BRCMSTB
				52	tristate "Broadcom STB reset controller"
				53	depends on ARCH_BRCMSTB \|\| COMPILE_TEST
				54	default ARCH_BRCMSTB
				55	help
				56	This enables the reset controller driver for Broadcom STB SoCs using
				57	a SUN_TOP_CTRL_SW_INIT style controller.
				58
Jim Quinlan	4cf176e	2020-01-03 11:04:29 -0800	[diff] [blame]	59	config RESET_BRCMSTB_RESCAL
				60	bool "Broadcom STB RESCAL reset controller"
Brendan Higgins	7fbcc53	2020-01-27 15:53:53 -0800	[diff] [blame]	61	depends on HAS_IOMEM
Jim Quinlan	4cf176e	2020-01-03 11:04:29 -0800	[diff] [blame]	62	default ARCH_BRCMSTB \|\| COMPILE_TEST
				63	help
				64	This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
				65	BCM7216.
				66
Vineet Gupta	1354122	2017-08-31 11:06:07 -0700	[diff] [blame]	67	config RESET_HSDK
				68	bool "Synopsys HSDK Reset Driver"
Thomas Meyer	2d48a23	2017-09-09 06:02:46 +0200	[diff] [blame]	69	depends on HAS_IOMEM
Geert Uytterhoeven	544e3bf	2017-09-11 14:22:08 +0200	[diff] [blame]	70	depends on ARC_SOC_HSDK \|\| COMPILE_TEST
Eugeniy Paltsev	e0be864	2017-07-19 21:45:11 +0300	[diff] [blame]	71	help
Vineet Gupta	1354122	2017-08-31 11:06:07 -0700	[diff] [blame]	72	This enables the reset controller driver for HSDK board.
Eugeniy Paltsev	e0be864	2017-07-19 21:45:11 +0300	[diff] [blame]	73
Andrey Smirnov	abf9775	2017-02-21 08:13:31 -0800	[diff] [blame]	74	config RESET_IMX7
Anson Huang	a442abb	2020-07-20 22:21:59 +0800	[diff] [blame]	75	tristate "i.MX7/8 Reset Driver"
Masahiro Yamada	8fa5662	2018-03-06 20:15:11 +0900	[diff] [blame]	76	depends on HAS_IOMEM
Anson Huang	a442abb	2020-07-20 22:21:59 +0800	[diff] [blame]	77	depends on SOC_IMX7D \|\| (ARM64 && ARCH_MXC) \|\| COMPILE_TEST
				78	default y if SOC_IMX7D
Andrey Smirnov	abf9775	2017-02-21 08:13:31 -0800	[diff] [blame]	79	select MFD_SYSCON
				80	help
				81	This enables the reset controller driver for i.MX7 SoCs.
				82
Dilip Kota	c9aef21	2020-01-03 18:00:18 +0800	[diff] [blame]	83	config RESET_INTEL_GW
				84	bool "Intel Reset Controller Driver"
Brendan Higgins	b460e0a	2020-01-27 15:53:54 -0800	[diff] [blame]	85	depends on OF && HAS_IOMEM
Dilip Kota	c9aef21	2020-01-03 18:00:18 +0800	[diff] [blame]	86	select REGMAP_MMIO
				87	help
				88	This enables the reset controller driver for Intel Gateway SoCs.
				89	Say Y to control the reset signals provided by reset controller.
				90	Otherwise, say N.
				91
Damien Le Moal	5a2308d	2020-12-13 22:50:47 +0900	[diff] [blame]	92	config RESET_K210
				93	bool "Reset controller driver for Canaan Kendryte K210 SoC"
				94	depends on (SOC_CANAAN \|\| COMPILE_TEST) && OF
				95	select MFD_SYSCON
				96	default SOC_CANAAN
				97	help
				98	Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
				99	Say Y if you want to control reset signals provided by this
				100	controller.
				101
Martin Blumenstingl	79797b6	2017-08-20 00:18:17 +0200	[diff] [blame]	102	config RESET_LANTIQ
				103	bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
				104	default SOC_TYPE_XWAY
				105	help
				106	This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
				107
Philipp Zabel	cd7f4b8	2016-07-28 15:32:01 +0200	[diff] [blame]	108	config RESET_LPC18XX
				109	bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
				110	default ARCH_LPC18XX
				111	help
				112	This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
				113
Philipp Zabel	44336c2	2016-07-28 15:32:36 +0200	[diff] [blame]	114	config RESET_MESON
Neil Armstrong	3bfe893	2020-10-19 16:48:09 +0200	[diff] [blame]	115	tristate "Meson Reset Driver"
				116	depends on ARCH_MESON \|\| COMPILE_TEST
Philipp Zabel	44336c2	2016-07-28 15:32:36 +0200	[diff] [blame]	117	default ARCH_MESON
				118	help
				119	This enables the reset driver for Amlogic Meson SoCs.
				120
Jerome Brunet	d903779	2018-07-20 17:26:33 +0200	[diff] [blame]	121	config RESET_MESON_AUDIO_ARB
				122	tristate "Meson Audio Memory Arbiter Reset Driver"
				123	depends on ARCH_MESON \|\| COMPILE_TEST
				124	help
				125	This enables the reset driver for Audio Memory Arbiter of
				126	Amlogic's A113 based SoCs
				127
Tomer Maimon	9c81b2c	2019-11-06 16:53:31 +0200	[diff] [blame]	128	config RESET_NPCM
				129	bool "NPCM BMC Reset Driver" if COMPILE_TEST
				130	default ARCH_NPCM
				131	help
				132	This enables the reset controller driver for Nuvoton NPCM
				133	BMC SoCs.
				134
Neil Armstrong	6e667fa	2016-04-01 16:16:13 +0200	[diff] [blame]	135	config RESET_OXNAS
				136	bool
				137
Philipp Zabel	fab3f73	2016-07-28 15:33:07 +0200	[diff] [blame]	138	config RESET_PISTACHIO
				139	bool "Pistachio Reset Driver" if COMPILE_TEST
				140	default MACH_PISTACHIO
				141	help
				142	This enables the reset driver for ImgTec Pistachio SoCs.
				143
Sibi Sankar	5ecb065	2018-06-27 19:54:43 +0530	[diff] [blame]	144	config RESET_QCOM_AOSS
John Stultz	e2d5e83	2020-01-08 00:19:13 +0000	[diff] [blame]	145	tristate "Qcom AOSS Reset Driver"
Sibi Sankar	5ecb065	2018-06-27 19:54:43 +0530	[diff] [blame]	146	depends on ARCH_QCOM \|\| COMPILE_TEST
				147	help
				148	This enables the AOSS (always on subsystem) reset driver
				149	for Qualcomm SDM845 SoCs. Say Y if you want to control
				150	reset signals provided by AOSS for Modem, Venus, ADSP,
				151	GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
				152
Sibi Sankar	eea2926	2018-08-30 00:42:11 +0530	[diff] [blame]	153	config RESET_QCOM_PDC
				154	tristate "Qualcomm PDC Reset Driver"
				155	depends on ARCH_QCOM \|\| COMPILE_TEST
				156	help
				157	This enables the PDC (Power Domain Controller) reset driver
				158	for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
				159	to control reset signals provided by PDC for Modem, Compute,
				160	Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
				161
Nicolas Saenz Julienne	abffc82	2020-06-29 18:18:38 +0200	[diff] [blame]	162	config RESET_RASPBERRYPI
				163	tristate "Raspberry Pi 4 Firmware Reset Driver"
				164	depends on RASPBERRYPI_FIRMWARE \|\| (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
				165	default USB_XHCI_PCI
				166	help
				167	Raspberry Pi 4's co-processor controls some of the board's HW
				168	initialization process, but it's up to Linux to trigger it when
				169	relevant. This driver provides a reset controller capable of
				170	interfacing with RPi4's co-processor and model these firmware
				171	initialization routines as reset lines.
				172
Sudeep Holla	c8ae9c2d	2019-07-08 09:41:08 +0100	[diff] [blame]	173	config RESET_SCMI
				174	tristate "Reset driver controlled via ARM SCMI interface"
				175	depends on ARM_SCMI_PROTOCOL \|\| COMPILE_TEST
				176	default ARM_SCMI_PROTOCOL
				177	help
				178	This driver provides support for reset signal/domains that are
				179	controlled by firmware that implements the SCMI interface.
				180
				181	This driver uses SCMI Message Protocol to interact with the
				182	firmware controlling all the reset signals.
				183
Philipp Zabel	81c22ad	2017-08-11 12:58:43 +0200	[diff] [blame]	184	config RESET_SIMPLE
				185	bool "Simple Reset Controller Driver" if COMPILE_TEST
Krzysztof Kozlowski	4a9a1a5	2021-03-11 16:25:38 +0100	[diff] [blame]	186	default ARCH_ASPEED \|\| ARCH_BCM4908 \|\| ARCH_BITMAIN \|\| ARCH_REALTEK \|\| ARCH_STM32 \|\| (ARCH_INTEL_SOCFPGA && ARM64) \|\| ARCH_SUNXI \|\| ARC
Philipp Zabel	81c22ad	2017-08-11 12:58:43 +0200	[diff] [blame]	187	help
				188	This enables a simple reset controller driver for reset lines that
				189	that can be asserted and deasserted by toggling bits in a contiguous,
				190	exclusive register space.
				191
Joel Stanley	1d7592f	2018-02-20 12:13:29 +1030	[diff] [blame]	192	Currently this driver supports:
				193	- Altera SoCFPGAs
				194	- ASPEED BMC SoCs
Andreas Färber	5ac33ee	2019-10-23 12:13:09 +0200	[diff] [blame]	195	- Bitmain BM1880 SoC
Andreas Färber	3ab831e	2019-10-23 12:13:10 +0200	[diff] [blame]	196	- Realtek SoCs
Joel Stanley	1d7592f	2018-02-20 12:13:29 +1030	[diff] [blame]	197	- RCC reset controller in STM32 MCUs
				198	- Allwinner SoCs
				199	- ZTE's zx2967 family
Greentime Hu	e4d368e	2021-05-04 18:59:36 +0800	[diff] [blame]	200	- SiFive FU740 SoCs
Philipp Zabel	7e0e901	2016-07-28 15:34:15 +0200	[diff] [blame]	201
Gabriel Fernandez	197858b	2018-03-19 08:25:51 +0100	[diff] [blame]	202	config RESET_STM32MP157
				203	bool "STM32MP157 Reset Driver" if COMPILE_TEST
				204	default MACH_STM32MP157
				205	help
				206	This enables the RCC reset controller driver for STM32 MPUs.
				207
Dinh Nguyen	b3ca988	2018-11-13 12:50:48 -0600	[diff] [blame]	208	config RESET_SOCFPGA
Krzysztof Kozlowski	225c13f	2021-03-11 16:27:41 +0100	[diff] [blame]	209	bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM \|\| !ARCH_INTEL_SOCFPGA)
				210	default ARM && ARCH_INTEL_SOCFPGA
Dinh Nguyen	b3ca988	2018-11-13 12:50:48 -0600	[diff] [blame]	211	select RESET_SIMPLE
				212	help
				213	This enables the reset driver for the SoCFPGA ARMv7 platforms. This
				214	driver gets initialized early during platform init calls.
				215
Philipp Zabel	0ae0841	2016-08-09 09:28:44 +0200	[diff] [blame]	216	config RESET_SUNXI
				217	bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
				218	default ARCH_SUNXI
Philipp Zabel	e13c205	2017-08-11 12:58:43 +0200	[diff] [blame]	219	select RESET_SIMPLE
Philipp Zabel	0ae0841	2016-08-09 09:28:44 +0200	[diff] [blame]	220	help
				221	This enables the reset driver for Allwinner SoCs.
				222
Andrew F. Davis	28df169	2017-05-24 13:09:30 -0500	[diff] [blame]	223	config RESET_TI_SCI
				224	tristate "TI System Control Interface (TI-SCI) reset driver"
				225	depends on TI_SCI_PROTOCOL
				226	help
				227	This enables the reset driver support over TI System Control Interface
				228	available on some new TI's SoCs. If you wish to use reset resources
				229	managed by the TI System Controller, say Y here. Otherwise, say N.
				230
Suman Anna	dd9bf86	2017-05-23 22:00:12 -0500	[diff] [blame]	231	config RESET_TI_SYSCON
Andrew F. Davis	cc7c2bb	2016-06-27 12:12:17 -0500	[diff] [blame]	232	tristate "TI SYSCON Reset Driver"
				233	depends on HAS_IOMEM
				234	select MFD_SYSCON
				235	help
				236	This enables the reset driver support for TI devices with
				237	memory-mapped reset registers as part of a syscon device node. If
				238	you wish to use the reset framework for such memory-mapped devices,
				239	say Y here. Otherwise, say N.
				240
Masahiro Yamada	54e991b	2016-08-02 13:18:29 +0900	[diff] [blame]	241	config RESET_UNIPHIER
				242	tristate "Reset controller driver for UniPhier SoCs"
				243	depends on ARCH_UNIPHIER \|\| COMPILE_TEST
				244	depends on OF && MFD_SYSCON
				245	default ARCH_UNIPHIER
				246	help
				247	Support for reset controllers on UniPhier SoCs.
				248	Say Y if you want to control reset signals provided by System Control
				249	block, Media I/O block, Peripheral Block.
				250
Kunihiko Hayashi	3eb8f76	2018-11-09 10:42:05 +0900	[diff] [blame]	251	config RESET_UNIPHIER_GLUE
				252	tristate "Reset driver in glue layer for UniPhier SoCs"
Kunihiko Hayashi	499fef0	2018-07-10 10:14:17 +0900	[diff] [blame]	253	depends on (ARCH_UNIPHIER \|\| COMPILE_TEST) && OF
				254	default ARCH_UNIPHIER
				255	select RESET_SIMPLE
				256	help
Kunihiko Hayashi	3eb8f76	2018-11-09 10:42:05 +0900	[diff] [blame]	257	Support for peripheral core reset included in its own glue layer
				258	on UniPhier SoCs. Say Y if you want to control reset signals
				259	provided by the glue layer.
Kunihiko Hayashi	499fef0	2018-07-10 10:14:17 +0900	[diff] [blame]	260
Philipp Zabel	6f51b86	2016-08-09 09:28:54 +0200	[diff] [blame]	261	config RESET_ZYNQ
				262	bool "ZYNQ Reset Driver" if COMPILE_TEST
				263	default ARCH_ZYNQ
				264	help
				265	This enables the reset controller driver for Xilinx Zynq SoCs.
				266
Stephen Gallimore	e5d7607	2013-08-07 15:53:12 +0100	[diff] [blame]	267	source "drivers/reset/sti/Kconfig"
Chen Feng	f59d23c	2015-11-20 10:10:05 +0800	[diff] [blame]	268	source "drivers/reset/hisilicon/Kconfig"
Thierry Reding	dc606c5	2016-08-18 15:50:09 +0200	[diff] [blame]	269	source "drivers/reset/tegra/Kconfig"
Masahiro Yamada	998cd46	2016-05-03 15:29:52 +0900	[diff] [blame]	270
				271	endif