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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 208e4ea61437930bbf8785c864ee7af1c693a561 / . / arch / arm / boot / dts / imx28.dtsi
blob: 2f4ebe0318d32cfa18c7a02f55dc59654d77ff99 [file] [log] [blame]
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
Michael Heimpold25fc2282014-03-27 23:51:29 +0100[diff] [blame]12#include <dt-bindings/gpio/gpio.h>
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]13#include "imx28-pinfunc.h"
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]14
15/ {
Fabio Estevam7f107882016-11-12 13:30:35 -0200[diff] [blame]16 #address-cells = <1>;
17 #size-cells = <1>;
18
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]19 interrupt-parent = <&icoll>;
Fabio Estevama971c552017-01-23 14:54:10 -0200[diff] [blame]20 /*
21 * The decompressor and also some bootloaders rely on a
22 * pre-existing /chosen node to be available to insert the
23 * command line and merge other ATAGS info.
24 * Also for U-Boot there must be a pre-existing /memory node.
25 */
26 chosen {};
27 memory { device_type = "memory"; reg = <0 0>; };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]28
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]29 aliases {
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]30 ethernet0 = &mac0;
31 ethernet1 = &mac1;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]32 gpio0 = &gpio0;
33 gpio1 = &gpio1;
34 gpio2 = &gpio2;
35 gpio3 = &gpio3;
36 gpio4 = &gpio4;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]37 saif0 = &saif0;
38 saif1 = &saif1;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]39 serial0 = &auart0;
40 serial1 = &auart1;
41 serial2 = &auart2;
42 serial3 = &auart3;
43 serial4 = &auart4;
Fabio Estevam6bf6eb02013-07-22 17:57:01 -0300[diff] [blame]44 spi0 = &ssp1;
45 spi1 = &ssp2;
Peter Chen1f35cc62013-12-20 15:52:05 +0800[diff] [blame]46 usbphy0 = &usbphy0;
47 usbphy1 = &usbphy1;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]48 };
49
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]50 cpus {
Fabio Estevamd447dd82016-11-16 13:15:38 -0200[diff] [blame]51 #address-cells = <1>;
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +0100[diff] [blame]52 #size-cells = <0>;
53
Fabio Estevamd447dd82016-11-16 13:15:38 -0200[diff] [blame]54 cpu@0 {
Lorenzo Pieralisi7925e892013-04-18 18:34:06 +0100[diff] [blame]55 compatible = "arm,arm926ej-s";
56 device_type = "cpu";
Fabio Estevamd447dd82016-11-16 13:15:38 -0200[diff] [blame]57 reg = <0>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]58 };
59 };
60
61 apb@80000000 {
62 compatible = "simple-bus";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 reg = <0x80000000 0x80000>;
66 ranges;
67
68 apbh@80000000 {
69 compatible = "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 reg = <0x80000000 0x3c900>;
73 ranges;
74
75 icoll: interrupt-controller@80000000 {
Shawn Guo83a84ef2012-08-20 21:34:56 +0800[diff] [blame]76 compatible = "fsl,imx28-icoll", "fsl,icoll";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]77 interrupt-controller;
78 #interrupt-cells = <1>;
79 reg = <0x80000000 0x2000>;
80 };
81
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]82 hsadc: hsadc@80002000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]83 reg = <0x80002000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]84 interrupts = <13>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]85 dmas = <&dma_apbh 12>;
86 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]87 status = "disabled";
88 };
89
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]90 dma_apbh: dma-apbh@80004000 {
Dong Aisheng84f35702012-05-04 20:12:19 +0800[diff] [blame]91 compatible = "fsl,imx28-dma-apbh";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]92 reg = <0x80004000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]93 interrupts = <82 83 84 85
94 88 88 88 88
95 88 88 88 88
96 87 86 0 0>;
97 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
98 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
99 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
100 "hsadc", "lcdif", "empty", "empty";
101 #dma-cells = <1>;
102 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]103 clocks = <&clks 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]104 };
105
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]106 perfmon: perfmon@80006000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]107 reg = <0x80006000 0x800>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]108 interrupts = <27>;
109 status = "disabled";
110 };
111
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]112 gpmi: gpmi-nand@8000c000 {
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]113 compatible = "fsl,imx28-gpmi-nand";
114 #address-cells = <1>;
115 #size-cells = <1>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]116 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]117 reg-names = "gpmi-nand", "bch";
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]118 interrupts = <41>;
119 interrupt-names = "bch";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]120 clocks = <&clks 50>;
Huang Shijieb6442552012-10-10 18:27:09 +0800[diff] [blame]121 clock-names = "gpmi_io";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]122 dmas = <&dma_apbh 4>;
123 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]124 status = "disabled";
125 };
126
127 ssp0: ssp@80010000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]128 #address-cells = <1>;
129 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]130 reg = <0x80010000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]131 interrupts = <96>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]132 clocks = <&clks 46>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]133 dmas = <&dma_apbh 0>;
134 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]135 status = "disabled";
136 };
137
138 ssp1: ssp@80012000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]139 #address-cells = <1>;
140 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]141 reg = <0x80012000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]142 interrupts = <97>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]143 clocks = <&clks 47>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]144 dmas = <&dma_apbh 1>;
145 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]146 status = "disabled";
147 };
148
149 ssp2: ssp@80014000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]150 #address-cells = <1>;
151 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]152 reg = <0x80014000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]153 interrupts = <98>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]154 clocks = <&clks 48>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]155 dmas = <&dma_apbh 2>;
156 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]157 status = "disabled";
158 };
159
160 ssp3: ssp@80016000 {
Maxime Ripard41bf5702012-09-04 10:44:02 +0200[diff] [blame]161 #address-cells = <1>;
162 #size-cells = <0>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]163 reg = <0x80016000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]164 interrupts = <99>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]165 clocks = <&clks 49>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]166 dmas = <&dma_apbh 3>;
167 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]168 status = "disabled";
169 };
170
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]171 pinctrl: pinctrl@80018000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]172 #address-cells = <1>;
173 #size-cells = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]174 compatible = "fsl,imx28-pinctrl", "simple-bus";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]175 reg = <0x80018000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]176
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]177 gpio0: gpio@0 {
178 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]179 reg = <0>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]180 interrupts = <127>;
181 gpio-controller;
182 #gpio-cells = <2>;
183 interrupt-controller;
184 #interrupt-cells = <2>;
185 };
186
187 gpio1: gpio@1 {
188 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]189 reg = <1>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]190 interrupts = <126>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 interrupt-controller;
194 #interrupt-cells = <2>;
195 };
196
197 gpio2: gpio@2 {
198 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]199 reg = <2>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]200 interrupts = <125>;
201 gpio-controller;
202 #gpio-cells = <2>;
203 interrupt-controller;
204 #interrupt-cells = <2>;
205 };
206
207 gpio3: gpio@3 {
208 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]209 reg = <3>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]210 interrupts = <124>;
211 gpio-controller;
212 #gpio-cells = <2>;
213 interrupt-controller;
214 #interrupt-cells = <2>;
215 };
216
217 gpio4: gpio@4 {
218 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
Stefan Wahrene57609a2016-06-05 13:49:27 +0000[diff] [blame]219 reg = <4>;
Shawn Guoce4c6f92012-05-04 14:32:35 +0800[diff] [blame]220 interrupts = <123>;
221 gpio-controller;
222 #gpio-cells = <2>;
223 interrupt-controller;
224 #interrupt-cells = <2>;
225 };
226
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]227 duart_pins_a: duart@0 {
228 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]229 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]230 MX28_PAD_PWM0__DUART_RX
231 MX28_PAD_PWM1__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]232 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]233 fsl,drive-strength = <MXS_DRIVE_4mA>;
234 fsl,voltage = <MXS_VOLTAGE_HIGH>;
235 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]236 };
237
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]238 duart_pins_b: duart@1 {
239 reg = <1>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]240 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]241 MX28_PAD_AUART0_CTS__DUART_RX
242 MX28_PAD_AUART0_RTS__DUART_TX
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]243 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]244 fsl,drive-strength = <MXS_DRIVE_4mA>;
245 fsl,voltage = <MXS_VOLTAGE_HIGH>;
246 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]247 };
248
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]249 duart_4pins_a: duart-4pins@0 {
250 reg = <0>;
251 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]252 MX28_PAD_AUART0_CTS__DUART_RX
253 MX28_PAD_AUART0_RTS__DUART_TX
254 MX28_PAD_AUART0_RX__DUART_CTS
255 MX28_PAD_AUART0_TX__DUART_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]256 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]257 fsl,drive-strength = <MXS_DRIVE_4mA>;
258 fsl,voltage = <MXS_VOLTAGE_HIGH>;
259 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]260 };
261
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]262 gpmi_pins_a: gpmi-nand@0 {
263 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]264 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]265 MX28_PAD_GPMI_D00__GPMI_D0
266 MX28_PAD_GPMI_D01__GPMI_D1
267 MX28_PAD_GPMI_D02__GPMI_D2
268 MX28_PAD_GPMI_D03__GPMI_D3
269 MX28_PAD_GPMI_D04__GPMI_D4
270 MX28_PAD_GPMI_D05__GPMI_D5
271 MX28_PAD_GPMI_D06__GPMI_D6
272 MX28_PAD_GPMI_D07__GPMI_D7
273 MX28_PAD_GPMI_CE0N__GPMI_CE0N
274 MX28_PAD_GPMI_RDY0__GPMI_READY0
275 MX28_PAD_GPMI_RDN__GPMI_RDN
276 MX28_PAD_GPMI_WRN__GPMI_WRN
277 MX28_PAD_GPMI_ALE__GPMI_ALE
278 MX28_PAD_GPMI_CLE__GPMI_CLE
279 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]280 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]281 fsl,drive-strength = <MXS_DRIVE_4mA>;
282 fsl,voltage = <MXS_VOLTAGE_HIGH>;
283 fsl,pull-up = <MXS_PULL_DISABLE>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]284 };
285
286 gpmi_status_cfg: gpmi-status-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]287 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]288 MX28_PAD_GPMI_RDN__GPMI_RDN
289 MX28_PAD_GPMI_WRN__GPMI_WRN
290 MX28_PAD_GPMI_RESETN__GPMI_RESETN
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]291 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]292 fsl,drive-strength = <MXS_DRIVE_12mA>;
Huang Shijie7a8e5142012-05-25 17:25:35 +0800[diff] [blame]293 };
294
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]295 auart0_pins_a: auart0@0 {
296 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]297 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]298 MX28_PAD_AUART0_RX__AUART0_RX
299 MX28_PAD_AUART0_TX__AUART0_TX
300 MX28_PAD_AUART0_CTS__AUART0_CTS
301 MX28_PAD_AUART0_RTS__AUART0_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]302 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]303 fsl,drive-strength = <MXS_DRIVE_4mA>;
304 fsl,voltage = <MXS_VOLTAGE_HIGH>;
305 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]306 };
307
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]308 auart0_2pins_a: auart0-2pins@0 {
309 reg = <0>;
310 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]311 MX28_PAD_AUART0_RX__AUART0_RX
312 MX28_PAD_AUART0_TX__AUART0_TX
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]313 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]314 fsl,drive-strength = <MXS_DRIVE_4mA>;
315 fsl,voltage = <MXS_VOLTAGE_HIGH>;
316 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasut8fa62e12012-07-07 21:21:38 +0800[diff] [blame]317 };
318
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]319 auart1_pins_a: auart1@0 {
320 reg = <0>;
321 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]322 MX28_PAD_AUART1_RX__AUART1_RX
323 MX28_PAD_AUART1_TX__AUART1_TX
324 MX28_PAD_AUART1_CTS__AUART1_CTS
325 MX28_PAD_AUART1_RTS__AUART1_RTS
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]326 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]327 fsl,drive-strength = <MXS_DRIVE_4mA>;
328 fsl,voltage = <MXS_VOLTAGE_HIGH>;
329 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]330 };
331
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]332 auart1_2pins_a: auart1-2pins@0 {
333 reg = <0>;
334 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]335 MX28_PAD_AUART1_RX__AUART1_RX
336 MX28_PAD_AUART1_TX__AUART1_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]337 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]338 fsl,drive-strength = <MXS_DRIVE_4mA>;
339 fsl,voltage = <MXS_VOLTAGE_HIGH>;
340 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]341 };
342
343 auart2_2pins_a: auart2-2pins@0 {
344 reg = <0>;
345 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]346 MX28_PAD_SSP2_SCK__AUART2_RX
347 MX28_PAD_SSP2_MOSI__AUART2_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]348 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]349 fsl,drive-strength = <MXS_DRIVE_4mA>;
350 fsl,voltage = <MXS_VOLTAGE_HIGH>;
351 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]352 };
353
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]354 auart2_2pins_b: auart2-2pins@1 {
355 reg = <1>;
356 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]357 MX28_PAD_AUART2_RX__AUART2_RX
358 MX28_PAD_AUART2_TX__AUART2_TX
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]359 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]360 fsl,drive-strength = <MXS_DRIVE_4mA>;
361 fsl,voltage = <MXS_VOLTAGE_HIGH>;
362 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénardf8040cf2013-04-08 14:57:31 +0200[diff] [blame]363 };
364
Aida Mynzhasovacd0214c2013-10-23 10:58:57 +0400[diff] [blame]365 auart2_pins_a: auart2-pins@0 {
366 reg = <0>;
367 fsl,pinmux-ids = <
368 MX28_PAD_AUART2_RX__AUART2_RX
369 MX28_PAD_AUART2_TX__AUART2_TX
370 MX28_PAD_AUART2_CTS__AUART2_CTS
371 MX28_PAD_AUART2_RTS__AUART2_RTS
372 >;
373 fsl,drive-strength = <MXS_DRIVE_4mA>;
374 fsl,voltage = <MXS_VOLTAGE_HIGH>;
375 fsl,pull-up = <MXS_PULL_DISABLE>;
376 };
377
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]378 auart3_pins_a: auart3@0 {
379 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]380 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]381 MX28_PAD_AUART3_RX__AUART3_RX
382 MX28_PAD_AUART3_TX__AUART3_TX
383 MX28_PAD_AUART3_CTS__AUART3_CTS
384 MX28_PAD_AUART3_RTS__AUART3_RTS
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]385 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]386 fsl,drive-strength = <MXS_DRIVE_4mA>;
387 fsl,voltage = <MXS_VOLTAGE_HIGH>;
388 fsl,pull-up = <MXS_PULL_DISABLE>;
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]389 };
390
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]391 auart3_2pins_a: auart3-2pins@0 {
392 reg = <0>;
393 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]394 MX28_PAD_SSP2_MISO__AUART3_RX
395 MX28_PAD_SSP2_SS0__AUART3_TX
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]396 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]397 fsl,drive-strength = <MXS_DRIVE_4mA>;
398 fsl,voltage = <MXS_VOLTAGE_HIGH>;
399 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo3143bbb2012-07-07 23:12:03 +0800[diff] [blame]400 };
401
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]402 auart3_2pins_b: auart3-2pins@1 {
403 reg = <1>;
404 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]405 MX28_PAD_AUART3_RX__AUART3_RX
406 MX28_PAD_AUART3_TX__AUART3_TX
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]407 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]408 fsl,drive-strength = <MXS_DRIVE_4mA>;
409 fsl,voltage = <MXS_VOLTAGE_HIGH>;
410 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard4812e742013-04-08 14:57:32 +0200[diff] [blame]411 };
412
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]413 auart4_2pins_a: auart4@0 {
414 reg = <0>;
415 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]416 MX28_PAD_SSP3_SCK__AUART4_TX
417 MX28_PAD_SSP3_MOSI__AUART4_RX
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]418 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]419 fsl,drive-strength = <MXS_DRIVE_4mA>;
420 fsl,voltage = <MXS_VOLTAGE_HIGH>;
421 fsl,pull-up = <MXS_PULL_DISABLE>;
Eric Bénard33678d12013-04-08 14:57:33 +0200[diff] [blame]422 };
423
Mans Rullgardcfa1dd92015-12-11 13:36:26 +0000[diff] [blame]424 auart4_2pins_b: auart4@1 {
425 reg = <1>;
426 fsl,pinmux-ids = <
427 MX28_PAD_AUART0_CTS__AUART4_RX
428 MX28_PAD_AUART0_RTS__AUART4_TX
429 >;
430 fsl,drive-strength = <MXS_DRIVE_4mA>;
431 fsl,voltage = <MXS_VOLTAGE_HIGH>;
432 fsl,pull-up = <MXS_PULL_DISABLE>;
433 };
434
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]435 mac0_pins_a: mac0@0 {
436 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]437 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]438 MX28_PAD_ENET0_MDC__ENET0_MDC
439 MX28_PAD_ENET0_MDIO__ENET0_MDIO
440 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
441 MX28_PAD_ENET0_RXD0__ENET0_RXD0
442 MX28_PAD_ENET0_RXD1__ENET0_RXD1
443 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
444 MX28_PAD_ENET0_TXD0__ENET0_TXD0
445 MX28_PAD_ENET0_TXD1__ENET0_TXD1
446 MX28_PAD_ENET_CLK__CLKCTRL_ENET
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]447 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]448 fsl,drive-strength = <MXS_DRIVE_8mA>;
449 fsl,voltage = <MXS_VOLTAGE_HIGH>;
450 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]451 };
452
Uwe Kleine-König9eb7db12016-04-06 09:32:59 +0200[diff] [blame]453 mac0_pins_b: mac0@1 {
454 reg = <1>;
455 fsl,pinmux-ids = <
456 MX28_PAD_ENET0_MDC__ENET0_MDC
457 MX28_PAD_ENET0_MDIO__ENET0_MDIO
458 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
459 MX28_PAD_ENET0_RXD0__ENET0_RXD0
460 MX28_PAD_ENET0_RXD1__ENET0_RXD1
461 MX28_PAD_ENET0_RXD2__ENET0_RXD2
462 MX28_PAD_ENET0_RXD3__ENET0_RXD3
463 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
464 MX28_PAD_ENET0_TXD0__ENET0_TXD0
465 MX28_PAD_ENET0_TXD1__ENET0_TXD1
466 MX28_PAD_ENET0_TXD2__ENET0_TXD2
467 MX28_PAD_ENET0_TXD3__ENET0_TXD3
468 MX28_PAD_ENET_CLK__CLKCTRL_ENET
469 MX28_PAD_ENET0_COL__ENET0_COL
470 MX28_PAD_ENET0_CRS__ENET0_CRS
471 MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
472 MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
473 >;
474 fsl,drive-strength = <MXS_DRIVE_8mA>;
475 fsl,voltage = <MXS_VOLTAGE_HIGH>;
476 fsl,pull-up = <MXS_PULL_ENABLE>;
477 };
478
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]479 mac1_pins_a: mac1@0 {
480 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]481 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]482 MX28_PAD_ENET0_CRS__ENET1_RX_EN
483 MX28_PAD_ENET0_RXD2__ENET1_RXD0
484 MX28_PAD_ENET0_RXD3__ENET1_RXD1
485 MX28_PAD_ENET0_COL__ENET1_TX_EN
486 MX28_PAD_ENET0_TXD2__ENET1_TXD0
487 MX28_PAD_ENET0_TXD3__ENET1_TXD1
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]488 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]489 fsl,drive-strength = <MXS_DRIVE_8mA>;
490 fsl,voltage = <MXS_VOLTAGE_HIGH>;
491 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]492 };
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]493
494 mmc0_8bit_pins_a: mmc0-8bit@0 {
495 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]496 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]497 MX28_PAD_SSP0_DATA0__SSP0_D0
498 MX28_PAD_SSP0_DATA1__SSP0_D1
499 MX28_PAD_SSP0_DATA2__SSP0_D2
500 MX28_PAD_SSP0_DATA3__SSP0_D3
501 MX28_PAD_SSP0_DATA4__SSP0_D4
502 MX28_PAD_SSP0_DATA5__SSP0_D5
503 MX28_PAD_SSP0_DATA6__SSP0_D6
504 MX28_PAD_SSP0_DATA7__SSP0_D7
505 MX28_PAD_SSP0_CMD__SSP0_CMD
506 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
507 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]508 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]509 fsl,drive-strength = <MXS_DRIVE_8mA>;
510 fsl,voltage = <MXS_VOLTAGE_HIGH>;
511 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]512 };
513
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]514 mmc0_4bit_pins_a: mmc0-4bit@0 {
515 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]516 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]517 MX28_PAD_SSP0_DATA0__SSP0_D0
518 MX28_PAD_SSP0_DATA1__SSP0_D1
519 MX28_PAD_SSP0_DATA2__SSP0_D2
520 MX28_PAD_SSP0_DATA3__SSP0_D3
521 MX28_PAD_SSP0_CMD__SSP0_CMD
522 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
523 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]524 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]525 fsl,drive-strength = <MXS_DRIVE_8mA>;
526 fsl,voltage = <MXS_VOLTAGE_HIGH>;
527 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard8385e7c2012-06-27 10:18:11 +0200[diff] [blame]528 };
529
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]530 mmc0_cd_cfg: mmc0-cd-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]531 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]532 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]533 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]534 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]535 };
536
537 mmc0_sck_cfg: mmc0-sck-cfg {
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]538 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]539 MX28_PAD_SSP0_SCK__SSP0_SCK
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]540 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]541 fsl,drive-strength = <MXS_DRIVE_12mA>;
542 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo35d23042012-05-06 16:33:34 +0800[diff] [blame]543 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]544
Marc Kleine-Budde77d63862014-08-08 11:24:21 +0200[diff] [blame]545 mmc1_4bit_pins_a: mmc1-4bit@0 {
546 reg = <0>;
547 fsl,pinmux-ids = <
548 MX28_PAD_GPMI_D00__SSP1_D0
549 MX28_PAD_GPMI_D01__SSP1_D1
550 MX28_PAD_GPMI_D02__SSP1_D2
551 MX28_PAD_GPMI_D03__SSP1_D3
552 MX28_PAD_GPMI_RDY1__SSP1_CMD
553 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
554 MX28_PAD_GPMI_WRN__SSP1_SCK
555 >;
556 fsl,drive-strength = <MXS_DRIVE_8mA>;
557 fsl,voltage = <MXS_VOLTAGE_HIGH>;
558 fsl,pull-up = <MXS_PULL_ENABLE>;
559 };
560
561 mmc1_cd_cfg: mmc1-cd-cfg {
562 fsl,pinmux-ids = <
563 MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
564 >;
565 fsl,pull-up = <MXS_PULL_DISABLE>;
566 };
567
568 mmc1_sck_cfg: mmc1-sck-cfg {
569 fsl,pinmux-ids = <
570 MX28_PAD_GPMI_WRN__SSP1_SCK
571 >;
572 fsl,drive-strength = <MXS_DRIVE_12mA>;
573 fsl,pull-up = <MXS_PULL_DISABLE>;
574 };
575
576
Marek Vasut5550e8e92013-09-26 13:16:16 +0200[diff] [blame]577 mmc2_4bit_pins_a: mmc2-4bit@0 {
578 reg = <0>;
579 fsl,pinmux-ids = <
580 MX28_PAD_SSP0_DATA4__SSP2_D0
581 MX28_PAD_SSP1_SCK__SSP2_D1
582 MX28_PAD_SSP1_CMD__SSP2_D2
583 MX28_PAD_SSP0_DATA5__SSP2_D3
584 MX28_PAD_SSP0_DATA6__SSP2_CMD
585 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
586 MX28_PAD_SSP0_DATA7__SSP2_SCK
587 >;
588 fsl,drive-strength = <MXS_DRIVE_8mA>;
589 fsl,voltage = <MXS_VOLTAGE_HIGH>;
590 fsl,pull-up = <MXS_PULL_ENABLE>;
591 };
592
Michael Heimpolddf937262017-02-09 08:42:41 +0100[diff] [blame]593 mmc2_4bit_pins_b: mmc2-4bit@1 {
594 reg = <1>;
595 fsl,pinmux-ids = <
596 MX28_PAD_SSP2_SCK__SSP2_SCK
597 MX28_PAD_SSP2_MOSI__SSP2_CMD
598 MX28_PAD_SSP2_MISO__SSP2_D0
599 MX28_PAD_SSP2_SS0__SSP2_D3
600 MX28_PAD_SSP2_SS1__SSP2_D1
601 MX28_PAD_SSP2_SS2__SSP2_D2
602 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
603 >;
604 fsl,drive-strength = <MXS_DRIVE_8mA>;
605 fsl,voltage = <MXS_VOLTAGE_HIGH>;
606 fsl,pull-up = <MXS_PULL_ENABLE>;
607 };
608
Marek Vasut5550e8e92013-09-26 13:16:16 +0200[diff] [blame]609 mmc2_cd_cfg: mmc2-cd-cfg {
610 fsl,pinmux-ids = <
611 MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
612 >;
613 fsl,pull-up = <MXS_PULL_DISABLE>;
614 };
615
Michael Heimpold45e89542017-02-09 08:42:42 +0100[diff] [blame]616 mmc2_sck_cfg_a: mmc2-sck-cfg@0 {
617 reg = <0>;
Marek Vasut5550e8e92013-09-26 13:16:16 +0200[diff] [blame]618 fsl,pinmux-ids = <
619 MX28_PAD_SSP0_DATA7__SSP2_SCK
620 >;
621 fsl,drive-strength = <MXS_DRIVE_12mA>;
622 fsl,pull-up = <MXS_PULL_DISABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]623 };
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]624
Michael Heimpold620885e2017-02-09 08:42:43 +0100[diff] [blame]625 mmc2_sck_cfg_b: mmc2-sck-cfg@1 {
626 reg = <1>;
627 fsl,pinmux-ids = <
628 MX28_PAD_SSP2_SCK__SSP2_SCK
629 >;
630 fsl,drive-strength = <MXS_DRIVE_12mA>;
631 fsl,pull-up = <MXS_PULL_DISABLE>;
632 };
633
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]634 i2c0_pins_a: i2c0@0 {
635 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]636 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]637 MX28_PAD_I2C0_SCL__I2C0_SCL
638 MX28_PAD_I2C0_SDA__I2C0_SDA
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]639 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]640 fsl,drive-strength = <MXS_DRIVE_8mA>;
641 fsl,voltage = <MXS_VOLTAGE_HIGH>;
642 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]643 };
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]644
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]645 i2c0_pins_b: i2c0@1 {
646 reg = <1>;
647 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]648 MX28_PAD_AUART0_RX__I2C0_SCL
649 MX28_PAD_AUART0_TX__I2C0_SDA
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]650 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]651 fsl,drive-strength = <MXS_DRIVE_8mA>;
652 fsl,voltage = <MXS_VOLTAGE_HIGH>;
653 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripard5c697ea2012-08-23 10:42:29 +0200[diff] [blame]654 };
655
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]656 i2c1_pins_a: i2c1@0 {
657 reg = <0>;
658 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]659 MX28_PAD_PWM0__I2C1_SCL
660 MX28_PAD_PWM1__I2C1_SDA
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]661 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]662 fsl,drive-strength = <MXS_DRIVE_8mA>;
663 fsl,voltage = <MXS_VOLTAGE_HIGH>;
664 fsl,pull-up = <MXS_PULL_ENABLE>;
Maxime Ripardde7e9342012-08-31 16:00:40 +0200[diff] [blame]665 };
666
Uwe Kleine-König17c63dd2014-08-08 11:24:22 +0200[diff] [blame]667 i2c1_pins_b: i2c1@1 {
668 reg = <1>;
669 fsl,pinmux-ids = <
670 MX28_PAD_AUART2_CTS__I2C1_SCL
671 MX28_PAD_AUART2_RTS__I2C1_SDA
672 >;
673 fsl,drive-strength = <MXS_DRIVE_8mA>;
674 fsl,voltage = <MXS_VOLTAGE_HIGH>;
675 fsl,pull-up = <MXS_PULL_ENABLE>;
676 };
677
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]678 saif0_pins_a: saif0@0 {
679 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]680 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]681 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
682 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
683 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
684 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]685 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]686 fsl,drive-strength = <MXS_DRIVE_12mA>;
687 fsl,voltage = <MXS_VOLTAGE_HIGH>;
688 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]689 };
690
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]691 saif0_pins_b: saif0@1 {
692 reg = <1>;
693 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]694 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
695 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
696 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]697 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]698 fsl,drive-strength = <MXS_DRIVE_12mA>;
699 fsl,voltage = <MXS_VOLTAGE_HIGH>;
700 fsl,pull-up = <MXS_PULL_ENABLE>;
Lothar Waßmann2e1dd9f2013-08-08 14:51:22 +0200[diff] [blame]701 };
702
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]703 saif1_pins_a: saif1@0 {
704 reg = <0>;
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]705 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]706 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
Shawn Guof14da762012-06-28 11:44:57 +0800[diff] [blame]707 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]708 fsl,drive-strength = <MXS_DRIVE_12mA>;
709 fsl,voltage = <MXS_VOLTAGE_HIGH>;
710 fsl,pull-up = <MXS_PULL_ENABLE>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]711 };
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]712
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]713 pwm0_pins_a: pwm0@0 {
714 reg = <0>;
715 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]716 MX28_PAD_PWM0__PWM_0
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]717 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]718 fsl,drive-strength = <MXS_DRIVE_4mA>;
719 fsl,voltage = <MXS_VOLTAGE_HIGH>;
720 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoe1a4d182012-07-09 12:34:35 +0800[diff] [blame]721 };
722
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]723 pwm2_pins_a: pwm2@0 {
724 reg = <0>;
725 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]726 MX28_PAD_PWM2__PWM_2
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]727 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]728 fsl,drive-strength = <MXS_DRIVE_4mA>;
729 fsl,voltage = <MXS_VOLTAGE_HIGH>;
730 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]731 };
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]732
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]733 pwm3_pins_a: pwm3@0 {
734 reg = <0>;
735 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]736 MX28_PAD_PWM3__PWM_3
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]737 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]738 fsl,drive-strength = <MXS_DRIVE_4mA>;
739 fsl,voltage = <MXS_VOLTAGE_HIGH>;
740 fsl,pull-up = <MXS_PULL_DISABLE>;
Julien Boibessot2bde51c2012-10-27 12:15:46 +0200[diff] [blame]741 };
742
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]743 pwm3_pins_b: pwm3@1 {
744 reg = <1>;
745 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]746 MX28_PAD_SAIF0_MCLK__PWM_3
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]747 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]748 fsl,drive-strength = <MXS_DRIVE_4mA>;
749 fsl,voltage = <MXS_VOLTAGE_HIGH>;
750 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripardd2486202013-01-25 09:54:06 +0100[diff] [blame]751 };
752
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]753 pwm4_pins_a: pwm4@0 {
754 reg = <0>;
755 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]756 MX28_PAD_PWM4__PWM_4
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]757 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]758 fsl,drive-strength = <MXS_DRIVE_4mA>;
759 fsl,voltage = <MXS_VOLTAGE_HIGH>;
760 fsl,pull-up = <MXS_PULL_DISABLE>;
Maxime Ripard2f442112012-08-23 10:42:30 +0200[diff] [blame]761 };
762
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]763 lcdif_24bit_pins_a: lcdif-24bit@0 {
764 reg = <0>;
765 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]766 MX28_PAD_LCD_D00__LCD_D0
767 MX28_PAD_LCD_D01__LCD_D1
768 MX28_PAD_LCD_D02__LCD_D2
769 MX28_PAD_LCD_D03__LCD_D3
770 MX28_PAD_LCD_D04__LCD_D4
771 MX28_PAD_LCD_D05__LCD_D5
772 MX28_PAD_LCD_D06__LCD_D6
773 MX28_PAD_LCD_D07__LCD_D7
774 MX28_PAD_LCD_D08__LCD_D8
775 MX28_PAD_LCD_D09__LCD_D9
776 MX28_PAD_LCD_D10__LCD_D10
777 MX28_PAD_LCD_D11__LCD_D11
778 MX28_PAD_LCD_D12__LCD_D12
779 MX28_PAD_LCD_D13__LCD_D13
780 MX28_PAD_LCD_D14__LCD_D14
781 MX28_PAD_LCD_D15__LCD_D15
782 MX28_PAD_LCD_D16__LCD_D16
783 MX28_PAD_LCD_D17__LCD_D17
784 MX28_PAD_LCD_D18__LCD_D18
785 MX28_PAD_LCD_D19__LCD_D19
786 MX28_PAD_LCD_D20__LCD_D20
787 MX28_PAD_LCD_D21__LCD_D21
788 MX28_PAD_LCD_D22__LCD_D22
789 MX28_PAD_LCD_D23__LCD_D23
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]790 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]791 fsl,drive-strength = <MXS_DRIVE_4mA>;
792 fsl,voltage = <MXS_VOLTAGE_HIGH>;
793 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]794 };
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]795
Denis Carikliec985eb2013-12-05 14:28:04 +0100[diff] [blame]796 lcdif_18bit_pins_a: lcdif-18bit@0 {
797 reg = <0>;
798 fsl,pinmux-ids = <
799 MX28_PAD_LCD_D00__LCD_D0
800 MX28_PAD_LCD_D01__LCD_D1
801 MX28_PAD_LCD_D02__LCD_D2
802 MX28_PAD_LCD_D03__LCD_D3
803 MX28_PAD_LCD_D04__LCD_D4
804 MX28_PAD_LCD_D05__LCD_D5
805 MX28_PAD_LCD_D06__LCD_D6
806 MX28_PAD_LCD_D07__LCD_D7
807 MX28_PAD_LCD_D08__LCD_D8
808 MX28_PAD_LCD_D09__LCD_D9
809 MX28_PAD_LCD_D10__LCD_D10
810 MX28_PAD_LCD_D11__LCD_D11
811 MX28_PAD_LCD_D12__LCD_D12
812 MX28_PAD_LCD_D13__LCD_D13
813 MX28_PAD_LCD_D14__LCD_D14
814 MX28_PAD_LCD_D15__LCD_D15
815 MX28_PAD_LCD_D16__LCD_D16
816 MX28_PAD_LCD_D17__LCD_D17
817 >;
818 fsl,drive-strength = <MXS_DRIVE_4mA>;
819 fsl,voltage = <MXS_VOLTAGE_HIGH>;
820 fsl,pull-up = <MXS_PULL_DISABLE>;
821 };
822
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]823 lcdif_16bit_pins_a: lcdif-16bit@0 {
824 reg = <0>;
825 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]826 MX28_PAD_LCD_D00__LCD_D0
827 MX28_PAD_LCD_D01__LCD_D1
828 MX28_PAD_LCD_D02__LCD_D2
829 MX28_PAD_LCD_D03__LCD_D3
830 MX28_PAD_LCD_D04__LCD_D4
831 MX28_PAD_LCD_D05__LCD_D5
832 MX28_PAD_LCD_D06__LCD_D6
833 MX28_PAD_LCD_D07__LCD_D7
834 MX28_PAD_LCD_D08__LCD_D8
835 MX28_PAD_LCD_D09__LCD_D9
836 MX28_PAD_LCD_D10__LCD_D10
837 MX28_PAD_LCD_D11__LCD_D11
838 MX28_PAD_LCD_D12__LCD_D12
839 MX28_PAD_LCD_D13__LCD_D13
840 MX28_PAD_LCD_D14__LCD_D14
841 MX28_PAD_LCD_D15__LCD_D15
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]842 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]843 fsl,drive-strength = <MXS_DRIVE_4mA>;
844 fsl,voltage = <MXS_VOLTAGE_HIGH>;
845 fsl,pull-up = <MXS_PULL_DISABLE>;
Gwenhael Goavec-Merou4ced2a42012-11-01 17:50:59 +0100[diff] [blame]846 };
847
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]848 lcdif_sync_pins_a: lcdif-sync@0 {
849 reg = <0>;
850 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]851 MX28_PAD_LCD_RS__LCD_DOTCLK
852 MX28_PAD_LCD_CS__LCD_ENABLE
853 MX28_PAD_LCD_RD_E__LCD_VSYNC
854 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]855 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]856 fsl,drive-strength = <MXS_DRIVE_4mA>;
857 fsl,voltage = <MXS_VOLTAGE_HIGH>;
858 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann23ad6f62013-08-08 14:51:24 +0200[diff] [blame]859 };
860
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]861 can0_pins_a: can0@0 {
862 reg = <0>;
863 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]864 MX28_PAD_GPMI_RDY2__CAN0_TX
865 MX28_PAD_GPMI_RDY3__CAN0_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]866 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]867 fsl,drive-strength = <MXS_DRIVE_4mA>;
868 fsl,voltage = <MXS_VOLTAGE_HIGH>;
869 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]870 };
871
872 can1_pins_a: can1@0 {
873 reg = <0>;
874 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]875 MX28_PAD_GPMI_CE2N__CAN1_TX
876 MX28_PAD_GPMI_CE3N__CAN1_RX
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]877 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]878 fsl,drive-strength = <MXS_DRIVE_4mA>;
879 fsl,voltage = <MXS_VOLTAGE_HIGH>;
880 fsl,pull-up = <MXS_PULL_DISABLE>;
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]881 };
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]882
883 spi2_pins_a: spi2@0 {
884 reg = <0>;
885 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]886 MX28_PAD_SSP2_SCK__SSP2_SCK
887 MX28_PAD_SSP2_MOSI__SSP2_CMD
888 MX28_PAD_SSP2_MISO__SSP2_D0
889 MX28_PAD_SSP2_SS0__SSP2_D3
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]890 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]891 fsl,drive-strength = <MXS_DRIVE_8mA>;
892 fsl,voltage = <MXS_VOLTAGE_HIGH>;
893 fsl,pull-up = <MXS_PULL_ENABLE>;
Marek Vasut7f122212012-08-25 01:51:37 +0200[diff] [blame]894 };
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]895
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]896 spi3_pins_a: spi3@0 {
897 reg = <0>;
898 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]899 MX28_PAD_AUART2_RX__SSP3_D4
900 MX28_PAD_AUART2_TX__SSP3_D5
901 MX28_PAD_SSP3_SCK__SSP3_SCK
902 MX28_PAD_SSP3_MOSI__SSP3_CMD
903 MX28_PAD_SSP3_MISO__SSP3_D0
904 MX28_PAD_SSP3_SS0__SSP3_D3
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]905 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]906 fsl,drive-strength = <MXS_DRIVE_8mA>;
907 fsl,voltage = <MXS_VOLTAGE_HIGH>;
908 fsl,pull-up = <MXS_PULL_DISABLE>;
Lothar Waßmann3314d2b2013-08-08 14:51:23 +0200[diff] [blame]909 };
910
Uwe Kleine-König8f0b07a2015-03-19 10:55:47 +0100[diff] [blame]911 spi3_pins_b: spi3@1 {
912 reg = <1>;
913 fsl,pinmux-ids = <
914 MX28_PAD_SSP3_SCK__SSP3_SCK
915 MX28_PAD_SSP3_MOSI__SSP3_CMD
916 MX28_PAD_SSP3_MISO__SSP3_D0
917 MX28_PAD_SSP3_SS0__SSP3_D3
918 >;
919 fsl,drive-strength = <MXS_DRIVE_8mA>;
920 fsl,voltage = <MXS_VOLTAGE_HIGH>;
921 fsl,pull-up = <MXS_PULL_ENABLE>;
922 };
923
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]924 usb0_pins_a: usb0@0 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]925 reg = <0>;
926 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]927 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]928 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]929 fsl,drive-strength = <MXS_DRIVE_12mA>;
930 fsl,voltage = <MXS_VOLTAGE_HIGH>;
931 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]932 };
933
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]934 usb0_pins_b: usb0@1 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]935 reg = <1>;
936 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]937 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]938 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]939 fsl,drive-strength = <MXS_DRIVE_12mA>;
940 fsl,voltage = <MXS_VOLTAGE_HIGH>;
941 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]942 };
943
Michael Grzeschikc8e42bc2013-12-06 15:56:40 +0100[diff] [blame]944 usb1_pins_a: usb1@0 {
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]945 reg = <0>;
946 fsl,pinmux-ids = <
Lothar Waßmannbc3875f2013-09-19 08:59:48 +0200[diff] [blame]947 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]948 >;
Lothar Waßmann4191c342013-09-22 14:02:59 +0800[diff] [blame]949 fsl,drive-strength = <MXS_DRIVE_12mA>;
950 fsl,voltage = <MXS_VOLTAGE_HIGH>;
951 fsl,pull-up = <MXS_PULL_DISABLE>;
Marek Vasutbb2f1262012-08-25 01:51:38 +0200[diff] [blame]952 };
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]953
954 usb0_id_pins_a: usb0id@0 {
955 reg = <0>;
956 fsl,pinmux-ids = <
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]957 MX28_PAD_AUART1_RTS__USB0_ID
Fabio Estevam69c02f92013-08-21 10:27:03 -0300[diff] [blame]958 >;
Lothar Waßmanne96e1782013-09-23 14:20:27 +0200[diff] [blame]959 fsl,drive-strength = <MXS_DRIVE_12mA>;
960 fsl,voltage = <MXS_VOLTAGE_HIGH>;
961 fsl,pull-up = <MXS_PULL_ENABLE>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]962 };
Denis Cariklibb89b8d2013-12-05 14:28:05 +0100[diff] [blame]963
964 usb0_id_pins_b: usb0id1@0 {
965 reg = <0>;
966 fsl,pinmux-ids = <
967 MX28_PAD_PWM2__USB0_ID
968 >;
969 fsl,drive-strength = <MXS_DRIVE_12mA>;
970 fsl,voltage = <MXS_VOLTAGE_HIGH>;
971 fsl,pull-up = <MXS_PULL_ENABLE>;
972 };
973
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]974 };
975
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]976 digctl: digctl@8001c000 {
Fabio Estevam115581c2013-06-04 10:18:44 -0300[diff] [blame]977 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]978 reg = <0x8001c000 0x2000>;
979 interrupts = <89>;
980 status = "disabled";
981 };
982
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]983 etm: etm@80022000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]984 reg = <0x80022000 0x2000>;
985 status = "disabled";
986 };
987
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]988 dma_apbx: dma-apbx@80024000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]989 compatible = "fsl,imx28-dma-apbx";
990 reg = <0x80024000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]991 interrupts = <78 79 66 0
992 80 81 68 69
993 70 71 72 73
994 74 75 76 77>;
Marek Vasut4ada77e2015-04-24 13:29:47 +0200[diff] [blame]995 interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]996 "saif0", "saif1", "i2c0", "i2c1",
997 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
998 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
999 #dma-cells = <1>;
1000 dma-channels = <16>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1001 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1002 };
1003
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1004 dcp: dcp@80028000 {
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]1005 compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1006 reg = <0x80028000 0x2000>;
1007 interrupts = <52 53 54>;
Marek Vasut7d56a282013-12-10 20:26:22 +0100[diff] [blame]1008 status = "okay";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1009 };
1010
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1011 pxp: pxp@8002a000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1012 reg = <0x8002a000 0x2000>;
1013 interrupts = <39>;
1014 status = "disabled";
1015 };
1016
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1017 ocotp: ocotp@8002c000 {
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000[diff] [blame]1018 compatible = "fsl,imx28-ocotp", "fsl,ocotp";
1019 #address-cells = <1>;
1020 #size-cells = <1>;
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1021 reg = <0x8002c000 0x2000>;
Stefan Wahrena7be1e62015-08-12 22:21:56 +0000[diff] [blame]1022 clocks = <&clks 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1023 };
1024
1025 axi-ahb@8002e000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1026 reg = <0x8002e000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1027 status = "disabled";
1028 };
1029
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1030 lcdif: lcdif@80030000 {
Shawn Guoa915ee42012-06-28 11:45:07 +0800[diff] [blame]1031 compatible = "fsl,imx28-lcdif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1032 reg = <0x80030000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1033 interrupts = <38>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1034 clocks = <&clks 55>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1035 dmas = <&dma_apbh 13>;
1036 dma-names = "rx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1037 status = "disabled";
1038 };
1039
1040 can0: can@80032000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]1041 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1042 reg = <0x80032000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1043 interrupts = <8>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1044 clocks = <&clks 58>, <&clks 58>;
1045 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1046 status = "disabled";
1047 };
1048
1049 can1: can@80034000 {
Shawn Guo6ca44ac2012-06-28 11:45:03 +0800[diff] [blame]1050 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1051 reg = <0x80034000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1052 interrupts = <9>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1053 clocks = <&clks 59>, <&clks 59>;
1054 clock-names = "ipg", "per";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1055 status = "disabled";
1056 };
1057
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1058 simdbg: simdbg@8003c000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1059 reg = <0x8003c000 0x200>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1060 status = "disabled";
1061 };
1062
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1063 simgpmisel: simgpmisel@8003c200 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1064 reg = <0x8003c200 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1065 status = "disabled";
1066 };
1067
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1068 simsspsel: simsspsel@8003c300 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1069 reg = <0x8003c300 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1070 status = "disabled";
1071 };
1072
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1073 simmemsel: simmemsel@8003c400 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1074 reg = <0x8003c400 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1075 status = "disabled";
1076 };
1077
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1078 gpiomon: gpiomon@8003c500 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1079 reg = <0x8003c500 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1080 status = "disabled";
1081 };
1082
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1083 simenet: simenet@8003c700 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1084 reg = <0x8003c700 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1085 status = "disabled";
1086 };
1087
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1088 armjtag: armjtag@8003c800 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1089 reg = <0x8003c800 0x100>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1090 status = "disabled";
1091 };
Lothar Waßmann07a3ce72013-08-08 14:51:20 +0200[diff] [blame]1092 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1093
1094 apbx@80040000 {
1095 compatible = "simple-bus";
1096 #address-cells = <1>;
1097 #size-cells = <1>;
1098 reg = <0x80040000 0x40000>;
1099 ranges;
1100
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1101 clks: clkctrl@80040000 {
Shawn Guo8f7cf882013-03-29 09:33:09 +0800[diff] [blame]1102 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1103 reg = <0x80040000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1104 #clock-cells = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1105 };
1106
1107 saif0: saif@80042000 {
Jörg Krause27767d62016-12-20 16:35:16 +0100[diff] [blame]1108 #sound-dai-cells = <0>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]1109 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1110 reg = <0x80042000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1111 interrupts = <59>;
Shawn Guo66acaf32013-07-01 15:46:05 +0800[diff] [blame]1112 #clock-cells = <0>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1113 clocks = <&clks 53>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1114 dmas = <&dma_apbx 4>;
1115 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1116 status = "disabled";
1117 };
1118
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1119 power: power@80044000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1120 reg = <0x80044000 0x2000>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1121 status = "disabled";
1122 };
1123
1124 saif1: saif@80046000 {
Jörg Krause27767d62016-12-20 16:35:16 +0100[diff] [blame]1125 #sound-dai-cells = <0>;
Shawn Guo530f1d42012-05-10 15:03:16 +0800[diff] [blame]1126 compatible = "fsl,imx28-saif";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1127 reg = <0x80046000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1128 interrupts = <58>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1129 clocks = <&clks 54>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1130 dmas = <&dma_apbx 5>;
1131 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1132 status = "disabled";
1133 };
1134
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1135 lradc: lradc@80050000 {
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]1136 compatible = "fsl,imx28-lradc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1137 reg = <0x80050000 0x2000>;
Marek Vasutaef35102012-08-17 10:42:52 +0800[diff] [blame]1138 interrupts = <10 14 15 16 17 18 19
1139 20 21 22 23 24 25>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1140 status = "disabled";
Juergen Beisert18da7552013-09-23 15:36:00 +0100[diff] [blame]1141 clocks = <&clks 41>;
Alexandre Belloni40dde682013-12-06 21:20:31 +0100[diff] [blame]1142 #io-channel-cells = <1>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1143 };
1144
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1145 spdif: spdif@80054000 {
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1146 reg = <0x80054000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1147 interrupts = <45>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1148 dmas = <&dma_apbx 2>;
1149 dma-names = "tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1150 status = "disabled";
1151 };
1152
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1153 mxs_rtc: rtc@80056000 {
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]1154 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1155 reg = <0x80056000 0x2000>;
Shawn Guof98c9902012-06-28 11:45:05 +0800[diff] [blame]1156 interrupts = <29>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1157 };
1158
1159 i2c0: i2c@80058000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]1160 #address-cells = <1>;
1161 #size-cells = <0>;
1162 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1163 reg = <0x80058000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1164 interrupts = <111>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]1165 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1166 dmas = <&dma_apbx 6>;
1167 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1168 status = "disabled";
1169 };
1170
1171 i2c1: i2c@8005a000 {
Shawn Guo2a96e392012-05-10 15:02:10 +0800[diff] [blame]1172 #address-cells = <1>;
1173 #size-cells = <0>;
1174 compatible = "fsl,imx28-i2c";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1175 reg = <0x8005a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1176 interrupts = <110>;
Marek Vasutcd4f2d42012-07-09 18:22:53 +0200[diff] [blame]1177 clock-frequency = <100000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1178 dmas = <&dma_apbx 7>;
1179 dma-names = "rx-tx";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1180 status = "disabled";
1181 };
1182
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]1183 pwm: pwm@80064000 {
1184 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1185 reg = <0x80064000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1186 clocks = <&clks 44>;
Shawn Guo52f71762012-06-28 11:45:06 +0800[diff] [blame]1187 #pwm-cells = <2>;
1188 fsl,pwm-number = <8>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1189 status = "disabled";
1190 };
1191
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1192 timer: timrot@80068000 {
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]1193 compatible = "fsl,imx28-timrot", "fsl,timrot";
Fabio Estevam0f06cde2012-07-30 21:29:19 -0300[diff] [blame]1194 reg = <0x80068000 0x2000>;
Shawn Guoeeca6e62012-08-20 08:51:45 +0800[diff] [blame]1195 interrupts = <48 49 50 51>;
Shawn Guo2efb9502013-03-25 22:57:14 +0800[diff] [blame]1196 clocks = <&clks 26>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1197 };
1198
1199 auart0: serial@8006a000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1200 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1201 reg = <0x8006a000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1202 interrupts = <112>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1203 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1204 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1205 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1206 status = "disabled";
1207 };
1208
1209 auart1: serial@8006c000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1210 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1211 reg = <0x8006c000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1212 interrupts = <113>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1213 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1214 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1215 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1216 status = "disabled";
1217 };
1218
1219 auart2: serial@8006e000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1220 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1221 reg = <0x8006e000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1222 interrupts = <114>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1223 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1224 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1225 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1226 status = "disabled";
1227 };
1228
1229 auart3: serial@80070000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1230 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1231 reg = <0x80070000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1232 interrupts = <115>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1233 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1234 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1235 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1236 status = "disabled";
1237 };
1238
1239 auart4: serial@80072000 {
Fabio Estevam80d969e2012-06-15 12:35:56 -0300[diff] [blame]1240 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1241 reg = <0x80072000 0x2000>;
Shawn Guo7f2b9282013-07-16 17:10:55 +0800[diff] [blame]1242 interrupts = <116>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]1243 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1244 dma-names = "rx", "tx";
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1245 clocks = <&clks 45>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1246 status = "disabled";
1247 };
1248
1249 duart: serial@80074000 {
1250 compatible = "arm,pl011", "arm,primecell";
1251 reg = <0x80074000 0x1000>;
1252 interrupts = <47>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1253 clocks = <&clks 45>, <&clks 26>;
1254 clock-names = "uart", "apb_pclk";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1255 status = "disabled";
1256 };
1257
1258 usbphy0: usbphy@8007c000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1259 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1260 reg = <0x8007c000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1261 clocks = <&clks 62>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1262 status = "disabled";
1263 };
1264
1265 usbphy1: usbphy@8007e000 {
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1266 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1267 reg = <0x8007e000 0x2000>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1268 clocks = <&clks 63>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1269 status = "disabled";
1270 };
1271 };
1272 };
1273
1274 ahb@80080000 {
1275 compatible = "simple-bus";
1276 #address-cells = <1>;
1277 #size-cells = <1>;
1278 reg = <0x80080000 0x80000>;
1279 ranges;
1280
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1281 usb0: usb@80080000 {
1282 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1283 reg = <0x80080000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1284 interrupts = <93>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1285 clocks = <&clks 60>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1286 fsl,usbphy = <&usbphy0>;
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1287 status = "disabled";
1288 };
1289
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1290 usb1: usb@80090000 {
1291 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1292 reg = <0x80090000 0x10000>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1293 interrupts = <92>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1294 clocks = <&clks 61>;
Richard Zhao5da01272012-07-12 10:25:27 +0800[diff] [blame]1295 fsl,usbphy = <&usbphy1>;
Matt Porter3ec481e2015-02-27 09:06:00 -0500[diff] [blame]1296 dr_mode = "host";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1297 status = "disabled";
1298 };
1299
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1300 dflpt: dflpt@800c0000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1301 reg = <0x800c0000 0x10000>;
1302 status = "disabled";
1303 };
1304
1305 mac0: ethernet@800f0000 {
1306 compatible = "fsl,imx28-fec";
1307 reg = <0x800f0000 0x4000>;
1308 interrupts = <101>;
Wolfram Sangf231a9f2013-01-29 15:46:12 +0100[diff] [blame]1309 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1310 clock-names = "ipg", "ahb", "enet_out";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1311 status = "disabled";
1312 };
1313
1314 mac1: ethernet@800f4000 {
1315 compatible = "fsl,imx28-fec";
1316 reg = <0x800f4000 0x4000>;
1317 interrupts = <102>;
Shawn Guob598b9f2012-08-22 21:36:29 +0800[diff] [blame]1318 clocks = <&clks 57>, <&clks 57>;
1319 clock-names = "ipg", "ahb";
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1320 status = "disabled";
1321 };
1322
Lothar Waßmann296f8cd2013-08-08 14:51:21 +0200[diff] [blame]1323 etn_switch: switch@800f8000 {
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1324 reg = <0x800f8000 0x8000>;
1325 status = "disabled";
1326 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1327 };
Alexandre Bellonif92dfb02013-12-18 19:50:55 +0100[diff] [blame]1328
Sanchayan Maity0b452cc2016-02-16 10:30:54 +0530[diff] [blame]1329 iio-hwmon {
Alexandre Bellonif92dfb02013-12-18 19:50:55 +0100[diff] [blame]1330 compatible = "iio-hwmon";
1331 io-channels = <&lradc 8>;
1332 };
Dong Aishengbc3a59c2012-03-31 21:26:57 +0800[diff] [blame]1333};