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Sascha Hauer9eb67f12015-04-23 10:35:43 +02001Mediatek topckgen controller
2============================
3
4The Mediatek topckgen controller provides various clocks to the system.
5
6Required Properties:
7
James Liao6a5887032016-08-19 13:34:50 +08008- compatible: Should be one of:
9 - "mediatek,mt2701-topckgen"
weiyi.lu@mediatek.comeb522df2017-10-23 12:10:32 +080010 - "mediatek,mt2712-topckgen", "syscon"
mtk01761171f68a2019-08-19 17:21:39 +080011 - "mediatek,mt6779-topckgen", "syscon"
Kevin-CW Chen2b51f512017-04-08 09:20:28 +080012 - "mediatek,mt6797-topckgen"
Sean Wang808ecf42017-10-05 11:50:22 +080013 - "mediatek,mt7622-topckgen"
Matthias Bruggerfd2a9f12018-10-03 11:09:09 +020014 - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
Ryder Lee0cd41af2018-11-05 16:43:56 +080015 - "mediatek,mt7629-topckgen"
Sascha Hauer9eb67f12015-04-23 10:35:43 +020016 - "mediatek,mt8135-topckgen"
17 - "mediatek,mt8173-topckgen"
Weiyi Lu2f41cd92019-03-05 13:05:41 +080018 - "mediatek,mt8183-topckgen", "syscon"
Fabien Parent67ea1512019-03-23 22:15:59 +010019 - "mediatek,mt8516-topckgen"
Sascha Hauer9eb67f12015-04-23 10:35:43 +020020- #clock-cells: Must be 1
21
22The topckgen controller uses the common clk binding from
23Documentation/devicetree/bindings/clock/clock-bindings.txt
24The available clocks are defined in dt-bindings/clock/mt*-clk.h.
25
26Example:
27
Sascha Hauerc4b6c262015-05-07 10:14:58 +020028topckgen: power-controller@10000000 {
Sascha Hauer9eb67f12015-04-23 10:35:43 +020029 compatible = "mediatek,mt8173-topckgen";
30 reg = <0 0x10000000 0 0x1000>;
31 #clock-cells = <1>;
32};