Sascha Hauer | 9eb67f1 | 2015-04-23 10:35:43 +0200 | [diff] [blame] | 1 | Mediatek topckgen controller |
| 2 | ============================ |
| 3 | |
| 4 | The Mediatek topckgen controller provides various clocks to the system. |
| 5 | |
| 6 | Required Properties: |
| 7 | |
James Liao | 6a588703 | 2016-08-19 13:34:50 +0800 | [diff] [blame] | 8 | - compatible: Should be one of: |
| 9 | - "mediatek,mt2701-topckgen" |
weiyi.lu@mediatek.com | eb522df | 2017-10-23 12:10:32 +0800 | [diff] [blame] | 10 | - "mediatek,mt2712-topckgen", "syscon" |
Kevin-CW Chen | 2b51f51 | 2017-04-08 09:20:28 +0800 | [diff] [blame] | 11 | - "mediatek,mt6797-topckgen" |
Sean Wang | 808ecf4 | 2017-10-05 11:50:22 +0800 | [diff] [blame^] | 12 | - "mediatek,mt7622-topckgen" |
Sascha Hauer | 9eb67f1 | 2015-04-23 10:35:43 +0200 | [diff] [blame] | 13 | - "mediatek,mt8135-topckgen" |
| 14 | - "mediatek,mt8173-topckgen" |
| 15 | - #clock-cells: Must be 1 |
| 16 | |
| 17 | The topckgen controller uses the common clk binding from |
| 18 | Documentation/devicetree/bindings/clock/clock-bindings.txt |
| 19 | The available clocks are defined in dt-bindings/clock/mt*-clk.h. |
| 20 | |
| 21 | Example: |
| 22 | |
Sascha Hauer | c4b6c26 | 2015-05-07 10:14:58 +0200 | [diff] [blame] | 23 | topckgen: power-controller@10000000 { |
Sascha Hauer | 9eb67f1 | 2015-04-23 10:35:43 +0200 | [diff] [blame] | 24 | compatible = "mediatek,mt8173-topckgen"; |
| 25 | reg = <0 0x10000000 0 0x1000>; |
| 26 | #clock-cells = <1>; |
| 27 | }; |