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Kumar Gala5516b542007-06-27 01:17:57 -05001/*
2 * Contains common pci routines for ALL ppc platform
Kumar Galacf1d8a82007-06-28 22:56:24 -05003 * (based on pci_32.c and pci_64.c)
4 *
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
7 *
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
10 *
11 * Common pmac/prep/chrp pci routines. -- Cort
Kumar Gala5516b542007-06-27 01:17:57 -050012 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18
Kumar Gala5516b542007-06-27 01:17:57 -050019#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
Paul Gortmaker66b15db2011-05-27 10:46:24 -040024#include <linux/export.h>
Grant Likely22ae7822010-07-29 11:49:01 -060025#include <linux/of_address.h>
Sebastian Andrzej Siewior04bea682011-01-24 09:58:55 +053026#include <linux/of_pci.h>
Kumar Gala5516b542007-06-27 01:17:57 -050027#include <linux/mm.h>
28#include <linux/list.h>
29#include <linux/syscalls.h>
30#include <linux/irq.h>
31#include <linux/vmalloc.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Kumar Gala5516b542007-06-27 01:17:57 -050033
34#include <asm/processor.h>
35#include <asm/io.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#include <asm/byteorder.h>
39#include <asm/machdep.h>
40#include <asm/ppc-pci.h>
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +000041#include <asm/eeh.h>
Kumar Gala5516b542007-06-27 01:17:57 -050042
Kumar Galaa4c9e322007-06-27 13:09:43 -050043static DEFINE_SPINLOCK(hose_spinlock);
Milton Millerc3bd5172009-01-08 02:19:46 +000044LIST_HEAD(hose_list);
Kumar Galaa4c9e322007-06-27 13:09:43 -050045
46/* XXX kill that some day ... */
Stephen Rothwellebfc00f2007-11-19 16:56:15 +110047static int global_phb_number; /* Global phb counter */
Kumar Galaa4c9e322007-06-27 13:09:43 -050048
Benjamin Herrenschmidt25e81f92007-12-11 14:48:17 +110049/* ISA Memory physical address */
50resource_size_t isa_mem_base;
51
Kumar Galaa4c9e322007-06-27 13:09:43 -050052
FUJITA Tomonori45223c52009-08-04 19:08:25 +000053static struct dma_map_ops *pci_dma_ops = &dma_direct_ops;
Becky Bruce4fc665b2008-09-12 10:34:46 +000054
FUJITA Tomonori45223c52009-08-04 19:08:25 +000055void set_pci_dma_ops(struct dma_map_ops *dma_ops)
Becky Bruce4fc665b2008-09-12 10:34:46 +000056{
57 pci_dma_ops = dma_ops;
58}
59
FUJITA Tomonori45223c52009-08-04 19:08:25 +000060struct dma_map_ops *get_pci_dma_ops(void)
Becky Bruce4fc665b2008-09-12 10:34:46 +000061{
62 return pci_dma_ops;
63}
64EXPORT_SYMBOL(get_pci_dma_ops);
65
Stephen Rothwelle60516e2007-12-11 11:02:07 +110066struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
Kumar Galaa4c9e322007-06-27 13:09:43 -050067{
68 struct pci_controller *phb;
69
Stephen Rothwelle60516e2007-12-11 11:02:07 +110070 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
Kumar Galaa4c9e322007-06-27 13:09:43 -050071 if (phb == NULL)
72 return NULL;
Stephen Rothwelle60516e2007-12-11 11:02:07 +110073 spin_lock(&hose_spinlock);
74 phb->global_number = global_phb_number++;
75 list_add_tail(&phb->list_node, &hose_list);
76 spin_unlock(&hose_spinlock);
Stephen Rothwell44ef3392007-12-10 14:33:21 +110077 phb->dn = dev;
Kumar Galaa4c9e322007-06-27 13:09:43 -050078 phb->is_dynamic = mem_init_done;
79#ifdef CONFIG_PPC64
80 if (dev) {
81 int nid = of_node_to_nid(dev);
82
83 if (nid < 0 || !node_online(nid))
84 nid = -1;
85
86 PHB_SET_NODE(phb, nid);
87 }
88#endif
89 return phb;
90}
91
92void pcibios_free_controller(struct pci_controller *phb)
93{
94 spin_lock(&hose_spinlock);
95 list_del(&phb->list_node);
96 spin_unlock(&hose_spinlock);
97
98 if (phb->is_dynamic)
99 kfree(phb);
100}
101
Gavin Shan4c2245b2012-09-11 16:59:46 -0600102/*
103 * The function is used to return the minimal alignment
104 * for memory or I/O windows of the associated P2P bridge.
105 * By default, 4KiB alignment for I/O windows and 1MiB for
106 * memory windows.
107 */
108resource_size_t pcibios_window_alignment(struct pci_bus *bus,
109 unsigned long type)
110{
111 if (ppc_md.pcibios_window_alignment)
112 return ppc_md.pcibios_window_alignment(bus, type);
113
114 /*
115 * PCI core will figure out the default
116 * alignment: 4KiB for I/O and 1MiB for
117 * memory window.
118 */
119 return 1;
120}
121
Milton Millerc3bd5172009-01-08 02:19:46 +0000122static resource_size_t pcibios_io_size(const struct pci_controller *hose)
123{
124#ifdef CONFIG_PPC64
125 return hose->pci_io_size;
126#else
Joe Perches28f65c112011-06-09 09:13:32 -0700127 return resource_size(&hose->io_resource);
Milton Millerc3bd5172009-01-08 02:19:46 +0000128#endif
129}
130
Benjamin Herrenschmidt6dfbde22007-07-26 14:07:13 +1000131int pcibios_vaddr_is_ioport(void __iomem *address)
132{
133 int ret = 0;
134 struct pci_controller *hose;
Milton Millerc3bd5172009-01-08 02:19:46 +0000135 resource_size_t size;
Benjamin Herrenschmidt6dfbde22007-07-26 14:07:13 +1000136
137 spin_lock(&hose_spinlock);
138 list_for_each_entry(hose, &hose_list, list_node) {
Milton Millerc3bd5172009-01-08 02:19:46 +0000139 size = pcibios_io_size(hose);
Benjamin Herrenschmidt6dfbde22007-07-26 14:07:13 +1000140 if (address >= hose->io_base_virt &&
141 address < (hose->io_base_virt + size)) {
142 ret = 1;
143 break;
144 }
145 }
146 spin_unlock(&hose_spinlock);
147 return ret;
148}
149
Milton Millerc3bd5172009-01-08 02:19:46 +0000150unsigned long pci_address_to_pio(phys_addr_t address)
151{
152 struct pci_controller *hose;
153 resource_size_t size;
154 unsigned long ret = ~0;
155
156 spin_lock(&hose_spinlock);
157 list_for_each_entry(hose, &hose_list, list_node) {
158 size = pcibios_io_size(hose);
159 if (address >= hose->io_base_phys &&
160 address < (hose->io_base_phys + size)) {
161 unsigned long base =
162 (unsigned long)hose->io_base_virt - _IO_BASE;
163 ret = base + (address - hose->io_base_phys);
164 break;
165 }
166 }
167 spin_unlock(&hose_spinlock);
168
169 return ret;
170}
171EXPORT_SYMBOL_GPL(pci_address_to_pio);
172
Kumar Gala5516b542007-06-27 01:17:57 -0500173/*
174 * Return the domain number for this bus.
175 */
176int pci_domain_nr(struct pci_bus *bus)
177{
Stephen Rothwell6207e812007-12-07 02:04:33 +1100178 struct pci_controller *hose = pci_bus_to_host(bus);
Kumar Gala5516b542007-06-27 01:17:57 -0500179
Stephen Rothwell6207e812007-12-07 02:04:33 +1100180 return hose->global_number;
Kumar Gala5516b542007-06-27 01:17:57 -0500181}
Kumar Gala5516b542007-06-27 01:17:57 -0500182EXPORT_SYMBOL(pci_domain_nr);
Kumar Gala58083da2007-06-27 11:07:51 -0500183
Kumar Galaa4c9e322007-06-27 13:09:43 -0500184/* This routine is meant to be used early during boot, when the
185 * PCI bus numbers have not yet been assigned, and you need to
186 * issue PCI config cycles to an OF device.
187 * It could also be used to "fix" RTAS config cycles if you want
188 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
189 * config cycles.
190 */
191struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
192{
Kumar Galaa4c9e322007-06-27 13:09:43 -0500193 while(node) {
194 struct pci_controller *hose, *tmp;
195 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
Stephen Rothwell44ef3392007-12-10 14:33:21 +1100196 if (hose->dn == node)
Kumar Galaa4c9e322007-06-27 13:09:43 -0500197 return hose;
198 node = node->parent;
199 }
200 return NULL;
201}
202
Kumar Gala58083da2007-06-27 11:07:51 -0500203static ssize_t pci_show_devspec(struct device *dev,
204 struct device_attribute *attr, char *buf)
205{
206 struct pci_dev *pdev;
207 struct device_node *np;
208
209 pdev = to_pci_dev (dev);
210 np = pci_device_to_OF_node(pdev);
211 if (np == NULL || np->full_name == NULL)
212 return 0;
213 return sprintf(buf, "%s", np->full_name);
214}
215static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
Kumar Gala58083da2007-06-27 11:07:51 -0500216
217/* Add sysfs properties */
Tony Breeds4f3731d2007-07-18 11:03:55 +1000218int pcibios_add_platform_entries(struct pci_dev *pdev)
Kumar Gala58083da2007-06-27 11:07:51 -0500219{
Tony Breeds4f3731d2007-07-18 11:03:55 +1000220 return device_create_file(&pdev->dev, &dev_attr_devspec);
Kumar Gala58083da2007-06-27 11:07:51 -0500221}
222
Kumar Gala58083da2007-06-27 11:07:51 -0500223/*
224 * Reads the interrupt pin to determine if interrupt is use by card.
225 * If the interrupt is used, then gets the interrupt line from the
226 * openfirmware and sets it in the pci_dev and pci_config line.
227 */
Benjamin Herrenschmidt4666ca22011-11-29 20:16:25 +0000228static int pci_read_irq_line(struct pci_dev *pci_dev)
Kumar Gala58083da2007-06-27 11:07:51 -0500229{
230 struct of_irq oirq;
231 unsigned int virq;
232
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +0000233 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
Kumar Gala58083da2007-06-27 11:07:51 -0500234
235#ifdef DEBUG
236 memset(&oirq, 0xff, sizeof(oirq));
237#endif
238 /* Try to get a mapping from the device-tree */
239 if (of_irq_map_pci(pci_dev, &oirq)) {
240 u8 line, pin;
241
242 /* If that fails, lets fallback to what is in the config
243 * space and map that through the default controller. We
244 * also set the type to level low since that's what PCI
245 * interrupts are. If your platform does differently, then
246 * either provide a proper interrupt tree or don't use this
247 * function.
248 */
249 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
250 return -1;
251 if (pin == 0)
252 return -1;
253 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
Benjamin Herrenschmidt54a24cb2007-12-20 15:10:02 +1100254 line == 0xff || line == 0) {
Kumar Gala58083da2007-06-27 11:07:51 -0500255 return -1;
256 }
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +0000257 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
258 line, pin);
Kumar Gala58083da2007-06-27 11:07:51 -0500259
260 virq = irq_create_mapping(NULL, line);
261 if (virq != NO_IRQ)
Thomas Gleixnerec775d02011-03-25 16:45:20 +0100262 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
Kumar Gala58083da2007-06-27 11:07:51 -0500263 } else {
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +0000264 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
265 oirq.size, oirq.specifier[0], oirq.specifier[1],
Grant Likely74a7f082012-06-15 11:50:25 -0600266 of_node_full_name(oirq.controller));
Kumar Gala58083da2007-06-27 11:07:51 -0500267
268 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
269 oirq.size);
270 }
271 if(virq == NO_IRQ) {
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +0000272 pr_debug(" Failed to map !\n");
Kumar Gala58083da2007-06-27 11:07:51 -0500273 return -1;
274 }
275
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +0000276 pr_debug(" Mapped to linux irq %d\n", virq);
Kumar Gala58083da2007-06-27 11:07:51 -0500277
278 pci_dev->irq = virq;
279
280 return 0;
281}
Kumar Gala58083da2007-06-27 11:07:51 -0500282
283/*
284 * Platform support for /proc/bus/pci/X/Y mmap()s,
285 * modelled on the sparc64 implementation by Dave Miller.
286 * -- paulus.
287 */
288
289/*
290 * Adjust vm_pgoff of VMA such that it is the physical page offset
291 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
292 *
293 * Basically, the user finds the base address for his device which he wishes
294 * to mmap. They read the 32-bit value from the config space base register,
295 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
296 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
297 *
298 * Returns negative error code on failure, zero on success.
299 */
300static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
301 resource_size_t *offset,
302 enum pci_mmap_state mmap_state)
303{
304 struct pci_controller *hose = pci_bus_to_host(dev->bus);
305 unsigned long io_offset = 0;
306 int i, res_bit;
307
308 if (hose == 0)
309 return NULL; /* should never happen */
310
311 /* If memory, add on the PCI bridge address offset */
312 if (mmap_state == pci_mmap_mem) {
313#if 0 /* See comment in pci_resource_to_user() for why this is disabled */
314 *offset += hose->pci_mem_offset;
315#endif
316 res_bit = IORESOURCE_MEM;
317 } else {
318 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
319 *offset += io_offset;
320 res_bit = IORESOURCE_IO;
321 }
322
323 /*
324 * Check that the offset requested corresponds to one of the
325 * resources of the device.
326 */
327 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
328 struct resource *rp = &dev->resource[i];
329 int flags = rp->flags;
330
331 /* treat ROM as memory (should be already) */
332 if (i == PCI_ROM_RESOURCE)
333 flags |= IORESOURCE_MEM;
334
335 /* Active and same type? */
336 if ((flags & res_bit) == 0)
337 continue;
338
339 /* In the range of this resource? */
340 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
341 continue;
342
343 /* found it! construct the final physical address */
344 if (mmap_state == pci_mmap_io)
345 *offset += hose->io_base_phys - io_offset;
346 return rp;
347 }
348
349 return NULL;
350}
351
352/*
353 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
354 * device mapping.
355 */
356static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
357 pgprot_t protection,
358 enum pci_mmap_state mmap_state,
359 int write_combine)
360{
361 unsigned long prot = pgprot_val(protection);
362
363 /* Write combine is always 0 on non-memory space mappings. On
364 * memory space, if the user didn't pass 1, we check for a
365 * "prefetchable" resource. This is a bit hackish, but we use
366 * this to workaround the inability of /sysfs to provide a write
367 * combine bit
368 */
369 if (mmap_state != pci_mmap_mem)
370 write_combine = 0;
371 else if (write_combine == 0) {
372 if (rp->flags & IORESOURCE_PREFETCH)
373 write_combine = 1;
374 }
375
376 /* XXX would be nice to have a way to ask for write-through */
Kumar Gala58083da2007-06-27 11:07:51 -0500377 if (write_combine)
Benjamin Herrenschmidt64b3d0e2008-12-18 19:13:51 +0000378 return pgprot_noncached_wc(prot);
Kumar Gala58083da2007-06-27 11:07:51 -0500379 else
Benjamin Herrenschmidt64b3d0e2008-12-18 19:13:51 +0000380 return pgprot_noncached(prot);
Kumar Gala58083da2007-06-27 11:07:51 -0500381}
382
383/*
384 * This one is used by /dev/mem and fbdev who have no clue about the
385 * PCI device, it tries to find the PCI device first and calls the
386 * above routine
387 */
388pgprot_t pci_phys_mem_access_prot(struct file *file,
389 unsigned long pfn,
390 unsigned long size,
Benjamin Herrenschmidt64b3d0e2008-12-18 19:13:51 +0000391 pgprot_t prot)
Kumar Gala58083da2007-06-27 11:07:51 -0500392{
393 struct pci_dev *pdev = NULL;
394 struct resource *found = NULL;
Benjamin Herrenschmidt7c12d902008-10-01 15:30:04 +0000395 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
Kumar Gala58083da2007-06-27 11:07:51 -0500396 int i;
397
398 if (page_is_ram(pfn))
Benjamin Herrenschmidt64b3d0e2008-12-18 19:13:51 +0000399 return prot;
Kumar Gala58083da2007-06-27 11:07:51 -0500400
Benjamin Herrenschmidt64b3d0e2008-12-18 19:13:51 +0000401 prot = pgprot_noncached(prot);
Kumar Gala58083da2007-06-27 11:07:51 -0500402 for_each_pci_dev(pdev) {
403 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
404 struct resource *rp = &pdev->resource[i];
405 int flags = rp->flags;
406
407 /* Active and same type? */
408 if ((flags & IORESOURCE_MEM) == 0)
409 continue;
410 /* In the range of this resource? */
411 if (offset < (rp->start & PAGE_MASK) ||
412 offset > rp->end)
413 continue;
414 found = rp;
415 break;
416 }
417 if (found)
418 break;
419 }
420 if (found) {
421 if (found->flags & IORESOURCE_PREFETCH)
Benjamin Herrenschmidt64b3d0e2008-12-18 19:13:51 +0000422 prot = pgprot_noncached_wc(prot);
Kumar Gala58083da2007-06-27 11:07:51 -0500423 pci_dev_put(pdev);
424 }
425
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +0000426 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
Benjamin Herrenschmidt64b3d0e2008-12-18 19:13:51 +0000427 (unsigned long long)offset, pgprot_val(prot));
Kumar Gala58083da2007-06-27 11:07:51 -0500428
Benjamin Herrenschmidt64b3d0e2008-12-18 19:13:51 +0000429 return prot;
Kumar Gala58083da2007-06-27 11:07:51 -0500430}
431
432
433/*
434 * Perform the actual remap of the pages for a PCI device mapping, as
435 * appropriate for this architecture. The region in the process to map
436 * is described by vm_start and vm_end members of VMA, the base physical
437 * address is found in vm_pgoff.
438 * The pci device structure is provided so that architectures may make mapping
439 * decisions on a per-device or per-bus basis.
440 *
441 * Returns a negative error code on failure, zero on success.
442 */
443int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
444 enum pci_mmap_state mmap_state, int write_combine)
445{
Benjamin Herrenschmidt7c12d902008-10-01 15:30:04 +0000446 resource_size_t offset =
447 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
Kumar Gala58083da2007-06-27 11:07:51 -0500448 struct resource *rp;
449 int ret;
450
451 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
452 if (rp == NULL)
453 return -EINVAL;
454
455 vma->vm_pgoff = offset >> PAGE_SHIFT;
456 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
457 vma->vm_page_prot,
458 mmap_state, write_combine);
459
460 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
461 vma->vm_end - vma->vm_start, vma->vm_page_prot);
462
463 return ret;
464}
465
Benjamin Herrenschmidte9f82cb2008-10-14 11:55:31 +1100466/* This provides legacy IO read access on a bus */
467int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
468{
469 unsigned long offset;
470 struct pci_controller *hose = pci_bus_to_host(bus);
471 struct resource *rp = &hose->io_resource;
472 void __iomem *addr;
473
474 /* Check if port can be supported by that bus. We only check
475 * the ranges of the PHB though, not the bus itself as the rules
476 * for forwarding legacy cycles down bridges are not our problem
477 * here. So if the host bridge supports it, we do it.
478 */
479 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
480 offset += port;
481
482 if (!(rp->flags & IORESOURCE_IO))
483 return -ENXIO;
484 if (offset < rp->start || (offset + size) > rp->end)
485 return -ENXIO;
486 addr = hose->io_base_virt + port;
487
488 switch(size) {
489 case 1:
490 *((u8 *)val) = in_8(addr);
491 return 1;
492 case 2:
493 if (port & 1)
494 return -EINVAL;
495 *((u16 *)val) = in_le16(addr);
496 return 2;
497 case 4:
498 if (port & 3)
499 return -EINVAL;
500 *((u32 *)val) = in_le32(addr);
501 return 4;
502 }
503 return -EINVAL;
504}
505
506/* This provides legacy IO write access on a bus */
507int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
508{
509 unsigned long offset;
510 struct pci_controller *hose = pci_bus_to_host(bus);
511 struct resource *rp = &hose->io_resource;
512 void __iomem *addr;
513
514 /* Check if port can be supported by that bus. We only check
515 * the ranges of the PHB though, not the bus itself as the rules
516 * for forwarding legacy cycles down bridges are not our problem
517 * here. So if the host bridge supports it, we do it.
518 */
519 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
520 offset += port;
521
522 if (!(rp->flags & IORESOURCE_IO))
523 return -ENXIO;
524 if (offset < rp->start || (offset + size) > rp->end)
525 return -ENXIO;
526 addr = hose->io_base_virt + port;
527
528 /* WARNING: The generic code is idiotic. It gets passed a pointer
529 * to what can be a 1, 2 or 4 byte quantity and always reads that
530 * as a u32, which means that we have to correct the location of
531 * the data read within those 32 bits for size 1 and 2
532 */
533 switch(size) {
534 case 1:
535 out_8(addr, val >> 24);
536 return 1;
537 case 2:
538 if (port & 1)
539 return -EINVAL;
540 out_le16(addr, val >> 16);
541 return 2;
542 case 4:
543 if (port & 3)
544 return -EINVAL;
545 out_le32(addr, val);
546 return 4;
547 }
548 return -EINVAL;
549}
550
551/* This provides legacy IO or memory mmap access on a bus */
552int pci_mmap_legacy_page_range(struct pci_bus *bus,
553 struct vm_area_struct *vma,
554 enum pci_mmap_state mmap_state)
555{
556 struct pci_controller *hose = pci_bus_to_host(bus);
557 resource_size_t offset =
558 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
559 resource_size_t size = vma->vm_end - vma->vm_start;
560 struct resource *rp;
561
562 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
563 pci_domain_nr(bus), bus->number,
564 mmap_state == pci_mmap_mem ? "MEM" : "IO",
565 (unsigned long long)offset,
566 (unsigned long long)(offset + size - 1));
567
568 if (mmap_state == pci_mmap_mem) {
Benjamin Herrenschmidt5b11abf2009-02-08 14:27:21 +0000569 /* Hack alert !
570 *
571 * Because X is lame and can fail starting if it gets an error trying
572 * to mmap legacy_mem (instead of just moving on without legacy memory
573 * access) we fake it here by giving it anonymous memory, effectively
574 * behaving just like /dev/zero
575 */
576 if ((offset + size) > hose->isa_mem_size) {
577 printk(KERN_DEBUG
578 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
579 current->comm, current->pid, pci_domain_nr(bus), bus->number);
580 if (vma->vm_flags & VM_SHARED)
581 return shmem_zero_setup(vma);
582 return 0;
583 }
Benjamin Herrenschmidte9f82cb2008-10-14 11:55:31 +1100584 offset += hose->isa_mem_phys;
585 } else {
586 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
587 unsigned long roffset = offset + io_offset;
588 rp = &hose->io_resource;
589 if (!(rp->flags & IORESOURCE_IO))
590 return -ENXIO;
591 if (roffset < rp->start || (roffset + size) > rp->end)
592 return -ENXIO;
593 offset += hose->io_base_phys;
594 }
595 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
596
597 vma->vm_pgoff = offset >> PAGE_SHIFT;
Benjamin Herrenschmidt64b3d0e2008-12-18 19:13:51 +0000598 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
Benjamin Herrenschmidte9f82cb2008-10-14 11:55:31 +1100599 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
600 vma->vm_end - vma->vm_start,
601 vma->vm_page_prot);
602}
603
Kumar Gala58083da2007-06-27 11:07:51 -0500604void pci_resource_to_user(const struct pci_dev *dev, int bar,
605 const struct resource *rsrc,
606 resource_size_t *start, resource_size_t *end)
607{
608 struct pci_controller *hose = pci_bus_to_host(dev->bus);
609 resource_size_t offset = 0;
610
611 if (hose == NULL)
612 return;
613
614 if (rsrc->flags & IORESOURCE_IO)
615 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
616
617 /* We pass a fully fixed up address to userland for MMIO instead of
618 * a BAR value because X is lame and expects to be able to use that
619 * to pass to /dev/mem !
620 *
621 * That means that we'll have potentially 64 bits values where some
622 * userland apps only expect 32 (like X itself since it thinks only
623 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
624 * 32 bits CHRPs :-(
625 *
626 * Hopefully, the sysfs insterface is immune to that gunk. Once X
627 * has been fixed (and the fix spread enough), we can re-enable the
628 * 2 lines below and pass down a BAR value to userland. In that case
629 * we'll also have to re-enable the matching code in
630 * __pci_mmap_make_offset().
631 *
632 * BenH.
633 */
634#if 0
635 else if (rsrc->flags & IORESOURCE_MEM)
636 offset = hose->pci_mem_offset;
637#endif
638
639 *start = rsrc->start - offset;
640 *end = rsrc->end - offset;
641}
Benjamin Herrenschmidt13dccb92007-12-11 14:48:18 +1100642
643/**
644 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
645 * @hose: newly allocated pci_controller to be setup
646 * @dev: device node of the host bridge
647 * @primary: set if primary bus (32 bits only, soon to be deprecated)
648 *
649 * This function will parse the "ranges" property of a PCI host bridge device
650 * node and setup the resource mapping of a pci controller based on its
651 * content.
652 *
653 * Life would be boring if it wasn't for a few issues that we have to deal
654 * with here:
655 *
656 * - We can only cope with one IO space range and up to 3 Memory space
657 * ranges. However, some machines (thanks Apple !) tend to split their
658 * space into lots of small contiguous ranges. So we have to coalesce.
659 *
660 * - We can only cope with all memory ranges having the same offset
661 * between CPU addresses and PCI addresses. Unfortunately, some bridges
662 * are setup for a large 1:1 mapping along with a small "window" which
663 * maps PCI address 0 to some arbitrary high address of the CPU space in
664 * order to give access to the ISA memory hole.
665 * The way out of here that I've chosen for now is to always set the
666 * offset based on the first resource found, then override it if we
667 * have a different offset and the previous was set by an ISA hole.
668 *
669 * - Some busses have IO space not starting at 0, which causes trouble with
670 * the way we do our IO resource renumbering. The code somewhat deals with
671 * it for 64 bits but I would expect problems on 32 bits.
672 *
673 * - Some 32 bits platforms such as 4xx can have physical space larger than
674 * 32 bits so we need to use 64 bits values for the parsing
675 */
676void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
677 struct device_node *dev,
678 int primary)
679{
680 const u32 *ranges;
681 int rlen;
682 int pna = of_n_addr_cells(dev);
683 int np = pna + 5;
684 int memno = 0, isa_hole = -1;
685 u32 pci_space;
686 unsigned long long pci_addr, cpu_addr, pci_next, cpu_next, size;
687 unsigned long long isa_mb = 0;
688 struct resource *res;
689
690 printk(KERN_INFO "PCI host bridge %s %s ranges:\n",
691 dev->full_name, primary ? "(primary)" : "");
692
693 /* Get ranges property */
694 ranges = of_get_property(dev, "ranges", &rlen);
695 if (ranges == NULL)
696 return;
697
698 /* Parse it */
699 while ((rlen -= np * 4) >= 0) {
700 /* Read next ranges element */
701 pci_space = ranges[0];
702 pci_addr = of_read_number(ranges + 1, 2);
703 cpu_addr = of_translate_address(dev, ranges + 3);
704 size = of_read_number(ranges + pna + 3, 2);
705 ranges += np;
Benjamin Herrenschmidte9f82cb2008-10-14 11:55:31 +1100706
707 /* If we failed translation or got a zero-sized region
708 * (some FW try to feed us with non sensical zero sized regions
709 * such as power3 which look like some kind of attempt at exposing
710 * the VGA memory hole)
711 */
Benjamin Herrenschmidt13dccb92007-12-11 14:48:18 +1100712 if (cpu_addr == OF_BAD_ADDR || size == 0)
713 continue;
714
715 /* Now consume following elements while they are contiguous */
716 for (; rlen >= np * sizeof(u32);
717 ranges += np, rlen -= np * 4) {
718 if (ranges[0] != pci_space)
719 break;
720 pci_next = of_read_number(ranges + 1, 2);
721 cpu_next = of_translate_address(dev, ranges + 3);
722 if (pci_next != pci_addr + size ||
723 cpu_next != cpu_addr + size)
724 break;
725 size += of_read_number(ranges + pna + 3, 2);
726 }
727
728 /* Act based on address space type */
729 res = NULL;
730 switch ((pci_space >> 24) & 0x3) {
731 case 1: /* PCI IO space */
732 printk(KERN_INFO
733 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
734 cpu_addr, cpu_addr + size - 1, pci_addr);
735
736 /* We support only one IO range */
737 if (hose->pci_io_size) {
738 printk(KERN_INFO
739 " \\--> Skipped (too many) !\n");
740 continue;
741 }
742#ifdef CONFIG_PPC32
743 /* On 32 bits, limit I/O space to 16MB */
744 if (size > 0x01000000)
745 size = 0x01000000;
746
747 /* 32 bits needs to map IOs here */
748 hose->io_base_virt = ioremap(cpu_addr, size);
749
750 /* Expect trouble if pci_addr is not 0 */
751 if (primary)
752 isa_io_base =
753 (unsigned long)hose->io_base_virt;
754#endif /* CONFIG_PPC32 */
755 /* pci_io_size and io_base_phys always represent IO
756 * space starting at 0 so we factor in pci_addr
757 */
758 hose->pci_io_size = pci_addr + size;
759 hose->io_base_phys = cpu_addr - pci_addr;
760
761 /* Build resource */
762 res = &hose->io_resource;
763 res->flags = IORESOURCE_IO;
764 res->start = pci_addr;
765 break;
766 case 2: /* PCI Memory space */
Benjamin Herrenschmidt67260ac2008-07-17 15:53:31 +1000767 case 3: /* PCI 64 bits Memory space */
Benjamin Herrenschmidt13dccb92007-12-11 14:48:18 +1100768 printk(KERN_INFO
769 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
770 cpu_addr, cpu_addr + size - 1, pci_addr,
771 (pci_space & 0x40000000) ? "Prefetch" : "");
772
773 /* We support only 3 memory ranges */
774 if (memno >= 3) {
775 printk(KERN_INFO
776 " \\--> Skipped (too many) !\n");
777 continue;
778 }
779 /* Handles ISA memory hole space here */
780 if (pci_addr == 0) {
781 isa_mb = cpu_addr;
782 isa_hole = memno;
783 if (primary || isa_mem_base == 0)
784 isa_mem_base = cpu_addr;
Benjamin Herrenschmidte9f82cb2008-10-14 11:55:31 +1100785 hose->isa_mem_phys = cpu_addr;
786 hose->isa_mem_size = size;
Benjamin Herrenschmidt13dccb92007-12-11 14:48:18 +1100787 }
788
789 /* We get the PCI/Mem offset from the first range or
790 * the, current one if the offset came from an ISA
791 * hole. If they don't match, bugger.
792 */
793 if (memno == 0 ||
794 (isa_hole >= 0 && pci_addr != 0 &&
795 hose->pci_mem_offset == isa_mb))
796 hose->pci_mem_offset = cpu_addr - pci_addr;
797 else if (pci_addr != 0 &&
798 hose->pci_mem_offset != cpu_addr - pci_addr) {
799 printk(KERN_INFO
800 " \\--> Skipped (offset mismatch) !\n");
801 continue;
802 }
803
804 /* Build resource */
805 res = &hose->mem_resources[memno++];
806 res->flags = IORESOURCE_MEM;
807 if (pci_space & 0x40000000)
808 res->flags |= IORESOURCE_PREFETCH;
809 res->start = cpu_addr;
810 break;
811 }
812 if (res != NULL) {
813 res->name = dev->full_name;
814 res->end = res->start + size - 1;
815 res->parent = NULL;
816 res->sibling = NULL;
817 res->child = NULL;
818 }
819 }
820
Benjamin Herrenschmidt8db13a02008-07-31 15:24:13 +1000821 /* If there's an ISA hole and the pci_mem_offset is -not- matching
822 * the ISA hole offset, then we need to remove the ISA hole from
823 * the resource list for that brige
824 */
825 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
826 unsigned int next = isa_hole + 1;
827 printk(KERN_INFO " Removing ISA hole at 0x%016llx\n", isa_mb);
828 if (next < memno)
829 memmove(&hose->mem_resources[isa_hole],
830 &hose->mem_resources[next],
831 sizeof(struct resource) * (memno - next));
832 hose->mem_resources[--memno].flags = 0;
Benjamin Herrenschmidt13dccb92007-12-11 14:48:18 +1100833 }
834}
Benjamin Herrenschmidtfa462f22007-12-20 14:54:49 +1100835
836/* Decide whether to display the domain number in /proc */
837int pci_proc_domain(struct pci_bus *bus)
838{
839 struct pci_controller *hose = pci_bus_to_host(bus);
Benjamin Herrenschmidt1fd0f522008-10-02 14:12:51 +0000840
Rob Herring0e47ff12011-07-12 09:25:51 -0500841 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
Benjamin Herrenschmidtfa462f22007-12-20 14:54:49 +1100842 return 0;
Rob Herring0e47ff12011-07-12 09:25:51 -0500843 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
Benjamin Herrenschmidtfa462f22007-12-20 14:54:49 +1100844 return hose->global_number != 0;
845 return 1;
Benjamin Herrenschmidtfa462f22007-12-20 14:54:49 +1100846}
847
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +1100848/* This header fixup will do the resource fixup for all devices as they are
849 * probed, but not for bridge ranges
850 */
851static void __devinit pcibios_fixup_resources(struct pci_dev *dev)
852{
853 struct pci_controller *hose = pci_bus_to_host(dev->bus);
854 int i;
855
856 if (!hose) {
857 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
858 pci_name(dev));
859 return;
860 }
861 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
862 struct resource *res = dev->resource + i;
863 if (!res->flags)
864 continue;
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +0000865
866 /* If we're going to re-assign everything, we mark all resources
867 * as unset (and 0-base them). In addition, we mark BARs starting
868 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
869 * since in that case, we don't want to re-assign anything
Benjamin Herrenschmidt7f172892008-02-29 14:58:03 +1100870 */
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +0000871 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
872 (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
873 /* Only print message if not re-assigning */
874 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
875 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
876 "is unassigned\n",
877 pci_name(dev), i,
878 (unsigned long long)res->start,
879 (unsigned long long)res->end,
880 (unsigned int)res->flags);
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +1100881 res->end -= res->start;
882 res->start = 0;
883 res->flags |= IORESOURCE_UNSET;
884 continue;
885 }
886
Bjorn Helgaas6c5705f2012-02-23 20:19:03 -0700887 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n",
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +1100888 pci_name(dev), i,
889 (unsigned long long)res->start,\
890 (unsigned long long)res->end,
891 (unsigned int)res->flags);
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +1100892 }
893
894 /* Call machine specific resource fixup */
895 if (ppc_md.pcibios_fixup_resources)
896 ppc_md.pcibios_fixup_resources(dev);
897}
898DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
899
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +0000900/* This function tries to figure out if a bridge resource has been initialized
901 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
902 * things go more smoothly when it gets it right. It should covers cases such
903 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
904 */
905static int __devinit pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
906 struct resource *res)
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +1100907{
Benjamin Herrenschmidtbe8cbcd2007-12-20 14:55:04 +1100908 struct pci_controller *hose = pci_bus_to_host(bus);
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +1100909 struct pci_dev *dev = bus->self;
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +0000910 resource_size_t offset;
911 u16 command;
912 int i;
913
914 /* We don't do anything if PCI_PROBE_ONLY is set */
Rob Herring0e47ff12011-07-12 09:25:51 -0500915 if (pci_has_flag(PCI_PROBE_ONLY))
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +0000916 return 0;
917
918 /* Job is a bit different between memory and IO */
919 if (res->flags & IORESOURCE_MEM) {
920 /* If the BAR is non-0 (res != pci_mem_offset) then it's probably been
921 * initialized by somebody
922 */
923 if (res->start != hose->pci_mem_offset)
924 return 0;
925
926 /* The BAR is 0, let's check if memory decoding is enabled on
927 * the bridge. If not, we consider it unassigned
928 */
929 pci_read_config_word(dev, PCI_COMMAND, &command);
930 if ((command & PCI_COMMAND_MEMORY) == 0)
931 return 1;
932
933 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
934 * resources covers that starting address (0 then it's good enough for
935 * us for memory
936 */
937 for (i = 0; i < 3; i++) {
938 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
939 hose->mem_resources[i].start == hose->pci_mem_offset)
940 return 0;
941 }
942
943 /* Well, it starts at 0 and we know it will collide so we may as
944 * well consider it as unassigned. That covers the Apple case.
945 */
946 return 1;
947 } else {
948 /* If the BAR is non-0, then we consider it assigned */
949 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
950 if (((res->start - offset) & 0xfffffffful) != 0)
951 return 0;
952
953 /* Here, we are a bit different than memory as typically IO space
954 * starting at low addresses -is- valid. What we do instead if that
955 * we consider as unassigned anything that doesn't have IO enabled
956 * in the PCI command register, and that's it.
957 */
958 pci_read_config_word(dev, PCI_COMMAND, &command);
959 if (command & PCI_COMMAND_IO)
960 return 0;
961
962 /* It's starting at 0 and IO is disabled in the bridge, consider
963 * it unassigned
964 */
965 return 1;
966 }
967}
968
969/* Fixup resources of a PCI<->PCI bridge */
970static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
971{
972 struct resource *res;
973 int i;
974
975 struct pci_dev *dev = bus->self;
976
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -0700977 pci_bus_for_each_resource(bus, res, i) {
978 if (!res || !res->flags)
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +0000979 continue;
980 if (i >= 3 && bus->self->transparent)
981 continue;
982
Gavin Shancf1a4cf2012-06-03 22:15:25 +0000983 /* If we're going to reassign everything, we can
984 * shrink the P2P resource to have size as being
985 * of 0 in order to save space.
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +0000986 */
987 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
988 res->flags |= IORESOURCE_UNSET;
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +0000989 res->start = 0;
Gavin Shancf1a4cf2012-06-03 22:15:25 +0000990 res->end = -1;
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +0000991 continue;
992 }
993
Bjorn Helgaas6c5705f2012-02-23 20:19:03 -0700994 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n",
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +0000995 pci_name(dev), i,
996 (unsigned long long)res->start,\
997 (unsigned long long)res->end,
998 (unsigned int)res->flags);
999
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +00001000 /* Try to detect uninitialized P2P bridge resources,
1001 * and clear them out so they get re-assigned later
1002 */
1003 if (pcibios_uninitialized_bridge_resource(bus, res)) {
1004 res->flags = 0;
1005 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
Benjamin Herrenschmidtb5561512008-10-13 13:56:31 +00001006 }
1007 }
1008}
1009
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +00001010void __devinit pcibios_setup_bus_self(struct pci_bus *bus)
1011{
Benjamin Herrenschmidt7eef4402008-10-27 19:48:56 +00001012 /* Fix up the bus resources for P2P bridges */
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +00001013 if (bus->self != NULL)
1014 pcibios_fixup_bridge(bus);
1015
1016 /* Platform specific bus fixups. This is currently only used
Benjamin Herrenschmidt7eef4402008-10-27 19:48:56 +00001017 * by fsl_pci and I'm hoping to get rid of it at some point
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +00001018 */
1019 if (ppc_md.pcibios_fixup_bus)
1020 ppc_md.pcibios_fixup_bus(bus);
1021
1022 /* Setup bus DMA mappings */
1023 if (ppc_md.pci_dma_bus_setup)
1024 ppc_md.pci_dma_bus_setup(bus);
1025}
1026
Benjamin Herrenschmidt7eef4402008-10-27 19:48:56 +00001027void __devinit pcibios_setup_bus_devices(struct pci_bus *bus)
1028{
1029 struct pci_dev *dev;
1030
1031 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1032 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1033
1034 list_for_each_entry(dev, &bus->devices, bus_list) {
Benjamin Herrenschmidt2d1c8612009-12-09 17:52:13 +11001035 /* Cardbus can call us to add new devices to a bus, so ignore
1036 * those who are already fully discovered
1037 */
1038 if (dev->is_added)
1039 continue;
1040
Benjamin Herrenschmidt7eef4402008-10-27 19:48:56 +00001041 /* Fixup NUMA node as it may not be setup yet by the generic
1042 * code and is needed by the DMA init
1043 */
1044 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
1045
1046 /* Hook up default DMA ops */
Nishanth Aravamudanbc0df9e2010-09-15 08:05:50 +00001047 set_dma_ops(&dev->dev, pci_dma_ops);
Becky Bruce738ef422009-09-21 08:26:35 +00001048 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET);
Benjamin Herrenschmidt7eef4402008-10-27 19:48:56 +00001049
1050 /* Additional platform DMA/iommu setup */
1051 if (ppc_md.pci_dma_dev_setup)
1052 ppc_md.pci_dma_dev_setup(dev);
1053
1054 /* Read default IRQs and fixup if necessary */
1055 pci_read_irq_line(dev);
1056 if (ppc_md.pci_irq_fixup)
1057 ppc_md.pci_irq_fixup(dev);
1058 }
1059}
1060
Myron Stowe79c8be82011-10-28 15:48:03 -06001061void pcibios_set_master(struct pci_dev *dev)
1062{
1063 /* No special bus mastering setup handling */
1064}
1065
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +11001066void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1067{
1068 /* When called from the generic PCI probe, read PCI<->PCI bridge
Benjamin Herrenschmidt7eef4402008-10-27 19:48:56 +00001069 * bases. This is -not- called when generating the PCI tree from
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +00001070 * the OF device-tree.
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +11001071 */
1072 if (bus->self != NULL)
1073 pci_read_bridge_bases(bus);
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +00001074
1075 /* Now fixup the bus bus */
1076 pcibios_setup_bus_self(bus);
1077
1078 /* Now fixup devices on that bus */
1079 pcibios_setup_bus_devices(bus);
Benjamin Herrenschmidtbf5e2ba2007-12-20 14:54:51 +11001080}
1081EXPORT_SYMBOL(pcibios_fixup_bus);
1082
Benjamin Herrenschmidt2d1c8612009-12-09 17:52:13 +11001083void __devinit pci_fixup_cardbus(struct pci_bus *bus)
1084{
1085 /* Now fixup devices on that bus */
1086 pcibios_setup_bus_devices(bus);
1087}
1088
1089
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001090static int skip_isa_ioresource_align(struct pci_dev *dev)
1091{
Rob Herring0e47ff12011-07-12 09:25:51 -05001092 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001093 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1094 return 1;
1095 return 0;
1096}
1097
1098/*
1099 * We need to avoid collisions with `mirrored' VGA ports
1100 * and other strange ISA hardware, so we always want the
1101 * addresses to be allocated in the 0x000-0x0ff region
1102 * modulo 0x400.
1103 *
1104 * Why? Because some silly external IO cards only decode
1105 * the low 10 bits of the IO address. The 0x00-0xff region
1106 * is reserved for motherboard devices that decode all 16
1107 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1108 * but we want to try to avoid allocating at 0x2900-0x2bff
1109 * which might have be mirrored at 0x0100-0x03ff..
1110 */
Dominik Brodowski3b7a17f2010-01-01 17:40:50 +01001111resource_size_t pcibios_align_resource(void *data, const struct resource *res,
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001112 resource_size_t size, resource_size_t align)
1113{
1114 struct pci_dev *dev = data;
Dominik Brodowskib26b2d42010-01-01 17:40:49 +01001115 resource_size_t start = res->start;
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001116
1117 if (res->flags & IORESOURCE_IO) {
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001118 if (skip_isa_ioresource_align(dev))
Dominik Brodowskib26b2d42010-01-01 17:40:49 +01001119 return start;
1120 if (start & 0x300)
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001121 start = (start + 0x3ff) & ~0x3ff;
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001122 }
Dominik Brodowskib26b2d42010-01-01 17:40:49 +01001123
1124 return start;
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001125}
1126EXPORT_SYMBOL(pcibios_align_resource);
1127
1128/*
1129 * Reparent resource children of pr that conflict with res
1130 * under res, and make res replace those children.
1131 */
Heiko Schocher0f6023d2009-09-24 02:45:14 +00001132static int reparent_resources(struct resource *parent,
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001133 struct resource *res)
1134{
1135 struct resource *p, **pp;
1136 struct resource **firstpp = NULL;
1137
1138 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1139 if (p->end < res->start)
1140 continue;
1141 if (res->end < p->start)
1142 break;
1143 if (p->start < res->start || p->end > res->end)
1144 return -1; /* not completely contained */
1145 if (firstpp == NULL)
1146 firstpp = pp;
1147 }
1148 if (firstpp == NULL)
1149 return -1; /* didn't find any conflicting entries? */
1150 res->parent = parent;
1151 res->child = *firstpp;
1152 res->sibling = *pp;
1153 *firstpp = res;
1154 *pp = NULL;
1155 for (p = res->child; p != NULL; p = p->sibling) {
1156 p->parent = res;
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +00001157 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1158 p->name,
1159 (unsigned long long)p->start,
1160 (unsigned long long)p->end, res->name);
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001161 }
1162 return 0;
1163}
1164
1165/*
1166 * Handle resources of PCI devices. If the world were perfect, we could
1167 * just allocate all the resource regions and do nothing more. It isn't.
1168 * On the other hand, we cannot just re-allocate all devices, as it would
1169 * require us to know lots of host bridge internals. So we attempt to
1170 * keep as much of the original configuration as possible, but tweak it
1171 * when it's found to be wrong.
1172 *
1173 * Known BIOS problems we have to work around:
1174 * - I/O or memory regions not configured
1175 * - regions configured, but not enabled in the command register
1176 * - bogus I/O addresses above 64K used
1177 * - expansion ROMs left enabled (this may sound harmless, but given
1178 * the fact the PCI specs explicitly allow address decoders to be
1179 * shared between expansion ROMs and other resource regions, it's
1180 * at least dangerous)
1181 *
1182 * Our solution:
1183 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1184 * This gives us fixed barriers on where we can allocate.
1185 * (2) Allocate resources for all enabled devices. If there is
1186 * a collision, just mark the resource as unallocated. Also
1187 * disable expansion ROMs during this step.
1188 * (3) Try to allocate resources for disabled devices. If the
1189 * resources were assigned correctly, everything goes well,
1190 * if they weren't, they won't disturb allocation of other
1191 * resources.
1192 * (4) Assign new addresses to resources which were either
1193 * not configured at all or misconfigured. If explicitly
1194 * requested by the user, configure expansion ROM address
1195 * as well.
1196 */
1197
Nathan Fontenote90a1312008-10-27 19:48:17 +00001198void pcibios_allocate_bus_resources(struct pci_bus *bus)
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001199{
Nathan Fontenote90a1312008-10-27 19:48:17 +00001200 struct pci_bus *b;
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001201 int i;
1202 struct resource *res, *pr;
1203
Benjamin Herrenschmidtb5ae5f92008-10-27 19:48:44 +00001204 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1205 pci_domain_nr(bus), bus->number);
1206
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -07001207 pci_bus_for_each_resource(bus, res, i) {
1208 if (!res || !res->flags || res->start > res->end || res->parent)
Nathan Fontenote90a1312008-10-27 19:48:17 +00001209 continue;
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +00001210
1211 /* If the resource was left unset at this point, we clear it */
1212 if (res->flags & IORESOURCE_UNSET)
1213 goto clear_resource;
1214
Nathan Fontenote90a1312008-10-27 19:48:17 +00001215 if (bus->parent == NULL)
1216 pr = (res->flags & IORESOURCE_IO) ?
1217 &ioport_resource : &iomem_resource;
1218 else {
Nathan Fontenote90a1312008-10-27 19:48:17 +00001219 pr = pci_find_parent_resource(bus->self, res);
1220 if (pr == res) {
1221 /* this happens when the generic PCI
1222 * code (wrongly) decides that this
1223 * bridge is transparent -- paulus
1224 */
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001225 continue;
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001226 }
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001227 }
Nathan Fontenote90a1312008-10-27 19:48:17 +00001228
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +00001229 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1230 "[0x%x], parent %p (%s)\n",
1231 bus->self ? pci_name(bus->self) : "PHB",
1232 bus->number, i,
1233 (unsigned long long)res->start,
1234 (unsigned long long)res->end,
1235 (unsigned int)res->flags,
1236 pr, (pr && pr->name) ? pr->name : "nil");
Nathan Fontenote90a1312008-10-27 19:48:17 +00001237
1238 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1239 if (request_resource(pr, res) == 0)
1240 continue;
1241 /*
1242 * Must be a conflict with an existing entry.
1243 * Move that entry (or entries) under the
1244 * bridge resource and try again.
1245 */
1246 if (reparent_resources(pr, res) == 0)
1247 continue;
1248 }
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +00001249 pr_warning("PCI: Cannot allocate resource region "
1250 "%d of PCI bridge %d, will remap\n", i, bus->number);
1251 clear_resource:
Gavin Shancf1a4cf2012-06-03 22:15:25 +00001252 /* The resource might be figured out when doing
1253 * reassignment based on the resources required
1254 * by the downstream PCI devices. Here we set
1255 * the size of the resource to be 0 in order to
1256 * save more space.
1257 */
1258 res->start = 0;
1259 res->end = -1;
Nathan Fontenote90a1312008-10-27 19:48:17 +00001260 res->flags = 0;
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001261 }
Nathan Fontenote90a1312008-10-27 19:48:17 +00001262
1263 list_for_each_entry(b, &bus->children, node)
1264 pcibios_allocate_bus_resources(b);
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001265}
1266
Paul Mackerras533b1922007-12-31 10:04:15 +11001267static inline void __devinit alloc_resource(struct pci_dev *dev, int idx)
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001268{
1269 struct resource *pr, *r = &dev->resource[idx];
1270
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +00001271 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1272 pci_name(dev), idx,
1273 (unsigned long long)r->start,
1274 (unsigned long long)r->end,
1275 (unsigned int)r->flags);
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001276
1277 pr = pci_find_parent_resource(dev, r);
1278 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1279 request_resource(pr, r) < 0) {
1280 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1281 " of device %s, will remap\n", idx, pci_name(dev));
1282 if (pr)
Benjamin Herrenschmidtb0494bc2008-10-27 19:48:22 +00001283 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1284 pr,
1285 (unsigned long long)pr->start,
1286 (unsigned long long)pr->end,
1287 (unsigned int)pr->flags);
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001288 /* We'll assign a new address later */
1289 r->flags |= IORESOURCE_UNSET;
1290 r->end -= r->start;
1291 r->start = 0;
1292 }
1293}
1294
1295static void __init pcibios_allocate_resources(int pass)
1296{
1297 struct pci_dev *dev = NULL;
1298 int idx, disabled;
1299 u16 command;
1300 struct resource *r;
1301
1302 for_each_pci_dev(dev) {
1303 pci_read_config_word(dev, PCI_COMMAND, &command);
Benjamin Herrenschmidtad892a62009-05-14 20:16:47 +00001304 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001305 r = &dev->resource[idx];
1306 if (r->parent) /* Already allocated */
1307 continue;
1308 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1309 continue; /* Not assigned at all */
Benjamin Herrenschmidtad892a62009-05-14 20:16:47 +00001310 /* We only allocate ROMs on pass 1 just in case they
1311 * have been screwed up by firmware
1312 */
1313 if (idx == PCI_ROM_RESOURCE )
1314 disabled = 1;
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001315 if (r->flags & IORESOURCE_IO)
1316 disabled = !(command & PCI_COMMAND_IO);
1317 else
1318 disabled = !(command & PCI_COMMAND_MEMORY);
Paul Mackerras533b1922007-12-31 10:04:15 +11001319 if (pass == disabled)
1320 alloc_resource(dev, idx);
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001321 }
1322 if (pass)
1323 continue;
1324 r = &dev->resource[PCI_ROM_RESOURCE];
Benjamin Herrenschmidtad892a62009-05-14 20:16:47 +00001325 if (r->flags) {
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001326 /* Turn the ROM off, leave the resource region,
1327 * but keep it unregistered.
1328 */
1329 u32 reg;
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001330 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
Benjamin Herrenschmidtad892a62009-05-14 20:16:47 +00001331 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1332 pr_debug("PCI: Switching off ROM of %s\n",
1333 pci_name(dev));
1334 r->flags &= ~IORESOURCE_ROM_ENABLE;
1335 pci_write_config_dword(dev, dev->rom_base_reg,
1336 reg & ~PCI_ROM_ADDRESS_ENABLE);
1337 }
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001338 }
1339 }
1340}
1341
Benjamin Herrenschmidtc1f34302008-11-11 17:45:52 +00001342static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1343{
1344 struct pci_controller *hose = pci_bus_to_host(bus);
1345 resource_size_t offset;
1346 struct resource *res, *pres;
1347 int i;
1348
1349 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1350
1351 /* Check for IO */
1352 if (!(hose->io_resource.flags & IORESOURCE_IO))
1353 goto no_io;
1354 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1355 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1356 BUG_ON(res == NULL);
1357 res->name = "Legacy IO";
1358 res->flags = IORESOURCE_IO;
1359 res->start = offset;
1360 res->end = (offset + 0xfff) & 0xfffffffful;
1361 pr_debug("Candidate legacy IO: %pR\n", res);
1362 if (request_resource(&hose->io_resource, res)) {
1363 printk(KERN_DEBUG
1364 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1365 pci_domain_nr(bus), bus->number, res);
1366 kfree(res);
1367 }
1368
1369 no_io:
1370 /* Check for memory */
1371 offset = hose->pci_mem_offset;
1372 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1373 for (i = 0; i < 3; i++) {
1374 pres = &hose->mem_resources[i];
1375 if (!(pres->flags & IORESOURCE_MEM))
1376 continue;
1377 pr_debug("hose mem res: %pR\n", pres);
1378 if ((pres->start - offset) <= 0xa0000 &&
1379 (pres->end - offset) >= 0xbffff)
1380 break;
1381 }
1382 if (i >= 3)
1383 return;
1384 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1385 BUG_ON(res == NULL);
1386 res->name = "Legacy VGA memory";
1387 res->flags = IORESOURCE_MEM;
1388 res->start = 0xa0000 + offset;
1389 res->end = 0xbffff + offset;
1390 pr_debug("Candidate VGA memory: %pR\n", res);
1391 if (request_resource(pres, res)) {
1392 printk(KERN_DEBUG
1393 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1394 pci_domain_nr(bus), bus->number, res);
1395 kfree(res);
1396 }
1397}
1398
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001399void __init pcibios_resource_survey(void)
1400{
Nathan Fontenote90a1312008-10-27 19:48:17 +00001401 struct pci_bus *b;
1402
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +00001403 /* Allocate and assign resources */
Nathan Fontenote90a1312008-10-27 19:48:17 +00001404 list_for_each_entry(b, &pci_root_buses, node)
1405 pcibios_allocate_bus_resources(b);
Benjamin Herrenschmidt48c2ce92011-11-06 18:55:58 +00001406 pcibios_allocate_resources(0);
1407 pcibios_allocate_resources(1);
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001408
Benjamin Herrenschmidtc1f34302008-11-11 17:45:52 +00001409 /* Before we start assigning unassigned resource, we try to reserve
1410 * the low IO area and the VGA memory area if they intersect the
1411 * bus available resources to avoid allocating things on top of them
1412 */
Rob Herring0e47ff12011-07-12 09:25:51 -05001413 if (!pci_has_flag(PCI_PROBE_ONLY)) {
Benjamin Herrenschmidtc1f34302008-11-11 17:45:52 +00001414 list_for_each_entry(b, &pci_root_buses, node)
1415 pcibios_reserve_legacy_regions(b);
1416 }
1417
1418 /* Now, if the platform didn't decide to blindly trust the firmware,
1419 * we proceed to assigning things that were left unassigned
1420 */
Rob Herring0e47ff12011-07-12 09:25:51 -05001421 if (!pci_has_flag(PCI_PROBE_ONLY)) {
Wolfram Sanga77acda2009-03-09 06:39:01 +00001422 pr_debug("PCI: Assigning unassigned resources...\n");
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001423 pci_assign_unassigned_resources();
1424 }
1425
1426 /* Call machine dependent fixup */
1427 if (ppc_md.pcibios_fixup)
1428 ppc_md.pcibios_fixup();
1429}
1430
1431#ifdef CONFIG_HOTPLUG
Benjamin Herrenschmidt8b8da352008-10-27 19:48:37 +00001432
Benjamin Herrenschmidtfd6852c2008-10-27 19:48:52 +00001433/* This is used by the PCI hotplug driver to allocate resource
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001434 * of newly plugged busses. We can try to consolidate with the
Benjamin Herrenschmidtfd6852c2008-10-27 19:48:52 +00001435 * rest of the code later, for now, keep it as-is as our main
1436 * resource allocation function doesn't deal with sub-trees yet.
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001437 */
Stephen Rothwellbaf75b02009-06-01 14:53:53 +00001438void pcibios_claim_one_bus(struct pci_bus *bus)
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001439{
1440 struct pci_dev *dev;
1441 struct pci_bus *child_bus;
1442
1443 list_for_each_entry(dev, &bus->devices, bus_list) {
1444 int i;
1445
1446 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1447 struct resource *r = &dev->resource[i];
1448
1449 if (r->parent || !r->start || !r->flags)
1450 continue;
Benjamin Herrenschmidtfd6852c2008-10-27 19:48:52 +00001451
1452 pr_debug("PCI: Claiming %s: "
1453 "Resource %d: %016llx..%016llx [%x]\n",
1454 pci_name(dev), i,
1455 (unsigned long long)r->start,
1456 (unsigned long long)r->end,
1457 (unsigned int)r->flags);
1458
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001459 pci_claim_resource(dev, i);
1460 }
1461 }
1462
1463 list_for_each_entry(child_bus, &bus->children, node)
1464 pcibios_claim_one_bus(child_bus);
1465}
Benjamin Herrenschmidtfd6852c2008-10-27 19:48:52 +00001466
1467
1468/* pcibios_finish_adding_to_bus
1469 *
1470 * This is to be called by the hotplug code after devices have been
1471 * added to a bus, this include calling it for a PHB that is just
1472 * being added
1473 */
1474void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1475{
1476 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1477 pci_domain_nr(bus), bus->number);
1478
1479 /* Allocate bus and devices resources */
1480 pcibios_allocate_bus_resources(bus);
1481 pcibios_claim_one_bus(bus);
1482
1483 /* Add new devices to global lists. Register in proc, sysfs. */
1484 pci_bus_add_devices(bus);
1485
1486 /* Fixup EEH */
1487 eeh_add_device_tree_late(bus);
1488}
1489EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1490
Benjamin Herrenschmidt3fd94c62007-12-20 14:54:53 +11001491#endif /* CONFIG_HOTPLUG */
Benjamin Herrenschmidt549beb92007-12-20 14:54:57 +11001492
1493int pcibios_enable_device(struct pci_dev *dev, int mask)
1494{
Benjamin Herrenschmidt549beb92007-12-20 14:54:57 +11001495 if (ppc_md.pcibios_enable_device_hook)
1496 if (ppc_md.pcibios_enable_device_hook(dev))
1497 return -EINVAL;
1498
Bjorn Helgaas7cfb5f92008-03-04 11:56:56 -07001499 return pci_enable_resources(dev, mask);
Benjamin Herrenschmidt549beb92007-12-20 14:54:57 +11001500}
Benjamin Herrenschmidt53280322008-10-27 19:48:29 +00001501
Bjorn Helgaas38973ba2012-03-16 17:48:09 -06001502resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1503{
1504 return (unsigned long) hose->io_base_virt - _IO_BASE;
1505}
1506
Bjorn Helgaas45a709f2011-10-28 16:27:43 -06001507static void __devinit pcibios_setup_phb_resources(struct pci_controller *hose, struct list_head *resources)
Benjamin Herrenschmidt53280322008-10-27 19:48:29 +00001508{
Benjamin Herrenschmidt53280322008-10-27 19:48:29 +00001509 struct resource *res;
1510 int i;
1511
1512 /* Hookup PHB IO resource */
Bjorn Helgaas45a709f2011-10-28 16:27:43 -06001513 res = &hose->io_resource;
Benjamin Herrenschmidt53280322008-10-27 19:48:29 +00001514
1515 if (!res->flags) {
1516 printk(KERN_WARNING "PCI: I/O resource not set for host"
1517 " bridge %s (domain %d)\n",
1518 hose->dn->full_name, hose->global_number);
1519#ifdef CONFIG_PPC32
1520 /* Workaround for lack of IO resource only on 32-bit */
1521 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1522 res->end = res->start + IO_SPACE_LIMIT;
1523 res->flags = IORESOURCE_IO;
1524#endif /* CONFIG_PPC32 */
1525 }
1526
1527 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1528 (unsigned long long)res->start,
1529 (unsigned long long)res->end,
1530 (unsigned long)res->flags);
Bjorn Helgaas38973ba2012-03-16 17:48:09 -06001531 pci_add_resource_offset(resources, res, pcibios_io_space_offset(hose));
Benjamin Herrenschmidt53280322008-10-27 19:48:29 +00001532
1533 /* Hookup PHB Memory resources */
1534 for (i = 0; i < 3; ++i) {
1535 res = &hose->mem_resources[i];
1536 if (!res->flags) {
1537 if (i > 0)
1538 continue;
1539 printk(KERN_ERR "PCI: Memory resource 0 not set for "
1540 "host bridge %s (domain %d)\n",
1541 hose->dn->full_name, hose->global_number);
1542#ifdef CONFIG_PPC32
1543 /* Workaround for lack of MEM resource only on 32-bit */
1544 res->start = hose->pci_mem_offset;
1545 res->end = (resource_size_t)-1LL;
1546 res->flags = IORESOURCE_MEM;
1547#endif /* CONFIG_PPC32 */
1548 }
Benjamin Herrenschmidt53280322008-10-27 19:48:29 +00001549
1550 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", i,
1551 (unsigned long long)res->start,
1552 (unsigned long long)res->end,
1553 (unsigned long)res->flags);
Bjorn Helgaas6c5705f2012-02-23 20:19:03 -07001554 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
Benjamin Herrenschmidt53280322008-10-27 19:48:29 +00001555 }
1556
1557 pr_debug("PCI: PHB MEM offset = %016llx\n",
1558 (unsigned long long)hose->pci_mem_offset);
1559 pr_debug("PCI: PHB IO offset = %08lx\n",
1560 (unsigned long)hose->io_base_virt - _IO_BASE);
1561
1562}
Kumar Gala89c2dd62009-08-25 16:20:45 +00001563
1564/*
1565 * Null PCI config access functions, for the case when we can't
1566 * find a hose.
1567 */
1568#define NULL_PCI_OP(rw, size, type) \
1569static int \
1570null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1571{ \
1572 return PCIBIOS_DEVICE_NOT_FOUND; \
1573}
1574
1575static int
1576null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1577 int len, u32 *val)
1578{
1579 return PCIBIOS_DEVICE_NOT_FOUND;
1580}
1581
1582static int
1583null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1584 int len, u32 val)
1585{
1586 return PCIBIOS_DEVICE_NOT_FOUND;
1587}
1588
1589static struct pci_ops null_pci_ops =
1590{
1591 .read = null_read_config,
1592 .write = null_write_config,
1593};
1594
1595/*
1596 * These functions are used early on before PCI scanning is done
1597 * and all of the pci_dev and pci_bus structures have been created.
1598 */
1599static struct pci_bus *
1600fake_pci_bus(struct pci_controller *hose, int busnr)
1601{
1602 static struct pci_bus bus;
1603
1604 if (hose == 0) {
1605 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1606 }
1607 bus.number = busnr;
1608 bus.sysdata = hose;
1609 bus.ops = hose? hose->ops: &null_pci_ops;
1610 return &bus;
1611}
1612
1613#define EARLY_PCI_OP(rw, size, type) \
1614int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1615 int devfn, int offset, type value) \
1616{ \
1617 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1618 devfn, offset, value); \
1619}
1620
1621EARLY_PCI_OP(read, byte, u8 *)
1622EARLY_PCI_OP(read, word, u16 *)
1623EARLY_PCI_OP(read, dword, u32 *)
1624EARLY_PCI_OP(write, byte, u8)
1625EARLY_PCI_OP(write, word, u16)
1626EARLY_PCI_OP(write, dword, u32)
1627
1628extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
1629int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1630 int cap)
1631{
1632 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1633}
Grant Likely0ed2c7222009-08-28 08:58:16 +00001634
Benjamin Herrenschmidt98d9f30c82011-04-11 11:37:07 +10001635struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1636{
1637 struct pci_controller *hose = bus->sysdata;
1638
1639 return of_node_get(hose->dn);
1640}
1641
Grant Likely0ed2c7222009-08-28 08:58:16 +00001642/**
1643 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1644 * @hose: Pointer to the PCI host controller instance structure
Grant Likely0ed2c7222009-08-28 08:58:16 +00001645 */
Grant Likelyb5d937d2011-02-04 11:24:11 -07001646void __devinit pcibios_scan_phb(struct pci_controller *hose)
Grant Likely0ed2c7222009-08-28 08:58:16 +00001647{
Bjorn Helgaas45a709f2011-10-28 16:27:43 -06001648 LIST_HEAD(resources);
Grant Likely0ed2c7222009-08-28 08:58:16 +00001649 struct pci_bus *bus;
1650 struct device_node *node = hose->dn;
1651 int mode;
1652
Grant Likely74a7f082012-06-15 11:50:25 -06001653 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
Grant Likely0ed2c7222009-08-28 08:58:16 +00001654
Grant Likely0ed2c7222009-08-28 08:58:16 +00001655 /* Get some IO space for the new PHB */
1656 pcibios_setup_phb_io_space(hose);
1657
1658 /* Wire up PHB bus resources */
Bjorn Helgaas45a709f2011-10-28 16:27:43 -06001659 pcibios_setup_phb_resources(hose, &resources);
1660
Yinghai Lube8e60d2012-05-17 18:51:12 -07001661 hose->busn.start = hose->first_busno;
1662 hose->busn.end = hose->last_busno;
1663 hose->busn.flags = IORESOURCE_BUS;
1664 pci_add_resource(&resources, &hose->busn);
1665
Bjorn Helgaas45a709f2011-10-28 16:27:43 -06001666 /* Create an empty bus for the toplevel */
1667 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1668 hose->ops, hose, &resources);
1669 if (bus == NULL) {
1670 pr_err("Failed to create bus for PCI domain %04x\n",
1671 hose->global_number);
1672 pci_free_resource_list(&resources);
1673 return;
1674 }
Bjorn Helgaas45a709f2011-10-28 16:27:43 -06001675 hose->bus = bus;
Grant Likely0ed2c7222009-08-28 08:58:16 +00001676
1677 /* Get probe mode and perform scan */
1678 mode = PCI_PROBE_NORMAL;
1679 if (node && ppc_md.pci_probe_mode)
1680 mode = ppc_md.pci_probe_mode(bus);
1681 pr_debug(" probe mode: %d\n", mode);
Yinghai Lube8e60d2012-05-17 18:51:12 -07001682 if (mode == PCI_PROBE_DEVTREE)
Grant Likely0ed2c7222009-08-28 08:58:16 +00001683 of_scan_bus(node, bus);
Grant Likely0ed2c7222009-08-28 08:58:16 +00001684
Yinghai Lube8e60d2012-05-17 18:51:12 -07001685 if (mode == PCI_PROBE_NORMAL) {
1686 pci_bus_update_busn_res_end(bus, 255);
1687 hose->last_busno = pci_scan_child_bus(bus);
1688 pci_bus_update_busn_res_end(bus, hose->last_busno);
1689 }
Benjamin Herrenschmidt781fb7a2011-09-19 17:44:50 +00001690
Benjamin Herrenschmidt491b98c2011-11-06 18:55:57 +00001691 /* Platform gets a chance to do some global fixups before
1692 * we proceed to resource allocation
1693 */
1694 if (ppc_md.pcibios_fixup_phb)
1695 ppc_md.pcibios_fixup_phb(hose);
1696
Benjamin Herrenschmidt781fb7a2011-09-19 17:44:50 +00001697 /* Configure PCI Express settings */
Benjamin Herrenschmidtbb36c442011-09-26 14:22:39 +10001698 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
Benjamin Herrenschmidt781fb7a2011-09-19 17:44:50 +00001699 struct pci_bus *child;
1700 list_for_each_entry(child, &bus->children, node) {
1701 struct pci_dev *self = child->self;
1702 if (!self)
1703 continue;
1704 pcie_bus_configure_settings(child, self->pcie_mpss);
1705 }
1706 }
Grant Likely0ed2c7222009-08-28 08:58:16 +00001707}
Kumar Galac0654882011-05-19 22:26:18 -05001708
1709static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1710{
1711 int i, class = dev->class >> 8;
Jason Jin05737c72011-10-28 16:08:00 +08001712 /* When configured as agent, programing interface = 1 */
1713 int prog_if = dev->class & 0xf;
Kumar Galac0654882011-05-19 22:26:18 -05001714
1715 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1716 class == PCI_CLASS_BRIDGE_OTHER) &&
1717 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
Jason Jin05737c72011-10-28 16:08:00 +08001718 (prog_if == 0) &&
Kumar Galac0654882011-05-19 22:26:18 -05001719 (dev->bus->parent == NULL)) {
1720 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1721 dev->resource[i].start = 0;
1722 dev->resource[i].end = 0;
1723 dev->resource[i].flags = 0;
1724 }
1725 }
1726}
1727DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1728DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);