blob: ad26fbcfbfc8fb9312bce5682a7050ccc38e0c25 [file] [log] [blame]
Thomas Gleixner52a65ff2018-03-14 22:15:19 +01001// SPDX-License-Identifier: GPL-2.0
Jiang Liuf3cf8bb2014-11-12 11:39:03 +01002/*
Jiang Liuf3cf8bb2014-11-12 11:39:03 +01003 * Copyright (C) 2014 Intel Corp.
4 * Author: Jiang Liu <jiang.liu@linux.intel.com>
5 *
6 * This file is licensed under GPLv2.
7 *
8 * This file contains common code to support Message Signalled Interrupt for
9 * PCI compatible and non PCI compatible devices.
10 */
Jiang Liuaeeb5962014-11-15 22:24:05 +080011#include <linux/types.h>
12#include <linux/device.h>
Jiang Liuf3cf8bb2014-11-12 11:39:03 +010013#include <linux/irq.h>
14#include <linux/irqdomain.h>
15#include <linux/msi.h>
Marc Zyngier4e201562016-11-22 09:21:16 +000016#include <linux/slab.h>
Jiang Liud9109692014-11-15 22:24:04 +080017
Thomas Gleixner07557cc2017-09-13 23:29:05 +020018#include "internals.h"
19
Thomas Gleixner28f4b042016-09-14 16:18:47 +020020/**
21 * alloc_msi_entry - Allocate an initialize msi_entry
22 * @dev: Pointer to the device for which this is allocated
23 * @nvec: The number of vectors used in this entry
24 * @affinity: Optional pointer to an affinity mask array size of @nvec
25 *
Dou Liyangbec04032018-12-04 23:51:20 +080026 * If @affinity is not NULL then an affinity array[@nvec] is allocated
27 * and the affinity masks and flags from @affinity are copied.
Thomas Gleixner28f4b042016-09-14 16:18:47 +020028 */
Dou Liyangbec04032018-12-04 23:51:20 +080029struct msi_desc *alloc_msi_entry(struct device *dev, int nvec,
30 const struct irq_affinity_desc *affinity)
Jiang Liuaa48b6f2015-07-09 16:00:47 +080031{
Thomas Gleixner28f4b042016-09-14 16:18:47 +020032 struct msi_desc *desc;
33
34 desc = kzalloc(sizeof(*desc), GFP_KERNEL);
Jiang Liuaa48b6f2015-07-09 16:00:47 +080035 if (!desc)
36 return NULL;
37
38 INIT_LIST_HEAD(&desc->list);
39 desc->dev = dev;
Thomas Gleixner28f4b042016-09-14 16:18:47 +020040 desc->nvec_used = nvec;
41 if (affinity) {
42 desc->affinity = kmemdup(affinity,
43 nvec * sizeof(*desc->affinity), GFP_KERNEL);
44 if (!desc->affinity) {
45 kfree(desc);
46 return NULL;
47 }
48 }
Jiang Liuaa48b6f2015-07-09 16:00:47 +080049
50 return desc;
51}
52
53void free_msi_entry(struct msi_desc *entry)
54{
Thomas Gleixner28f4b042016-09-14 16:18:47 +020055 kfree(entry->affinity);
Jiang Liuaa48b6f2015-07-09 16:00:47 +080056 kfree(entry);
57}
58
Jiang Liu38b6a1c2014-11-12 12:11:25 +010059void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
60{
61 *msg = entry->msg;
62}
63
64void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
65{
66 struct msi_desc *entry = irq_get_msi_desc(irq);
67
68 __get_cached_msi_msg(entry, msg);
69}
70EXPORT_SYMBOL_GPL(get_cached_msi_msg);
71
Jiang Liuf3cf8bb2014-11-12 11:39:03 +010072#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
Thomas Gleixner74faaf72014-12-06 21:20:20 +010073static inline void irq_chip_write_msi_msg(struct irq_data *data,
74 struct msi_msg *msg)
75{
76 data->chip->irq_write_msi_msg(data, msg);
77}
78
Marc Zyngier0be81532018-05-08 13:14:30 +010079static void msi_check_level(struct irq_domain *domain, struct msi_msg *msg)
80{
81 struct msi_domain_info *info = domain->host_data;
82
83 /*
84 * If the MSI provider has messed with the second message and
85 * not advertized that it is level-capable, signal the breakage.
86 */
87 WARN_ON(!((info->flags & MSI_FLAG_LEVEL_CAPABLE) &&
88 (info->chip->flags & IRQCHIP_SUPPORTS_LEVEL_MSI)) &&
89 (msg[1].address_lo || msg[1].address_hi || msg[1].data));
90}
91
Jiang Liuf3cf8bb2014-11-12 11:39:03 +010092/**
93 * msi_domain_set_affinity - Generic affinity setter function for MSI domains
94 * @irq_data: The irq data associated to the interrupt
95 * @mask: The affinity mask to set
96 * @force: Flag to enforce setting (disable online checks)
97 *
98 * Intended to be used by MSI interrupt controllers which are
99 * implemented with hierarchical domains.
100 */
101int msi_domain_set_affinity(struct irq_data *irq_data,
102 const struct cpumask *mask, bool force)
103{
104 struct irq_data *parent = irq_data->parent_data;
Marc Zyngier0be81532018-05-08 13:14:30 +0100105 struct msi_msg msg[2] = { [1] = { }, };
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100106 int ret;
107
108 ret = parent->chip->irq_set_affinity(parent, mask, force);
109 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
Marc Zyngier0be81532018-05-08 13:14:30 +0100110 BUG_ON(irq_chip_compose_msi_msg(irq_data, msg));
111 msi_check_level(irq_data->domain, msg);
112 irq_chip_write_msi_msg(irq_data, msg);
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100113 }
114
115 return ret;
116}
117
Thomas Gleixner72491642017-09-13 23:29:10 +0200118static int msi_domain_activate(struct irq_domain *domain,
119 struct irq_data *irq_data, bool early)
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100120{
Marc Zyngier0be81532018-05-08 13:14:30 +0100121 struct msi_msg msg[2] = { [1] = { }, };
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100122
Marc Zyngier0be81532018-05-08 13:14:30 +0100123 BUG_ON(irq_chip_compose_msi_msg(irq_data, msg));
124 msi_check_level(irq_data->domain, msg);
125 irq_chip_write_msi_msg(irq_data, msg);
Thomas Gleixner72491642017-09-13 23:29:10 +0200126 return 0;
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100127}
128
129static void msi_domain_deactivate(struct irq_domain *domain,
130 struct irq_data *irq_data)
131{
Marc Zyngier0be81532018-05-08 13:14:30 +0100132 struct msi_msg msg[2];
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100133
Marc Zyngier0be81532018-05-08 13:14:30 +0100134 memset(msg, 0, sizeof(msg));
135 irq_chip_write_msi_msg(irq_data, msg);
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100136}
137
138static int msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
139 unsigned int nr_irqs, void *arg)
140{
141 struct msi_domain_info *info = domain->host_data;
142 struct msi_domain_ops *ops = info->ops;
143 irq_hw_number_t hwirq = ops->get_hwirq(info, arg);
144 int i, ret;
145
146 if (irq_find_mapping(domain, hwirq) > 0)
147 return -EEXIST;
148
Liu Jiangbf6f8692016-01-12 13:18:06 -0700149 if (domain->parent) {
150 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
151 if (ret < 0)
152 return ret;
153 }
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100154
155 for (i = 0; i < nr_irqs; i++) {
156 ret = ops->msi_init(domain, info, virq + i, hwirq + i, arg);
157 if (ret < 0) {
158 if (ops->msi_free) {
159 for (i--; i > 0; i--)
160 ops->msi_free(domain, info, virq + i);
161 }
162 irq_domain_free_irqs_top(domain, virq, nr_irqs);
163 return ret;
164 }
165 }
166
167 return 0;
168}
169
170static void msi_domain_free(struct irq_domain *domain, unsigned int virq,
171 unsigned int nr_irqs)
172{
173 struct msi_domain_info *info = domain->host_data;
174 int i;
175
176 if (info->ops->msi_free) {
177 for (i = 0; i < nr_irqs; i++)
178 info->ops->msi_free(domain, info, virq + i);
179 }
180 irq_domain_free_irqs_top(domain, virq, nr_irqs);
181}
182
Krzysztof Kozlowski01364022015-04-27 21:54:23 +0900183static const struct irq_domain_ops msi_domain_ops = {
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100184 .alloc = msi_domain_alloc,
185 .free = msi_domain_free,
186 .activate = msi_domain_activate,
187 .deactivate = msi_domain_deactivate,
188};
189
Jiang Liuaeeb5962014-11-15 22:24:05 +0800190#ifdef GENERIC_MSI_DOMAIN_OPS
191static irq_hw_number_t msi_domain_ops_get_hwirq(struct msi_domain_info *info,
192 msi_alloc_info_t *arg)
193{
194 return arg->hwirq;
195}
196
197static int msi_domain_ops_prepare(struct irq_domain *domain, struct device *dev,
198 int nvec, msi_alloc_info_t *arg)
199{
200 memset(arg, 0, sizeof(*arg));
201 return 0;
202}
203
204static void msi_domain_ops_set_desc(msi_alloc_info_t *arg,
205 struct msi_desc *desc)
206{
207 arg->desc = desc;
208}
209#else
210#define msi_domain_ops_get_hwirq NULL
211#define msi_domain_ops_prepare NULL
212#define msi_domain_ops_set_desc NULL
213#endif /* !GENERIC_MSI_DOMAIN_OPS */
214
215static int msi_domain_ops_init(struct irq_domain *domain,
216 struct msi_domain_info *info,
217 unsigned int virq, irq_hw_number_t hwirq,
218 msi_alloc_info_t *arg)
219{
220 irq_domain_set_hwirq_and_chip(domain, virq, hwirq, info->chip,
221 info->chip_data);
222 if (info->handler && info->handler_name) {
223 __irq_set_handler(virq, info->handler, 0, info->handler_name);
224 if (info->handler_data)
225 irq_set_handler_data(virq, info->handler_data);
226 }
227 return 0;
228}
229
230static int msi_domain_ops_check(struct irq_domain *domain,
231 struct msi_domain_info *info,
232 struct device *dev)
233{
234 return 0;
235}
236
237static struct msi_domain_ops msi_domain_ops_default = {
238 .get_hwirq = msi_domain_ops_get_hwirq,
239 .msi_init = msi_domain_ops_init,
240 .msi_check = msi_domain_ops_check,
241 .msi_prepare = msi_domain_ops_prepare,
242 .set_desc = msi_domain_ops_set_desc,
243};
244
245static void msi_domain_update_dom_ops(struct msi_domain_info *info)
246{
247 struct msi_domain_ops *ops = info->ops;
248
249 if (ops == NULL) {
250 info->ops = &msi_domain_ops_default;
251 return;
252 }
253
254 if (ops->get_hwirq == NULL)
255 ops->get_hwirq = msi_domain_ops_default.get_hwirq;
256 if (ops->msi_init == NULL)
257 ops->msi_init = msi_domain_ops_default.msi_init;
258 if (ops->msi_check == NULL)
259 ops->msi_check = msi_domain_ops_default.msi_check;
260 if (ops->msi_prepare == NULL)
261 ops->msi_prepare = msi_domain_ops_default.msi_prepare;
262 if (ops->set_desc == NULL)
263 ops->set_desc = msi_domain_ops_default.set_desc;
264}
265
266static void msi_domain_update_chip_ops(struct msi_domain_info *info)
267{
268 struct irq_chip *chip = info->chip;
269
Marc Zyngier0701c532015-10-13 19:14:45 +0100270 BUG_ON(!chip || !chip->irq_mask || !chip->irq_unmask);
Jiang Liuaeeb5962014-11-15 22:24:05 +0800271 if (!chip->irq_set_affinity)
272 chip->irq_set_affinity = msi_domain_set_affinity;
273}
274
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100275/**
276 * msi_create_irq_domain - Create a MSI interrupt domain
Marc Zyngierbe5436c2015-10-13 12:51:44 +0100277 * @fwnode: Optional fwnode of the interrupt controller
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100278 * @info: MSI domain info
279 * @parent: Parent irq domain
280 */
Marc Zyngierbe5436c2015-10-13 12:51:44 +0100281struct irq_domain *msi_create_irq_domain(struct fwnode_handle *fwnode,
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100282 struct msi_domain_info *info,
283 struct irq_domain *parent)
284{
Marc Zyngiera97b8522017-05-12 12:55:37 +0100285 struct irq_domain *domain;
286
Jiang Liuaeeb5962014-11-15 22:24:05 +0800287 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
288 msi_domain_update_dom_ops(info);
289 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
290 msi_domain_update_chip_ops(info);
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100291
Marc Zyngiera97b8522017-05-12 12:55:37 +0100292 domain = irq_domain_create_hierarchy(parent, IRQ_DOMAIN_FLAG_MSI, 0,
293 fwnode, &msi_domain_ops, info);
Thomas Gleixner01653082017-06-20 01:37:04 +0200294
295 if (domain && !domain->name && info->chip)
Marc Zyngiera97b8522017-05-12 12:55:37 +0100296 domain->name = info->chip->name;
297
298 return domain;
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100299}
300
Marc Zyngierb2eba392015-11-23 08:26:05 +0000301int msi_domain_prepare_irqs(struct irq_domain *domain, struct device *dev,
302 int nvec, msi_alloc_info_t *arg)
303{
304 struct msi_domain_info *info = domain->host_data;
305 struct msi_domain_ops *ops = info->ops;
306 int ret;
307
308 ret = ops->msi_check(domain, info, dev);
309 if (ret == 0)
310 ret = ops->msi_prepare(domain, dev, nvec, arg);
311
312 return ret;
313}
314
Marc Zyngier2145ac92015-11-23 08:26:06 +0000315int msi_domain_populate_irqs(struct irq_domain *domain, struct device *dev,
316 int virq, int nvec, msi_alloc_info_t *arg)
317{
318 struct msi_domain_info *info = domain->host_data;
319 struct msi_domain_ops *ops = info->ops;
320 struct msi_desc *desc;
321 int ret = 0;
322
323 for_each_msi_entry(desc, dev) {
324 /* Don't even try the multi-MSI brain damage. */
325 if (WARN_ON(!desc->irq || desc->nvec_used != 1)) {
326 ret = -EINVAL;
327 break;
328 }
329
330 if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
331 continue;
332
333 ops->set_desc(arg, desc);
334 /* Assumes the domain mutex is held! */
John Keeping596a7a12017-09-06 10:35:40 +0100335 ret = irq_domain_alloc_irqs_hierarchy(domain, desc->irq, 1,
336 arg);
Marc Zyngier2145ac92015-11-23 08:26:06 +0000337 if (ret)
338 break;
339
John Keeping596a7a12017-09-06 10:35:40 +0100340 irq_set_msi_desc_off(desc->irq, 0, desc);
Marc Zyngier2145ac92015-11-23 08:26:06 +0000341 }
342
343 if (ret) {
344 /* Mop up the damage */
345 for_each_msi_entry(desc, dev) {
346 if (!(desc->irq >= virq && desc->irq < (virq + nvec)))
347 continue;
348
349 irq_domain_free_irqs_common(domain, desc->irq, 1);
350 }
351 }
352
353 return ret;
354}
355
Thomas Gleixnerbc976232017-12-29 10:47:22 +0100356/*
357 * Carefully check whether the device can use reservation mode. If
358 * reservation mode is enabled then the early activation will assign a
359 * dummy vector to the device. If the PCI/MSI device does not support
360 * masking of the entry then this can result in spurious interrupts when
361 * the device driver is not absolutely careful. But even then a malfunction
362 * of the hardware could result in a spurious interrupt on the dummy vector
363 * and render the device unusable. If the entry can be masked then the core
364 * logic will prevent the spurious interrupt and reservation mode can be
365 * used. For now reservation mode is restricted to PCI/MSI.
366 */
367static bool msi_check_reservation_mode(struct irq_domain *domain,
368 struct msi_domain_info *info,
369 struct device *dev)
Thomas Gleixnerda5dd9e2017-12-29 10:42:10 +0100370{
Thomas Gleixnerbc976232017-12-29 10:47:22 +0100371 struct msi_desc *desc;
372
373 if (domain->bus_token != DOMAIN_BUS_PCI_MSI)
374 return false;
375
Thomas Gleixnerda5dd9e2017-12-29 10:42:10 +0100376 if (!(info->flags & MSI_FLAG_MUST_REACTIVATE))
377 return false;
Thomas Gleixnerbc976232017-12-29 10:47:22 +0100378
379 if (IS_ENABLED(CONFIG_PCI_MSI) && pci_msi_ignore_mask)
380 return false;
381
382 /*
383 * Checking the first MSI descriptor is sufficient. MSIX supports
384 * masking and MSI does so when the maskbit is set.
385 */
386 desc = first_msi_entry(dev);
387 return desc->msi_attrib.is_msix || desc->msi_attrib.maskbit;
Thomas Gleixnerda5dd9e2017-12-29 10:42:10 +0100388}
389
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100390/**
Jiang Liud9109692014-11-15 22:24:04 +0800391 * msi_domain_alloc_irqs - Allocate interrupts from a MSI interrupt domain
392 * @domain: The domain to allocate from
393 * @dev: Pointer to device struct of the device for which the interrupts
394 * are allocated
395 * @nvec: The number of interrupts to allocate
396 *
397 * Returns 0 on success or an error code.
398 */
399int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev,
400 int nvec)
401{
402 struct msi_domain_info *info = domain->host_data;
403 struct msi_domain_ops *ops = info->ops;
Thomas Gleixnerda5dd9e2017-12-29 10:42:10 +0100404 struct irq_data *irq_data;
Jiang Liud9109692014-11-15 22:24:04 +0800405 struct msi_desc *desc;
Thomas Gleixnerda5dd9e2017-12-29 10:42:10 +0100406 msi_alloc_info_t arg;
Thomas Gleixnerb6140912016-07-04 17:39:22 +0900407 int i, ret, virq;
Thomas Gleixnerda5dd9e2017-12-29 10:42:10 +0100408 bool can_reserve;
Jiang Liud9109692014-11-15 22:24:04 +0800409
Marc Zyngierb2eba392015-11-23 08:26:05 +0000410 ret = msi_domain_prepare_irqs(domain, dev, nvec, &arg);
Jiang Liud9109692014-11-15 22:24:04 +0800411 if (ret)
412 return ret;
413
414 for_each_msi_entry(desc, dev) {
415 ops->set_desc(&arg, desc);
416
Thomas Gleixnerb6140912016-07-04 17:39:22 +0900417 virq = __irq_domain_alloc_irqs(domain, -1, desc->nvec_used,
Thomas Gleixner06ee6d52016-07-04 17:39:24 +0900418 dev_to_node(dev), &arg, false,
Thomas Gleixner0972fa52016-07-04 17:39:26 +0900419 desc->affinity);
Jiang Liud9109692014-11-15 22:24:04 +0800420 if (virq < 0) {
421 ret = -ENOSPC;
422 if (ops->handle_error)
423 ret = ops->handle_error(domain, desc, ret);
424 if (ops->msi_finish)
425 ops->msi_finish(&arg, ret);
426 return ret;
427 }
428
Thomas Gleixner07557cc2017-09-13 23:29:05 +0200429 for (i = 0; i < desc->nvec_used; i++) {
Jiang Liud9109692014-11-15 22:24:04 +0800430 irq_set_msi_desc_off(virq, i, desc);
Thomas Gleixner07557cc2017-09-13 23:29:05 +0200431 irq_debugfs_copy_devname(virq + i, dev);
432 }
Jiang Liud9109692014-11-15 22:24:04 +0800433 }
434
435 if (ops->msi_finish)
436 ops->msi_finish(&arg, 0);
437
Thomas Gleixnerbc976232017-12-29 10:47:22 +0100438 can_reserve = msi_check_reservation_mode(domain, info, dev);
Thomas Gleixnerda5dd9e2017-12-29 10:42:10 +0100439
Jiang Liud9109692014-11-15 22:24:04 +0800440 for_each_msi_entry(desc, dev) {
Thomas Gleixner4364e1a2016-07-04 15:32:25 +0200441 virq = desc->irq;
Jiang Liud9109692014-11-15 22:24:04 +0800442 if (desc->nvec_used == 1)
443 dev_dbg(dev, "irq %d for MSI\n", virq);
444 else
445 dev_dbg(dev, "irq [%d-%d] for MSI\n",
446 virq, virq + desc->nvec_used - 1);
Marc Zyngierf3b09462016-07-13 17:18:33 +0100447 /*
448 * This flag is set by the PCI layer as we need to activate
449 * the MSI entries before the PCI layer enables MSI in the
450 * card. Otherwise the card latches a random msi message.
451 */
Thomas Gleixnerda5dd9e2017-12-29 10:42:10 +0100452 if (!(info->flags & MSI_FLAG_ACTIVATE_EARLY))
453 continue;
Marc Zyngierf3b09462016-07-13 17:18:33 +0100454
Thomas Gleixnerda5dd9e2017-12-29 10:42:10 +0100455 irq_data = irq_domain_get_irq_data(domain, desc->irq);
Thomas Gleixnerbc976232017-12-29 10:47:22 +0100456 if (!can_reserve)
457 irqd_clr_can_reserve(irq_data);
458 ret = irq_domain_activate_irq(irq_data, can_reserve);
Thomas Gleixnerda5dd9e2017-12-29 10:42:10 +0100459 if (ret)
460 goto cleanup;
461 }
462
463 /*
464 * If these interrupts use reservation mode, clear the activated bit
465 * so request_irq() will assign the final vector.
466 */
467 if (can_reserve) {
468 for_each_msi_entry(desc, dev) {
Marc Zyngierf3b09462016-07-13 17:18:33 +0100469 irq_data = irq_domain_get_irq_data(domain, desc->irq);
Thomas Gleixnerda5dd9e2017-12-29 10:42:10 +0100470 irqd_clr_activated(irq_data);
Marc Zyngierf3b09462016-07-13 17:18:33 +0100471 }
Jiang Liud9109692014-11-15 22:24:04 +0800472 }
Jiang Liud9109692014-11-15 22:24:04 +0800473 return 0;
Thomas Gleixnerbb9b4282017-09-13 23:29:11 +0200474
475cleanup:
476 for_each_msi_entry(desc, dev) {
477 struct irq_data *irqd;
478
479 if (desc->irq == virq)
480 break;
481
482 irqd = irq_domain_get_irq_data(domain, desc->irq);
483 if (irqd_is_activated(irqd))
484 irq_domain_deactivate_irq(irqd);
485 }
486 msi_domain_free_irqs(domain, dev);
487 return ret;
Jiang Liud9109692014-11-15 22:24:04 +0800488}
489
490/**
491 * msi_domain_free_irqs - Free interrupts from a MSI interrupt @domain associated tp @dev
492 * @domain: The domain to managing the interrupts
493 * @dev: Pointer to device struct of the device for which the interrupts
494 * are free
495 */
496void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev)
497{
498 struct msi_desc *desc;
499
500 for_each_msi_entry(desc, dev) {
Marc Zyngierfe0c52f2015-01-26 19:10:19 +0000501 /*
502 * We might have failed to allocate an MSI early
503 * enough that there is no IRQ associated to this
504 * entry. If that's the case, don't do anything.
505 */
506 if (desc->irq) {
507 irq_domain_free_irqs(desc->irq, desc->nvec_used);
508 desc->irq = 0;
509 }
Jiang Liud9109692014-11-15 22:24:04 +0800510 }
511}
512
513/**
Jiang Liuf3cf8bb2014-11-12 11:39:03 +0100514 * msi_get_domain_info - Get the MSI interrupt domain info for @domain
515 * @domain: The interrupt domain to retrieve data from
516 *
517 * Returns the pointer to the msi_domain_info stored in
518 * @domain->host_data.
519 */
520struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain)
521{
522 return (struct msi_domain_info *)domain->host_data;
523}
524
525#endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */