Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/kernel/irq/msi.c |
| 3 | * |
| 4 | * Copyright (C) 2014 Intel Corp. |
| 5 | * Author: Jiang Liu <jiang.liu@linux.intel.com> |
| 6 | * |
| 7 | * This file is licensed under GPLv2. |
| 8 | * |
| 9 | * This file contains common code to support Message Signalled Interrupt for |
| 10 | * PCI compatible and non PCI compatible devices. |
| 11 | */ |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame^] | 12 | #include <linux/types.h> |
| 13 | #include <linux/device.h> |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 14 | #include <linux/irq.h> |
| 15 | #include <linux/irqdomain.h> |
| 16 | #include <linux/msi.h> |
| 17 | |
Jiang Liu | d910969 | 2014-11-15 22:24:04 +0800 | [diff] [blame] | 18 | /* Temparory solution for building, will be removed later */ |
| 19 | #include <linux/pci.h> |
| 20 | |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 21 | #ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN |
| 22 | /** |
| 23 | * msi_domain_set_affinity - Generic affinity setter function for MSI domains |
| 24 | * @irq_data: The irq data associated to the interrupt |
| 25 | * @mask: The affinity mask to set |
| 26 | * @force: Flag to enforce setting (disable online checks) |
| 27 | * |
| 28 | * Intended to be used by MSI interrupt controllers which are |
| 29 | * implemented with hierarchical domains. |
| 30 | */ |
| 31 | int msi_domain_set_affinity(struct irq_data *irq_data, |
| 32 | const struct cpumask *mask, bool force) |
| 33 | { |
| 34 | struct irq_data *parent = irq_data->parent_data; |
| 35 | struct msi_msg msg; |
| 36 | int ret; |
| 37 | |
| 38 | ret = parent->chip->irq_set_affinity(parent, mask, force); |
| 39 | if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) { |
| 40 | BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg)); |
| 41 | irq_chip_write_msi_msg(irq_data, &msg); |
| 42 | } |
| 43 | |
| 44 | return ret; |
| 45 | } |
| 46 | |
| 47 | static void msi_domain_activate(struct irq_domain *domain, |
| 48 | struct irq_data *irq_data) |
| 49 | { |
| 50 | struct msi_msg msg; |
| 51 | |
| 52 | BUG_ON(irq_chip_compose_msi_msg(irq_data, &msg)); |
| 53 | irq_chip_write_msi_msg(irq_data, &msg); |
| 54 | } |
| 55 | |
| 56 | static void msi_domain_deactivate(struct irq_domain *domain, |
| 57 | struct irq_data *irq_data) |
| 58 | { |
| 59 | struct msi_msg msg; |
| 60 | |
| 61 | memset(&msg, 0, sizeof(msg)); |
| 62 | irq_chip_write_msi_msg(irq_data, &msg); |
| 63 | } |
| 64 | |
| 65 | static int msi_domain_alloc(struct irq_domain *domain, unsigned int virq, |
| 66 | unsigned int nr_irqs, void *arg) |
| 67 | { |
| 68 | struct msi_domain_info *info = domain->host_data; |
| 69 | struct msi_domain_ops *ops = info->ops; |
| 70 | irq_hw_number_t hwirq = ops->get_hwirq(info, arg); |
| 71 | int i, ret; |
| 72 | |
| 73 | if (irq_find_mapping(domain, hwirq) > 0) |
| 74 | return -EEXIST; |
| 75 | |
| 76 | ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
| 77 | if (ret < 0) |
| 78 | return ret; |
| 79 | |
| 80 | for (i = 0; i < nr_irqs; i++) { |
| 81 | ret = ops->msi_init(domain, info, virq + i, hwirq + i, arg); |
| 82 | if (ret < 0) { |
| 83 | if (ops->msi_free) { |
| 84 | for (i--; i > 0; i--) |
| 85 | ops->msi_free(domain, info, virq + i); |
| 86 | } |
| 87 | irq_domain_free_irqs_top(domain, virq, nr_irqs); |
| 88 | return ret; |
| 89 | } |
| 90 | } |
| 91 | |
| 92 | return 0; |
| 93 | } |
| 94 | |
| 95 | static void msi_domain_free(struct irq_domain *domain, unsigned int virq, |
| 96 | unsigned int nr_irqs) |
| 97 | { |
| 98 | struct msi_domain_info *info = domain->host_data; |
| 99 | int i; |
| 100 | |
| 101 | if (info->ops->msi_free) { |
| 102 | for (i = 0; i < nr_irqs; i++) |
| 103 | info->ops->msi_free(domain, info, virq + i); |
| 104 | } |
| 105 | irq_domain_free_irqs_top(domain, virq, nr_irqs); |
| 106 | } |
| 107 | |
| 108 | static struct irq_domain_ops msi_domain_ops = { |
| 109 | .alloc = msi_domain_alloc, |
| 110 | .free = msi_domain_free, |
| 111 | .activate = msi_domain_activate, |
| 112 | .deactivate = msi_domain_deactivate, |
| 113 | }; |
| 114 | |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame^] | 115 | #ifdef GENERIC_MSI_DOMAIN_OPS |
| 116 | static irq_hw_number_t msi_domain_ops_get_hwirq(struct msi_domain_info *info, |
| 117 | msi_alloc_info_t *arg) |
| 118 | { |
| 119 | return arg->hwirq; |
| 120 | } |
| 121 | |
| 122 | static int msi_domain_ops_prepare(struct irq_domain *domain, struct device *dev, |
| 123 | int nvec, msi_alloc_info_t *arg) |
| 124 | { |
| 125 | memset(arg, 0, sizeof(*arg)); |
| 126 | return 0; |
| 127 | } |
| 128 | |
| 129 | static void msi_domain_ops_set_desc(msi_alloc_info_t *arg, |
| 130 | struct msi_desc *desc) |
| 131 | { |
| 132 | arg->desc = desc; |
| 133 | } |
| 134 | #else |
| 135 | #define msi_domain_ops_get_hwirq NULL |
| 136 | #define msi_domain_ops_prepare NULL |
| 137 | #define msi_domain_ops_set_desc NULL |
| 138 | #endif /* !GENERIC_MSI_DOMAIN_OPS */ |
| 139 | |
| 140 | static int msi_domain_ops_init(struct irq_domain *domain, |
| 141 | struct msi_domain_info *info, |
| 142 | unsigned int virq, irq_hw_number_t hwirq, |
| 143 | msi_alloc_info_t *arg) |
| 144 | { |
| 145 | irq_domain_set_hwirq_and_chip(domain, virq, hwirq, info->chip, |
| 146 | info->chip_data); |
| 147 | if (info->handler && info->handler_name) { |
| 148 | __irq_set_handler(virq, info->handler, 0, info->handler_name); |
| 149 | if (info->handler_data) |
| 150 | irq_set_handler_data(virq, info->handler_data); |
| 151 | } |
| 152 | return 0; |
| 153 | } |
| 154 | |
| 155 | static int msi_domain_ops_check(struct irq_domain *domain, |
| 156 | struct msi_domain_info *info, |
| 157 | struct device *dev) |
| 158 | { |
| 159 | return 0; |
| 160 | } |
| 161 | |
| 162 | static struct msi_domain_ops msi_domain_ops_default = { |
| 163 | .get_hwirq = msi_domain_ops_get_hwirq, |
| 164 | .msi_init = msi_domain_ops_init, |
| 165 | .msi_check = msi_domain_ops_check, |
| 166 | .msi_prepare = msi_domain_ops_prepare, |
| 167 | .set_desc = msi_domain_ops_set_desc, |
| 168 | }; |
| 169 | |
| 170 | static void msi_domain_update_dom_ops(struct msi_domain_info *info) |
| 171 | { |
| 172 | struct msi_domain_ops *ops = info->ops; |
| 173 | |
| 174 | if (ops == NULL) { |
| 175 | info->ops = &msi_domain_ops_default; |
| 176 | return; |
| 177 | } |
| 178 | |
| 179 | if (ops->get_hwirq == NULL) |
| 180 | ops->get_hwirq = msi_domain_ops_default.get_hwirq; |
| 181 | if (ops->msi_init == NULL) |
| 182 | ops->msi_init = msi_domain_ops_default.msi_init; |
| 183 | if (ops->msi_check == NULL) |
| 184 | ops->msi_check = msi_domain_ops_default.msi_check; |
| 185 | if (ops->msi_prepare == NULL) |
| 186 | ops->msi_prepare = msi_domain_ops_default.msi_prepare; |
| 187 | if (ops->set_desc == NULL) |
| 188 | ops->set_desc = msi_domain_ops_default.set_desc; |
| 189 | } |
| 190 | |
| 191 | static void msi_domain_update_chip_ops(struct msi_domain_info *info) |
| 192 | { |
| 193 | struct irq_chip *chip = info->chip; |
| 194 | |
| 195 | BUG_ON(!chip); |
| 196 | if (!chip->irq_mask) |
| 197 | chip->irq_mask = pci_msi_mask_irq; |
| 198 | if (!chip->irq_unmask) |
| 199 | chip->irq_unmask = pci_msi_unmask_irq; |
| 200 | if (!chip->irq_set_affinity) |
| 201 | chip->irq_set_affinity = msi_domain_set_affinity; |
| 202 | } |
| 203 | |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 204 | /** |
| 205 | * msi_create_irq_domain - Create a MSI interrupt domain |
| 206 | * @of_node: Optional device-tree node of the interrupt controller |
| 207 | * @info: MSI domain info |
| 208 | * @parent: Parent irq domain |
| 209 | */ |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame^] | 210 | struct irq_domain *msi_create_irq_domain(struct device_node *node, |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 211 | struct msi_domain_info *info, |
| 212 | struct irq_domain *parent) |
| 213 | { |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame^] | 214 | if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS) |
| 215 | msi_domain_update_dom_ops(info); |
| 216 | if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS) |
| 217 | msi_domain_update_chip_ops(info); |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 218 | |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame^] | 219 | return irq_domain_add_hierarchy(parent, 0, 0, node, &msi_domain_ops, |
| 220 | info); |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 221 | } |
| 222 | |
| 223 | /** |
Jiang Liu | d910969 | 2014-11-15 22:24:04 +0800 | [diff] [blame] | 224 | * msi_domain_alloc_irqs - Allocate interrupts from a MSI interrupt domain |
| 225 | * @domain: The domain to allocate from |
| 226 | * @dev: Pointer to device struct of the device for which the interrupts |
| 227 | * are allocated |
| 228 | * @nvec: The number of interrupts to allocate |
| 229 | * |
| 230 | * Returns 0 on success or an error code. |
| 231 | */ |
| 232 | int msi_domain_alloc_irqs(struct irq_domain *domain, struct device *dev, |
| 233 | int nvec) |
| 234 | { |
| 235 | struct msi_domain_info *info = domain->host_data; |
| 236 | struct msi_domain_ops *ops = info->ops; |
| 237 | msi_alloc_info_t arg; |
| 238 | struct msi_desc *desc; |
| 239 | int i, ret, virq = -1; |
| 240 | |
| 241 | ret = ops->msi_check(domain, info, dev); |
| 242 | if (ret == 0) |
| 243 | ret = ops->msi_prepare(domain, dev, nvec, &arg); |
| 244 | if (ret) |
| 245 | return ret; |
| 246 | |
| 247 | for_each_msi_entry(desc, dev) { |
| 248 | ops->set_desc(&arg, desc); |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame^] | 249 | if (info->flags & MSI_FLAG_IDENTITY_MAP) |
| 250 | virq = (int)ops->get_hwirq(info, &arg); |
| 251 | else |
| 252 | virq = -1; |
Jiang Liu | d910969 | 2014-11-15 22:24:04 +0800 | [diff] [blame] | 253 | |
Jiang Liu | aeeb596 | 2014-11-15 22:24:05 +0800 | [diff] [blame^] | 254 | virq = __irq_domain_alloc_irqs(domain, virq, desc->nvec_used, |
Jiang Liu | d910969 | 2014-11-15 22:24:04 +0800 | [diff] [blame] | 255 | dev_to_node(dev), &arg, false); |
| 256 | if (virq < 0) { |
| 257 | ret = -ENOSPC; |
| 258 | if (ops->handle_error) |
| 259 | ret = ops->handle_error(domain, desc, ret); |
| 260 | if (ops->msi_finish) |
| 261 | ops->msi_finish(&arg, ret); |
| 262 | return ret; |
| 263 | } |
| 264 | |
| 265 | for (i = 0; i < desc->nvec_used; i++) |
| 266 | irq_set_msi_desc_off(virq, i, desc); |
| 267 | } |
| 268 | |
| 269 | if (ops->msi_finish) |
| 270 | ops->msi_finish(&arg, 0); |
| 271 | |
| 272 | for_each_msi_entry(desc, dev) { |
| 273 | if (desc->nvec_used == 1) |
| 274 | dev_dbg(dev, "irq %d for MSI\n", virq); |
| 275 | else |
| 276 | dev_dbg(dev, "irq [%d-%d] for MSI\n", |
| 277 | virq, virq + desc->nvec_used - 1); |
| 278 | } |
| 279 | |
| 280 | return 0; |
| 281 | } |
| 282 | |
| 283 | /** |
| 284 | * msi_domain_free_irqs - Free interrupts from a MSI interrupt @domain associated tp @dev |
| 285 | * @domain: The domain to managing the interrupts |
| 286 | * @dev: Pointer to device struct of the device for which the interrupts |
| 287 | * are free |
| 288 | */ |
| 289 | void msi_domain_free_irqs(struct irq_domain *domain, struct device *dev) |
| 290 | { |
| 291 | struct msi_desc *desc; |
| 292 | |
| 293 | for_each_msi_entry(desc, dev) { |
| 294 | irq_domain_free_irqs(desc->irq, desc->nvec_used); |
| 295 | desc->irq = 0; |
| 296 | } |
| 297 | } |
| 298 | |
| 299 | /** |
Jiang Liu | f3cf8bb | 2014-11-12 11:39:03 +0100 | [diff] [blame] | 300 | * msi_get_domain_info - Get the MSI interrupt domain info for @domain |
| 301 | * @domain: The interrupt domain to retrieve data from |
| 302 | * |
| 303 | * Returns the pointer to the msi_domain_info stored in |
| 304 | * @domain->host_data. |
| 305 | */ |
| 306 | struct msi_domain_info *msi_get_domain_info(struct irq_domain *domain) |
| 307 | { |
| 308 | return (struct msi_domain_info *)domain->host_data; |
| 309 | } |
| 310 | |
| 311 | #endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */ |