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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / 7295493682aaa68e0826b61af4b88941363075ca / . / drivers / scsi / pm8001 / pm80xx_hwi.c
blob: 5ca9732f4704a0e988a8987473cbbab4dcb81941 [file] [log] [blame]
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1/*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
peter chang3e253d92019-11-14 15:39:07 +0530[diff] [blame]40 #include <linux/version.h>
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]41 #include <linux/slab.h>
42 #include "pm8001_sas.h"
43 #include "pm80xx_hwi.h"
44 #include "pm8001_chips.h"
45 #include "pm8001_ctl.h"
46
47#define SMP_DIRECT 1
48#define SMP_INDIRECT 2
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]49
50
51int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
52{
53 u32 reg_val;
54 unsigned long start;
55 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
56 /* confirm the setting is written */
57 start = jiffies + HZ; /* 1 sec */
58 do {
59 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
60 } while ((reg_val != shift_value) && time_before(jiffies, start));
61 if (reg_val != shift_value) {
62 PM8001_FAIL_DBG(pm8001_ha,
63 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
64 " = 0x%x\n", reg_val));
65 return -1;
66 }
67 return 0;
68}
69
70void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset,
71 const void *destination,
72 u32 dw_count, u32 bus_base_number)
73{
74 u32 index, value, offset;
75 u32 *destination1;
76 destination1 = (u32 *)destination;
77
78 for (index = 0; index < dw_count; index += 4, destination1++) {
79 offset = (soffset + index / 4);
80 if (offset < (64 * 1024)) {
81 value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
82 *destination1 = cpu_to_le32(value);
83 }
84 }
85 return;
86}
87
88ssize_t pm80xx_get_fatal_dump(struct device *cdev,
89 struct device_attribute *attr, char *buf)
90{
91 struct Scsi_Host *shost = class_to_shost(cdev);
92 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
93 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
94 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]95 u32 accum_len , reg_val, index, *temp;
96 unsigned long start;
97 u8 *direct_data;
98 char *fatal_error_data = buf;
99
100 pm8001_ha->forensic_info.data_buf.direct_data = buf;
101 if (pm8001_ha->chip_id == chip_8001) {
102 pm8001_ha->forensic_info.data_buf.direct_data +=
103 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
104 "Not supported for SPC controller");
105 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
106 (char *)buf;
107 }
108 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
109 PM8001_IO_DBG(pm8001_ha,
110 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
111 direct_data = (u8 *)fatal_error_data;
112 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
113 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]114 pm8001_ha->forensic_info.data_buf.read_len = 0;
115
116 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]117
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]118 /* start to get data */
119 /* Program the MEMBASE II Shifting Register with 0x00.*/
120 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
121 pm8001_ha->fatal_forensic_shift_offset);
122 pm8001_ha->forensic_last_offset = 0;
123 pm8001_ha->forensic_fatal_step = 0;
124 pm8001_ha->fatal_bar_loc = 0;
125 }
Viswas Gcf370062013-12-10 10:31:38 +0530[diff] [blame]126
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]127 /* Read until accum_len is retrived */
128 accum_len = pm8001_mr32(fatal_table_address,
129 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
130 PM8001_IO_DBG(pm8001_ha, pm8001_printk("accum_len 0x%x\n",
131 accum_len));
132 if (accum_len == 0xFFFFFFFF) {
133 PM8001_IO_DBG(pm8001_ha,
134 pm8001_printk("Possible PCI issue 0x%x not expected\n",
135 accum_len));
Viswas Gcf370062013-12-10 10:31:38 +0530[diff] [blame]136 return -EIO;
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]137 }
138 if (accum_len == 0 || accum_len >= 0x100000) {
139 pm8001_ha->forensic_info.data_buf.direct_data +=
140 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
141 "%08x ", 0xFFFFFFFF);
142 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
143 (char *)buf;
144 }
145 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
146 if (pm8001_ha->forensic_fatal_step == 0) {
147moreData:
148 if (pm8001_ha->forensic_info.data_buf.direct_data) {
149 /* Data is in bar, copy to host memory */
150 pm80xx_pci_mem_copy(pm8001_ha, pm8001_ha->fatal_bar_loc,
151 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
152 pm8001_ha->forensic_info.data_buf.direct_len ,
153 1);
154 }
155 pm8001_ha->fatal_bar_loc +=
156 pm8001_ha->forensic_info.data_buf.direct_len;
157 pm8001_ha->forensic_info.data_buf.direct_offset +=
158 pm8001_ha->forensic_info.data_buf.direct_len;
159 pm8001_ha->forensic_last_offset +=
160 pm8001_ha->forensic_info.data_buf.direct_len;
161 pm8001_ha->forensic_info.data_buf.read_len =
162 pm8001_ha->forensic_info.data_buf.direct_len;
163
164 if (pm8001_ha->forensic_last_offset >= accum_len) {
165 pm8001_ha->forensic_info.data_buf.direct_data +=
166 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
167 "%08x ", 3);
168 for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
169 pm8001_ha->forensic_info.data_buf.direct_data +=
170 sprintf(pm8001_ha->
171 forensic_info.data_buf.direct_data,
172 "%08x ", *(temp + index));
173 }
174
175 pm8001_ha->fatal_bar_loc = 0;
176 pm8001_ha->forensic_fatal_step = 1;
177 pm8001_ha->fatal_forensic_shift_offset = 0;
178 pm8001_ha->forensic_last_offset = 0;
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]179 return (char *)pm8001_ha->
180 forensic_info.data_buf.direct_data -
181 (char *)buf;
182 }
183 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
184 pm8001_ha->forensic_info.data_buf.direct_data +=
185 sprintf(pm8001_ha->
186 forensic_info.data_buf.direct_data,
187 "%08x ", 2);
188 for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
189 pm8001_ha->forensic_info.data_buf.direct_data +=
190 sprintf(pm8001_ha->
191 forensic_info.data_buf.direct_data,
192 "%08x ", *(temp + index));
193 }
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]194 return (char *)pm8001_ha->
195 forensic_info.data_buf.direct_data -
196 (char *)buf;
197 }
198
199 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
200 pm8001_ha->forensic_info.data_buf.direct_data +=
201 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
202 "%08x ", 2);
203 for (index = 0; index < 256; index++) {
204 pm8001_ha->forensic_info.data_buf.direct_data +=
205 sprintf(pm8001_ha->
206 forensic_info.data_buf.direct_data,
207 "%08x ", *(temp + index));
208 }
209 pm8001_ha->fatal_forensic_shift_offset += 0x100;
210 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
211 pm8001_ha->fatal_forensic_shift_offset);
212 pm8001_ha->fatal_bar_loc = 0;
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]213 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
214 (char *)buf;
215 }
216 if (pm8001_ha->forensic_fatal_step == 1) {
217 pm8001_ha->fatal_forensic_shift_offset = 0;
218 /* Read 64K of the debug data. */
219 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
220 pm8001_ha->fatal_forensic_shift_offset);
221 pm8001_mw32(fatal_table_address,
222 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
223 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
224
225 /* Poll FDDHSHK until clear */
226 start = jiffies + (2 * HZ); /* 2 sec */
227
228 do {
229 reg_val = pm8001_mr32(fatal_table_address,
230 MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
231 } while ((reg_val) && time_before(jiffies, start));
232
233 if (reg_val != 0) {
234 PM8001_FAIL_DBG(pm8001_ha,
235 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
236 " = 0x%x\n", reg_val));
Viswas Gcf370062013-12-10 10:31:38 +0530[diff] [blame]237 return -EIO;
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]238 }
239
240 /* Read the next 64K of the debug data. */
241 pm8001_ha->forensic_fatal_step = 0;
242 if (pm8001_mr32(fatal_table_address,
243 MPI_FATAL_EDUMP_TABLE_STATUS) !=
244 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
245 pm8001_mw32(fatal_table_address,
246 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 0);
247 goto moreData;
248 } else {
249 pm8001_ha->forensic_info.data_buf.direct_data +=
250 sprintf(pm8001_ha->
251 forensic_info.data_buf.direct_data,
252 "%08x ", 4);
253 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
254 pm8001_ha->forensic_info.data_buf.direct_len = 0;
255 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
256 pm8001_ha->forensic_info.data_buf.read_len = 0;
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]257 }
258 }
259
260 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
261 (char *)buf;
262}
263
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]264/**
265 * read_main_config_table - read the configure table and save it.
266 * @pm8001_ha: our hba card information
267 */
268static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
269{
270 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
271
272 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
273 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
274 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
275 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
276 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
277 pm8001_mr32(address, MAIN_FW_REVISION);
278 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
279 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
280 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
281 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
282 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
283 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
284 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
285 pm8001_mr32(address, MAIN_GST_OFFSET);
286 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
287 pm8001_mr32(address, MAIN_IBQ_OFFSET);
288 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
289 pm8001_mr32(address, MAIN_OBQ_OFFSET);
290
291 /* read Error Dump Offset and Length */
292 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
293 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
294 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
295 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
296 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
297 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
298 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
299 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
300
301 /* read GPIO LED settings from the configuration table */
302 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
303 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
304
305 /* read analog Setting offset from the configuration table */
306 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
307 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
308
309 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
310 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
311 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
312 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]313 /* read port recover and reset timeout */
314 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
315 pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
Viswas G24fff012017-10-18 11:39:08 +0530[diff] [blame]316 /* read ILA and inactive firmware version */
317 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
318 pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
319 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
320 pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]321
322 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
323 "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n",
324 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
325 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
326 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev));
327
328 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
329 "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n",
330 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
331 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
332 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
333 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
334 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset));
335
336 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
337 "Main cfg table; ila rev:%x Inactive fw rev:%x\n",
338 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
339 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]340}
341
342/**
343 * read_general_status_table - read the general status table and save it.
344 * @pm8001_ha: our hba card information
345 */
346static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
347{
348 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
349 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
350 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
351 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
352 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
353 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
354 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
355 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
356 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
357 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
358 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
359 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
360 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
361 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
362 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
363 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
364 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
365 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
366 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
367 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
368 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
369 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
370 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
371 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
372 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
373 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
374 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
375 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
376 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
377}
378/**
379 * read_phy_attr_table - read the phy attribute table and save it.
380 * @pm8001_ha: our hba card information
381 */
382static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
383{
384 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
385 pm8001_ha->phy_attr_table.phystart1_16[0] =
386 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
387 pm8001_ha->phy_attr_table.phystart1_16[1] =
388 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
389 pm8001_ha->phy_attr_table.phystart1_16[2] =
390 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
391 pm8001_ha->phy_attr_table.phystart1_16[3] =
392 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
393 pm8001_ha->phy_attr_table.phystart1_16[4] =
394 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
395 pm8001_ha->phy_attr_table.phystart1_16[5] =
396 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
397 pm8001_ha->phy_attr_table.phystart1_16[6] =
398 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
399 pm8001_ha->phy_attr_table.phystart1_16[7] =
400 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
401 pm8001_ha->phy_attr_table.phystart1_16[8] =
402 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
403 pm8001_ha->phy_attr_table.phystart1_16[9] =
404 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
405 pm8001_ha->phy_attr_table.phystart1_16[10] =
406 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
407 pm8001_ha->phy_attr_table.phystart1_16[11] =
408 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
409 pm8001_ha->phy_attr_table.phystart1_16[12] =
410 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
411 pm8001_ha->phy_attr_table.phystart1_16[13] =
412 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
413 pm8001_ha->phy_attr_table.phystart1_16[14] =
414 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
415 pm8001_ha->phy_attr_table.phystart1_16[15] =
416 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
417
418 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
419 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
420 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
421 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
422 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
423 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
424 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
425 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
426 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
427 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
428 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
429 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
430 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
431 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
432 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
433 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
434 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
435 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
436 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
437 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
438 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
439 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
440 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
441 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
442 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
443 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
444 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
445 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
446 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
447 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
448 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
449 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
450
451}
452
453/**
454 * read_inbnd_queue_table - read the inbound queue table and save it.
455 * @pm8001_ha: our hba card information
456 */
457static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
458{
459 int i;
460 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
461 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
462 u32 offset = i * 0x20;
463 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
464 get_pci_bar_index(pm8001_mr32(address,
465 (offset + IB_PIPCI_BAR)));
466 pm8001_ha->inbnd_q_tbl[i].pi_offset =
467 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
468 }
469}
470
471/**
472 * read_outbnd_queue_table - read the outbound queue table and save it.
473 * @pm8001_ha: our hba card information
474 */
475static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
476{
477 int i;
478 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
479 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
480 u32 offset = i * 0x24;
481 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
482 get_pci_bar_index(pm8001_mr32(address,
483 (offset + OB_CIPCI_BAR)));
484 pm8001_ha->outbnd_q_tbl[i].ci_offset =
485 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
486 }
487}
488
489/**
490 * init_default_table_values - init the default table.
491 * @pm8001_ha: our hba card information
492 */
493static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
494{
495 int i;
496 u32 offsetib, offsetob;
497 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
498 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
499
500 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
501 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
502 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
503 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
504 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
505 PM8001_EVENT_LOG_SIZE;
506 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
507 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
508 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
509 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
510 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
511 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
512 PM8001_EVENT_LOG_SIZE;
513 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
514 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
515
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]516 /* Disable end to end CRC checking */
517 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
518
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]519 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
520 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
Hans Verkuil9504a922013-07-26 18:43:45 +0200[diff] [blame]521 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]522 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
523 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
524 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
525 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
526 pm8001_ha->inbnd_q_tbl[i].base_virt =
527 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
528 pm8001_ha->inbnd_q_tbl[i].total_length =
529 pm8001_ha->memoryMap.region[IB + i].total_len;
530 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
531 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
532 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
533 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
534 pm8001_ha->inbnd_q_tbl[i].ci_virt =
535 pm8001_ha->memoryMap.region[CI + i].virt_ptr;
536 offsetib = i * 0x20;
537 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
538 get_pci_bar_index(pm8001_mr32(addressib,
539 (offsetib + 0x14)));
540 pm8001_ha->inbnd_q_tbl[i].pi_offset =
541 pm8001_mr32(addressib, (offsetib + 0x18));
542 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
543 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]544
545 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
546 "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,
547 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,
548 pm8001_ha->inbnd_q_tbl[i].pi_offset));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]549 }
550 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
551 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
Hans Verkuil9504a922013-07-26 18:43:45 +0200[diff] [blame]552 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]553 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
554 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
555 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
556 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
557 pm8001_ha->outbnd_q_tbl[i].base_virt =
558 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
559 pm8001_ha->outbnd_q_tbl[i].total_length =
560 pm8001_ha->memoryMap.region[OB + i].total_len;
561 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
562 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
563 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
564 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
565 /* interrupt vector based on oq */
566 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
567 pm8001_ha->outbnd_q_tbl[i].pi_virt =
568 pm8001_ha->memoryMap.region[PI + i].virt_ptr;
569 offsetob = i * 0x24;
570 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
571 get_pci_bar_index(pm8001_mr32(addressob,
572 offsetob + 0x14));
573 pm8001_ha->outbnd_q_tbl[i].ci_offset =
574 pm8001_mr32(addressob, (offsetob + 0x18));
575 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
576 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]577
578 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
579 "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,
580 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,
581 pm8001_ha->outbnd_q_tbl[i].ci_offset));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]582 }
583}
584
585/**
586 * update_main_config_table - update the main default table to the HBA.
587 * @pm8001_ha: our hba card information
588 */
589static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
590{
591 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
592 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
593 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
594 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
595 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
596 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
597 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
598 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
599 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
600 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
601 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
602 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
603 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
604 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
605 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
606 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
607 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
608 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
609 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
Deepak Ukey72349b62018-09-11 14:18:04 +0530[diff] [blame]610 /* Update Fatal error interrupt vector */
611 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
612 ((pm8001_ha->number_of_intr - 1) << 8);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]613 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
614 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]615 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
616 "Updated Fatal error interrupt vector 0x%x\n",
617 pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT)));
618
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]619 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
620 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]621
622 /* SPCv specific */
623 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
624 /* Set GPIOLED to 0x2 for LED indicator */
625 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
626 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
627 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]628 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
629 "Programming DW 0x21 in main cfg table with 0x%x\n",
630 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET)));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]631
632 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
633 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
634 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
635 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]636
637 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
638 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
639 PORT_RECOVERY_TIMEOUT;
Viswas G61daffd2017-10-18 11:39:12 +0530[diff] [blame]640 if (pm8001_ha->chip_id == chip_8006) {
641 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
642 0x0000ffff;
643 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
Deepak Ukey196ba662019-07-09 15:30:48 +0530[diff] [blame]644 CHIP_8006_PORT_RECOVERY_TIMEOUT;
Viswas G61daffd2017-10-18 11:39:12 +0530[diff] [blame]645 }
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]646 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
647 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]648}
649
650/**
651 * update_inbnd_queue_table - update the inbound queue table to the HBA.
652 * @pm8001_ha: our hba card information
653 */
654static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
655 int number)
656{
657 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
658 u16 offset = number * 0x20;
659 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
660 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
661 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
662 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
663 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
664 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
665 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
666 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
667 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
668 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]669
670 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
671 "IQ %d: Element pri size 0x%x\n",
672 number,
673 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt));
674
675 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
676 "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",
677 pm8001_ha->inbnd_q_tbl[number].upper_base_addr,
678 pm8001_ha->inbnd_q_tbl[number].lower_base_addr));
679
680 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
681 "CI upper base addr 0x%x CI lower base addr 0x%x\n",
682 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,
683 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]684}
685
686/**
687 * update_outbnd_queue_table - update the outbound queue table to the HBA.
688 * @pm8001_ha: our hba card information
689 */
690static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
691 int number)
692{
693 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
694 u16 offset = number * 0x24;
695 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
696 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
697 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
698 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
699 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
700 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
701 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
702 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
703 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
704 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
705 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
706 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]707
708 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
709 "OQ %d: Element pri size 0x%x\n",
710 number,
711 pm8001_ha->outbnd_q_tbl[number].element_size_cnt));
712
713 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
714 "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",
715 pm8001_ha->outbnd_q_tbl[number].upper_base_addr,
716 pm8001_ha->outbnd_q_tbl[number].lower_base_addr));
717
718 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
719 "PI upper base addr 0x%x PI lower base addr 0x%x\n",
720 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,
721 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]722}
723
724/**
725 * mpi_init_check - check firmware initialization status.
726 * @pm8001_ha: our hba card information
727 */
728static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
729{
730 u32 max_wait_count;
731 u32 value;
732 u32 gst_len_mpistate;
733
734 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
735 table is updated */
736 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
737 /* wait until Inbound DoorBell Clear Register toggled */
Anand Kumar Santhanama9a923e2013-09-03 15:09:42 +0530[diff] [blame]738 if (IS_SPCV_12G(pm8001_ha->pdev)) {
ianyare90e23622019-11-14 15:39:03 +0530[diff] [blame]739 max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
Anand Kumar Santhanama9a923e2013-09-03 15:09:42 +0530[diff] [blame]740 } else {
ianyare90e23622019-11-14 15:39:03 +0530[diff] [blame]741 max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
Anand Kumar Santhanama9a923e2013-09-03 15:09:42 +0530[diff] [blame]742 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]743 do {
744 udelay(1);
745 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
746 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
747 } while ((value != 0) && (--max_wait_count));
748
749 if (!max_wait_count)
750 return -1;
751 /* check the MPI-State for initialization upto 100ms*/
752 max_wait_count = 100 * 1000;/* 100 msec */
753 do {
754 udelay(1);
755 gst_len_mpistate =
756 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
757 GST_GSTLEN_MPIS_OFFSET);
758 } while ((GST_MPI_STATE_INIT !=
759 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
760 if (!max_wait_count)
761 return -1;
762
763 /* check MPI Initialization error */
764 gst_len_mpistate = gst_len_mpistate >> 16;
765 if (0x0000 != gst_len_mpistate)
766 return -1;
767
768 return 0;
769}
770
771/**
772 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
773 * @pm8001_ha: our hba card information
774 */
775static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
776{
777 u32 value;
778 u32 max_wait_count;
779 u32 max_wait_time;
780 int ret = 0;
781
782 /* reset / PCIe ready */
783 max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */
784 do {
785 udelay(1);
786 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
787 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
788
789 /* check ila status */
790 max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */
791 do {
792 udelay(1);
793 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
794 } while (((value & SCRATCH_PAD_ILA_READY) !=
795 SCRATCH_PAD_ILA_READY) && (--max_wait_count));
796 if (!max_wait_count)
797 ret = -1;
798 else {
799 PM8001_MSG_DBG(pm8001_ha,
800 pm8001_printk(" ila ready status in %d millisec\n",
801 (max_wait_time - max_wait_count)));
802 }
803
804 /* check RAAE status */
805 max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */
806 do {
807 udelay(1);
808 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
809 } while (((value & SCRATCH_PAD_RAAE_READY) !=
810 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
811 if (!max_wait_count)
812 ret = -1;
813 else {
814 PM8001_MSG_DBG(pm8001_ha,
815 pm8001_printk(" raae ready status in %d millisec\n",
816 (max_wait_time - max_wait_count)));
817 }
818
819 /* check iop0 status */
820 max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */
821 do {
822 udelay(1);
823 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
824 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
825 (--max_wait_count));
826 if (!max_wait_count)
827 ret = -1;
828 else {
829 PM8001_MSG_DBG(pm8001_ha,
830 pm8001_printk(" iop0 ready status in %d millisec\n",
831 (max_wait_time - max_wait_count)));
832 }
833
834 /* check iop1 status only for 16 port controllers */
835 if ((pm8001_ha->chip_id != chip_8008) &&
836 (pm8001_ha->chip_id != chip_8009)) {
837 /* 200 milli sec */
838 max_wait_time = max_wait_count = 200 * 1000;
839 do {
840 udelay(1);
841 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
842 } while (((value & SCRATCH_PAD_IOP1_READY) !=
843 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
844 if (!max_wait_count)
845 ret = -1;
846 else {
847 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
848 "iop1 ready status in %d millisec\n",
849 (max_wait_time - max_wait_count)));
850 }
851 }
852
853 return ret;
854}
855
856static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
857{
858 void __iomem *base_addr;
859 u32 value;
860 u32 offset;
861 u32 pcibar;
862 u32 pcilogic;
863
864 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
865 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
866
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]867 PM8001_DEV_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]868 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
869 offset, value));
870 pcilogic = (value & 0xFC000000) >> 26;
871 pcibar = get_pci_bar_index(pcilogic);
872 PM8001_INIT_DBG(pm8001_ha,
873 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
874 pm8001_ha->main_cfg_tbl_addr = base_addr =
875 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
876 pm8001_ha->general_stat_tbl_addr =
877 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
878 0xFFFFFF);
879 pm8001_ha->inbnd_q_tbl_addr =
880 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
881 0xFFFFFF);
882 pm8001_ha->outbnd_q_tbl_addr =
883 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
884 0xFFFFFF);
885 pm8001_ha->ivt_tbl_addr =
886 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
887 0xFFFFFF);
888 pm8001_ha->pspa_q_tbl_addr =
889 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
890 0xFFFFFF);
Anand Kumar Santhanamd078b512013-09-04 12:57:00 +0530[diff] [blame]891 pm8001_ha->fatal_tbl_addr =
892 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
893 0xFFFFFF);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]894
895 PM8001_INIT_DBG(pm8001_ha,
896 pm8001_printk("GST OFFSET 0x%x\n",
897 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
898 PM8001_INIT_DBG(pm8001_ha,
899 pm8001_printk("INBND OFFSET 0x%x\n",
900 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
901 PM8001_INIT_DBG(pm8001_ha,
902 pm8001_printk("OBND OFFSET 0x%x\n",
903 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
904 PM8001_INIT_DBG(pm8001_ha,
905 pm8001_printk("IVT OFFSET 0x%x\n",
906 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
907 PM8001_INIT_DBG(pm8001_ha,
908 pm8001_printk("PSPA OFFSET 0x%x\n",
909 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
910 PM8001_INIT_DBG(pm8001_ha,
911 pm8001_printk("addr - main cfg %p general status %p\n",
912 pm8001_ha->main_cfg_tbl_addr,
913 pm8001_ha->general_stat_tbl_addr));
914 PM8001_INIT_DBG(pm8001_ha,
915 pm8001_printk("addr - inbnd %p obnd %p\n",
916 pm8001_ha->inbnd_q_tbl_addr,
917 pm8001_ha->outbnd_q_tbl_addr));
918 PM8001_INIT_DBG(pm8001_ha,
919 pm8001_printk("addr - pspa %p ivt %p\n",
920 pm8001_ha->pspa_q_tbl_addr,
921 pm8001_ha->ivt_tbl_addr));
922}
923
924/**
925 * pm80xx_set_thermal_config - support the thermal configuration
926 * @pm8001_ha: our hba card information.
927 */
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]928int
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]929pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
930{
931 struct set_ctrl_cfg_req payload;
932 struct inbound_queue_table *circularQ;
933 int rc;
934 u32 tag;
935 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
Viswas G842784e2015-08-11 15:06:27 +0530[diff] [blame]936 u32 page_code;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]937
938 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
939 rc = pm8001_tag_alloc(pm8001_ha, &tag);
940 if (rc)
941 return -1;
942
943 circularQ = &pm8001_ha->inbnd_q_tbl[0];
944 payload.tag = cpu_to_le32(tag);
Viswas G842784e2015-08-11 15:06:27 +0530[diff] [blame]945
946 if (IS_SPCV_12G(pm8001_ha->pdev))
947 page_code = THERMAL_PAGE_CODE_7H;
948 else
949 page_code = THERMAL_PAGE_CODE_8H;
950
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]951 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
Viswas G842784e2015-08-11 15:06:27 +0530[diff] [blame]952 (THERMAL_ENABLE << 8) | page_code;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]953 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
954
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]955 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
956 "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",
957 payload.cfg_pg[0], payload.cfg_pg[1]));
958
peter chang91a43fa2019-11-14 15:39:05 +0530[diff] [blame]959 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
960 sizeof(payload), 0);
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]961 if (rc)
962 pm8001_tag_free(pm8001_ha, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]963 return rc;
964
965}
966
967/**
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]968* pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
969* Timer configuration page
970* @pm8001_ha: our hba card information.
971*/
972static int
973pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
974{
975 struct set_ctrl_cfg_req payload;
976 struct inbound_queue_table *circularQ;
977 SASProtocolTimerConfig_t SASConfigPage;
978 int rc;
979 u32 tag;
980 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
981
982 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
983 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
984
985 rc = pm8001_tag_alloc(pm8001_ha, &tag);
986
987 if (rc)
988 return -1;
989
990 circularQ = &pm8001_ha->inbnd_q_tbl[0];
991 payload.tag = cpu_to_le32(tag);
992
993 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE;
994 SASConfigPage.MST_MSI = 3 << 15;
995 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO;
996 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) |
997 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
998 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME;
999
1000 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
1001 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
1002
1003
1004 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) |
1005 SAS_OPNRJT_RTRY_INTVL;
1006 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16)
1007 | SAS_COPNRJT_RTRY_TMO;
1008 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16)
1009 | SAS_COPNRJT_RTRY_THR;
1010 SASConfigPage.MAX_AIP = SAS_MAX_AIP;
1011
1012 PM8001_INIT_DBG(pm8001_ha,
1013 pm8001_printk("SASConfigPage.pageCode "
1014 "0x%08x\n", SASConfigPage.pageCode));
1015 PM8001_INIT_DBG(pm8001_ha,
1016 pm8001_printk("SASConfigPage.MST_MSI "
1017 " 0x%08x\n", SASConfigPage.MST_MSI));
1018 PM8001_INIT_DBG(pm8001_ha,
1019 pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
1020 " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
1021 PM8001_INIT_DBG(pm8001_ha,
1022 pm8001_printk("SASConfigPage.STP_FRM_TMO "
1023 " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
1024 PM8001_INIT_DBG(pm8001_ha,
1025 pm8001_printk("SASConfigPage.STP_IDLE_TMO "
1026 " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
1027 PM8001_INIT_DBG(pm8001_ha,
1028 pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
1029 " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
1030 PM8001_INIT_DBG(pm8001_ha,
1031 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
1032 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
1033 PM8001_INIT_DBG(pm8001_ha,
1034 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
1035 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
1036 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
1037 " 0x%08x\n", SASConfigPage.MAX_AIP));
1038
1039 memcpy(&payload.cfg_pg, &SASConfigPage,
1040 sizeof(SASProtocolTimerConfig_t));
1041
peter chang91a43fa2019-11-14 15:39:05 +0530[diff] [blame]1042 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1043 sizeof(payload), 0);
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1044 if (rc)
1045 pm8001_tag_free(pm8001_ha, tag);
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]1046
1047 return rc;
1048}
1049
1050/**
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1051 * pm80xx_get_encrypt_info - Check for encryption
1052 * @pm8001_ha: our hba card information.
1053 */
1054static int
1055pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
1056{
1057 u32 scratch3_value;
Rickard Strandqvistda225492014-07-09 17:20:10 +0530[diff] [blame]1058 int ret = -1;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1059
1060 /* Read encryption status from SCRATCH PAD 3 */
1061 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1062
1063 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1064 SCRATCH_PAD3_ENC_READY) {
1065 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1066 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1067 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1068 SCRATCH_PAD3_SMF_ENABLED)
1069 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1070 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1071 SCRATCH_PAD3_SMA_ENABLED)
1072 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1073 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1074 SCRATCH_PAD3_SMB_ENABLED)
1075 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1076 pm8001_ha->encrypt_info.status = 0;
1077 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1078 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
1079 "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
1080 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1081 pm8001_ha->encrypt_info.sec_mode,
1082 pm8001_ha->encrypt_info.status));
1083 ret = 0;
1084 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1085 SCRATCH_PAD3_ENC_DISABLED) {
1086 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1087 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1088 scratch3_value));
1089 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1090 pm8001_ha->encrypt_info.cipher_mode = 0;
1091 pm8001_ha->encrypt_info.sec_mode = 0;
Rickard Strandqvistda225492014-07-09 17:20:10 +0530[diff] [blame]1092 ret = 0;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1093 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1094 SCRATCH_PAD3_ENC_DIS_ERR) {
1095 pm8001_ha->encrypt_info.status =
1096 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1097 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1098 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1099 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1100 SCRATCH_PAD3_SMF_ENABLED)
1101 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1102 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1103 SCRATCH_PAD3_SMA_ENABLED)
1104 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1105 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1106 SCRATCH_PAD3_SMB_ENABLED)
1107 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1108 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1109 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
1110 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1111 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1112 pm8001_ha->encrypt_info.sec_mode,
1113 pm8001_ha->encrypt_info.status));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1114 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1115 SCRATCH_PAD3_ENC_ENA_ERR) {
1116
1117 pm8001_ha->encrypt_info.status =
1118 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1119 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1120 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1121 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1122 SCRATCH_PAD3_SMF_ENABLED)
1123 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1124 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1125 SCRATCH_PAD3_SMA_ENABLED)
1126 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1127 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1128 SCRATCH_PAD3_SMB_ENABLED)
1129 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1130
1131 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1132 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
1133 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1134 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1135 pm8001_ha->encrypt_info.sec_mode,
1136 pm8001_ha->encrypt_info.status));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1137 }
1138 return ret;
1139}
1140
1141/**
1142 * pm80xx_encrypt_update - update flash with encryption informtion
1143 * @pm8001_ha: our hba card information.
1144 */
1145static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1146{
1147 struct kek_mgmt_req payload;
1148 struct inbound_queue_table *circularQ;
1149 int rc;
1150 u32 tag;
1151 u32 opc = OPC_INB_KEK_MANAGEMENT;
1152
1153 memset(&payload, 0, sizeof(struct kek_mgmt_req));
1154 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1155 if (rc)
1156 return -1;
1157
1158 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1159 payload.tag = cpu_to_le32(tag);
1160 /* Currently only one key is used. New KEK index is 1.
1161 * Current KEK index is 1. Store KEK to NVRAM is 1.
1162 */
1163 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
1164 KEK_MGMT_SUBOP_KEYCARDUPDATE);
1165
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]1166 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
1167 "Saving Encryption info to flash. payload 0x%x\n",
1168 payload.new_curidx_ksop));
1169
peter chang91a43fa2019-11-14 15:39:05 +0530[diff] [blame]1170 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
1171 sizeof(payload), 0);
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1172 if (rc)
1173 pm8001_tag_free(pm8001_ha, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1174
1175 return rc;
1176}
1177
1178/**
1179 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
1180 * @pm8001_ha: our hba card information
1181 */
1182static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1183{
1184 int ret;
1185 u8 i = 0;
1186
1187 /* check the firmware status */
1188 if (-1 == check_fw_ready(pm8001_ha)) {
1189 PM8001_FAIL_DBG(pm8001_ha,
1190 pm8001_printk("Firmware is not ready!\n"));
1191 return -EBUSY;
1192 }
1193
Deepak Ukey72349b62018-09-11 14:18:04 +0530[diff] [blame]1194 /* Initialize the controller fatal error flag */
1195 pm8001_ha->controller_fatal_error = false;
1196
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1197 /* Initialize pci space address eg: mpi offset */
1198 init_pci_device_addresses(pm8001_ha);
1199 init_default_table_values(pm8001_ha);
1200 read_main_config_table(pm8001_ha);
1201 read_general_status_table(pm8001_ha);
1202 read_inbnd_queue_table(pm8001_ha);
1203 read_outbnd_queue_table(pm8001_ha);
1204 read_phy_attr_table(pm8001_ha);
1205
1206 /* update main config table ,inbound table and outbound table */
1207 update_main_config_table(pm8001_ha);
1208 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
1209 update_inbnd_queue_table(pm8001_ha, i);
1210 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
1211 update_outbnd_queue_table(pm8001_ha, i);
1212
1213 /* notify firmware update finished and check initialization status */
1214 if (0 == mpi_init_check(pm8001_ha)) {
1215 PM8001_INIT_DBG(pm8001_ha,
1216 pm8001_printk("MPI initialize successful!\n"));
1217 } else
1218 return -EBUSY;
1219
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]1220 /* send SAS protocol timer configuration page to FW */
1221 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1222
1223 /* Check for encryption */
1224 if (pm8001_ha->chip->encrypt) {
1225 PM8001_INIT_DBG(pm8001_ha,
1226 pm8001_printk("Checking for encryption\n"));
1227 ret = pm80xx_get_encrypt_info(pm8001_ha);
1228 if (ret == -1) {
1229 PM8001_INIT_DBG(pm8001_ha,
1230 pm8001_printk("Encryption error !!\n"));
1231 if (pm8001_ha->encrypt_info.status == 0x81) {
1232 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1233 "Encryption enabled with error."
1234 "Saving encryption key to flash\n"));
1235 pm80xx_encrypt_update(pm8001_ha);
1236 }
1237 }
1238 }
1239 return 0;
1240}
1241
1242static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1243{
1244 u32 max_wait_count;
1245 u32 value;
1246 u32 gst_len_mpistate;
1247 init_pci_device_addresses(pm8001_ha);
1248 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1249 table is stop */
1250 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1251
1252 /* wait until Inbound DoorBell Clear Register toggled */
Anand Kumar Santhanama9a923e2013-09-03 15:09:42 +0530[diff] [blame]1253 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1254 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
1255 } else {
1256 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1257 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1258 do {
1259 udelay(1);
1260 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1261 value &= SPCv_MSGU_CFG_TABLE_RESET;
1262 } while ((value != 0) && (--max_wait_count));
1263
1264 if (!max_wait_count) {
1265 PM8001_FAIL_DBG(pm8001_ha,
1266 pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
1267 return -1;
1268 }
1269
1270 /* check the MPI-State for termination in progress */
1271 /* wait until Inbound DoorBell Clear Register toggled */
1272 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
1273 do {
1274 udelay(1);
1275 gst_len_mpistate =
1276 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1277 GST_GSTLEN_MPIS_OFFSET);
1278 if (GST_MPI_STATE_UNINIT ==
1279 (gst_len_mpistate & GST_MPI_STATE_MASK))
1280 break;
1281 } while (--max_wait_count);
1282 if (!max_wait_count) {
1283 PM8001_FAIL_DBG(pm8001_ha,
1284 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
1285 gst_len_mpistate & GST_MPI_STATE_MASK));
1286 return -1;
1287 }
1288
1289 return 0;
1290}
1291
1292/**
1293 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
1294 * the FW register status to the originated status.
1295 * @pm8001_ha: our hba card information
1296 */
1297
1298static int
1299pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1300{
1301 u32 regval;
1302 u32 bootloader_state;
Anand Kumar Santhanam06f12f222013-09-17 14:32:20 +0530[diff] [blame]1303 u32 ibutton0, ibutton1;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1304
Deepak Ukey72349b62018-09-11 14:18:04 +0530[diff] [blame]1305 /* Process MPI table uninitialization only if FW is ready */
1306 if (!pm8001_ha->controller_fatal_error) {
1307 /* Check if MPI is in ready state to reset */
1308 if (mpi_uninit_check(pm8001_ha) != 0) {
1309 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1310 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1311 "MPI state is not ready scratch1 :0x%x\n",
1312 regval));
1313 return -1;
1314 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1315 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1316 /* checked for reset register normal state; 0x0 */
1317 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1318 PM8001_INIT_DBG(pm8001_ha,
1319 pm8001_printk("reset register before write : 0x%x\n", regval));
1320
1321 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
Vikram Auradkar4daf1ef2019-11-14 15:39:01 +0530[diff] [blame]1322 msleep(500);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1323
1324 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1325 PM8001_INIT_DBG(pm8001_ha,
1326 pm8001_printk("reset register after write 0x%x\n", regval));
1327
1328 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1329 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1330 PM8001_MSG_DBG(pm8001_ha,
1331 pm8001_printk(" soft reset successful [regval: 0x%x]\n",
1332 regval));
1333 } else {
1334 PM8001_MSG_DBG(pm8001_ha,
1335 pm8001_printk(" soft reset failed [regval: 0x%x]\n",
1336 regval));
1337
1338 /* check bootloader is successfully executed or in HDA mode */
1339 bootloader_state =
1340 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1341 SCRATCH_PAD1_BOOTSTATE_MASK;
1342
1343 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1344 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1345 "Bootloader state - HDA mode SEEPROM\n"));
1346 } else if (bootloader_state ==
1347 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1348 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1349 "Bootloader state - HDA mode Bootstrap Pin\n"));
1350 } else if (bootloader_state ==
1351 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1352 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1353 "Bootloader state - HDA mode soft reset\n"));
1354 } else if (bootloader_state ==
1355 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1356 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1357 "Bootloader state-HDA mode critical error\n"));
1358 }
1359 return -EBUSY;
1360 }
1361
1362 /* check the firmware status after reset */
1363 if (-1 == check_fw_ready(pm8001_ha)) {
1364 PM8001_FAIL_DBG(pm8001_ha,
1365 pm8001_printk("Firmware is not ready!\n"));
Anand Kumar Santhanam06f12f222013-09-17 14:32:20 +0530[diff] [blame]1366 /* check iButton feature support for motherboard controller */
1367 if (pm8001_ha->pdev->subsystem_vendor !=
1368 PCI_VENDOR_ID_ADAPTEC2 &&
Benjamin Roodfaf321b2015-10-30 10:53:29 -0400[diff] [blame]1369 pm8001_ha->pdev->subsystem_vendor !=
1370 PCI_VENDOR_ID_ATTO &&
Anand Kumar Santhanam06f12f222013-09-17 14:32:20 +0530[diff] [blame]1371 pm8001_ha->pdev->subsystem_vendor != 0) {
1372 ibutton0 = pm8001_cr32(pm8001_ha, 0,
1373 MSGU_HOST_SCRATCH_PAD_6);
1374 ibutton1 = pm8001_cr32(pm8001_ha, 0,
1375 MSGU_HOST_SCRATCH_PAD_7);
1376 if (!ibutton0 && !ibutton1) {
1377 PM8001_FAIL_DBG(pm8001_ha,
1378 pm8001_printk("iButton Feature is"
1379 " not Available!!!\n"));
1380 return -EBUSY;
1381 }
1382 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1383 PM8001_FAIL_DBG(pm8001_ha,
1384 pm8001_printk("CRC Check for iButton"
1385 " Feature Failed!!!\n"));
1386 return -EBUSY;
1387 }
1388 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1389 }
1390 PM8001_INIT_DBG(pm8001_ha,
1391 pm8001_printk("SPCv soft reset Complete\n"));
1392 return 0;
1393}
1394
1395static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1396{
Colin Ian King9e2a07e2019-03-17 18:15:32 +0000[diff] [blame]1397 u32 i;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1398
1399 PM8001_INIT_DBG(pm8001_ha,
1400 pm8001_printk("chip reset start\n"));
1401
1402 /* do SPCv chip reset. */
1403 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1404 PM8001_INIT_DBG(pm8001_ha,
1405 pm8001_printk("SPC soft reset Complete\n"));
1406
1407 /* Check this ..whether delay is required or no */
1408 /* delay 10 usec */
1409 udelay(10);
1410
1411 /* wait for 20 msec until the firmware gets reloaded */
1412 i = 20;
1413 do {
1414 mdelay(1);
1415 } while ((--i) != 0);
1416
1417 PM8001_INIT_DBG(pm8001_ha,
1418 pm8001_printk("chip reset finished\n"));
1419}
1420
1421/**
1422 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1423 * @pm8001_ha: our hba card information
1424 */
1425static void
1426pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1427{
1428 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1429 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1430}
1431
1432/**
1433 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1434 * @pm8001_ha: our hba card information
1435 */
1436static void
1437pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1438{
1439 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1440}
1441
1442/**
1443 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1444 * @pm8001_ha: our hba card information
1445 */
1446static void
1447pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1448{
1449#ifdef PM8001_USE_MSIX
1450 u32 mask;
1451 mask = (u32)(1 << vec);
1452
1453 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1454 return;
1455#endif
1456 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1457
1458}
1459
1460/**
1461 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1462 * @pm8001_ha: our hba card information
1463 */
1464static void
1465pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1466{
1467#ifdef PM8001_USE_MSIX
1468 u32 mask;
1469 if (vec == 0xFF)
1470 mask = 0xFFFFFFFF;
1471 else
1472 mask = (u32)(1 << vec);
1473 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1474 return;
1475#endif
1476 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1477}
1478
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1479static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1480 struct pm8001_device *pm8001_ha_dev)
1481{
1482 int res;
1483 u32 ccb_tag;
1484 struct pm8001_ccb_info *ccb;
1485 struct sas_task *task = NULL;
1486 struct task_abort_req task_abort;
1487 struct inbound_queue_table *circularQ;
1488 u32 opc = OPC_INB_SATA_ABORT;
1489 int ret;
1490
1491 if (!pm8001_ha_dev) {
1492 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1493 return;
1494 }
1495
1496 task = sas_alloc_slow_task(GFP_ATOMIC);
1497
1498 if (!task) {
1499 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1500 "allocate task\n"));
1501 return;
1502 }
1503
1504 task->task_done = pm8001_task_done;
1505
1506 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1507 if (res) {
1508 sas_free_task(task);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1509 return;
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1510 }
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1511
1512 ccb = &pm8001_ha->ccb_info[ccb_tag];
1513 ccb->device = pm8001_ha_dev;
1514 ccb->ccb_tag = ccb_tag;
1515 ccb->task = task;
1516
1517 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1518
1519 memset(&task_abort, 0, sizeof(task_abort));
1520 task_abort.abort_all = cpu_to_le32(1);
1521 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1522 task_abort.tag = cpu_to_le32(ccb_tag);
1523
peter chang91a43fa2019-11-14 15:39:05 +0530[diff] [blame]1524 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
1525 sizeof(task_abort), 0);
1526 PM8001_FAIL_DBG(pm8001_ha,
1527 pm8001_printk("Executing abort task end\n"));
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1528 if (ret) {
1529 sas_free_task(task);
1530 pm8001_tag_free(pm8001_ha, ccb_tag);
1531 }
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1532}
1533
1534static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1535 struct pm8001_device *pm8001_ha_dev)
1536{
1537 struct sata_start_req sata_cmd;
1538 int res;
1539 u32 ccb_tag;
1540 struct pm8001_ccb_info *ccb;
1541 struct sas_task *task = NULL;
1542 struct host_to_dev_fis fis;
1543 struct domain_device *dev;
1544 struct inbound_queue_table *circularQ;
1545 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1546
1547 task = sas_alloc_slow_task(GFP_ATOMIC);
1548
1549 if (!task) {
1550 PM8001_FAIL_DBG(pm8001_ha,
1551 pm8001_printk("cannot allocate task !!!\n"));
1552 return;
1553 }
1554 task->task_done = pm8001_task_done;
1555
1556 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1557 if (res) {
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1558 sas_free_task(task);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1559 PM8001_FAIL_DBG(pm8001_ha,
1560 pm8001_printk("cannot allocate tag !!!\n"));
1561 return;
1562 }
1563
1564 /* allocate domain device by ourselves as libsas
1565 * is not going to provide any
1566 */
1567 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1568 if (!dev) {
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1569 sas_free_task(task);
1570 pm8001_tag_free(pm8001_ha, ccb_tag);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1571 PM8001_FAIL_DBG(pm8001_ha,
1572 pm8001_printk("Domain device cannot be allocated\n"));
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1573 return;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1574 }
1575
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1576 task->dev = dev;
1577 task->dev->lldd_dev = pm8001_ha_dev;
1578
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1579 ccb = &pm8001_ha->ccb_info[ccb_tag];
1580 ccb->device = pm8001_ha_dev;
1581 ccb->ccb_tag = ccb_tag;
1582 ccb->task = task;
Viswas G0b6df112017-10-18 11:39:14 +0530[diff] [blame]1583 ccb->n_elem = 0;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1584 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1585 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1586
1587 memset(&sata_cmd, 0, sizeof(sata_cmd));
1588 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1589
1590 /* construct read log FIS */
1591 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1592 fis.fis_type = 0x27;
1593 fis.flags = 0x80;
1594 fis.command = ATA_CMD_READ_LOG_EXT;
1595 fis.lbal = 0x10;
1596 fis.sector_count = 0x1;
1597
1598 sata_cmd.tag = cpu_to_le32(ccb_tag);
1599 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1600 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1601 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1602
peter chang91a43fa2019-11-14 15:39:05 +0530[diff] [blame]1603 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
1604 sizeof(sata_cmd), 0);
1605 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Executing read log end\n"));
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]1606 if (res) {
1607 sas_free_task(task);
1608 pm8001_tag_free(pm8001_ha, ccb_tag);
1609 kfree(dev);
1610 }
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]1611}
1612
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1613/**
1614 * mpi_ssp_completion- process the event that FW response to the SSP request.
1615 * @pm8001_ha: our hba card information
1616 * @piomb: the message contents of this outbound message.
1617 *
1618 * When FW has completed a ssp request for example a IO request, after it has
1619 * filled the SG data with the data, it will trigger this event represent
1620 * that he has finished the job,please check the coresponding buffer.
1621 * So we will tell the caller who maybe waiting the result to tell upper layer
1622 * that the task has been finished.
1623 */
1624static void
1625mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1626{
1627 struct sas_task *t;
1628 struct pm8001_ccb_info *ccb;
1629 unsigned long flags;
1630 u32 status;
1631 u32 param;
1632 u32 tag;
1633 struct ssp_completion_resp *psspPayload;
1634 struct task_status_struct *ts;
1635 struct ssp_response_iu *iu;
1636 struct pm8001_device *pm8001_dev;
1637 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1638 status = le32_to_cpu(psspPayload->status);
1639 tag = le32_to_cpu(psspPayload->tag);
1640 ccb = &pm8001_ha->ccb_info[tag];
1641 if ((status == IO_ABORTED) && ccb->open_retry) {
1642 /* Being completed by another */
1643 ccb->open_retry = 0;
1644 return;
1645 }
1646 pm8001_dev = ccb->device;
1647 param = le32_to_cpu(psspPayload->param);
1648 t = ccb->task;
1649
1650 if (status && status != IO_UNDERFLOW)
1651 PM8001_FAIL_DBG(pm8001_ha,
1652 pm8001_printk("sas IO status 0x%x\n", status));
1653 if (unlikely(!t || !t->lldd_task || !t->dev))
1654 return;
1655 ts = &t->task_status;
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]1656
1657 PM8001_DEV_DBG(pm8001_ha, pm8001_printk(
1658 "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t));
1659
Anand Kumar Santhanamcb269c22013-09-17 16:47:21 +0530[diff] [blame]1660 /* Print sas address of IO failed device */
1661 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1662 (status != IO_UNDERFLOW))
1663 PM8001_FAIL_DBG(pm8001_ha,
1664 pm8001_printk("SAS Address of IO Failure Drive"
1665 ":%016llx", SAS_ADDR(t->dev->sas_addr)));
1666
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1667 switch (status) {
1668 case IO_SUCCESS:
1669 PM8001_IO_DBG(pm8001_ha,
1670 pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1671 param));
1672 if (param == 0) {
1673 ts->resp = SAS_TASK_COMPLETE;
1674 ts->stat = SAM_STAT_GOOD;
1675 } else {
1676 ts->resp = SAS_TASK_COMPLETE;
1677 ts->stat = SAS_PROTO_RESPONSE;
1678 ts->residual = param;
1679 iu = &psspPayload->ssp_resp_iu;
1680 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1681 }
1682 if (pm8001_dev)
1683 pm8001_dev->running_req--;
1684 break;
1685 case IO_ABORTED:
1686 PM8001_IO_DBG(pm8001_ha,
1687 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1688 ts->resp = SAS_TASK_COMPLETE;
1689 ts->stat = SAS_ABORTED_TASK;
1690 break;
1691 case IO_UNDERFLOW:
1692 /* SSP Completion with error */
1693 PM8001_IO_DBG(pm8001_ha,
1694 pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1695 param));
1696 ts->resp = SAS_TASK_COMPLETE;
1697 ts->stat = SAS_DATA_UNDERRUN;
1698 ts->residual = param;
1699 if (pm8001_dev)
1700 pm8001_dev->running_req--;
1701 break;
1702 case IO_NO_DEVICE:
1703 PM8001_IO_DBG(pm8001_ha,
1704 pm8001_printk("IO_NO_DEVICE\n"));
1705 ts->resp = SAS_TASK_UNDELIVERED;
1706 ts->stat = SAS_PHY_DOWN;
1707 break;
1708 case IO_XFER_ERROR_BREAK:
1709 PM8001_IO_DBG(pm8001_ha,
1710 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1711 ts->resp = SAS_TASK_COMPLETE;
1712 ts->stat = SAS_OPEN_REJECT;
1713 /* Force the midlayer to retry */
1714 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1715 break;
1716 case IO_XFER_ERROR_PHY_NOT_READY:
1717 PM8001_IO_DBG(pm8001_ha,
1718 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1719 ts->resp = SAS_TASK_COMPLETE;
1720 ts->stat = SAS_OPEN_REJECT;
1721 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1722 break;
Viswas G27ecfa52015-08-11 15:06:31 +0530[diff] [blame]1723 case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
1724 PM8001_IO_DBG(pm8001_ha,
1725 pm8001_printk("IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n"));
1726 ts->resp = SAS_TASK_COMPLETE;
1727 ts->stat = SAS_OPEN_REJECT;
1728 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1729 break;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1730 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1731 PM8001_IO_DBG(pm8001_ha,
1732 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1733 ts->resp = SAS_TASK_COMPLETE;
1734 ts->stat = SAS_OPEN_REJECT;
1735 ts->open_rej_reason = SAS_OREJ_EPROTO;
1736 break;
1737 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1738 PM8001_IO_DBG(pm8001_ha,
1739 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1740 ts->resp = SAS_TASK_COMPLETE;
1741 ts->stat = SAS_OPEN_REJECT;
1742 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1743 break;
1744 case IO_OPEN_CNX_ERROR_BREAK:
1745 PM8001_IO_DBG(pm8001_ha,
1746 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1747 ts->resp = SAS_TASK_COMPLETE;
1748 ts->stat = SAS_OPEN_REJECT;
1749 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1750 break;
1751 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]1752 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1753 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1754 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1755 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1756 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1757 PM8001_IO_DBG(pm8001_ha,
1758 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1759 ts->resp = SAS_TASK_COMPLETE;
1760 ts->stat = SAS_OPEN_REJECT;
1761 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1762 if (!t->uldd_task)
1763 pm8001_handle_event(pm8001_ha,
1764 pm8001_dev,
1765 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1766 break;
1767 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1768 PM8001_IO_DBG(pm8001_ha,
1769 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1770 ts->resp = SAS_TASK_COMPLETE;
1771 ts->stat = SAS_OPEN_REJECT;
1772 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1773 break;
1774 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1775 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1776 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1777 ts->resp = SAS_TASK_COMPLETE;
1778 ts->stat = SAS_OPEN_REJECT;
1779 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1780 break;
1781 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1782 PM8001_IO_DBG(pm8001_ha,
1783 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1784 ts->resp = SAS_TASK_UNDELIVERED;
1785 ts->stat = SAS_OPEN_REJECT;
1786 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1787 break;
1788 case IO_XFER_ERROR_NAK_RECEIVED:
1789 PM8001_IO_DBG(pm8001_ha,
1790 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1791 ts->resp = SAS_TASK_COMPLETE;
1792 ts->stat = SAS_OPEN_REJECT;
1793 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1794 break;
1795 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1796 PM8001_IO_DBG(pm8001_ha,
1797 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1798 ts->resp = SAS_TASK_COMPLETE;
1799 ts->stat = SAS_NAK_R_ERR;
1800 break;
1801 case IO_XFER_ERROR_DMA:
1802 PM8001_IO_DBG(pm8001_ha,
1803 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1804 ts->resp = SAS_TASK_COMPLETE;
1805 ts->stat = SAS_OPEN_REJECT;
1806 break;
1807 case IO_XFER_OPEN_RETRY_TIMEOUT:
1808 PM8001_IO_DBG(pm8001_ha,
1809 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1810 ts->resp = SAS_TASK_COMPLETE;
1811 ts->stat = SAS_OPEN_REJECT;
1812 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1813 break;
1814 case IO_XFER_ERROR_OFFSET_MISMATCH:
1815 PM8001_IO_DBG(pm8001_ha,
1816 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1817 ts->resp = SAS_TASK_COMPLETE;
1818 ts->stat = SAS_OPEN_REJECT;
1819 break;
1820 case IO_PORT_IN_RESET:
1821 PM8001_IO_DBG(pm8001_ha,
1822 pm8001_printk("IO_PORT_IN_RESET\n"));
1823 ts->resp = SAS_TASK_COMPLETE;
1824 ts->stat = SAS_OPEN_REJECT;
1825 break;
1826 case IO_DS_NON_OPERATIONAL:
1827 PM8001_IO_DBG(pm8001_ha,
1828 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1829 ts->resp = SAS_TASK_COMPLETE;
1830 ts->stat = SAS_OPEN_REJECT;
1831 if (!t->uldd_task)
1832 pm8001_handle_event(pm8001_ha,
1833 pm8001_dev,
1834 IO_DS_NON_OPERATIONAL);
1835 break;
1836 case IO_DS_IN_RECOVERY:
1837 PM8001_IO_DBG(pm8001_ha,
1838 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1839 ts->resp = SAS_TASK_COMPLETE;
1840 ts->stat = SAS_OPEN_REJECT;
1841 break;
1842 case IO_TM_TAG_NOT_FOUND:
1843 PM8001_IO_DBG(pm8001_ha,
1844 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1845 ts->resp = SAS_TASK_COMPLETE;
1846 ts->stat = SAS_OPEN_REJECT;
1847 break;
1848 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1849 PM8001_IO_DBG(pm8001_ha,
1850 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1851 ts->resp = SAS_TASK_COMPLETE;
1852 ts->stat = SAS_OPEN_REJECT;
1853 break;
1854 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1855 PM8001_IO_DBG(pm8001_ha,
1856 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1857 ts->resp = SAS_TASK_COMPLETE;
1858 ts->stat = SAS_OPEN_REJECT;
1859 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1860 break;
1861 default:
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]1862 PM8001_DEVIO_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1863 pm8001_printk("Unknown status 0x%x\n", status));
1864 /* not allowed case. Therefore, return failed status */
1865 ts->resp = SAS_TASK_COMPLETE;
1866 ts->stat = SAS_OPEN_REJECT;
1867 break;
1868 }
1869 PM8001_IO_DBG(pm8001_ha,
1870 pm8001_printk("scsi_status = 0x%x\n ",
1871 psspPayload->ssp_resp_iu.status));
1872 spin_lock_irqsave(&t->task_state_lock, flags);
1873 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1874 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1875 t->task_state_flags |= SAS_TASK_STATE_DONE;
1876 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1877 spin_unlock_irqrestore(&t->task_state_lock, flags);
1878 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1879 "task 0x%p done with io_status 0x%x resp 0x%x "
1880 "stat 0x%x but aborted by upper layer!\n",
1881 t, status, ts->resp, ts->stat));
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]1882 if (t->slow_task)
1883 complete(&t->slow_task->completion);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1884 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1885 } else {
1886 spin_unlock_irqrestore(&t->task_state_lock, flags);
1887 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1888 mb();/* in order to force CPU ordering */
1889 t->task_done(t);
1890 }
1891}
1892
1893/*See the comments for mpi_ssp_completion */
1894static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1895{
1896 struct sas_task *t;
1897 unsigned long flags;
1898 struct task_status_struct *ts;
1899 struct pm8001_ccb_info *ccb;
1900 struct pm8001_device *pm8001_dev;
1901 struct ssp_event_resp *psspPayload =
1902 (struct ssp_event_resp *)(piomb + 4);
1903 u32 event = le32_to_cpu(psspPayload->event);
1904 u32 tag = le32_to_cpu(psspPayload->tag);
1905 u32 port_id = le32_to_cpu(psspPayload->port_id);
1906
1907 ccb = &pm8001_ha->ccb_info[tag];
1908 t = ccb->task;
1909 pm8001_dev = ccb->device;
1910 if (event)
1911 PM8001_FAIL_DBG(pm8001_ha,
1912 pm8001_printk("sas IO status 0x%x\n", event));
1913 if (unlikely(!t || !t->lldd_task || !t->dev))
1914 return;
1915 ts = &t->task_status;
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]1916 PM8001_IOERR_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1917 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1918 port_id, tag, event));
1919 switch (event) {
1920 case IO_OVERFLOW:
1921 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1922 ts->resp = SAS_TASK_COMPLETE;
1923 ts->stat = SAS_DATA_OVERRUN;
1924 ts->residual = 0;
1925 if (pm8001_dev)
1926 pm8001_dev->running_req--;
1927 break;
1928 case IO_XFER_ERROR_BREAK:
1929 PM8001_IO_DBG(pm8001_ha,
1930 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1931 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1932 return;
1933 case IO_XFER_ERROR_PHY_NOT_READY:
1934 PM8001_IO_DBG(pm8001_ha,
1935 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1936 ts->resp = SAS_TASK_COMPLETE;
1937 ts->stat = SAS_OPEN_REJECT;
1938 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1939 break;
1940 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1941 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1942 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1943 ts->resp = SAS_TASK_COMPLETE;
1944 ts->stat = SAS_OPEN_REJECT;
1945 ts->open_rej_reason = SAS_OREJ_EPROTO;
1946 break;
1947 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1948 PM8001_IO_DBG(pm8001_ha,
1949 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1950 ts->resp = SAS_TASK_COMPLETE;
1951 ts->stat = SAS_OPEN_REJECT;
1952 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1953 break;
1954 case IO_OPEN_CNX_ERROR_BREAK:
1955 PM8001_IO_DBG(pm8001_ha,
1956 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1957 ts->resp = SAS_TASK_COMPLETE;
1958 ts->stat = SAS_OPEN_REJECT;
1959 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1960 break;
1961 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]1962 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1963 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1964 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1965 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1966 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]1967 PM8001_IO_DBG(pm8001_ha,
1968 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1969 ts->resp = SAS_TASK_COMPLETE;
1970 ts->stat = SAS_OPEN_REJECT;
1971 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1972 if (!t->uldd_task)
1973 pm8001_handle_event(pm8001_ha,
1974 pm8001_dev,
1975 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1976 break;
1977 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1978 PM8001_IO_DBG(pm8001_ha,
1979 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1980 ts->resp = SAS_TASK_COMPLETE;
1981 ts->stat = SAS_OPEN_REJECT;
1982 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1983 break;
1984 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1985 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1986 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1987 ts->resp = SAS_TASK_COMPLETE;
1988 ts->stat = SAS_OPEN_REJECT;
1989 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1990 break;
1991 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1992 PM8001_IO_DBG(pm8001_ha,
1993 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1994 ts->resp = SAS_TASK_COMPLETE;
1995 ts->stat = SAS_OPEN_REJECT;
1996 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1997 break;
1998 case IO_XFER_ERROR_NAK_RECEIVED:
1999 PM8001_IO_DBG(pm8001_ha,
2000 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2001 ts->resp = SAS_TASK_COMPLETE;
2002 ts->stat = SAS_OPEN_REJECT;
2003 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2004 break;
2005 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2006 PM8001_IO_DBG(pm8001_ha,
2007 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2008 ts->resp = SAS_TASK_COMPLETE;
2009 ts->stat = SAS_NAK_R_ERR;
2010 break;
2011 case IO_XFER_OPEN_RETRY_TIMEOUT:
2012 PM8001_IO_DBG(pm8001_ha,
2013 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2014 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2015 return;
2016 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2017 PM8001_IO_DBG(pm8001_ha,
2018 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2019 ts->resp = SAS_TASK_COMPLETE;
2020 ts->stat = SAS_DATA_OVERRUN;
2021 break;
2022 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2023 PM8001_IO_DBG(pm8001_ha,
2024 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2025 ts->resp = SAS_TASK_COMPLETE;
2026 ts->stat = SAS_DATA_OVERRUN;
2027 break;
2028 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2029 PM8001_IO_DBG(pm8001_ha,
2030 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2031 ts->resp = SAS_TASK_COMPLETE;
2032 ts->stat = SAS_DATA_OVERRUN;
2033 break;
2034 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2035 PM8001_IO_DBG(pm8001_ha,
2036 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
2037 ts->resp = SAS_TASK_COMPLETE;
2038 ts->stat = SAS_DATA_OVERRUN;
2039 break;
2040 case IO_XFER_ERROR_OFFSET_MISMATCH:
2041 PM8001_IO_DBG(pm8001_ha,
2042 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2043 ts->resp = SAS_TASK_COMPLETE;
2044 ts->stat = SAS_DATA_OVERRUN;
2045 break;
2046 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2047 PM8001_IO_DBG(pm8001_ha,
2048 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2049 ts->resp = SAS_TASK_COMPLETE;
2050 ts->stat = SAS_DATA_OVERRUN;
2051 break;
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2052 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]2053 PM8001_IOERR_DBG(pm8001_ha,
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2054 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2055 /* TBC: used default set values */
2056 ts->resp = SAS_TASK_COMPLETE;
2057 ts->stat = SAS_DATA_OVERRUN;
2058 break;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2059 case IO_XFER_CMD_FRAME_ISSUED:
2060 PM8001_IO_DBG(pm8001_ha,
2061 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2062 return;
2063 default:
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]2064 PM8001_DEVIO_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2065 pm8001_printk("Unknown status 0x%x\n", event));
2066 /* not allowed case. Therefore, return failed status */
2067 ts->resp = SAS_TASK_COMPLETE;
2068 ts->stat = SAS_DATA_OVERRUN;
2069 break;
2070 }
2071 spin_lock_irqsave(&t->task_state_lock, flags);
2072 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2073 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2074 t->task_state_flags |= SAS_TASK_STATE_DONE;
2075 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2076 spin_unlock_irqrestore(&t->task_state_lock, flags);
2077 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2078 "task 0x%p done with event 0x%x resp 0x%x "
2079 "stat 0x%x but aborted by upper layer!\n",
2080 t, event, ts->resp, ts->stat));
2081 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2082 } else {
2083 spin_unlock_irqrestore(&t->task_state_lock, flags);
2084 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2085 mb();/* in order to force CPU ordering */
2086 t->task_done(t);
2087 }
2088}
2089
2090/*See the comments for mpi_ssp_completion */
2091static void
2092mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2093{
2094 struct sas_task *t;
2095 struct pm8001_ccb_info *ccb;
2096 u32 param;
2097 u32 status;
2098 u32 tag;
Anand Kumar Santhanamcb269c22013-09-17 16:47:21 +0530[diff] [blame]2099 int i, j;
2100 u8 sata_addr_low[4];
2101 u32 temp_sata_addr_low, temp_sata_addr_hi;
2102 u8 sata_addr_hi[4];
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2103 struct sata_completion_resp *psataPayload;
2104 struct task_status_struct *ts;
2105 struct ata_task_resp *resp ;
2106 u32 *sata_resp;
2107 struct pm8001_device *pm8001_dev;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2108 unsigned long flags;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2109
2110 psataPayload = (struct sata_completion_resp *)(piomb + 4);
2111 status = le32_to_cpu(psataPayload->status);
2112 tag = le32_to_cpu(psataPayload->tag);
2113
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2114 if (!tag) {
2115 PM8001_FAIL_DBG(pm8001_ha,
2116 pm8001_printk("tag null\n"));
2117 return;
2118 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2119 ccb = &pm8001_ha->ccb_info[tag];
2120 param = le32_to_cpu(psataPayload->param);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2121 if (ccb) {
2122 t = ccb->task;
2123 pm8001_dev = ccb->device;
2124 } else {
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2125 PM8001_FAIL_DBG(pm8001_ha,
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2126 pm8001_printk("ccb null\n"));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2127 return;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2128 }
2129
2130 if (t) {
2131 if (t->dev && (t->dev->lldd_dev))
2132 pm8001_dev = t->dev->lldd_dev;
2133 } else {
2134 PM8001_FAIL_DBG(pm8001_ha,
2135 pm8001_printk("task null\n"));
2136 return;
2137 }
2138
2139 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2140 && unlikely(!t || !t->lldd_task || !t->dev)) {
2141 PM8001_FAIL_DBG(pm8001_ha,
2142 pm8001_printk("task or dev null\n"));
2143 return;
2144 }
2145
2146 ts = &t->task_status;
2147 if (!ts) {
2148 PM8001_FAIL_DBG(pm8001_ha,
2149 pm8001_printk("ts null\n"));
2150 return;
2151 }
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]2152
2153 if (unlikely(status))
2154 PM8001_IOERR_DBG(pm8001_ha, pm8001_printk(
2155 "status:0x%x, tag:0x%x, task::0x%p\n",
2156 status, tag, t));
2157
Anand Kumar Santhanamcb269c22013-09-17 16:47:21 +0530[diff] [blame]2158 /* Print sas address of IO failed device */
2159 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2160 (status != IO_UNDERFLOW)) {
2161 if (!((t->dev->parent) &&
John Garry924a3542019-06-10 20:41:41 +0800[diff] [blame]2162 (dev_is_expander(t->dev->parent->dev_type)))) {
Anand Kumar Santhanamcb269c22013-09-17 16:47:21 +0530[diff] [blame]2163 for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
2164 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2165 for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
2166 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2167 memcpy(&temp_sata_addr_low, sata_addr_low,
2168 sizeof(sata_addr_low));
2169 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2170 sizeof(sata_addr_hi));
2171 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2172 |((temp_sata_addr_hi << 8) &
2173 0xff0000) |
2174 ((temp_sata_addr_hi >> 8)
2175 & 0xff00) |
2176 ((temp_sata_addr_hi << 24) &
2177 0xff000000));
2178 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2179 & 0xff) |
2180 ((temp_sata_addr_low << 8)
2181 & 0xff0000) |
2182 ((temp_sata_addr_low >> 8)
2183 & 0xff00) |
2184 ((temp_sata_addr_low << 24)
2185 & 0xff000000)) +
2186 pm8001_dev->attached_phy +
2187 0x10);
2188 PM8001_FAIL_DBG(pm8001_ha,
2189 pm8001_printk("SAS Address of IO Failure Drive:"
2190 "%08x%08x", temp_sata_addr_hi,
2191 temp_sata_addr_low));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2192
Anand Kumar Santhanamcb269c22013-09-17 16:47:21 +0530[diff] [blame]2193 } else {
2194 PM8001_FAIL_DBG(pm8001_ha,
2195 pm8001_printk("SAS Address of IO Failure Drive:"
2196 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2197 }
2198 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2199 switch (status) {
2200 case IO_SUCCESS:
2201 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2202 if (param == 0) {
2203 ts->resp = SAS_TASK_COMPLETE;
2204 ts->stat = SAM_STAT_GOOD;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2205 /* check if response is for SEND READ LOG */
2206 if (pm8001_dev &&
2207 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2208 /* set new bit for abort_all */
2209 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2210 /* clear bit for read log */
2211 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2212 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2213 /* Free the tag */
2214 pm8001_tag_free(pm8001_ha, tag);
2215 sas_free_task(t);
2216 return;
2217 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2218 } else {
2219 u8 len;
2220 ts->resp = SAS_TASK_COMPLETE;
2221 ts->stat = SAS_PROTO_RESPONSE;
2222 ts->residual = param;
2223 PM8001_IO_DBG(pm8001_ha,
2224 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2225 param));
2226 sata_resp = &psataPayload->sata_resp[0];
2227 resp = (struct ata_task_resp *)ts->buf;
2228 if (t->ata_task.dma_xfer == 0 &&
Christoph Hellwigf73bdeb2018-10-10 19:59:50 +0200[diff] [blame]2229 t->data_dir == DMA_FROM_DEVICE) {
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2230 len = sizeof(struct pio_setup_fis);
2231 PM8001_IO_DBG(pm8001_ha,
2232 pm8001_printk("PIO read len = %d\n", len));
2233 } else if (t->ata_task.use_ncq) {
2234 len = sizeof(struct set_dev_bits_fis);
2235 PM8001_IO_DBG(pm8001_ha,
2236 pm8001_printk("FPDMA len = %d\n", len));
2237 } else {
2238 len = sizeof(struct dev_to_host_fis);
2239 PM8001_IO_DBG(pm8001_ha,
2240 pm8001_printk("other len = %d\n", len));
2241 }
2242 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2243 resp->frame_len = len;
2244 memcpy(&resp->ending_fis[0], sata_resp, len);
2245 ts->buf_valid_size = sizeof(*resp);
2246 } else
2247 PM8001_IO_DBG(pm8001_ha,
2248 pm8001_printk("response to large\n"));
2249 }
2250 if (pm8001_dev)
2251 pm8001_dev->running_req--;
2252 break;
2253 case IO_ABORTED:
2254 PM8001_IO_DBG(pm8001_ha,
2255 pm8001_printk("IO_ABORTED IOMB Tag\n"));
2256 ts->resp = SAS_TASK_COMPLETE;
2257 ts->stat = SAS_ABORTED_TASK;
2258 if (pm8001_dev)
2259 pm8001_dev->running_req--;
2260 break;
2261 /* following cases are to do cases */
2262 case IO_UNDERFLOW:
2263 /* SATA Completion with error */
2264 PM8001_IO_DBG(pm8001_ha,
2265 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2266 ts->resp = SAS_TASK_COMPLETE;
2267 ts->stat = SAS_DATA_UNDERRUN;
2268 ts->residual = param;
2269 if (pm8001_dev)
2270 pm8001_dev->running_req--;
2271 break;
2272 case IO_NO_DEVICE:
2273 PM8001_IO_DBG(pm8001_ha,
2274 pm8001_printk("IO_NO_DEVICE\n"));
2275 ts->resp = SAS_TASK_UNDELIVERED;
2276 ts->stat = SAS_PHY_DOWN;
2277 break;
2278 case IO_XFER_ERROR_BREAK:
2279 PM8001_IO_DBG(pm8001_ha,
2280 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2281 ts->resp = SAS_TASK_COMPLETE;
2282 ts->stat = SAS_INTERRUPTED;
2283 break;
2284 case IO_XFER_ERROR_PHY_NOT_READY:
2285 PM8001_IO_DBG(pm8001_ha,
2286 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2287 ts->resp = SAS_TASK_COMPLETE;
2288 ts->stat = SAS_OPEN_REJECT;
2289 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2290 break;
2291 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2292 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2293 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2294 ts->resp = SAS_TASK_COMPLETE;
2295 ts->stat = SAS_OPEN_REJECT;
2296 ts->open_rej_reason = SAS_OREJ_EPROTO;
2297 break;
2298 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2299 PM8001_IO_DBG(pm8001_ha,
2300 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2301 ts->resp = SAS_TASK_COMPLETE;
2302 ts->stat = SAS_OPEN_REJECT;
2303 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2304 break;
2305 case IO_OPEN_CNX_ERROR_BREAK:
2306 PM8001_IO_DBG(pm8001_ha,
2307 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2308 ts->resp = SAS_TASK_COMPLETE;
2309 ts->stat = SAS_OPEN_REJECT;
2310 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2311 break;
2312 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2313 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2314 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2315 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2316 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2317 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2318 PM8001_IO_DBG(pm8001_ha,
2319 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2320 ts->resp = SAS_TASK_COMPLETE;
2321 ts->stat = SAS_DEV_NO_RESPONSE;
2322 if (!t->uldd_task) {
2323 pm8001_handle_event(pm8001_ha,
2324 pm8001_dev,
2325 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2326 ts->resp = SAS_TASK_UNDELIVERED;
2327 ts->stat = SAS_QUEUE_FULL;
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2328 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2329 return;
2330 }
2331 break;
2332 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2333 PM8001_IO_DBG(pm8001_ha,
2334 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2335 ts->resp = SAS_TASK_UNDELIVERED;
2336 ts->stat = SAS_OPEN_REJECT;
2337 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2338 if (!t->uldd_task) {
2339 pm8001_handle_event(pm8001_ha,
2340 pm8001_dev,
2341 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2342 ts->resp = SAS_TASK_UNDELIVERED;
2343 ts->stat = SAS_QUEUE_FULL;
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2344 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2345 return;
2346 }
2347 break;
2348 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2349 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2350 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2351 ts->resp = SAS_TASK_COMPLETE;
2352 ts->stat = SAS_OPEN_REJECT;
2353 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2354 break;
2355 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2356 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2357 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
2358 ts->resp = SAS_TASK_COMPLETE;
2359 ts->stat = SAS_DEV_NO_RESPONSE;
2360 if (!t->uldd_task) {
2361 pm8001_handle_event(pm8001_ha,
2362 pm8001_dev,
2363 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2364 ts->resp = SAS_TASK_UNDELIVERED;
2365 ts->stat = SAS_QUEUE_FULL;
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2366 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2367 return;
2368 }
2369 break;
2370 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2371 PM8001_IO_DBG(pm8001_ha,
2372 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2373 ts->resp = SAS_TASK_COMPLETE;
2374 ts->stat = SAS_OPEN_REJECT;
2375 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2376 break;
2377 case IO_XFER_ERROR_NAK_RECEIVED:
2378 PM8001_IO_DBG(pm8001_ha,
2379 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2380 ts->resp = SAS_TASK_COMPLETE;
2381 ts->stat = SAS_NAK_R_ERR;
2382 break;
2383 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2384 PM8001_IO_DBG(pm8001_ha,
2385 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2386 ts->resp = SAS_TASK_COMPLETE;
2387 ts->stat = SAS_NAK_R_ERR;
2388 break;
2389 case IO_XFER_ERROR_DMA:
2390 PM8001_IO_DBG(pm8001_ha,
2391 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2392 ts->resp = SAS_TASK_COMPLETE;
2393 ts->stat = SAS_ABORTED_TASK;
2394 break;
2395 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2396 PM8001_IO_DBG(pm8001_ha,
2397 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2398 ts->resp = SAS_TASK_UNDELIVERED;
2399 ts->stat = SAS_DEV_NO_RESPONSE;
2400 break;
2401 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2402 PM8001_IO_DBG(pm8001_ha,
2403 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2404 ts->resp = SAS_TASK_COMPLETE;
2405 ts->stat = SAS_DATA_UNDERRUN;
2406 break;
2407 case IO_XFER_OPEN_RETRY_TIMEOUT:
2408 PM8001_IO_DBG(pm8001_ha,
2409 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2410 ts->resp = SAS_TASK_COMPLETE;
2411 ts->stat = SAS_OPEN_TO;
2412 break;
2413 case IO_PORT_IN_RESET:
2414 PM8001_IO_DBG(pm8001_ha,
2415 pm8001_printk("IO_PORT_IN_RESET\n"));
2416 ts->resp = SAS_TASK_COMPLETE;
2417 ts->stat = SAS_DEV_NO_RESPONSE;
2418 break;
2419 case IO_DS_NON_OPERATIONAL:
2420 PM8001_IO_DBG(pm8001_ha,
2421 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2422 ts->resp = SAS_TASK_COMPLETE;
2423 ts->stat = SAS_DEV_NO_RESPONSE;
2424 if (!t->uldd_task) {
2425 pm8001_handle_event(pm8001_ha, pm8001_dev,
2426 IO_DS_NON_OPERATIONAL);
2427 ts->resp = SAS_TASK_UNDELIVERED;
2428 ts->stat = SAS_QUEUE_FULL;
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2429 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2430 return;
2431 }
2432 break;
2433 case IO_DS_IN_RECOVERY:
2434 PM8001_IO_DBG(pm8001_ha,
2435 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2436 ts->resp = SAS_TASK_COMPLETE;
2437 ts->stat = SAS_DEV_NO_RESPONSE;
2438 break;
2439 case IO_DS_IN_ERROR:
2440 PM8001_IO_DBG(pm8001_ha,
2441 pm8001_printk("IO_DS_IN_ERROR\n"));
2442 ts->resp = SAS_TASK_COMPLETE;
2443 ts->stat = SAS_DEV_NO_RESPONSE;
2444 if (!t->uldd_task) {
2445 pm8001_handle_event(pm8001_ha, pm8001_dev,
2446 IO_DS_IN_ERROR);
2447 ts->resp = SAS_TASK_UNDELIVERED;
2448 ts->stat = SAS_QUEUE_FULL;
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2449 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2450 return;
2451 }
2452 break;
2453 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2454 PM8001_IO_DBG(pm8001_ha,
2455 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2456 ts->resp = SAS_TASK_COMPLETE;
2457 ts->stat = SAS_OPEN_REJECT;
2458 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
Johannes Thumshirn50acde82015-08-17 15:52:32 +0200[diff] [blame]2459 break;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2460 default:
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]2461 PM8001_DEVIO_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2462 pm8001_printk("Unknown status 0x%x\n", status));
2463 /* not allowed case. Therefore, return failed status */
2464 ts->resp = SAS_TASK_COMPLETE;
2465 ts->stat = SAS_DEV_NO_RESPONSE;
2466 break;
2467 }
2468 spin_lock_irqsave(&t->task_state_lock, flags);
2469 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2470 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2471 t->task_state_flags |= SAS_TASK_STATE_DONE;
2472 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2473 spin_unlock_irqrestore(&t->task_state_lock, flags);
2474 PM8001_FAIL_DBG(pm8001_ha,
2475 pm8001_printk("task 0x%p done with io_status 0x%x"
2476 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2477 t, status, ts->resp, ts->stat));
peter changce21c632019-11-14 15:38:58 +0530[diff] [blame]2478 if (t->slow_task)
2479 complete(&t->slow_task->completion);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2480 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2481 } else {
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2482 spin_unlock_irqrestore(&t->task_state_lock, flags);
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2483 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2484 }
2485}
2486
2487/*See the comments for mpi_ssp_completion */
2488static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2489{
2490 struct sas_task *t;
2491 struct task_status_struct *ts;
2492 struct pm8001_ccb_info *ccb;
2493 struct pm8001_device *pm8001_dev;
2494 struct sata_event_resp *psataPayload =
2495 (struct sata_event_resp *)(piomb + 4);
2496 u32 event = le32_to_cpu(psataPayload->event);
2497 u32 tag = le32_to_cpu(psataPayload->tag);
2498 u32 port_id = le32_to_cpu(psataPayload->port_id);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2499 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2500 unsigned long flags;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2501
2502 ccb = &pm8001_ha->ccb_info[tag];
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2503
2504 if (ccb) {
2505 t = ccb->task;
2506 pm8001_dev = ccb->device;
2507 } else {
2508 PM8001_FAIL_DBG(pm8001_ha,
2509 pm8001_printk("No CCB !!!. returning\n"));
2510 return;
2511 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2512 if (event)
2513 PM8001_FAIL_DBG(pm8001_ha,
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2514 pm8001_printk("SATA EVENT 0x%x\n", event));
2515
2516 /* Check if this is NCQ error */
2517 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2518 /* find device using device id */
2519 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2520 /* send read log extension */
2521 if (pm8001_dev)
2522 pm80xx_send_read_log(pm8001_ha, pm8001_dev);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2523 return;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]2524 }
2525
2526 if (unlikely(!t || !t->lldd_task || !t->dev)) {
2527 PM8001_FAIL_DBG(pm8001_ha,
2528 pm8001_printk("task or dev null\n"));
2529 return;
2530 }
2531
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2532 ts = &t->task_status;
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]2533 PM8001_IOERR_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2534 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2535 port_id, tag, event));
2536 switch (event) {
2537 case IO_OVERFLOW:
2538 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2539 ts->resp = SAS_TASK_COMPLETE;
2540 ts->stat = SAS_DATA_OVERRUN;
2541 ts->residual = 0;
2542 if (pm8001_dev)
2543 pm8001_dev->running_req--;
2544 break;
2545 case IO_XFER_ERROR_BREAK:
2546 PM8001_IO_DBG(pm8001_ha,
2547 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2548 ts->resp = SAS_TASK_COMPLETE;
2549 ts->stat = SAS_INTERRUPTED;
2550 break;
2551 case IO_XFER_ERROR_PHY_NOT_READY:
2552 PM8001_IO_DBG(pm8001_ha,
2553 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2554 ts->resp = SAS_TASK_COMPLETE;
2555 ts->stat = SAS_OPEN_REJECT;
2556 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2557 break;
2558 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2559 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2560 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2561 ts->resp = SAS_TASK_COMPLETE;
2562 ts->stat = SAS_OPEN_REJECT;
2563 ts->open_rej_reason = SAS_OREJ_EPROTO;
2564 break;
2565 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2566 PM8001_IO_DBG(pm8001_ha,
2567 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2568 ts->resp = SAS_TASK_COMPLETE;
2569 ts->stat = SAS_OPEN_REJECT;
2570 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2571 break;
2572 case IO_OPEN_CNX_ERROR_BREAK:
2573 PM8001_IO_DBG(pm8001_ha,
2574 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2575 ts->resp = SAS_TASK_COMPLETE;
2576 ts->stat = SAS_OPEN_REJECT;
2577 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2578 break;
2579 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2580 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2581 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2582 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2583 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2584 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2585 PM8001_FAIL_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2586 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2587 ts->resp = SAS_TASK_UNDELIVERED;
2588 ts->stat = SAS_DEV_NO_RESPONSE;
2589 if (!t->uldd_task) {
2590 pm8001_handle_event(pm8001_ha,
2591 pm8001_dev,
2592 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2593 ts->resp = SAS_TASK_COMPLETE;
2594 ts->stat = SAS_QUEUE_FULL;
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2595 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2596 return;
2597 }
2598 break;
2599 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2600 PM8001_IO_DBG(pm8001_ha,
2601 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2602 ts->resp = SAS_TASK_UNDELIVERED;
2603 ts->stat = SAS_OPEN_REJECT;
2604 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2605 break;
2606 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2607 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2608 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2609 ts->resp = SAS_TASK_COMPLETE;
2610 ts->stat = SAS_OPEN_REJECT;
2611 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2612 break;
2613 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2614 PM8001_IO_DBG(pm8001_ha,
2615 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2616 ts->resp = SAS_TASK_COMPLETE;
2617 ts->stat = SAS_OPEN_REJECT;
2618 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2619 break;
2620 case IO_XFER_ERROR_NAK_RECEIVED:
2621 PM8001_IO_DBG(pm8001_ha,
2622 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2623 ts->resp = SAS_TASK_COMPLETE;
2624 ts->stat = SAS_NAK_R_ERR;
2625 break;
2626 case IO_XFER_ERROR_PEER_ABORTED:
2627 PM8001_IO_DBG(pm8001_ha,
2628 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2629 ts->resp = SAS_TASK_COMPLETE;
2630 ts->stat = SAS_NAK_R_ERR;
2631 break;
2632 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2633 PM8001_IO_DBG(pm8001_ha,
2634 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2635 ts->resp = SAS_TASK_COMPLETE;
2636 ts->stat = SAS_DATA_UNDERRUN;
2637 break;
2638 case IO_XFER_OPEN_RETRY_TIMEOUT:
2639 PM8001_IO_DBG(pm8001_ha,
2640 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2641 ts->resp = SAS_TASK_COMPLETE;
2642 ts->stat = SAS_OPEN_TO;
2643 break;
2644 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2645 PM8001_IO_DBG(pm8001_ha,
2646 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2647 ts->resp = SAS_TASK_COMPLETE;
2648 ts->stat = SAS_OPEN_TO;
2649 break;
2650 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2651 PM8001_IO_DBG(pm8001_ha,
2652 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2653 ts->resp = SAS_TASK_COMPLETE;
2654 ts->stat = SAS_OPEN_TO;
2655 break;
2656 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2657 PM8001_IO_DBG(pm8001_ha,
2658 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2659 ts->resp = SAS_TASK_COMPLETE;
2660 ts->stat = SAS_OPEN_TO;
2661 break;
2662 case IO_XFER_ERROR_OFFSET_MISMATCH:
2663 PM8001_IO_DBG(pm8001_ha,
2664 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2665 ts->resp = SAS_TASK_COMPLETE;
2666 ts->stat = SAS_OPEN_TO;
2667 break;
2668 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2669 PM8001_IO_DBG(pm8001_ha,
2670 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2671 ts->resp = SAS_TASK_COMPLETE;
2672 ts->stat = SAS_OPEN_TO;
2673 break;
2674 case IO_XFER_CMD_FRAME_ISSUED:
2675 PM8001_IO_DBG(pm8001_ha,
2676 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2677 break;
2678 case IO_XFER_PIO_SETUP_ERROR:
2679 PM8001_IO_DBG(pm8001_ha,
2680 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2681 ts->resp = SAS_TASK_COMPLETE;
2682 ts->stat = SAS_OPEN_TO;
2683 break;
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2684 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2685 PM8001_FAIL_DBG(pm8001_ha,
2686 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2687 /* TBC: used default set values */
2688 ts->resp = SAS_TASK_COMPLETE;
2689 ts->stat = SAS_OPEN_TO;
2690 break;
2691 case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2692 PM8001_FAIL_DBG(pm8001_ha,
2693 pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2694 /* TBC: used default set values */
2695 ts->resp = SAS_TASK_COMPLETE;
2696 ts->stat = SAS_OPEN_TO;
2697 break;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2698 default:
2699 PM8001_IO_DBG(pm8001_ha,
2700 pm8001_printk("Unknown status 0x%x\n", event));
2701 /* not allowed case. Therefore, return failed status */
2702 ts->resp = SAS_TASK_COMPLETE;
2703 ts->stat = SAS_OPEN_TO;
2704 break;
2705 }
2706 spin_lock_irqsave(&t->task_state_lock, flags);
2707 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2708 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2709 t->task_state_flags |= SAS_TASK_STATE_DONE;
2710 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2711 spin_unlock_irqrestore(&t->task_state_lock, flags);
2712 PM8001_FAIL_DBG(pm8001_ha,
2713 pm8001_printk("task 0x%p done with io_status 0x%x"
2714 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2715 t, event, ts->resp, ts->stat));
2716 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2717 } else {
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2718 spin_unlock_irqrestore(&t->task_state_lock, flags);
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]2719 pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2720 }
2721}
2722
2723/*See the comments for mpi_ssp_completion */
2724static void
2725mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2726{
2727 u32 param, i;
2728 struct sas_task *t;
2729 struct pm8001_ccb_info *ccb;
2730 unsigned long flags;
2731 u32 status;
2732 u32 tag;
2733 struct smp_completion_resp *psmpPayload;
2734 struct task_status_struct *ts;
2735 struct pm8001_device *pm8001_dev;
2736 char *pdma_respaddr = NULL;
2737
2738 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2739 status = le32_to_cpu(psmpPayload->status);
2740 tag = le32_to_cpu(psmpPayload->tag);
2741
2742 ccb = &pm8001_ha->ccb_info[tag];
2743 param = le32_to_cpu(psmpPayload->param);
2744 t = ccb->task;
2745 ts = &t->task_status;
2746 pm8001_dev = ccb->device;
2747 if (status)
2748 PM8001_FAIL_DBG(pm8001_ha,
2749 pm8001_printk("smp IO status 0x%x\n", status));
2750 if (unlikely(!t || !t->lldd_task || !t->dev))
2751 return;
2752
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]2753 PM8001_DEV_DBG(pm8001_ha,
2754 pm8001_printk("tag::0x%x status::0x%x\n", tag, status));
2755
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2756 switch (status) {
2757
2758 case IO_SUCCESS:
2759 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2760 ts->resp = SAS_TASK_COMPLETE;
2761 ts->stat = SAM_STAT_GOOD;
2762 if (pm8001_dev)
2763 pm8001_dev->running_req--;
2764 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2765 PM8001_IO_DBG(pm8001_ha,
2766 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2767 param));
2768 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2769 ((u64)sg_dma_address
2770 (&t->smp_task.smp_resp))));
2771 for (i = 0; i < param; i++) {
2772 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2773 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2774 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2775 i, *(pdma_respaddr+i),
2776 psmpPayload->_r_a[i]));
2777 }
2778 }
2779 break;
2780 case IO_ABORTED:
2781 PM8001_IO_DBG(pm8001_ha,
2782 pm8001_printk("IO_ABORTED IOMB\n"));
2783 ts->resp = SAS_TASK_COMPLETE;
2784 ts->stat = SAS_ABORTED_TASK;
2785 if (pm8001_dev)
2786 pm8001_dev->running_req--;
2787 break;
2788 case IO_OVERFLOW:
2789 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2790 ts->resp = SAS_TASK_COMPLETE;
2791 ts->stat = SAS_DATA_OVERRUN;
2792 ts->residual = 0;
2793 if (pm8001_dev)
2794 pm8001_dev->running_req--;
2795 break;
2796 case IO_NO_DEVICE:
2797 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2798 ts->resp = SAS_TASK_COMPLETE;
2799 ts->stat = SAS_PHY_DOWN;
2800 break;
2801 case IO_ERROR_HW_TIMEOUT:
2802 PM8001_IO_DBG(pm8001_ha,
2803 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2804 ts->resp = SAS_TASK_COMPLETE;
2805 ts->stat = SAM_STAT_BUSY;
2806 break;
2807 case IO_XFER_ERROR_BREAK:
2808 PM8001_IO_DBG(pm8001_ha,
2809 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2810 ts->resp = SAS_TASK_COMPLETE;
2811 ts->stat = SAM_STAT_BUSY;
2812 break;
2813 case IO_XFER_ERROR_PHY_NOT_READY:
2814 PM8001_IO_DBG(pm8001_ha,
2815 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2816 ts->resp = SAS_TASK_COMPLETE;
2817 ts->stat = SAM_STAT_BUSY;
2818 break;
2819 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2820 PM8001_IO_DBG(pm8001_ha,
2821 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2822 ts->resp = SAS_TASK_COMPLETE;
2823 ts->stat = SAS_OPEN_REJECT;
2824 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2825 break;
2826 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2827 PM8001_IO_DBG(pm8001_ha,
2828 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2829 ts->resp = SAS_TASK_COMPLETE;
2830 ts->stat = SAS_OPEN_REJECT;
2831 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2832 break;
2833 case IO_OPEN_CNX_ERROR_BREAK:
2834 PM8001_IO_DBG(pm8001_ha,
2835 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2836 ts->resp = SAS_TASK_COMPLETE;
2837 ts->stat = SAS_OPEN_REJECT;
2838 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2839 break;
2840 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]2841 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2842 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2843 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2844 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2845 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2846 PM8001_IO_DBG(pm8001_ha,
2847 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2848 ts->resp = SAS_TASK_COMPLETE;
2849 ts->stat = SAS_OPEN_REJECT;
2850 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2851 pm8001_handle_event(pm8001_ha,
2852 pm8001_dev,
2853 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2854 break;
2855 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2856 PM8001_IO_DBG(pm8001_ha,
2857 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2858 ts->resp = SAS_TASK_COMPLETE;
2859 ts->stat = SAS_OPEN_REJECT;
2860 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2861 break;
2862 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2863 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2864 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2865 ts->resp = SAS_TASK_COMPLETE;
2866 ts->stat = SAS_OPEN_REJECT;
2867 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2868 break;
2869 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2870 PM8001_IO_DBG(pm8001_ha,
2871 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2872 ts->resp = SAS_TASK_COMPLETE;
2873 ts->stat = SAS_OPEN_REJECT;
2874 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2875 break;
2876 case IO_XFER_ERROR_RX_FRAME:
2877 PM8001_IO_DBG(pm8001_ha,
2878 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2879 ts->resp = SAS_TASK_COMPLETE;
2880 ts->stat = SAS_DEV_NO_RESPONSE;
2881 break;
2882 case IO_XFER_OPEN_RETRY_TIMEOUT:
2883 PM8001_IO_DBG(pm8001_ha,
2884 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2885 ts->resp = SAS_TASK_COMPLETE;
2886 ts->stat = SAS_OPEN_REJECT;
2887 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2888 break;
2889 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2890 PM8001_IO_DBG(pm8001_ha,
2891 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2892 ts->resp = SAS_TASK_COMPLETE;
2893 ts->stat = SAS_QUEUE_FULL;
2894 break;
2895 case IO_PORT_IN_RESET:
2896 PM8001_IO_DBG(pm8001_ha,
2897 pm8001_printk("IO_PORT_IN_RESET\n"));
2898 ts->resp = SAS_TASK_COMPLETE;
2899 ts->stat = SAS_OPEN_REJECT;
2900 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2901 break;
2902 case IO_DS_NON_OPERATIONAL:
2903 PM8001_IO_DBG(pm8001_ha,
2904 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2905 ts->resp = SAS_TASK_COMPLETE;
2906 ts->stat = SAS_DEV_NO_RESPONSE;
2907 break;
2908 case IO_DS_IN_RECOVERY:
2909 PM8001_IO_DBG(pm8001_ha,
2910 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2911 ts->resp = SAS_TASK_COMPLETE;
2912 ts->stat = SAS_OPEN_REJECT;
2913 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2914 break;
2915 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2916 PM8001_IO_DBG(pm8001_ha,
2917 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2918 ts->resp = SAS_TASK_COMPLETE;
2919 ts->stat = SAS_OPEN_REJECT;
2920 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2921 break;
2922 default:
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]2923 PM8001_DEVIO_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2924 pm8001_printk("Unknown status 0x%x\n", status));
2925 ts->resp = SAS_TASK_COMPLETE;
2926 ts->stat = SAS_DEV_NO_RESPONSE;
2927 /* not allowed case. Therefore, return failed status */
2928 break;
2929 }
2930 spin_lock_irqsave(&t->task_state_lock, flags);
2931 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2932 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2933 t->task_state_flags |= SAS_TASK_STATE_DONE;
2934 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2935 spin_unlock_irqrestore(&t->task_state_lock, flags);
2936 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2937 "task 0x%p done with io_status 0x%x resp 0x%x"
2938 "stat 0x%x but aborted by upper layer!\n",
2939 t, status, ts->resp, ts->stat));
2940 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2941 } else {
2942 spin_unlock_irqrestore(&t->task_state_lock, flags);
2943 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2944 mb();/* in order to force CPU ordering */
2945 t->task_done(t);
2946 }
2947}
2948
2949/**
2950 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2951 * @pm8001_ha: our hba card information
2952 * @Qnum: the outbound queue message number.
2953 * @SEA: source of event to ack
2954 * @port_id: port id.
2955 * @phyId: phy id.
2956 * @param0: parameter 0.
2957 * @param1: parameter 1.
2958 */
2959static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2960 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2961{
2962 struct hw_event_ack_req payload;
2963 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2964
2965 struct inbound_queue_table *circularQ;
2966
2967 memset((u8 *)&payload, 0, sizeof(payload));
2968 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2969 payload.tag = cpu_to_le32(1);
2970 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2971 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
2972 payload.param0 = cpu_to_le32(param0);
2973 payload.param1 = cpu_to_le32(param1);
peter chang91a43fa2019-11-14 15:39:05 +0530[diff] [blame]2974 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
2975 sizeof(payload), 0);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]2976}
2977
2978static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2979 u32 phyId, u32 phy_op);
2980
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]2981static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
2982 void *piomb)
2983{
2984 struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
2985 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2986 u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2987 u32 lr_status_evt_portid =
2988 le32_to_cpu(pPayload->lr_status_evt_portid);
2989 u8 deviceType = pPayload->sas_identify.dev_type;
2990 u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2991 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2992 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2993 struct pm8001_port *port = &pm8001_ha->port[port_id];
2994
2995 if (deviceType == SAS_END_DEVICE) {
2996 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2997 PHY_NOTIFY_ENABLE_SPINUP);
2998 }
2999
3000 port->wide_port_phymap |= (1U << phy_id);
3001 pm8001_get_lrate_mode(phy, link_rate);
3002 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3003 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3004 phy->phy_attached = 1;
3005}
3006
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3007/**
3008 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3009 * @pm8001_ha: our hba card information
3010 * @piomb: IO message buffer
3011 */
3012static void
3013hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3014{
3015 struct hw_event_resp *pPayload =
3016 (struct hw_event_resp *)(piomb + 4);
3017 u32 lr_status_evt_portid =
3018 le32_to_cpu(pPayload->lr_status_evt_portid);
3019 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3020
3021 u8 link_rate =
3022 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3023 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3024 u8 phy_id =
3025 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3026 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3027
3028 struct pm8001_port *port = &pm8001_ha->port[port_id];
3029 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3030 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3031 unsigned long flags;
3032 u8 deviceType = pPayload->sas_identify.dev_type;
3033 port->port_state = portstate;
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3034 port->wide_port_phymap |= (1U << phy_id);
Nikith Ganigarakoppal7d029002013-10-30 16:23:47 +0530[diff] [blame]3035 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3036 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3037 "portid:%d; phyid:%d; linkrate:%d; "
3038 "portstate:%x; devicetype:%x\n",
3039 port_id, phy_id, link_rate, portstate, deviceType));
3040
3041 switch (deviceType) {
3042 case SAS_PHY_UNUSED:
3043 PM8001_MSG_DBG(pm8001_ha,
3044 pm8001_printk("device type no device.\n"));
3045 break;
3046 case SAS_END_DEVICE:
3047 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
3048 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3049 PHY_NOTIFY_ENABLE_SPINUP);
3050 port->port_attached = 1;
3051 pm8001_get_lrate_mode(phy, link_rate);
3052 break;
3053 case SAS_EDGE_EXPANDER_DEVICE:
3054 PM8001_MSG_DBG(pm8001_ha,
3055 pm8001_printk("expander device.\n"));
3056 port->port_attached = 1;
3057 pm8001_get_lrate_mode(phy, link_rate);
3058 break;
3059 case SAS_FANOUT_EXPANDER_DEVICE:
3060 PM8001_MSG_DBG(pm8001_ha,
3061 pm8001_printk("fanout expander device.\n"));
3062 port->port_attached = 1;
3063 pm8001_get_lrate_mode(phy, link_rate);
3064 break;
3065 default:
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]3066 PM8001_DEVIO_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3067 pm8001_printk("unknown device type(%x)\n", deviceType));
3068 break;
3069 }
3070 phy->phy_type |= PORT_TYPE_SAS;
3071 phy->identify.device_type = deviceType;
3072 phy->phy_attached = 1;
3073 if (phy->identify.device_type == SAS_END_DEVICE)
3074 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3075 else if (phy->identify.device_type != SAS_PHY_UNUSED)
3076 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3077 phy->sas_phy.oob_mode = SAS_OOB_MODE;
3078 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3079 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3080 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3081 sizeof(struct sas_identify_frame)-4);
3082 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3083 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3084 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3085 if (pm8001_ha->flags == PM8001F_RUN_TIME)
Vikram Auradkar4daf1ef2019-11-14 15:39:01 +0530[diff] [blame]3086 msleep(200);/*delay a moment to wait disk to spinup*/
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3087 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3088}
3089
3090/**
3091 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3092 * @pm8001_ha: our hba card information
3093 * @piomb: IO message buffer
3094 */
3095static void
3096hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3097{
3098 struct hw_event_resp *pPayload =
3099 (struct hw_event_resp *)(piomb + 4);
3100 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3101 u32 lr_status_evt_portid =
3102 le32_to_cpu(pPayload->lr_status_evt_portid);
3103 u8 link_rate =
3104 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3105 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3106 u8 phy_id =
3107 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3108
3109 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3110
3111 struct pm8001_port *port = &pm8001_ha->port[port_id];
3112 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3113 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3114 unsigned long flags;
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]3115 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3116 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
3117 port_id, phy_id, link_rate, portstate));
3118
3119 port->port_state = portstate;
Nikith Ganigarakoppal7d029002013-10-30 16:23:47 +0530[diff] [blame]3120 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3121 port->port_attached = 1;
3122 pm8001_get_lrate_mode(phy, link_rate);
3123 phy->phy_type |= PORT_TYPE_SATA;
3124 phy->phy_attached = 1;
3125 phy->sas_phy.oob_mode = SATA_OOB_MODE;
3126 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
3127 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3128 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3129 sizeof(struct dev_to_host_fis));
3130 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3131 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
James Bottomleyaa9f8322013-05-07 14:44:06 -0700[diff] [blame]3132 phy->identify.device_type = SAS_SATA_DEV;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3133 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3134 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3135 pm8001_bytes_dmaed(pm8001_ha, phy_id);
3136}
3137
3138/**
3139 * hw_event_phy_down -we should notify the libsas the phy is down.
3140 * @pm8001_ha: our hba card information
3141 * @piomb: IO message buffer
3142 */
3143static void
3144hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3145{
3146 struct hw_event_resp *pPayload =
3147 (struct hw_event_resp *)(piomb + 4);
3148
3149 u32 lr_status_evt_portid =
3150 le32_to_cpu(pPayload->lr_status_evt_portid);
3151 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3152 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3153 u8 phy_id =
3154 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3155 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3156
3157 struct pm8001_port *port = &pm8001_ha->port[port_id];
3158 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]3159 u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3160 port->port_state = portstate;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3161 phy->identify.device_type = 0;
3162 phy->phy_attached = 0;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3163 switch (portstate) {
3164 case PORT_VALID:
3165 break;
3166 case PORT_INVALID:
3167 PM8001_MSG_DBG(pm8001_ha,
3168 pm8001_printk(" PortInvalid portID %d\n", port_id));
3169 PM8001_MSG_DBG(pm8001_ha,
3170 pm8001_printk(" Last phy Down and port invalid\n"));
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]3171 if (port_sata) {
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3172 phy->phy_type = 0;
3173 port->port_attached = 0;
3174 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3175 port_id, phy_id, 0, 0);
3176 }
3177 sas_phy_disconnected(&phy->sas_phy);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3178 break;
3179 case PORT_IN_RESET:
3180 PM8001_MSG_DBG(pm8001_ha,
3181 pm8001_printk(" Port In Reset portID %d\n", port_id));
3182 break;
3183 case PORT_NOT_ESTABLISHED:
3184 PM8001_MSG_DBG(pm8001_ha,
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3185 pm8001_printk(" Phy Down and PORT_NOT_ESTABLISHED\n"));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3186 port->port_attached = 0;
3187 break;
3188 case PORT_LOSTCOMM:
3189 PM8001_MSG_DBG(pm8001_ha,
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3190 pm8001_printk(" Phy Down and PORT_LOSTCOMM\n"));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3191 PM8001_MSG_DBG(pm8001_ha,
3192 pm8001_printk(" Last phy Down and port invalid\n"));
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]3193 if (port_sata) {
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3194 port->port_attached = 0;
3195 phy->phy_type = 0;
3196 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3197 port_id, phy_id, 0, 0);
3198 }
3199 sas_phy_disconnected(&phy->sas_phy);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3200 break;
3201 default:
3202 port->port_attached = 0;
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]3203 PM8001_DEVIO_DBG(pm8001_ha,
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3204 pm8001_printk(" Phy Down and(default) = 0x%x\n",
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3205 portstate));
3206 break;
3207
3208 }
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]3209 if (port_sata && (portstate != PORT_IN_RESET)) {
3210 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3211
3212 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3213 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3214}
3215
3216static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3217{
3218 struct phy_start_resp *pPayload =
3219 (struct phy_start_resp *)(piomb + 4);
3220 u32 status =
3221 le32_to_cpu(pPayload->status);
3222 u32 phy_id =
3223 le32_to_cpu(pPayload->phyid);
3224 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3225
3226 PM8001_INIT_DBG(pm8001_ha,
3227 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
3228 status, phy_id));
3229 if (status == 0) {
Deepak Ukeycd135752018-09-11 14:18:02 +0530[diff] [blame]3230 phy->phy_state = PHY_LINK_DOWN;
3231 if (pm8001_ha->flags == PM8001F_RUN_TIME &&
peter change7039772019-11-14 15:38:59 +0530[diff] [blame]3232 phy->enable_completion != NULL) {
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3233 complete(phy->enable_completion);
peter change7039772019-11-14 15:38:59 +0530[diff] [blame]3234 phy->enable_completion = NULL;
3235 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3236 }
3237 return 0;
3238
3239}
3240
3241/**
3242 * mpi_thermal_hw_event -The hw event has come.
3243 * @pm8001_ha: our hba card information
3244 * @piomb: IO message buffer
3245 */
3246static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3247{
3248 struct thermal_hw_event *pPayload =
3249 (struct thermal_hw_event *)(piomb + 4);
3250
3251 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3252 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3253
3254 if (thermal_event & 0x40) {
3255 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3256 "Thermal Event: Local high temperature violated!\n"));
3257 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3258 "Thermal Event: Measured local high temperature %d\n",
3259 ((rht_lht & 0xFF00) >> 8)));
3260 }
3261 if (thermal_event & 0x10) {
3262 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3263 "Thermal Event: Remote high temperature violated!\n"));
3264 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3265 "Thermal Event: Measured remote high temperature %d\n",
3266 ((rht_lht & 0xFF000000) >> 24)));
3267 }
3268 return 0;
3269}
3270
3271/**
3272 * mpi_hw_event -The hw event has come.
3273 * @pm8001_ha: our hba card information
3274 * @piomb: IO message buffer
3275 */
3276static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3277{
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3278 unsigned long flags, i;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3279 struct hw_event_resp *pPayload =
3280 (struct hw_event_resp *)(piomb + 4);
3281 u32 lr_status_evt_portid =
3282 le32_to_cpu(pPayload->lr_status_evt_portid);
3283 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3284 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3285 u8 phy_id =
3286 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3287 u16 eventType =
3288 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3289 u8 status =
3290 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3291 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3292 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3293 struct pm8001_port *port = &pm8001_ha->port[port_id];
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3294 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]3295 PM8001_DEV_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3296 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
3297 port_id, phy_id, eventType, status));
3298
3299 switch (eventType) {
3300
3301 case HW_EVENT_SAS_PHY_UP:
3302 PM8001_MSG_DBG(pm8001_ha,
3303 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3304 hw_event_sas_phy_up(pm8001_ha, piomb);
3305 break;
3306 case HW_EVENT_SATA_PHY_UP:
3307 PM8001_MSG_DBG(pm8001_ha,
3308 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3309 hw_event_sata_phy_up(pm8001_ha, piomb);
3310 break;
3311 case HW_EVENT_SATA_SPINUP_HOLD:
3312 PM8001_MSG_DBG(pm8001_ha,
3313 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3314 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3315 break;
3316 case HW_EVENT_PHY_DOWN:
3317 PM8001_MSG_DBG(pm8001_ha,
3318 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]3319 hw_event_phy_down(pm8001_ha, piomb);
3320 if (pm8001_ha->reset_in_progress) {
3321 PM8001_MSG_DBG(pm8001_ha,
3322 pm8001_printk("Reset in progress\n"));
3323 return 0;
3324 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3325 phy->phy_attached = 0;
Deepak Ukeycd135752018-09-11 14:18:02 +0530[diff] [blame]3326 phy->phy_state = PHY_LINK_DISABLE;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3327 break;
3328 case HW_EVENT_PORT_INVALID:
3329 PM8001_MSG_DBG(pm8001_ha,
3330 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3331 sas_phy_disconnected(sas_phy);
3332 phy->phy_attached = 0;
3333 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3334 break;
3335 /* the broadcast change primitive received, tell the LIBSAS this event
3336 to revalidate the sas domain*/
3337 case HW_EVENT_BROADCAST_CHANGE:
3338 PM8001_MSG_DBG(pm8001_ha,
3339 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3340 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3341 port_id, phy_id, 1, 0);
3342 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3343 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3344 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3345 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3346 break;
3347 case HW_EVENT_PHY_ERROR:
3348 PM8001_MSG_DBG(pm8001_ha,
3349 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3350 sas_phy_disconnected(&phy->sas_phy);
3351 phy->phy_attached = 0;
3352 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3353 break;
3354 case HW_EVENT_BROADCAST_EXP:
3355 PM8001_MSG_DBG(pm8001_ha,
3356 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3357 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3358 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3359 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3360 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3361 break;
3362 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3363 PM8001_MSG_DBG(pm8001_ha,
3364 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3365 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3366 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3367 break;
3368 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3369 PM8001_MSG_DBG(pm8001_ha,
3370 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3371 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3372 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3373 port_id, phy_id, 0, 0);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3374 break;
3375 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3376 PM8001_MSG_DBG(pm8001_ha,
3377 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3378 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3379 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3380 port_id, phy_id, 0, 0);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3381 break;
3382 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3383 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3384 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3385 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3386 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3387 port_id, phy_id, 0, 0);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3388 break;
3389 case HW_EVENT_MALFUNCTION:
3390 PM8001_MSG_DBG(pm8001_ha,
3391 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3392 break;
3393 case HW_EVENT_BROADCAST_SES:
3394 PM8001_MSG_DBG(pm8001_ha,
3395 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3396 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3397 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3398 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3399 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3400 break;
3401 case HW_EVENT_INBOUND_CRC_ERROR:
3402 PM8001_MSG_DBG(pm8001_ha,
3403 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3404 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3405 HW_EVENT_INBOUND_CRC_ERROR,
3406 port_id, phy_id, 0, 0);
3407 break;
3408 case HW_EVENT_HARD_RESET_RECEIVED:
3409 PM8001_MSG_DBG(pm8001_ha,
3410 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3411 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3412 break;
3413 case HW_EVENT_ID_FRAME_TIMEOUT:
3414 PM8001_MSG_DBG(pm8001_ha,
3415 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3416 sas_phy_disconnected(sas_phy);
3417 phy->phy_attached = 0;
3418 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3419 break;
3420 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3421 PM8001_MSG_DBG(pm8001_ha,
3422 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3423 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3424 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3425 port_id, phy_id, 0, 0);
3426 sas_phy_disconnected(sas_phy);
3427 phy->phy_attached = 0;
3428 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3429 break;
3430 case HW_EVENT_PORT_RESET_TIMER_TMO:
3431 PM8001_MSG_DBG(pm8001_ha,
3432 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]3433 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3434 port_id, phy_id, 0, 0);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3435 sas_phy_disconnected(sas_phy);
3436 phy->phy_attached = 0;
3437 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]3438 if (pm8001_ha->phy[phy_id].reset_completion) {
3439 pm8001_ha->phy[phy_id].port_reset_status =
3440 PORT_RESET_TMO;
3441 complete(pm8001_ha->phy[phy_id].reset_completion);
3442 pm8001_ha->phy[phy_id].reset_completion = NULL;
3443 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3444 break;
3445 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3446 PM8001_MSG_DBG(pm8001_ha,
3447 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
Sakthivel Ka6cb3d02013-03-19 18:08:40 +0530[diff] [blame]3448 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3449 HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3450 port_id, phy_id, 0, 0);
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3451 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3452 if (port->wide_port_phymap & (1 << i)) {
3453 phy = &pm8001_ha->phy[i];
3454 sas_ha->notify_phy_event(&phy->sas_phy,
3455 PHYE_LOSS_OF_SIGNAL);
3456 port->wide_port_phymap &= ~(1 << i);
3457 }
3458 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3459 break;
3460 case HW_EVENT_PORT_RECOVER:
3461 PM8001_MSG_DBG(pm8001_ha,
3462 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
Viswas G8414cd82015-08-11 15:06:30 +0530[diff] [blame]3463 hw_event_port_recover(pm8001_ha, piomb);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3464 break;
3465 case HW_EVENT_PORT_RESET_COMPLETE:
3466 PM8001_MSG_DBG(pm8001_ha,
3467 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
Viswas G869ddbd2017-10-18 11:39:13 +0530[diff] [blame]3468 if (pm8001_ha->phy[phy_id].reset_completion) {
3469 pm8001_ha->phy[phy_id].port_reset_status =
3470 PORT_RESET_SUCCESS;
3471 complete(pm8001_ha->phy[phy_id].reset_completion);
3472 pm8001_ha->phy[phy_id].reset_completion = NULL;
3473 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3474 break;
3475 case EVENT_BROADCAST_ASYNCH_EVENT:
3476 PM8001_MSG_DBG(pm8001_ha,
3477 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3478 break;
3479 default:
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]3480 PM8001_DEVIO_DBG(pm8001_ha,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3481 pm8001_printk("Unknown event type 0x%x\n", eventType));
3482 break;
3483 }
3484 return 0;
3485}
3486
3487/**
3488 * mpi_phy_stop_resp - SPCv specific
3489 * @pm8001_ha: our hba card information
3490 * @piomb: IO message buffer
3491 */
3492static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3493{
3494 struct phy_stop_resp *pPayload =
3495 (struct phy_stop_resp *)(piomb + 4);
3496 u32 status =
3497 le32_to_cpu(pPayload->status);
3498 u32 phyid =
Deepak Ukeycd135752018-09-11 14:18:02 +0530[diff] [blame]3499 le32_to_cpu(pPayload->phyid) & 0xFF;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3500 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3501 PM8001_MSG_DBG(pm8001_ha,
3502 pm8001_printk("phy:0x%x status:0x%x\n",
3503 phyid, status));
Deepak Ukeycd135752018-09-11 14:18:02 +0530[diff] [blame]3504 if (status == PHY_STOP_SUCCESS ||
3505 status == PHY_STOP_ERR_DEVICE_ATTACHED)
3506 phy->phy_state = PHY_LINK_DISABLE;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3507 return 0;
3508}
3509
3510/**
3511 * mpi_set_controller_config_resp - SPCv specific
3512 * @pm8001_ha: our hba card information
3513 * @piomb: IO message buffer
3514 */
3515static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3516 void *piomb)
3517{
3518 struct set_ctrl_cfg_resp *pPayload =
3519 (struct set_ctrl_cfg_resp *)(piomb + 4);
3520 u32 status = le32_to_cpu(pPayload->status);
3521 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3522
3523 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3524 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3525 status, err_qlfr_pgcd));
3526
3527 return 0;
3528}
3529
3530/**
3531 * mpi_get_controller_config_resp - SPCv specific
3532 * @pm8001_ha: our hba card information
3533 * @piomb: IO message buffer
3534 */
3535static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3536 void *piomb)
3537{
3538 PM8001_MSG_DBG(pm8001_ha,
3539 pm8001_printk(" pm80xx_addition_functionality\n"));
3540
3541 return 0;
3542}
3543
3544/**
3545 * mpi_get_phy_profile_resp - SPCv specific
3546 * @pm8001_ha: our hba card information
3547 * @piomb: IO message buffer
3548 */
3549static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3550 void *piomb)
3551{
3552 PM8001_MSG_DBG(pm8001_ha,
3553 pm8001_printk(" pm80xx_addition_functionality\n"));
3554
3555 return 0;
3556}
3557
3558/**
3559 * mpi_flash_op_ext_resp - SPCv specific
3560 * @pm8001_ha: our hba card information
3561 * @piomb: IO message buffer
3562 */
3563static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3564{
3565 PM8001_MSG_DBG(pm8001_ha,
3566 pm8001_printk(" pm80xx_addition_functionality\n"));
3567
3568 return 0;
3569}
3570
3571/**
3572 * mpi_set_phy_profile_resp - SPCv specific
3573 * @pm8001_ha: our hba card information
3574 * @piomb: IO message buffer
3575 */
3576static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3577 void *piomb)
3578{
Anand Kumar Santhanam27909402013-09-18 13:02:44 +0530[diff] [blame]3579 u8 page_code;
3580 struct set_phy_profile_resp *pPayload =
3581 (struct set_phy_profile_resp *)(piomb + 4);
3582 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3583 u32 status = le32_to_cpu(pPayload->status);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3584
Anand Kumar Santhanam27909402013-09-18 13:02:44 +0530[diff] [blame]3585 page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3586 if (status) {
3587 /* status is FAILED */
3588 PM8001_FAIL_DBG(pm8001_ha,
3589 pm8001_printk("PhyProfile command failed with status "
3590 "0x%08X \n", status));
3591 return -1;
3592 } else {
3593 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3594 PM8001_FAIL_DBG(pm8001_ha,
3595 pm8001_printk("Invalid page code 0x%X\n",
3596 page_code));
3597 return -1;
3598 }
3599 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3600 return 0;
3601}
3602
3603/**
3604 * mpi_kek_management_resp - SPCv specific
3605 * @pm8001_ha: our hba card information
3606 * @piomb: IO message buffer
3607 */
3608static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3609 void *piomb)
3610{
3611 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3612
3613 u32 status = le32_to_cpu(pPayload->status);
3614 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3615 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3616
3617 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3618 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3619 status, kidx_new_curr_ksop, err_qlfr));
3620
3621 return 0;
3622}
3623
3624/**
3625 * mpi_dek_management_resp - SPCv specific
3626 * @pm8001_ha: our hba card information
3627 * @piomb: IO message buffer
3628 */
3629static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3630 void *piomb)
3631{
3632 PM8001_MSG_DBG(pm8001_ha,
3633 pm8001_printk(" pm80xx_addition_functionality\n"));
3634
3635 return 0;
3636}
3637
3638/**
3639 * ssp_coalesced_comp_resp - SPCv specific
3640 * @pm8001_ha: our hba card information
3641 * @piomb: IO message buffer
3642 */
3643static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3644 void *piomb)
3645{
3646 PM8001_MSG_DBG(pm8001_ha,
3647 pm8001_printk(" pm80xx_addition_functionality\n"));
3648
3649 return 0;
3650}
3651
3652/**
3653 * process_one_iomb - process one outbound Queue memory block
3654 * @pm8001_ha: our hba card information
3655 * @piomb: IO message buffer
3656 */
3657static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3658{
3659 __le32 pHeader = *(__le32 *)piomb;
3660 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3661
3662 switch (opc) {
3663 case OPC_OUB_ECHO:
3664 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3665 break;
3666 case OPC_OUB_HW_EVENT:
3667 PM8001_MSG_DBG(pm8001_ha,
3668 pm8001_printk("OPC_OUB_HW_EVENT\n"));
3669 mpi_hw_event(pm8001_ha, piomb);
3670 break;
3671 case OPC_OUB_THERM_HW_EVENT:
3672 PM8001_MSG_DBG(pm8001_ha,
3673 pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3674 mpi_thermal_hw_event(pm8001_ha, piomb);
3675 break;
3676 case OPC_OUB_SSP_COMP:
3677 PM8001_MSG_DBG(pm8001_ha,
3678 pm8001_printk("OPC_OUB_SSP_COMP\n"));
3679 mpi_ssp_completion(pm8001_ha, piomb);
3680 break;
3681 case OPC_OUB_SMP_COMP:
3682 PM8001_MSG_DBG(pm8001_ha,
3683 pm8001_printk("OPC_OUB_SMP_COMP\n"));
3684 mpi_smp_completion(pm8001_ha, piomb);
3685 break;
3686 case OPC_OUB_LOCAL_PHY_CNTRL:
3687 PM8001_MSG_DBG(pm8001_ha,
3688 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3689 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3690 break;
3691 case OPC_OUB_DEV_REGIST:
3692 PM8001_MSG_DBG(pm8001_ha,
3693 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3694 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3695 break;
3696 case OPC_OUB_DEREG_DEV:
3697 PM8001_MSG_DBG(pm8001_ha,
Masanari Iida8b513d02013-05-21 23:13:12 +0900[diff] [blame]3698 pm8001_printk("unregister the device\n"));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3699 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3700 break;
3701 case OPC_OUB_GET_DEV_HANDLE:
3702 PM8001_MSG_DBG(pm8001_ha,
3703 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3704 break;
3705 case OPC_OUB_SATA_COMP:
3706 PM8001_MSG_DBG(pm8001_ha,
3707 pm8001_printk("OPC_OUB_SATA_COMP\n"));
3708 mpi_sata_completion(pm8001_ha, piomb);
3709 break;
3710 case OPC_OUB_SATA_EVENT:
3711 PM8001_MSG_DBG(pm8001_ha,
3712 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3713 mpi_sata_event(pm8001_ha, piomb);
3714 break;
3715 case OPC_OUB_SSP_EVENT:
3716 PM8001_MSG_DBG(pm8001_ha,
3717 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3718 mpi_ssp_event(pm8001_ha, piomb);
3719 break;
3720 case OPC_OUB_DEV_HANDLE_ARRIV:
3721 PM8001_MSG_DBG(pm8001_ha,
3722 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3723 /*This is for target*/
3724 break;
3725 case OPC_OUB_SSP_RECV_EVENT:
3726 PM8001_MSG_DBG(pm8001_ha,
3727 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3728 /*This is for target*/
3729 break;
3730 case OPC_OUB_FW_FLASH_UPDATE:
3731 PM8001_MSG_DBG(pm8001_ha,
3732 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3733 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3734 break;
3735 case OPC_OUB_GPIO_RESPONSE:
3736 PM8001_MSG_DBG(pm8001_ha,
3737 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3738 break;
3739 case OPC_OUB_GPIO_EVENT:
3740 PM8001_MSG_DBG(pm8001_ha,
3741 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3742 break;
3743 case OPC_OUB_GENERAL_EVENT:
3744 PM8001_MSG_DBG(pm8001_ha,
3745 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3746 pm8001_mpi_general_event(pm8001_ha, piomb);
3747 break;
3748 case OPC_OUB_SSP_ABORT_RSP:
3749 PM8001_MSG_DBG(pm8001_ha,
3750 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3751 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3752 break;
3753 case OPC_OUB_SATA_ABORT_RSP:
3754 PM8001_MSG_DBG(pm8001_ha,
3755 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3756 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3757 break;
3758 case OPC_OUB_SAS_DIAG_MODE_START_END:
3759 PM8001_MSG_DBG(pm8001_ha,
3760 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3761 break;
3762 case OPC_OUB_SAS_DIAG_EXECUTE:
3763 PM8001_MSG_DBG(pm8001_ha,
3764 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3765 break;
3766 case OPC_OUB_GET_TIME_STAMP:
3767 PM8001_MSG_DBG(pm8001_ha,
3768 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3769 break;
3770 case OPC_OUB_SAS_HW_EVENT_ACK:
3771 PM8001_MSG_DBG(pm8001_ha,
3772 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3773 break;
3774 case OPC_OUB_PORT_CONTROL:
3775 PM8001_MSG_DBG(pm8001_ha,
3776 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3777 break;
3778 case OPC_OUB_SMP_ABORT_RSP:
3779 PM8001_MSG_DBG(pm8001_ha,
3780 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3781 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3782 break;
3783 case OPC_OUB_GET_NVMD_DATA:
3784 PM8001_MSG_DBG(pm8001_ha,
3785 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3786 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3787 break;
3788 case OPC_OUB_SET_NVMD_DATA:
3789 PM8001_MSG_DBG(pm8001_ha,
3790 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3791 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3792 break;
3793 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3794 PM8001_MSG_DBG(pm8001_ha,
3795 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3796 break;
3797 case OPC_OUB_SET_DEVICE_STATE:
3798 PM8001_MSG_DBG(pm8001_ha,
3799 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3800 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3801 break;
3802 case OPC_OUB_GET_DEVICE_STATE:
3803 PM8001_MSG_DBG(pm8001_ha,
3804 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3805 break;
3806 case OPC_OUB_SET_DEV_INFO:
3807 PM8001_MSG_DBG(pm8001_ha,
3808 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3809 break;
3810 /* spcv specifc commands */
3811 case OPC_OUB_PHY_START_RESP:
3812 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3813 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3814 mpi_phy_start_resp(pm8001_ha, piomb);
3815 break;
3816 case OPC_OUB_PHY_STOP_RESP:
3817 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3818 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3819 mpi_phy_stop_resp(pm8001_ha, piomb);
3820 break;
3821 case OPC_OUB_SET_CONTROLLER_CONFIG:
3822 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3823 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3824 mpi_set_controller_config_resp(pm8001_ha, piomb);
3825 break;
3826 case OPC_OUB_GET_CONTROLLER_CONFIG:
3827 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3828 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3829 mpi_get_controller_config_resp(pm8001_ha, piomb);
3830 break;
3831 case OPC_OUB_GET_PHY_PROFILE:
3832 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3833 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3834 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3835 break;
3836 case OPC_OUB_FLASH_OP_EXT:
3837 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3838 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3839 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3840 break;
3841 case OPC_OUB_SET_PHY_PROFILE:
3842 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3843 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3844 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3845 break;
3846 case OPC_OUB_KEK_MANAGEMENT_RESP:
3847 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3848 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3849 mpi_kek_management_resp(pm8001_ha, piomb);
3850 break;
3851 case OPC_OUB_DEK_MANAGEMENT_RESP:
3852 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3853 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3854 mpi_dek_management_resp(pm8001_ha, piomb);
3855 break;
3856 case OPC_OUB_SSP_COALESCED_COMP_RESP:
3857 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3858 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3859 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3860 break;
3861 default:
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]3862 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3863 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3864 break;
3865 }
3866}
3867
Deepak Ukey72349b62018-09-11 14:18:04 +0530[diff] [blame]3868static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
3869{
3870 PM8001_FAIL_DBG(pm8001_ha,
3871 pm8001_printk("MSGU_SCRATCH_PAD_0: 0x%x\n",
3872 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
3873 PM8001_FAIL_DBG(pm8001_ha,
3874 pm8001_printk("MSGU_SCRATCH_PAD_1:0x%x\n",
3875 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)));
3876 PM8001_FAIL_DBG(pm8001_ha,
3877 pm8001_printk("MSGU_SCRATCH_PAD_2: 0x%x\n",
3878 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)));
3879 PM8001_FAIL_DBG(pm8001_ha,
3880 pm8001_printk("MSGU_SCRATCH_PAD_3: 0x%x\n",
3881 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
3882 PM8001_FAIL_DBG(pm8001_ha,
3883 pm8001_printk("MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
3884 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0)));
3885 PM8001_FAIL_DBG(pm8001_ha,
3886 pm8001_printk("MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
3887 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1)));
3888 PM8001_FAIL_DBG(pm8001_ha,
3889 pm8001_printk("MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
3890 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2)));
3891 PM8001_FAIL_DBG(pm8001_ha,
3892 pm8001_printk("MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
3893 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3)));
3894 PM8001_FAIL_DBG(pm8001_ha,
3895 pm8001_printk("MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
3896 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4)));
3897 PM8001_FAIL_DBG(pm8001_ha,
3898 pm8001_printk("MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
3899 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5)));
3900 PM8001_FAIL_DBG(pm8001_ha,
3901 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
3902 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_6)));
3903 PM8001_FAIL_DBG(pm8001_ha,
3904 pm8001_printk("MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
3905 pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_7)));
3906}
3907
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3908static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3909{
3910 struct outbound_queue_table *circularQ;
3911 void *pMsg1 = NULL;
3912 u8 uninitialized_var(bc);
3913 u32 ret = MPI_IO_STATUS_FAIL;
3914 unsigned long flags;
Deepak Ukey72349b62018-09-11 14:18:04 +0530[diff] [blame]3915 u32 regval;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3916
Deepak Ukey72349b62018-09-11 14:18:04 +0530[diff] [blame]3917 if (vec == (pm8001_ha->number_of_intr - 1)) {
3918 regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
3919 if ((regval & SCRATCH_PAD_MIPSALL_READY) !=
3920 SCRATCH_PAD_MIPSALL_READY) {
3921 pm8001_ha->controller_fatal_error = true;
3922 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
3923 "Firmware Fatal error! Regval:0x%x\n", regval));
3924 print_scratchpad_registers(pm8001_ha);
3925 return ret;
3926 }
3927 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3928 spin_lock_irqsave(&pm8001_ha->lock, flags);
3929 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3930 do {
Deepak Ukey72349b62018-09-11 14:18:04 +0530[diff] [blame]3931 /* spurious interrupt during setup if kexec-ing and
3932 * driver doing a doorbell access w/ the pre-kexec oq
3933 * interrupt setup.
3934 */
3935 if (!circularQ->pi_virt)
3936 break;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3937 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3938 if (MPI_IO_STATUS_SUCCESS == ret) {
3939 /* process the outbound message */
3940 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3941 /* free the message from the outbound circular buffer */
3942 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3943 circularQ, bc);
3944 }
3945 if (MPI_IO_STATUS_BUSY == ret) {
3946 /* Update the producer index from SPC */
3947 circularQ->producer_index =
3948 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3949 if (le32_to_cpu(circularQ->producer_index) ==
3950 circularQ->consumer_idx)
3951 /* OQ is empty */
3952 break;
3953 }
3954 } while (1);
3955 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3956 return ret;
3957}
3958
Christoph Hellwigf73bdeb2018-10-10 19:59:50 +0200[diff] [blame]3959/* DMA_... to our direction translation. */
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3960static const u8 data_dir_flags[] = {
Christoph Hellwigf73bdeb2018-10-10 19:59:50 +0200[diff] [blame]3961 [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
3962 [DMA_TO_DEVICE] = DATA_DIR_OUT, /* OUTBOUND */
3963 [DMA_FROM_DEVICE] = DATA_DIR_IN, /* INBOUND */
3964 [DMA_NONE] = DATA_DIR_NONE, /* NO TRANSFER */
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]3965};
3966
3967static void build_smp_cmd(u32 deviceID, __le32 hTag,
3968 struct smp_req *psmp_cmd, int mode, int length)
3969{
3970 psmp_cmd->tag = hTag;
3971 psmp_cmd->device_id = cpu_to_le32(deviceID);
3972 if (mode == SMP_DIRECT) {
3973 length = length - 4; /* subtract crc */
3974 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
3975 } else {
3976 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3977 }
3978}
3979
3980/**
3981 * pm8001_chip_smp_req - send a SMP task to FW
3982 * @pm8001_ha: our hba card information.
3983 * @ccb: the ccb information this request used.
3984 */
3985static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3986 struct pm8001_ccb_info *ccb)
3987{
3988 int elem, rc;
3989 struct sas_task *task = ccb->task;
3990 struct domain_device *dev = task->dev;
3991 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3992 struct scatterlist *sg_req, *sg_resp;
3993 u32 req_len, resp_len;
3994 struct smp_req smp_cmd;
3995 u32 opc;
3996 struct inbound_queue_table *circularQ;
3997 char *preq_dma_addr = NULL;
3998 __le64 tmp_addr;
3999 u32 i, length;
4000
4001 memset(&smp_cmd, 0, sizeof(smp_cmd));
4002 /*
4003 * DMA-map SMP request, response buffers
4004 */
4005 sg_req = &task->smp_task.smp_req;
Christoph Hellwigf73bdeb2018-10-10 19:59:50 +0200[diff] [blame]4006 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4007 if (!elem)
4008 return -ENOMEM;
4009 req_len = sg_dma_len(sg_req);
4010
4011 sg_resp = &task->smp_task.smp_resp;
Christoph Hellwigf73bdeb2018-10-10 19:59:50 +0200[diff] [blame]4012 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4013 if (!elem) {
4014 rc = -ENOMEM;
4015 goto err_out;
4016 }
4017 resp_len = sg_dma_len(sg_resp);
4018 /* must be in dwords */
4019 if ((req_len & 0x3) || (resp_len & 0x3)) {
4020 rc = -EINVAL;
4021 goto err_out_2;
4022 }
4023
4024 opc = OPC_INB_SMP_REQUEST;
4025 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4026 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4027
4028 length = sg_req->length;
4029 PM8001_IO_DBG(pm8001_ha,
4030 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
4031 if (!(length - 8))
4032 pm8001_ha->smp_exp_mode = SMP_DIRECT;
4033 else
4034 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
4035
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4036
4037 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
4038 preq_dma_addr = (char *)phys_to_virt(tmp_addr);
4039
4040 /* INDIRECT MODE command settings. Use DMA */
4041 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
4042 PM8001_IO_DBG(pm8001_ha,
4043 pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
4044 /* for SPCv indirect mode. Place the top 4 bytes of
4045 * SMP Request header here. */
4046 for (i = 0; i < 4; i++)
4047 smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
4048 /* exclude top 4 bytes for SMP req header */
4049 smp_cmd.long_smp_req.long_req_addr =
4050 cpu_to_le64((u64)sg_dma_address
Anand Kumar Santhanamcb993e52013-09-17 14:37:14 +0530[diff] [blame]4051 (&task->smp_task.smp_req) + 4);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4052 /* exclude 4 bytes for SMP req header and CRC */
4053 smp_cmd.long_smp_req.long_req_size =
4054 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
4055 smp_cmd.long_smp_req.long_resp_addr =
4056 cpu_to_le64((u64)sg_dma_address
4057 (&task->smp_task.smp_resp));
4058 smp_cmd.long_smp_req.long_resp_size =
4059 cpu_to_le32((u32)sg_dma_len
4060 (&task->smp_task.smp_resp)-4);
4061 } else { /* DIRECT MODE */
4062 smp_cmd.long_smp_req.long_req_addr =
4063 cpu_to_le64((u64)sg_dma_address
4064 (&task->smp_task.smp_req));
4065 smp_cmd.long_smp_req.long_req_size =
4066 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4067 smp_cmd.long_smp_req.long_resp_addr =
4068 cpu_to_le64((u64)sg_dma_address
4069 (&task->smp_task.smp_resp));
4070 smp_cmd.long_smp_req.long_resp_size =
4071 cpu_to_le32
4072 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4073 }
4074 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
4075 PM8001_IO_DBG(pm8001_ha,
4076 pm8001_printk("SMP REQUEST DIRECT MODE\n"));
4077 for (i = 0; i < length; i++)
4078 if (i < 16) {
4079 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
4080 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4081 "Byte[%d]:%x (DMA data:%x)\n",
4082 i, smp_cmd.smp_req16[i],
4083 *(preq_dma_addr)));
4084 } else {
4085 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
4086 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4087 "Byte[%d]:%x (DMA data:%x)\n",
4088 i, smp_cmd.smp_req[i],
4089 *(preq_dma_addr)));
4090 }
4091 }
4092
4093 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
4094 &smp_cmd, pm8001_ha->smp_exp_mode, length);
peter chang91a43fa2019-11-14 15:39:05 +0530[diff] [blame]4095 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &smp_cmd,
4096 sizeof(smp_cmd), 0);
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]4097 if (rc)
4098 goto err_out_2;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4099 return 0;
4100
4101err_out_2:
4102 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
Christoph Hellwigf73bdeb2018-10-10 19:59:50 +0200[diff] [blame]4103 DMA_FROM_DEVICE);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4104err_out:
4105 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
Christoph Hellwigf73bdeb2018-10-10 19:59:50 +0200[diff] [blame]4106 DMA_TO_DEVICE);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4107 return rc;
4108}
4109
4110static int check_enc_sas_cmd(struct sas_task *task)
4111{
James Bottomleye73823f2013-05-07 15:38:18 -0700[diff] [blame]4112 u8 cmd = task->ssp_task.cmd->cmnd[0];
4113
4114 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4115 return 1;
4116 else
4117 return 0;
4118}
4119
4120static int check_enc_sat_cmd(struct sas_task *task)
4121{
4122 int ret = 0;
4123 switch (task->ata_task.fis.command) {
4124 case ATA_CMD_FPDMA_READ:
4125 case ATA_CMD_READ_EXT:
4126 case ATA_CMD_READ:
4127 case ATA_CMD_FPDMA_WRITE:
4128 case ATA_CMD_WRITE_EXT:
4129 case ATA_CMD_WRITE:
4130 case ATA_CMD_PIO_READ:
4131 case ATA_CMD_PIO_READ_EXT:
4132 case ATA_CMD_PIO_WRITE:
4133 case ATA_CMD_PIO_WRITE_EXT:
4134 ret = 1;
4135 break;
4136 default:
4137 ret = 0;
4138 break;
4139 }
4140 return ret;
4141}
4142
4143/**
4144 * pm80xx_chip_ssp_io_req - send a SSP task to FW
4145 * @pm8001_ha: our hba card information.
4146 * @ccb: the ccb information this request used.
4147 */
4148static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4149 struct pm8001_ccb_info *ccb)
4150{
4151 struct sas_task *task = ccb->task;
4152 struct domain_device *dev = task->dev;
4153 struct pm8001_device *pm8001_dev = dev->lldd_dev;
4154 struct ssp_ini_io_start_req ssp_cmd;
4155 u32 tag = ccb->ccb_tag;
4156 int ret;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]4157 u64 phys_addr, start_addr, end_addr;
4158 u32 end_addr_high, end_addr_low;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4159 struct inbound_queue_table *circularQ;
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4160 u32 q_index;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4161 u32 opc = OPC_INB_SSPINIIOSTART;
4162 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4163 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4164 /* data address domain added for spcv; set to 0 by host,
4165 * used internally by controller
4166 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
4167 */
4168 ssp_cmd.dad_dir_m_tlr =
4169 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4170 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4171 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4172 ssp_cmd.tag = cpu_to_le32(tag);
4173 if (task->ssp_task.enable_first_burst)
4174 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
4175 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4176 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
James Bottomleye73823f2013-05-07 15:38:18 -0700[diff] [blame]4177 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4178 task->ssp_task.cmd->cmd_len);
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4179 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4180 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4181
4182 /* Check if encryption is set */
4183 if (pm8001_ha->chip->encrypt &&
4184 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4185 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4186 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
James Bottomleye73823f2013-05-07 15:38:18 -0700[diff] [blame]4187 task->ssp_task.cmd->cmnd[0]));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4188 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4189 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4190 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4191 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4192
4193 /* fill in PRD (scatter/gather) table, if any */
4194 if (task->num_scatter > 1) {
4195 pm8001_chip_make_sg(task->scatter,
4196 ccb->n_elem, ccb->buf_prd);
4197 phys_addr = ccb->ccb_dma_handle +
4198 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4199 ssp_cmd.enc_addr_low =
4200 cpu_to_le32(lower_32_bits(phys_addr));
4201 ssp_cmd.enc_addr_high =
4202 cpu_to_le32(upper_32_bits(phys_addr));
4203 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4204 } else if (task->num_scatter == 1) {
4205 u64 dma_addr = sg_dma_address(task->scatter);
4206 ssp_cmd.enc_addr_low =
4207 cpu_to_le32(lower_32_bits(dma_addr));
4208 ssp_cmd.enc_addr_high =
4209 cpu_to_le32(upper_32_bits(dma_addr));
4210 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4211 ssp_cmd.enc_esgl = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]4212 /* Check 4G Boundary */
4213 start_addr = cpu_to_le64(dma_addr);
4214 end_addr = (start_addr + ssp_cmd.enc_len) - 1;
4215 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4216 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4217 if (end_addr_high != ssp_cmd.enc_addr_high) {
4218 PM8001_FAIL_DBG(pm8001_ha,
4219 pm8001_printk("The sg list address "
4220 "start_addr=0x%016llx data_len=0x%x "
4221 "end_addr_high=0x%08x end_addr_low="
4222 "0x%08x has crossed 4G boundary\n",
4223 start_addr, ssp_cmd.enc_len,
4224 end_addr_high, end_addr_low));
4225 pm8001_chip_make_sg(task->scatter, 1,
4226 ccb->buf_prd);
4227 phys_addr = ccb->ccb_dma_handle +
4228 offsetof(struct pm8001_ccb_info,
4229 buf_prd[0]);
4230 ssp_cmd.enc_addr_low =
4231 cpu_to_le32(lower_32_bits(phys_addr));
4232 ssp_cmd.enc_addr_high =
4233 cpu_to_le32(upper_32_bits(phys_addr));
4234 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4235 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4236 } else if (task->num_scatter == 0) {
4237 ssp_cmd.enc_addr_low = 0;
4238 ssp_cmd.enc_addr_high = 0;
4239 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4240 ssp_cmd.enc_esgl = 0;
4241 }
4242 /* XTS mode. All other fields are 0 */
4243 ssp_cmd.key_cmode = 0x6 << 4;
4244 /* set tweak values. Should be the start lba */
James Bottomleye73823f2013-05-07 15:38:18 -0700[diff] [blame]4245 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4246 (task->ssp_task.cmd->cmnd[3] << 16) |
4247 (task->ssp_task.cmd->cmnd[4] << 8) |
4248 (task->ssp_task.cmd->cmnd[5]));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4249 } else {
4250 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4251 "Sending Normal SAS command 0x%x inb q %x\n",
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4252 task->ssp_task.cmd->cmnd[0], q_index));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4253 /* fill in PRD (scatter/gather) table, if any */
4254 if (task->num_scatter > 1) {
4255 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4256 ccb->buf_prd);
4257 phys_addr = ccb->ccb_dma_handle +
4258 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4259 ssp_cmd.addr_low =
4260 cpu_to_le32(lower_32_bits(phys_addr));
4261 ssp_cmd.addr_high =
4262 cpu_to_le32(upper_32_bits(phys_addr));
4263 ssp_cmd.esgl = cpu_to_le32(1<<31);
4264 } else if (task->num_scatter == 1) {
4265 u64 dma_addr = sg_dma_address(task->scatter);
4266 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4267 ssp_cmd.addr_high =
4268 cpu_to_le32(upper_32_bits(dma_addr));
4269 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4270 ssp_cmd.esgl = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]4271 /* Check 4G Boundary */
4272 start_addr = cpu_to_le64(dma_addr);
4273 end_addr = (start_addr + ssp_cmd.len) - 1;
4274 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4275 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4276 if (end_addr_high != ssp_cmd.addr_high) {
4277 PM8001_FAIL_DBG(pm8001_ha,
4278 pm8001_printk("The sg list address "
4279 "start_addr=0x%016llx data_len=0x%x "
4280 "end_addr_high=0x%08x end_addr_low="
4281 "0x%08x has crossed 4G boundary\n",
4282 start_addr, ssp_cmd.len,
4283 end_addr_high, end_addr_low));
4284 pm8001_chip_make_sg(task->scatter, 1,
4285 ccb->buf_prd);
4286 phys_addr = ccb->ccb_dma_handle +
4287 offsetof(struct pm8001_ccb_info,
4288 buf_prd[0]);
4289 ssp_cmd.addr_low =
4290 cpu_to_le32(lower_32_bits(phys_addr));
4291 ssp_cmd.addr_high =
4292 cpu_to_le32(upper_32_bits(phys_addr));
4293 ssp_cmd.esgl = cpu_to_le32(1<<31);
4294 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4295 } else if (task->num_scatter == 0) {
4296 ssp_cmd.addr_low = 0;
4297 ssp_cmd.addr_high = 0;
4298 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4299 ssp_cmd.esgl = 0;
4300 }
4301 }
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4302 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4303 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
peter chang91a43fa2019-11-14 15:39:05 +0530[diff] [blame]4304 &ssp_cmd, sizeof(ssp_cmd), q_index);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4305 return ret;
4306}
4307
4308static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4309 struct pm8001_ccb_info *ccb)
4310{
4311 struct sas_task *task = ccb->task;
4312 struct domain_device *dev = task->dev;
4313 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4314 u32 tag = ccb->ccb_tag;
4315 int ret;
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4316 u32 q_index;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4317 struct sata_start_req sata_cmd;
4318 u32 hdr_tag, ncg_tag = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]4319 u64 phys_addr, start_addr, end_addr;
4320 u32 end_addr_high, end_addr_low;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4321 u32 ATAP = 0x0;
4322 u32 dir;
4323 struct inbound_queue_table *circularQ;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]4324 unsigned long flags;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4325 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4326 memset(&sata_cmd, 0, sizeof(sata_cmd));
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4327 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4328 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4329
Christoph Hellwigf73bdeb2018-10-10 19:59:50 +0200[diff] [blame]4330 if (task->data_dir == DMA_NONE) {
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4331 ATAP = 0x04; /* no data*/
4332 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4333 } else if (likely(!task->ata_task.device_control_reg_update)) {
4334 if (task->ata_task.dma_xfer) {
4335 ATAP = 0x06; /* DMA */
4336 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4337 } else {
4338 ATAP = 0x05; /* PIO*/
4339 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4340 }
4341 if (task->ata_task.use_ncq &&
Hannes Reinecke1cbd7722014-11-05 13:08:20 +0100[diff] [blame]4342 dev->sata_dev.class != ATA_DEV_ATAPI) {
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4343 ATAP = 0x07; /* FPDMA */
4344 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4345 }
4346 }
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]4347 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4348 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4349 ncg_tag = hdr_tag;
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]4350 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4351 dir = data_dir_flags[task->data_dir] << 8;
4352 sata_cmd.tag = cpu_to_le32(tag);
4353 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4354 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4355
4356 sata_cmd.sata_fis = task->ata_task.fis;
4357 if (likely(!task->ata_task.device_control_reg_update))
4358 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4359 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4360
4361 /* Check if encryption is set */
4362 if (pm8001_ha->chip->encrypt &&
4363 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4364 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4365 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4366 sata_cmd.sata_fis.command));
4367 opc = OPC_INB_SATA_DIF_ENC_IO;
4368
4369 /* set encryption bit */
4370 sata_cmd.ncqtag_atap_dir_m_dad =
4371 cpu_to_le32(((ncg_tag & 0xff)<<16)|
4372 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4373 /* dad (bit 0-1) is 0 */
4374 /* fill in PRD (scatter/gather) table, if any */
4375 if (task->num_scatter > 1) {
4376 pm8001_chip_make_sg(task->scatter,
4377 ccb->n_elem, ccb->buf_prd);
4378 phys_addr = ccb->ccb_dma_handle +
4379 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4380 sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
4381 sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
4382 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4383 } else if (task->num_scatter == 1) {
4384 u64 dma_addr = sg_dma_address(task->scatter);
4385 sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
4386 sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
4387 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4388 sata_cmd.enc_esgl = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]4389 /* Check 4G Boundary */
4390 start_addr = cpu_to_le64(dma_addr);
4391 end_addr = (start_addr + sata_cmd.enc_len) - 1;
4392 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4393 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4394 if (end_addr_high != sata_cmd.enc_addr_high) {
4395 PM8001_FAIL_DBG(pm8001_ha,
4396 pm8001_printk("The sg list address "
4397 "start_addr=0x%016llx data_len=0x%x "
4398 "end_addr_high=0x%08x end_addr_low"
4399 "=0x%08x has crossed 4G boundary\n",
4400 start_addr, sata_cmd.enc_len,
4401 end_addr_high, end_addr_low));
4402 pm8001_chip_make_sg(task->scatter, 1,
4403 ccb->buf_prd);
4404 phys_addr = ccb->ccb_dma_handle +
4405 offsetof(struct pm8001_ccb_info,
4406 buf_prd[0]);
4407 sata_cmd.enc_addr_low =
4408 lower_32_bits(phys_addr);
4409 sata_cmd.enc_addr_high =
4410 upper_32_bits(phys_addr);
4411 sata_cmd.enc_esgl =
4412 cpu_to_le32(1 << 31);
4413 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4414 } else if (task->num_scatter == 0) {
4415 sata_cmd.enc_addr_low = 0;
4416 sata_cmd.enc_addr_high = 0;
4417 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4418 sata_cmd.enc_esgl = 0;
4419 }
4420 /* XTS mode. All other fields are 0 */
4421 sata_cmd.key_index_mode = 0x6 << 4;
4422 /* set tweak values. Should be the start lba */
4423 sata_cmd.twk_val0 =
4424 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4425 (sata_cmd.sata_fis.lbah << 16) |
4426 (sata_cmd.sata_fis.lbam << 8) |
4427 (sata_cmd.sata_fis.lbal));
4428 sata_cmd.twk_val1 =
4429 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4430 (sata_cmd.sata_fis.lbam_exp));
4431 } else {
4432 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4433 "Sending Normal SATA command 0x%x inb %x\n",
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4434 sata_cmd.sata_fis.command, q_index));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4435 /* dad (bit 0-1) is 0 */
4436 sata_cmd.ncqtag_atap_dir_m_dad =
4437 cpu_to_le32(((ncg_tag & 0xff)<<16) |
4438 ((ATAP & 0x3f) << 10) | dir);
4439
4440 /* fill in PRD (scatter/gather) table, if any */
4441 if (task->num_scatter > 1) {
4442 pm8001_chip_make_sg(task->scatter,
4443 ccb->n_elem, ccb->buf_prd);
4444 phys_addr = ccb->ccb_dma_handle +
4445 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4446 sata_cmd.addr_low = lower_32_bits(phys_addr);
4447 sata_cmd.addr_high = upper_32_bits(phys_addr);
4448 sata_cmd.esgl = cpu_to_le32(1 << 31);
4449 } else if (task->num_scatter == 1) {
4450 u64 dma_addr = sg_dma_address(task->scatter);
4451 sata_cmd.addr_low = lower_32_bits(dma_addr);
4452 sata_cmd.addr_high = upper_32_bits(dma_addr);
4453 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4454 sata_cmd.esgl = 0;
Anand Kumar Santhanam0ecdf002013-09-18 11:14:54 +0530[diff] [blame]4455 /* Check 4G Boundary */
4456 start_addr = cpu_to_le64(dma_addr);
4457 end_addr = (start_addr + sata_cmd.len) - 1;
4458 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4459 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4460 if (end_addr_high != sata_cmd.addr_high) {
4461 PM8001_FAIL_DBG(pm8001_ha,
4462 pm8001_printk("The sg list address "
4463 "start_addr=0x%016llx data_len=0x%x"
4464 "end_addr_high=0x%08x end_addr_low="
4465 "0x%08x has crossed 4G boundary\n",
4466 start_addr, sata_cmd.len,
4467 end_addr_high, end_addr_low));
4468 pm8001_chip_make_sg(task->scatter, 1,
4469 ccb->buf_prd);
4470 phys_addr = ccb->ccb_dma_handle +
4471 offsetof(struct pm8001_ccb_info,
4472 buf_prd[0]);
4473 sata_cmd.addr_low =
4474 lower_32_bits(phys_addr);
4475 sata_cmd.addr_high =
4476 upper_32_bits(phys_addr);
4477 sata_cmd.esgl = cpu_to_le32(1 << 31);
4478 }
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4479 } else if (task->num_scatter == 0) {
4480 sata_cmd.addr_low = 0;
4481 sata_cmd.addr_high = 0;
4482 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4483 sata_cmd.esgl = 0;
4484 }
Colin Ian King9e2a07e2019-03-17 18:15:32 +0000[diff] [blame]4485 /* scsi cdb */
4486 sata_cmd.atapi_scsi_cdb[0] =
4487 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4488 (task->ata_task.atapi_packet[1] << 8) |
4489 (task->ata_task.atapi_packet[2] << 16) |
4490 (task->ata_task.atapi_packet[3] << 24)));
4491 sata_cmd.atapi_scsi_cdb[1] =
4492 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4493 (task->ata_task.atapi_packet[5] << 8) |
4494 (task->ata_task.atapi_packet[6] << 16) |
4495 (task->ata_task.atapi_packet[7] << 24)));
4496 sata_cmd.atapi_scsi_cdb[2] =
4497 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4498 (task->ata_task.atapi_packet[9] << 8) |
4499 (task->ata_task.atapi_packet[10] << 16) |
4500 (task->ata_task.atapi_packet[11] << 24)));
4501 sata_cmd.atapi_scsi_cdb[3] =
4502 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4503 (task->ata_task.atapi_packet[13] << 8) |
4504 (task->ata_task.atapi_packet[14] << 16) |
4505 (task->ata_task.atapi_packet[15] << 24)));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4506 }
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]4507
4508 /* Check for read log for failed drive and return */
4509 if (sata_cmd.sata_fis.command == 0x2f) {
4510 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4511 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4512 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4513 struct task_status_struct *ts;
4514
4515 pm8001_ha_dev->id &= 0xDFFFFFFF;
4516 ts = &task->task_status;
4517
4518 spin_lock_irqsave(&task->task_state_lock, flags);
4519 ts->resp = SAS_TASK_COMPLETE;
4520 ts->stat = SAM_STAT_GOOD;
4521 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4522 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4523 task->task_state_flags |= SAS_TASK_STATE_DONE;
4524 if (unlikely((task->task_state_flags &
4525 SAS_TASK_STATE_ABORTED))) {
4526 spin_unlock_irqrestore(&task->task_state_lock,
4527 flags);
4528 PM8001_FAIL_DBG(pm8001_ha,
4529 pm8001_printk("task 0x%p resp 0x%x "
4530 " stat 0x%x but aborted by upper layer "
4531 "\n", task, ts->resp, ts->stat));
4532 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4533 return 0;
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]4534 } else {
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]4535 spin_unlock_irqrestore(&task->task_state_lock,
4536 flags);
Suresh Thiagarajan2b01d812014-01-16 15:26:21 +0530[diff] [blame]4537 pm8001_ccb_task_free_done(pm8001_ha, task,
4538 ccb, tag);
Sakthivel Kc6b9ef52013-03-19 18:08:08 +0530[diff] [blame]4539 return 0;
4540 }
4541 }
4542 }
Anand Kumar Santhanamf9cd6cb2013-09-18 11:12:59 +0530[diff] [blame]4543 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4544 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
peter chang91a43fa2019-11-14 15:39:05 +0530[diff] [blame]4545 &sata_cmd, sizeof(sata_cmd), q_index);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4546 return ret;
4547}
4548
4549/**
4550 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4551 * @pm8001_ha: our hba card information.
4552 * @num: the inbound queue number
4553 * @phy_id: the phy id which we wanted to start up.
4554 */
4555static int
4556pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4557{
4558 struct phy_start_req payload;
4559 struct inbound_queue_table *circularQ;
4560 int ret;
4561 u32 tag = 0x01;
4562 u32 opcode = OPC_INB_PHYSTART;
4563 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4564 memset(&payload, 0, sizeof(payload));
4565 payload.tag = cpu_to_le32(tag);
4566
4567 PM8001_INIT_DBG(pm8001_ha,
4568 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
Anand Kumar Santhanama9a923e2013-09-03 15:09:42 +0530[diff] [blame]4569
peter chang3e253d92019-11-14 15:39:07 +0530[diff] [blame]4570 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4571 LINKMODE_AUTO | pm8001_ha->link_rate | phy_id);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4572 /* SSC Disable and SAS Analog ST configuration */
4573 /**
4574 payload.ase_sh_lm_slr_phyid =
4575 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4576 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4577 phy_id);
4578 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4579 **/
4580
James Bottomleyaa9f8322013-05-07 14:44:06 -0700[diff] [blame]4581 payload.sas_identify.dev_type = SAS_END_DEVICE;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4582 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4583 memcpy(payload.sas_identify.sas_addr,
peter chang3e253d92019-11-14 15:39:07 +0530[diff] [blame]4584 &pm8001_ha->sas_addr, SAS_ADDR_SIZE);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4585 payload.sas_identify.phy_id = phy_id;
peter chang91a43fa2019-11-14 15:39:05 +0530[diff] [blame]4586 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4587 sizeof(payload), 0);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4588 return ret;
4589}
4590
4591/**
4592 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4593 * @pm8001_ha: our hba card information.
4594 * @num: the inbound queue number
4595 * @phy_id: the phy id which we wanted to start up.
4596 */
4597static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4598 u8 phy_id)
4599{
4600 struct phy_stop_req payload;
4601 struct inbound_queue_table *circularQ;
4602 int ret;
4603 u32 tag = 0x01;
4604 u32 opcode = OPC_INB_PHYSTOP;
4605 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4606 memset(&payload, 0, sizeof(payload));
4607 payload.tag = cpu_to_le32(tag);
4608 payload.phy_id = cpu_to_le32(phy_id);
peter chang91a43fa2019-11-14 15:39:05 +0530[diff] [blame]4609 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload,
4610 sizeof(payload), 0);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4611 return ret;
4612}
4613
4614/**
4615 * see comments on pm8001_mpi_reg_resp.
4616 */
4617static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4618 struct pm8001_device *pm8001_dev, u32 flag)
4619{
4620 struct reg_dev_req payload;
4621 u32 opc;
4622 u32 stp_sspsmp_sata = 0x4;
4623 struct inbound_queue_table *circularQ;
4624 u32 linkrate, phy_id;
4625 int rc, tag = 0xdeadbeef;
4626 struct pm8001_ccb_info *ccb;
4627 u8 retryFlag = 0x1;
4628 u16 firstBurstSize = 0;
4629 u16 ITNT = 2000;
4630 struct domain_device *dev = pm8001_dev->sas_device;
4631 struct domain_device *parent_dev = dev->parent;
4632 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4633
4634 memset(&payload, 0, sizeof(payload));
4635 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4636 if (rc)
4637 return rc;
4638 ccb = &pm8001_ha->ccb_info[tag];
4639 ccb->device = pm8001_dev;
4640 ccb->ccb_tag = tag;
4641 payload.tag = cpu_to_le32(tag);
4642
4643 if (flag == 1) {
4644 stp_sspsmp_sata = 0x02; /*direct attached sata */
4645 } else {
James Bottomleyaa9f8322013-05-07 14:44:06 -0700[diff] [blame]4646 if (pm8001_dev->dev_type == SAS_SATA_DEV)
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4647 stp_sspsmp_sata = 0x00; /* stp*/
James Bottomleyaa9f8322013-05-07 14:44:06 -0700[diff] [blame]4648 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4649 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4650 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4651 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4652 }
John Garry924a3542019-06-10 20:41:41 +0800[diff] [blame]4653 if (parent_dev && dev_is_expander(parent_dev->dev_type))
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4654 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4655 else
4656 phy_id = pm8001_dev->attached_phy;
4657
4658 opc = OPC_INB_REG_DEV;
4659
4660 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4661 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4662
4663 payload.phyid_portid =
4664 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4665 ((phy_id & 0xFF) << 8));
4666
4667 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4668 ((linkrate & 0x0F) << 24) |
4669 ((stp_sspsmp_sata & 0x03) << 28));
4670 payload.firstburstsize_ITNexustimeout =
4671 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4672
4673 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4674 SAS_ADDR_SIZE);
4675
peter chang91a43fa2019-11-14 15:39:05 +0530[diff] [blame]4676 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4677 sizeof(payload), 0);
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]4678 if (rc)
4679 pm8001_tag_free(pm8001_ha, tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4680
4681 return rc;
4682}
4683
4684/**
4685 * pm80xx_chip_phy_ctl_req - support the local phy operation
4686 * @pm8001_ha: our hba card information.
4687 * @num: the inbound queue number
4688 * @phy_id: the phy id which we wanted to operate
4689 * @phy_op:
4690 */
4691static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4692 u32 phyId, u32 phy_op)
4693{
Viswas G25c6edb2017-10-18 11:39:10 +0530[diff] [blame]4694 u32 tag;
4695 int rc;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4696 struct local_phy_ctl_req payload;
4697 struct inbound_queue_table *circularQ;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4698 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4699 memset(&payload, 0, sizeof(payload));
Viswas G25c6edb2017-10-18 11:39:10 +0530[diff] [blame]4700 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4701 if (rc)
4702 return rc;
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4703 circularQ = &pm8001_ha->inbnd_q_tbl[0];
Viswas G25c6edb2017-10-18 11:39:10 +0530[diff] [blame]4704 payload.tag = cpu_to_le32(tag);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4705 payload.phyop_phyid =
4706 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
peter chang91a43fa2019-11-14 15:39:05 +0530[diff] [blame]4707 return pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4708 sizeof(payload), 0);
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4709}
4710
Colin Ian Kingf310a4e2019-03-29 23:44:23 +0000[diff] [blame]4711static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4712{
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4713#ifdef PM8001_USE_MSIX
4714 return 1;
Colin Ian King292c04c2019-03-28 23:43:28 +0000[diff] [blame]4715#else
4716 u32 value;
4717
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4718 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4719 if (value)
4720 return 1;
4721 return 0;
Colin Ian King292c04c2019-03-28 23:43:28 +0000[diff] [blame]4722#endif
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4723}
4724
4725/**
4726 * pm8001_chip_isr - PM8001 isr handler.
4727 * @pm8001_ha: our hba card information.
4728 * @irq: irq number.
4729 * @stat: stat.
4730 */
4731static irqreturn_t
4732pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4733{
4734 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
peter chang73706722019-11-14 15:39:02 +0530[diff] [blame]4735 PM8001_DEVIO_DBG(pm8001_ha, pm8001_printk(
4736 "irq vec %d, ODMR:0x%x\n",
4737 vec, pm8001_cr32(pm8001_ha, 0, 0x30)));
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4738 process_oq(pm8001_ha, vec);
4739 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4740 return IRQ_HANDLED;
4741}
4742
Anand Kumar Santhanam27909402013-09-18 13:02:44 +0530[diff] [blame]4743void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4744 u32 operation, u32 phyid, u32 length, u32 *buf)
4745{
4746 u32 tag , i, j = 0;
4747 int rc;
4748 struct set_phy_profile_req payload;
4749 struct inbound_queue_table *circularQ;
4750 u32 opc = OPC_INB_SET_PHY_PROFILE;
4751
4752 memset(&payload, 0, sizeof(payload));
4753 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4754 if (rc)
4755 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
4756 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4757 payload.tag = cpu_to_le32(tag);
4758 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF));
4759 PM8001_INIT_DBG(pm8001_ha,
4760 pm8001_printk(" phy profile command for phy %x ,length is %d\n",
4761 payload.ppc_phyid, length));
4762 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4763 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
4764 j++;
4765 }
peter chang91a43fa2019-11-14 15:39:05 +0530[diff] [blame]4766 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4767 sizeof(payload), 0);
Tomas Henzl5533abc2014-07-09 17:20:49 +0530[diff] [blame]4768 if (rc)
4769 pm8001_tag_free(pm8001_ha, tag);
Anand Kumar Santhanam27909402013-09-18 13:02:44 +0530[diff] [blame]4770}
4771
4772void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4773 u32 length, u8 *buf)
4774{
YueHaibingfdd0a662018-09-14 01:38:56 +0000[diff] [blame]4775 u32 i;
Anand Kumar Santhanam27909402013-09-18 13:02:44 +0530[diff] [blame]4776
Anand Kumar Santhanam27909402013-09-18 13:02:44 +0530[diff] [blame]4777 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4778 mpi_set_phy_profile_req(pm8001_ha,
4779 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4780 length = length + PHY_DWORD_LENGTH;
4781 }
4782 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
4783}
Benjamin Roodc5614df2015-10-30 10:53:28 -0400[diff] [blame]4784
4785void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
4786 u32 phy, u32 length, u32 *buf)
4787{
4788 u32 tag, opc;
4789 int rc, i;
4790 struct set_phy_profile_req payload;
4791 struct inbound_queue_table *circularQ;
4792
4793 memset(&payload, 0, sizeof(payload));
4794
4795 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4796 if (rc)
4797 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("Invalid tag"));
4798
4799 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4800 opc = OPC_INB_SET_PHY_PROFILE;
4801
4802 payload.tag = cpu_to_le32(tag);
4803 payload.ppc_phyid = (((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
4804 | (phy & 0xFF));
4805
4806 for (i = 0; i < length; i++)
4807 payload.reserved[i] = cpu_to_le32(*(buf + i));
4808
peter chang91a43fa2019-11-14 15:39:05 +0530[diff] [blame]4809 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
4810 sizeof(payload), 0);
Benjamin Roodc5614df2015-10-30 10:53:28 -0400[diff] [blame]4811 if (rc)
4812 pm8001_tag_free(pm8001_ha, tag);
4813
4814 PM8001_INIT_DBG(pm8001_ha,
4815 pm8001_printk("PHY %d settings applied", phy));
4816}
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4817const struct pm8001_dispatch pm8001_80xx_dispatch = {
4818 .name = "pmc80xx",
4819 .chip_init = pm80xx_chip_init,
4820 .chip_soft_rst = pm80xx_chip_soft_rst,
4821 .chip_rst = pm80xx_hw_chip_rst,
4822 .chip_iounmap = pm8001_chip_iounmap,
4823 .isr = pm80xx_chip_isr,
Colin Ian Kingf310a4e2019-03-29 23:44:23 +0000[diff] [blame]4824 .is_our_interrupt = pm80xx_chip_is_our_interrupt,
Sakthivel Kf5860992013-04-17 16:37:02 +0530[diff] [blame]4825 .isr_process_oq = process_oq,
4826 .interrupt_enable = pm80xx_chip_interrupt_enable,
4827 .interrupt_disable = pm80xx_chip_interrupt_disable,
4828 .make_prd = pm8001_chip_make_sg,
4829 .smp_req = pm80xx_chip_smp_req,
4830 .ssp_io_req = pm80xx_chip_ssp_io_req,
4831 .sata_req = pm80xx_chip_sata_req,
4832 .phy_start_req = pm80xx_chip_phy_start_req,
4833 .phy_stop_req = pm80xx_chip_phy_stop_req,
4834 .reg_dev_req = pm80xx_chip_reg_dev_req,
4835 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4836 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
4837 .task_abort = pm8001_chip_abort_task,
4838 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4839 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4840 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4841 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4842 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4843};