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Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Paul Mackerras14cf11a2005-09-26 16:04:21 +10002/*
Kumar Gala4c8d3d92005-11-13 16:06:30 -08003 * Modifications by Kumar Gala (galak@kernel.crashing.org) to support
Paul Mackerras14cf11a2005-09-26 16:04:21 +10004 * E500 Book E processors.
5 *
Kumar Gala78f62232010-05-13 14:38:21 -05006 * Copyright 2004,2010 Freescale Semiconductor, Inc.
Paul Mackerras14cf11a2005-09-26 16:04:21 +10007 *
8 * This file contains the routines for initializing the MMU
9 * on the 4xx series of chips.
10 * -- paulus
11 *
12 * Derived from arch/ppc/mm/init.c:
13 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
14 *
15 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
16 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
17 * Copyright (C) 1996 Paul Mackerras
Paul Mackerras14cf11a2005-09-26 16:04:21 +100018 *
19 * Derived from "arch/i386/mm/init.c"
20 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
Paul Mackerras14cf11a2005-09-26 16:04:21 +100021 */
22
Paul Mackerras14cf11a2005-09-26 16:04:21 +100023#include <linux/signal.h>
24#include <linux/sched.h>
25#include <linux/kernel.h>
26#include <linux/errno.h>
27#include <linux/string.h>
28#include <linux/types.h>
29#include <linux/ptrace.h>
30#include <linux/mman.h>
31#include <linux/mm.h>
32#include <linux/swap.h>
33#include <linux/stddef.h>
34#include <linux/vmalloc.h>
35#include <linux/init.h>
36#include <linux/delay.h>
37#include <linux/highmem.h>
Benjamin Herrenschmidte63075a2010-07-06 15:39:01 -070038#include <linux/memblock.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100039
Paul Mackerras14cf11a2005-09-26 16:04:21 +100040#include <asm/prom.h>
41#include <asm/io.h>
42#include <asm/mmu_context.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100043#include <asm/mmu.h>
Linus Torvalds7c0f6ba2016-12-24 11:46:01 -080044#include <linux/uaccess.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100045#include <asm/smp.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100046#include <asm/machdep.h>
47#include <asm/setup.h>
Scott Wood28efc352013-10-11 19:22:38 -050048#include <asm/paca.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100049
Christophe Leroy9d9f2cc2019-03-29 09:59:59 +000050#include <mm/mmu_decl.h>
Kumar Gala99c62dd72008-04-16 05:52:21 +100051
Paul Mackerras14cf11a2005-09-26 16:04:21 +100052unsigned int tlbcam_index;
Paul Mackerras14cf11a2005-09-26 16:04:21 +100053
Kumar Gala78f62232010-05-13 14:38:21 -050054#define NUM_TLBCAMS (64)
55struct tlbcam TLBCAM[NUM_TLBCAMS];
Paul Mackerras14cf11a2005-09-26 16:04:21 +100056
57struct tlbcamrange {
Kumar Gala8b27f0b2009-10-15 12:49:01 -050058 unsigned long start;
Paul Mackerras14cf11a2005-09-26 16:04:21 +100059 unsigned long limit;
60 phys_addr_t phys;
61} tlbcam_addrs[NUM_TLBCAMS];
62
Kumar Gala8b27f0b2009-10-15 12:49:01 -050063unsigned long tlbcam_sz(int idx)
64{
65 return tlbcam_addrs[idx].limit - tlbcam_addrs[idx].start + 1;
66}
67
Christophe Leroy3084cdb2016-02-09 17:07:58 +010068#ifdef CONFIG_FSL_BOOKE
Paul Mackerras14cf11a2005-09-26 16:04:21 +100069/*
70 * Return PA for this VA if it is mapped by a CAM, or 0
71 */
Christophe Leroy3084cdb2016-02-09 17:07:58 +010072phys_addr_t v_block_mapped(unsigned long va)
Paul Mackerras14cf11a2005-09-26 16:04:21 +100073{
74 int b;
75 for (b = 0; b < tlbcam_index; ++b)
76 if (va >= tlbcam_addrs[b].start && va < tlbcam_addrs[b].limit)
77 return tlbcam_addrs[b].phys + (va - tlbcam_addrs[b].start);
78 return 0;
79}
80
81/*
82 * Return VA for a given PA or 0 if not mapped
83 */
Christophe Leroy3084cdb2016-02-09 17:07:58 +010084unsigned long p_block_mapped(phys_addr_t pa)
Paul Mackerras14cf11a2005-09-26 16:04:21 +100085{
86 int b;
87 for (b = 0; b < tlbcam_index; ++b)
88 if (pa >= tlbcam_addrs[b].phys
Kumar Gala8b27f0b2009-10-15 12:49:01 -050089 && pa < (tlbcam_addrs[b].limit-tlbcam_addrs[b].start)
Paul Mackerras14cf11a2005-09-26 16:04:21 +100090 +tlbcam_addrs[b].phys)
91 return tlbcam_addrs[b].start+(pa-tlbcam_addrs[b].phys);
92 return 0;
93}
Christophe Leroy3084cdb2016-02-09 17:07:58 +010094#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +100095
96/*
Becky Bruced10ac372010-06-30 10:23:31 +000097 * Set up a variable-size TLB entry (tlbcam). The parameters are not checked;
Becky Bruce45594242011-10-12 16:17:02 -050098 * in particular size must be a power of 4 between 4k and the max supported by
99 * an implementation; max may further be limited by what can be represented in
100 * an unsigned long (for example, 32-bit implementations cannot support a 4GB
101 * size).
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000102 */
Kumar Gala8b27f0b2009-10-15 12:49:01 -0500103static void settlbcam(int index, unsigned long virt, phys_addr_t phys,
104 unsigned long size, unsigned long flags, unsigned int pid)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000105{
Becky Bruce45594242011-10-12 16:17:02 -0500106 unsigned int tsize;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000107
Becky Bruce45594242011-10-12 16:17:02 -0500108 tsize = __ilog2(size) - 10;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000109
Scott Woodc6023202015-07-18 14:24:58 -0500110#if defined(CONFIG_SMP) || defined(CONFIG_PPC_E500MC)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000111 if ((flags & _PAGE_NO_CACHE) == 0)
112 flags |= _PAGE_COHERENT;
113#endif
114
115 TLBCAM[index].MAS0 = MAS0_TLBSEL(1) | MAS0_ESEL(index) | MAS0_NV(index+1);
116 TLBCAM[index].MAS1 = MAS1_VALID | MAS1_IPROT | MAS1_TSIZE(tsize) | MAS1_TID(pid);
117 TLBCAM[index].MAS2 = virt & PAGE_MASK;
118
119 TLBCAM[index].MAS2 |= (flags & _PAGE_WRITETHRU) ? MAS2_W : 0;
120 TLBCAM[index].MAS2 |= (flags & _PAGE_NO_CACHE) ? MAS2_I : 0;
121 TLBCAM[index].MAS2 |= (flags & _PAGE_COHERENT) ? MAS2_M : 0;
122 TLBCAM[index].MAS2 |= (flags & _PAGE_GUARDED) ? MAS2_G : 0;
123 TLBCAM[index].MAS2 |= (flags & _PAGE_ENDIAN) ? MAS2_E : 0;
124
Christophe Leroy01116e62021-10-15 12:02:44 +0200125 TLBCAM[index].MAS3 = (phys & MAS3_RPN) | MAS3_SR;
126 TLBCAM[index].MAS3 |= (flags & _PAGE_BAP_SX) ? MAS3_SX : 0;
127 TLBCAM[index].MAS3 |= (flags & _PAGE_RW) ? MAS3_SW : 0;
Becky Brucee8137342010-04-12 11:21:50 -0500128 if (mmu_has_feature(MMU_FTR_BIG_PHYS))
Kumar Gala8b27f0b2009-10-15 12:49:01 -0500129 TLBCAM[index].MAS7 = (u64)phys >> 32;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000130
Paul Gortmaker92437d42010-09-24 12:44:52 -0400131 /* Below is unlikely -- only for large user pages or similar */
Michael Ellerman7e1e63c2016-04-29 23:25:32 +1000132 if (pte_user(__pte(flags))) {
Christophe Leroy01116e62021-10-15 12:02:44 +0200133 TLBCAM[index].MAS3 |= MAS3_UR;
134 TLBCAM[index].MAS3 |= (flags & _PAGE_EXEC) ? MAS3_UX : 0;
135 TLBCAM[index].MAS3 |= (flags & _PAGE_RW) ? MAS3_UW : 0;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000136 }
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000137
138 tlbcam_addrs[index].start = virt;
139 tlbcam_addrs[index].limit = virt + size - 1;
140 tlbcam_addrs[index].phys = phys;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000141}
142
Kumar Gala1dc91c32011-09-16 10:39:59 -0500143unsigned long calc_cam_sz(unsigned long ram, unsigned long virt,
144 phys_addr_t phys)
145{
Kumar Galaf0b8b342012-01-05 12:37:16 -0600146 unsigned int camsize = __ilog2(ram);
147 unsigned int align = __ffs(virt | phys);
148 unsigned long max_cam;
Kumar Gala1dc91c32011-09-16 10:39:59 -0500149
Kumar Galaf0b8b342012-01-05 12:37:16 -0600150 if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
151 /* Convert (4^max) kB to (2^max) bytes */
152 max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
153 camsize &= ~1U;
154 align &= ~1U;
155 } else {
156 /* Convert (2^max) kB to (2^max) bytes */
157 max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
158 }
Kumar Gala1dc91c32011-09-16 10:39:59 -0500159
160 if (camsize > align)
161 camsize = align;
162 if (camsize > max_cam)
163 camsize = max_cam;
164
165 return 1UL << camsize;
166}
167
Kevin Hao813125d2013-12-24 15:12:09 +0800168static unsigned long map_mem_in_cams_addr(phys_addr_t phys, unsigned long virt,
Scott Woodeba5de82015-10-06 22:48:10 -0500169 unsigned long ram, int max_cam_idx,
170 bool dryrun)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000171{
Kumar Gala8b27f0b2009-10-15 12:49:01 -0500172 int i;
Kumar Gala8b27f0b2009-10-15 12:49:01 -0500173 unsigned long amount_mapped = 0;
Kumar Gala8b27f0b2009-10-15 12:49:01 -0500174
175 /* Calculate CAM values */
176 for (i = 0; ram && i < max_cam_idx; i++) {
Kumar Gala8b27f0b2009-10-15 12:49:01 -0500177 unsigned long cam_sz;
178
Kumar Gala1dc91c32011-09-16 10:39:59 -0500179 cam_sz = calc_cam_sz(ram, virt, phys);
Scott Woodeba5de82015-10-06 22:48:10 -0500180 if (!dryrun)
181 settlbcam(i, virt, phys, cam_sz,
182 pgprot_val(PAGE_KERNEL_X), 0);
Kumar Gala8b27f0b2009-10-15 12:49:01 -0500183
184 ram -= cam_sz;
185 amount_mapped += cam_sz;
186 virt += cam_sz;
187 phys += cam_sz;
188 }
Scott Woodd9e18312015-10-06 22:48:09 -0500189
Scott Woodeba5de82015-10-06 22:48:10 -0500190 if (dryrun)
191 return amount_mapped;
192
Scott Woodd9e18312015-10-06 22:48:09 -0500193 loadcam_multi(0, i, max_cam_idx);
Kumar Gala8b27f0b2009-10-15 12:49:01 -0500194 tlbcam_index = i;
195
Scott Wood28efc352013-10-11 19:22:38 -0500196#ifdef CONFIG_PPC64
197 get_paca()->tcd.esel_next = i;
198 get_paca()->tcd.esel_max = mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY;
199 get_paca()->tcd.esel_first = i;
200#endif
201
Kumar Gala8b27f0b2009-10-15 12:49:01 -0500202 return amount_mapped;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000203}
204
Scott Woodeba5de82015-10-06 22:48:10 -0500205unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx, bool dryrun)
Kevin Hao813125d2013-12-24 15:12:09 +0800206{
207 unsigned long virt = PAGE_OFFSET;
208 phys_addr_t phys = memstart_addr;
209
Scott Woodeba5de82015-10-06 22:48:10 -0500210 return map_mem_in_cams_addr(phys, virt, ram, max_cam_idx, dryrun);
Kevin Hao813125d2013-12-24 15:12:09 +0800211}
212
Kumar Gala55fd7662009-10-16 18:48:40 -0500213#ifdef CONFIG_PPC32
214
215#if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS)
216#error "LOWMEM_CAM_NUM must be less than NUM_TLBCAMS"
217#endif
218
Christophe Leroy14e609d2019-02-21 19:08:38 +0000219unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000220{
Kumar Gala8b27f0b2009-10-15 12:49:01 -0500221 return tlbcam_addrs[tlbcam_index - 1].limit - PAGE_OFFSET + 1;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000222}
223
Christophe Leroy704dfe92020-08-14 05:56:27 +0000224void flush_instruction_cache(void)
225{
226 unsigned long tmp;
227
Christophe Leroy39c8bf22020-11-17 05:07:58 +0000228 tmp = mfspr(SPRN_L1CSR1);
229 tmp |= L1CSR1_ICFI | L1CSR1_ICLFR;
230 mtspr(SPRN_L1CSR1, tmp);
Christophe Leroy704dfe92020-08-14 05:56:27 +0000231 isync();
232}
233
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000234/*
235 * MMU_init_hw does the chip-specific initialization of the MMU hardware.
236 */
237void __init MMU_init_hw(void)
238{
239 flush_instruction_cache();
240}
241
Kumar Gala8b27f0b2009-10-15 12:49:01 -0500242void __init adjust_total_lowmem(void)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000243{
Kumar Gala8b27f0b2009-10-15 12:49:01 -0500244 unsigned long ram;
Trent Piephof88747e2008-12-08 19:34:57 -0800245 int i;
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000246
Trent Piephof88747e2008-12-08 19:34:57 -0800247 /* adjust lowmem size to __max_low_memory */
248 ram = min((phys_addr_t)__max_low_memory, (phys_addr_t)total_lowmem);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000249
Kevin Hao78a235e2013-12-24 15:12:07 +0800250 i = switch_to_as1();
Scott Woodeba5de82015-10-06 22:48:10 -0500251 __max_low_memory = map_mem_in_cams(ram, CONFIG_LOWMEM_CAM_NUM, false);
Kevin Hao0be7d969b2013-12-24 15:12:11 +0800252 restore_to_as0(i, 0, 0, 1);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000253
Kumar Gala8b27f0b2009-10-15 12:49:01 -0500254 pr_info("Memory CAM mapping: ");
255 for (i = 0; i < tlbcam_index - 1; i++)
256 pr_cont("%lu/", tlbcam_sz(i) >> 20);
257 pr_cont("%lu Mb, residual: %dMb\n", tlbcam_sz(tlbcam_index - 1) >> 20,
Kumar Gala96a8bac2009-02-12 09:39:23 -0600258 (unsigned int)((total_lowmem - __max_low_memory) >> 20));
Kumar Gala8b27f0b2009-10-15 12:49:01 -0500259
Benjamin Herrenschmidte63075a2010-07-06 15:39:01 -0700260 memblock_set_current_limit(memstart_addr + __max_low_memory);
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000261}
Benjamin Herrenschmidtcd3db0c2010-07-06 15:39:02 -0700262
263void setup_initial_memory_limit(phys_addr_t first_memblock_base,
264 phys_addr_t first_memblock_size)
265{
266 phys_addr_t limit = first_memblock_base + first_memblock_size;
267
268 /* 64M mapped initially according to head_fsl_booke.S */
269 memblock_set_current_limit(min_t(u64, limit, 0x04000000));
270}
Kevin Haodd189692013-12-24 15:12:06 +0800271
272#ifdef CONFIG_RELOCATABLE
Kevin Hao7d2471f2013-12-24 15:12:10 +0800273int __initdata is_second_reloc;
274notrace void __init relocate_init(u64 dt_ptr, phys_addr_t start)
Kevin Haodd189692013-12-24 15:12:06 +0800275{
Jason Yan2b0e86cc2019-09-20 17:45:40 +0800276 unsigned long base = kernstart_virt_addr;
277 phys_addr_t size;
Kevin Haodd189692013-12-24 15:12:06 +0800278
Kevin Hao7d2471f2013-12-24 15:12:10 +0800279 kernstart_addr = start;
280 if (is_second_reloc) {
281 virt_phys_offset = PAGE_OFFSET - memstart_addr;
Jason Yanb3960972019-09-20 17:45:42 +0800282 kaslr_late_init();
Kevin Hao7d2471f2013-12-24 15:12:10 +0800283 return;
284 }
285
Kevin Haodd189692013-12-24 15:12:06 +0800286 /*
287 * Relocatable kernel support based on processing of dynamic
Kevin Hao7d2471f2013-12-24 15:12:10 +0800288 * relocation entries. Before we get the real memstart_addr,
289 * We will compute the virt_phys_offset like this:
Kevin Haodd189692013-12-24 15:12:06 +0800290 * virt_phys_offset = stext.run - kernstart_addr
291 *
Kevin Hao7d2471f2013-12-24 15:12:10 +0800292 * stext.run = (KERNELBASE & ~0x3ffffff) +
293 * (kernstart_addr & 0x3ffffff)
Kevin Haodd189692013-12-24 15:12:06 +0800294 * When we relocate, we have :
295 *
296 * (kernstart_addr & 0x3ffffff) = (stext.run & 0x3ffffff)
297 *
298 * hence:
299 * virt_phys_offset = (KERNELBASE & ~0x3ffffff) -
300 * (kernstart_addr & ~0x3ffffff)
301 *
302 */
Kevin Haodd189692013-12-24 15:12:06 +0800303 start &= ~0x3ffffff;
304 base &= ~0x3ffffff;
305 virt_phys_offset = base - start;
Jason Yan2b0e86cc2019-09-20 17:45:40 +0800306 early_get_first_memblock_info(__va(dt_ptr), &size);
Kevin Hao7d2471f2013-12-24 15:12:10 +0800307 /*
308 * We now get the memstart_addr, then we should check if this
309 * address is the same as what the PAGE_OFFSET map to now. If
310 * not we have to change the map of PAGE_OFFSET to memstart_addr
311 * and do a second relocation.
312 */
313 if (start != memstart_addr) {
314 int n;
315 long offset = start - memstart_addr;
316
317 is_second_reloc = 1;
318 n = switch_to_as1();
319 /* map a 64M area for the second relocation */
320 if (memstart_addr > start)
Scott Woodeba5de82015-10-06 22:48:10 -0500321 map_mem_in_cams(0x4000000, CONFIG_LOWMEM_CAM_NUM,
322 false);
Kevin Hao7d2471f2013-12-24 15:12:10 +0800323 else
324 map_mem_in_cams_addr(start, PAGE_OFFSET + offset,
Scott Woodeba5de82015-10-06 22:48:10 -0500325 0x4000000, CONFIG_LOWMEM_CAM_NUM,
326 false);
Kevin Hao0be7d969b2013-12-24 15:12:11 +0800327 restore_to_as0(n, offset, __va(dt_ptr), 1);
Kevin Hao7d2471f2013-12-24 15:12:10 +0800328 /* We should never reach here */
329 panic("Relocation error");
330 }
Jason Yan2b0e86cc2019-09-20 17:45:40 +0800331
332 kaslr_early_init(__va(dt_ptr), size);
Kevin Haodd189692013-12-24 15:12:06 +0800333}
334#endif
Kumar Gala55fd7662009-10-16 18:48:40 -0500335#endif