Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011-2014, Intel Corporation. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | */ |
| 13 | |
| 14 | #ifndef _NVME_H |
| 15 | #define _NVME_H |
| 16 | |
| 17 | #include <linux/nvme.h> |
Christoph Hellwig | a6a5149 | 2017-10-18 16:59:25 +0200 | [diff] [blame] | 18 | #include <linux/cdev.h> |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 19 | #include <linux/pci.h> |
| 20 | #include <linux/kref.h> |
| 21 | #include <linux/blk-mq.h> |
Matias Bjørling | b0b4e09 | 2016-09-16 14:25:07 +0200 | [diff] [blame] | 22 | #include <linux/lightnvm.h> |
Scott Bauer | a98e58e5 | 2017-02-03 12:50:32 -0700 | [diff] [blame] | 23 | #include <linux/sed-opal.h> |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 24 | |
Marc Olson | 8ae4e44 | 2017-09-06 17:23:56 -0700 | [diff] [blame] | 25 | extern unsigned int nvme_io_timeout; |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 26 | #define NVME_IO_TIMEOUT (nvme_io_timeout * HZ) |
| 27 | |
Marc Olson | 8ae4e44 | 2017-09-06 17:23:56 -0700 | [diff] [blame] | 28 | extern unsigned int admin_timeout; |
Christoph Hellwig | 21d3471 | 2015-11-26 09:08:36 +0100 | [diff] [blame] | 29 | #define ADMIN_TIMEOUT (admin_timeout * HZ) |
| 30 | |
Sagi Grimberg | 038bd4c | 2016-06-13 16:45:28 +0200 | [diff] [blame] | 31 | #define NVME_DEFAULT_KATO 5 |
| 32 | #define NVME_KATO_GRACE 10 |
| 33 | |
Sagi Grimberg | 9a6327d | 2017-06-07 20:31:55 +0200 | [diff] [blame] | 34 | extern struct workqueue_struct *nvme_wq; |
| 35 | |
Matias Bjørling | ca06408 | 2015-10-29 17:57:29 +0900 | [diff] [blame] | 36 | enum { |
| 37 | NVME_NS_LBA = 0, |
| 38 | NVME_NS_LIGHTNVM = 1, |
| 39 | }; |
| 40 | |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 41 | /* |
Christoph Hellwig | 106198e | 2015-11-26 10:07:41 +0100 | [diff] [blame] | 42 | * List of workarounds for devices that required behavior not specified in |
| 43 | * the standard. |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 44 | */ |
Christoph Hellwig | 106198e | 2015-11-26 10:07:41 +0100 | [diff] [blame] | 45 | enum nvme_quirks { |
| 46 | /* |
| 47 | * Prefers I/O aligned to a stripe size specified in a vendor |
| 48 | * specific Identify field. |
| 49 | */ |
| 50 | NVME_QUIRK_STRIPE_SIZE = (1 << 0), |
Keith Busch | 540c801 | 2015-10-22 15:45:06 -0600 | [diff] [blame] | 51 | |
| 52 | /* |
| 53 | * The controller doesn't handle Identify value others than 0 or 1 |
| 54 | * correctly. |
| 55 | */ |
| 56 | NVME_QUIRK_IDENTIFY_CNS = (1 << 1), |
Keith Busch | 08095e7 | 2016-03-04 13:15:17 -0700 | [diff] [blame] | 57 | |
| 58 | /* |
Christoph Hellwig | e850fd1 | 2017-04-05 19:21:13 +0200 | [diff] [blame] | 59 | * The controller deterministically returns O's on reads to |
| 60 | * logical blocks that deallocate was called on. |
Keith Busch | 08095e7 | 2016-03-04 13:15:17 -0700 | [diff] [blame] | 61 | */ |
Christoph Hellwig | e850fd1 | 2017-04-05 19:21:13 +0200 | [diff] [blame] | 62 | NVME_QUIRK_DEALLOCATE_ZEROES = (1 << 2), |
Guilherme G. Piccoli | 54adc01 | 2016-06-14 18:22:41 -0300 | [diff] [blame] | 63 | |
| 64 | /* |
| 65 | * The controller needs a delay before starts checking the device |
| 66 | * readiness, which is done by reading the NVME_CSTS_RDY bit. |
| 67 | */ |
| 68 | NVME_QUIRK_DELAY_BEFORE_CHK_RDY = (1 << 3), |
Andy Lutomirski | c5552fd | 2017-02-07 10:08:45 -0800 | [diff] [blame] | 69 | |
| 70 | /* |
| 71 | * APST should not be used. |
| 72 | */ |
| 73 | NVME_QUIRK_NO_APST = (1 << 4), |
Andy Lutomirski | ff5350a | 2017-04-20 13:37:55 -0700 | [diff] [blame] | 74 | |
| 75 | /* |
| 76 | * The deepest sleep state should not be used. |
| 77 | */ |
| 78 | NVME_QUIRK_NO_DEEPEST_PS = (1 << 5), |
Christoph Hellwig | 608cc4b | 2017-09-06 11:45:24 +0200 | [diff] [blame] | 79 | |
| 80 | /* |
| 81 | * Supports the LighNVM command set if indicated in vs[1]. |
| 82 | */ |
| 83 | NVME_QUIRK_LIGHTNVM = (1 << 6), |
Christoph Hellwig | 106198e | 2015-11-26 10:07:41 +0100 | [diff] [blame] | 84 | }; |
| 85 | |
Christoph Hellwig | d49187e | 2016-11-10 07:32:33 -0800 | [diff] [blame] | 86 | /* |
| 87 | * Common request structure for NVMe passthrough. All drivers must have |
| 88 | * this structure as the first member of their request-private data. |
| 89 | */ |
| 90 | struct nvme_request { |
| 91 | struct nvme_command *cmd; |
| 92 | union nvme_result result; |
Christoph Hellwig | 44e44b2 | 2017-04-05 19:18:11 +0200 | [diff] [blame] | 93 | u8 retries; |
Christoph Hellwig | 27fa9bc | 2017-04-20 16:02:57 +0200 | [diff] [blame] | 94 | u8 flags; |
| 95 | u16 status; |
| 96 | }; |
| 97 | |
| 98 | enum { |
| 99 | NVME_REQ_CANCELLED = (1 << 0), |
Christoph Hellwig | d49187e | 2016-11-10 07:32:33 -0800 | [diff] [blame] | 100 | }; |
| 101 | |
| 102 | static inline struct nvme_request *nvme_req(struct request *req) |
| 103 | { |
| 104 | return blk_mq_rq_to_pdu(req); |
| 105 | } |
| 106 | |
Guilherme G. Piccoli | 54adc01 | 2016-06-14 18:22:41 -0300 | [diff] [blame] | 107 | /* The below value is the specific amount of delay needed before checking |
| 108 | * readiness in case of the PCI_DEVICE(0x1c58, 0x0003), which needs the |
| 109 | * NVME_QUIRK_DELAY_BEFORE_CHK_RDY quirk enabled. The value (in ms) was |
| 110 | * found empirically. |
| 111 | */ |
| 112 | #define NVME_QUIRK_DELAY_AMOUNT 2000 |
| 113 | |
Christoph Hellwig | bb8d261 | 2016-04-26 13:51:57 +0200 | [diff] [blame] | 114 | enum nvme_ctrl_state { |
| 115 | NVME_CTRL_NEW, |
| 116 | NVME_CTRL_LIVE, |
| 117 | NVME_CTRL_RESETTING, |
Christoph Hellwig | def61ec | 2016-07-06 21:55:49 +0900 | [diff] [blame] | 118 | NVME_CTRL_RECONNECTING, |
Christoph Hellwig | bb8d261 | 2016-04-26 13:51:57 +0200 | [diff] [blame] | 119 | NVME_CTRL_DELETING, |
Keith Busch | 0ff9d4e | 2016-05-12 08:37:14 -0600 | [diff] [blame] | 120 | NVME_CTRL_DEAD, |
Christoph Hellwig | bb8d261 | 2016-04-26 13:51:57 +0200 | [diff] [blame] | 121 | }; |
| 122 | |
Christoph Hellwig | 1c63dc6 | 2015-11-26 10:06:56 +0100 | [diff] [blame] | 123 | struct nvme_ctrl { |
Christoph Hellwig | bb8d261 | 2016-04-26 13:51:57 +0200 | [diff] [blame] | 124 | enum nvme_ctrl_state state; |
Andy Lutomirski | bd4da3a | 2017-02-22 13:32:36 -0700 | [diff] [blame] | 125 | bool identified; |
Christoph Hellwig | bb8d261 | 2016-04-26 13:51:57 +0200 | [diff] [blame] | 126 | spinlock_t lock; |
Christoph Hellwig | 1c63dc6 | 2015-11-26 10:06:56 +0100 | [diff] [blame] | 127 | const struct nvme_ctrl_ops *ops; |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 128 | struct request_queue *admin_q; |
Christoph Hellwig | 07bfcd0 | 2016-06-13 16:45:26 +0200 | [diff] [blame] | 129 | struct request_queue *connect_q; |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 130 | struct device *dev; |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 131 | int instance; |
Christoph Hellwig | 5bae7f7 | 2015-11-28 15:39:07 +0100 | [diff] [blame] | 132 | struct blk_mq_tag_set *tagset; |
Sagi Grimberg | 34b6c23 | 2017-07-10 09:22:29 +0300 | [diff] [blame] | 133 | struct blk_mq_tag_set *admin_tagset; |
Christoph Hellwig | 5bae7f7 | 2015-11-28 15:39:07 +0100 | [diff] [blame] | 134 | struct list_head namespaces; |
Christoph Hellwig | 69d3b8a | 2015-12-24 15:27:00 +0100 | [diff] [blame] | 135 | struct mutex namespaces_mutex; |
Christoph Hellwig | d22524a | 2017-10-18 13:25:42 +0200 | [diff] [blame] | 136 | struct device ctrl_device; |
Christoph Hellwig | 5bae7f7 | 2015-11-28 15:39:07 +0100 | [diff] [blame] | 137 | struct device *device; /* char device */ |
Christoph Hellwig | a6a5149 | 2017-10-18 16:59:25 +0200 | [diff] [blame] | 138 | struct cdev cdev; |
Keith Busch | 075790e | 2016-02-24 09:15:53 -0700 | [diff] [blame] | 139 | struct ida ns_ida; |
Christoph Hellwig | d86c4d8 | 2017-06-15 15:41:08 +0200 | [diff] [blame] | 140 | struct work_struct reset_work; |
Christoph Hellwig | c5017e8 | 2017-10-29 10:44:29 +0200 | [diff] [blame] | 141 | struct work_struct delete_work; |
Christoph Hellwig | 1c63dc6 | 2015-11-26 10:06:56 +0100 | [diff] [blame] | 142 | |
Christoph Hellwig | ab9e00c | 2017-11-09 13:48:55 +0100 | [diff] [blame] | 143 | struct nvme_subsystem *subsys; |
| 144 | struct list_head subsys_entry; |
| 145 | |
Christoph Hellwig | 4f1244c | 2017-02-17 13:59:39 +0100 | [diff] [blame] | 146 | struct opal_dev *opal_dev; |
Scott Bauer | a98e58e5 | 2017-02-03 12:50:32 -0700 | [diff] [blame] | 147 | |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 148 | char name[12]; |
Christoph Hellwig | 76e3914 | 2016-04-16 14:57:58 -0400 | [diff] [blame] | 149 | u16 cntlid; |
Christoph Hellwig | 5fd4ce1 | 2015-11-28 15:03:49 +0100 | [diff] [blame] | 150 | |
| 151 | u32 ctrl_config; |
Arnav Dawn | b6dccf7 | 2017-07-12 16:10:40 +0530 | [diff] [blame] | 152 | u16 mtfa; |
Sagi Grimberg | d858e5f | 2017-04-24 10:58:29 +0300 | [diff] [blame] | 153 | u32 queue_count; |
Christoph Hellwig | 5fd4ce1 | 2015-11-28 15:03:49 +0100 | [diff] [blame] | 154 | |
Sagi Grimberg | 20d0dfe | 2017-06-27 22:16:38 +0300 | [diff] [blame] | 155 | u64 cap; |
Christoph Hellwig | 5fd4ce1 | 2015-11-28 15:03:49 +0100 | [diff] [blame] | 156 | u32 page_size; |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 157 | u32 max_hw_sectors; |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 158 | u16 oncs; |
Scott Bauer | 8a9ae52 | 2017-02-17 13:59:40 +0100 | [diff] [blame] | 159 | u16 oacs; |
Jens Axboe | f5d1184 | 2017-06-27 12:03:06 -0600 | [diff] [blame] | 160 | u16 nssa; |
| 161 | u16 nr_streams; |
Christoph Hellwig | 6bf25d1 | 2015-11-20 09:36:44 +0100 | [diff] [blame] | 162 | atomic_t abort_limit; |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 163 | u8 vwc; |
Christoph Hellwig | f3ca80f | 2015-11-28 15:40:19 +0100 | [diff] [blame] | 164 | u32 vs; |
Christoph Hellwig | 07bfcd0 | 2016-06-13 16:45:26 +0200 | [diff] [blame] | 165 | u32 sgls; |
Sagi Grimberg | 038bd4c | 2016-06-13 16:45:28 +0200 | [diff] [blame] | 166 | u16 kas; |
Andy Lutomirski | c5552fd | 2017-02-07 10:08:45 -0800 | [diff] [blame] | 167 | u8 npss; |
| 168 | u8 apsta; |
Keith Busch | e3d7874 | 2017-11-07 15:13:14 -0700 | [diff] [blame] | 169 | u32 aen_result; |
Martin K. Petersen | 07fbd32 | 2017-08-25 19:14:50 -0400 | [diff] [blame] | 170 | unsigned int shutdown_timeout; |
Sagi Grimberg | 038bd4c | 2016-06-13 16:45:28 +0200 | [diff] [blame] | 171 | unsigned int kato; |
Christoph Hellwig | f3ca80f | 2015-11-28 15:40:19 +0100 | [diff] [blame] | 172 | bool subsystem; |
Christoph Hellwig | 106198e | 2015-11-26 10:07:41 +0100 | [diff] [blame] | 173 | unsigned long quirks; |
Andy Lutomirski | c5552fd | 2017-02-07 10:08:45 -0800 | [diff] [blame] | 174 | struct nvme_id_power_state psd[32]; |
Keith Busch | 84fef62 | 2017-11-07 10:28:32 -0700 | [diff] [blame] | 175 | struct nvme_effects_log *effects; |
Christoph Hellwig | 5955be2 | 2016-04-26 13:51:59 +0200 | [diff] [blame] | 176 | struct work_struct scan_work; |
Christoph Hellwig | f866fc42 | 2016-04-26 13:52:00 +0200 | [diff] [blame] | 177 | struct work_struct async_event_work; |
Sagi Grimberg | 038bd4c | 2016-06-13 16:45:28 +0200 | [diff] [blame] | 178 | struct delayed_work ka_work; |
Arnav Dawn | b6dccf7 | 2017-07-12 16:10:40 +0530 | [diff] [blame] | 179 | struct work_struct fw_act_work; |
Christoph Hellwig | 07bfcd0 | 2016-06-13 16:45:26 +0200 | [diff] [blame] | 180 | |
Andy Lutomirski | c5552fd | 2017-02-07 10:08:45 -0800 | [diff] [blame] | 181 | /* Power saving configuration */ |
| 182 | u64 ps_max_latency_us; |
Kai-Heng Feng | 76a5af8 | 2017-06-26 16:39:54 -0400 | [diff] [blame] | 183 | bool apst_enabled; |
Andy Lutomirski | c5552fd | 2017-02-07 10:08:45 -0800 | [diff] [blame] | 184 | |
Christoph Hellwig | 044a9df | 2017-09-11 12:09:28 -0400 | [diff] [blame] | 185 | /* PCIe only: */ |
Christoph Hellwig | fe6d53c | 2017-05-12 17:16:10 +0200 | [diff] [blame] | 186 | u32 hmpre; |
| 187 | u32 hmmin; |
Christoph Hellwig | 044a9df | 2017-09-11 12:09:28 -0400 | [diff] [blame] | 188 | u32 hmminds; |
| 189 | u16 hmmaxd; |
Christoph Hellwig | fe6d53c | 2017-05-12 17:16:10 +0200 | [diff] [blame] | 190 | |
Christoph Hellwig | 07bfcd0 | 2016-06-13 16:45:26 +0200 | [diff] [blame] | 191 | /* Fabrics only */ |
| 192 | u16 sqsize; |
| 193 | u32 ioccsz; |
| 194 | u32 iorcsz; |
| 195 | u16 icdoff; |
| 196 | u16 maxcmd; |
Sagi Grimberg | fdf9dfa | 2017-05-04 13:33:15 +0300 | [diff] [blame] | 197 | int nr_reconnects; |
Christoph Hellwig | 07bfcd0 | 2016-06-13 16:45:26 +0200 | [diff] [blame] | 198 | struct nvmf_ctrl_options *opts; |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 199 | }; |
| 200 | |
Christoph Hellwig | ab9e00c | 2017-11-09 13:48:55 +0100 | [diff] [blame] | 201 | struct nvme_subsystem { |
| 202 | int instance; |
| 203 | struct device dev; |
| 204 | /* |
| 205 | * Because we unregister the device on the last put we need |
| 206 | * a separate refcount. |
| 207 | */ |
| 208 | struct kref ref; |
| 209 | struct list_head entry; |
| 210 | struct mutex lock; |
| 211 | struct list_head ctrls; |
| 212 | char subnqn[NVMF_NQN_SIZE]; |
| 213 | char serial[20]; |
| 214 | char model[40]; |
| 215 | char firmware_rev[8]; |
| 216 | u8 cmic; |
| 217 | u16 vendor_id; |
| 218 | }; |
| 219 | |
Christoph Hellwig | 002fab0 | 2017-11-09 13:50:16 +0100 | [diff] [blame^] | 220 | /* |
| 221 | * Container structure for uniqueue namespace identifiers. |
| 222 | */ |
| 223 | struct nvme_ns_ids { |
| 224 | u8 eui64[8]; |
| 225 | u8 nguid[16]; |
| 226 | uuid_t uuid; |
| 227 | }; |
| 228 | |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 229 | struct nvme_ns { |
| 230 | struct list_head list; |
| 231 | |
Christoph Hellwig | 1c63dc6 | 2015-11-26 10:06:56 +0100 | [diff] [blame] | 232 | struct nvme_ctrl *ctrl; |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 233 | struct request_queue *queue; |
| 234 | struct gendisk *disk; |
Matias Bjørling | b0b4e09 | 2016-09-16 14:25:07 +0200 | [diff] [blame] | 235 | struct nvm_dev *ndev; |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 236 | struct kref kref; |
Keith Busch | 075790e | 2016-02-24 09:15:53 -0700 | [diff] [blame] | 237 | int instance; |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 238 | |
| 239 | unsigned ns_id; |
Christoph Hellwig | 002fab0 | 2017-11-09 13:50:16 +0100 | [diff] [blame^] | 240 | struct nvme_ns_ids ids; |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 241 | int lba_shift; |
| 242 | u16 ms; |
Jens Axboe | f5d1184 | 2017-06-27 12:03:06 -0600 | [diff] [blame] | 243 | u16 sgs; |
| 244 | u32 sws; |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 245 | bool ext; |
| 246 | u8 pi_type; |
Keith Busch | 646017a | 2016-02-24 09:15:54 -0700 | [diff] [blame] | 247 | unsigned long flags; |
Keith Busch | 646017a | 2016-02-24 09:15:54 -0700 | [diff] [blame] | 248 | #define NVME_NS_REMOVING 0 |
Keith Busch | 69d9a99 | 2016-02-24 09:15:56 -0700 | [diff] [blame] | 249 | #define NVME_NS_DEAD 1 |
Christoph Hellwig | 57eeaf8 | 2017-08-16 15:47:37 +0200 | [diff] [blame] | 250 | u16 noiob; |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 251 | }; |
| 252 | |
Christoph Hellwig | 1c63dc6 | 2015-11-26 10:06:56 +0100 | [diff] [blame] | 253 | struct nvme_ctrl_ops { |
Ming Lin | 1a353d8 | 2016-06-13 16:45:24 +0200 | [diff] [blame] | 254 | const char *name; |
Sagi Grimberg | e439bb1 | 2016-02-10 10:03:29 -0800 | [diff] [blame] | 255 | struct module *module; |
Christoph Hellwig | d3d5b87 | 2017-05-20 15:14:44 +0200 | [diff] [blame] | 256 | unsigned int flags; |
| 257 | #define NVME_F_FABRICS (1 << 0) |
Christoph Hellwig | c81bfba | 2017-05-20 15:14:45 +0200 | [diff] [blame] | 258 | #define NVME_F_METADATA_SUPPORTED (1 << 1) |
Christoph Hellwig | 1c63dc6 | 2015-11-26 10:06:56 +0100 | [diff] [blame] | 259 | int (*reg_read32)(struct nvme_ctrl *ctrl, u32 off, u32 *val); |
Christoph Hellwig | 5fd4ce1 | 2015-11-28 15:03:49 +0100 | [diff] [blame] | 260 | int (*reg_write32)(struct nvme_ctrl *ctrl, u32 off, u32 val); |
Christoph Hellwig | 7fd8930 | 2015-11-28 15:37:52 +0100 | [diff] [blame] | 261 | int (*reg_read64)(struct nvme_ctrl *ctrl, u32 off, u64 *val); |
Christoph Hellwig | 1673f1f | 2015-11-26 10:54:19 +0100 | [diff] [blame] | 262 | void (*free_ctrl)(struct nvme_ctrl *ctrl); |
Keith Busch | ad22c35 | 2017-11-07 15:13:12 -0700 | [diff] [blame] | 263 | void (*submit_async_event)(struct nvme_ctrl *ctrl); |
Christoph Hellwig | c5017e8 | 2017-10-29 10:44:29 +0200 | [diff] [blame] | 264 | void (*delete_ctrl)(struct nvme_ctrl *ctrl); |
Ming Lin | 1a353d8 | 2016-06-13 16:45:24 +0200 | [diff] [blame] | 265 | int (*get_address)(struct nvme_ctrl *ctrl, char *buf, int size); |
Sagi Grimberg | 31b8446 | 2017-10-11 12:53:07 +0300 | [diff] [blame] | 266 | int (*reinit_request)(void *data, struct request *rq); |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 267 | }; |
| 268 | |
Christoph Hellwig | 1c63dc6 | 2015-11-26 10:06:56 +0100 | [diff] [blame] | 269 | static inline bool nvme_ctrl_ready(struct nvme_ctrl *ctrl) |
| 270 | { |
| 271 | u32 val = 0; |
| 272 | |
| 273 | if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &val)) |
| 274 | return false; |
| 275 | return val & NVME_CSTS_RDY; |
| 276 | } |
| 277 | |
Christoph Hellwig | f3ca80f | 2015-11-28 15:40:19 +0100 | [diff] [blame] | 278 | static inline int nvme_reset_subsystem(struct nvme_ctrl *ctrl) |
| 279 | { |
| 280 | if (!ctrl->subsystem) |
| 281 | return -ENOTTY; |
| 282 | return ctrl->ops->reg_write32(ctrl, NVME_REG_NSSR, 0x4E564D65); |
| 283 | } |
| 284 | |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 285 | static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector) |
| 286 | { |
| 287 | return (sector >> (ns->lba_shift - 9)); |
| 288 | } |
| 289 | |
Ming Lin | 6904242 | 2016-04-25 14:33:20 -0700 | [diff] [blame] | 290 | static inline void nvme_cleanup_cmd(struct request *req) |
| 291 | { |
Christoph Hellwig | f9d03f9 | 2016-12-08 15:20:32 -0700 | [diff] [blame] | 292 | if (req->rq_flags & RQF_SPECIAL_PAYLOAD) { |
| 293 | kfree(page_address(req->special_vec.bv_page) + |
| 294 | req->special_vec.bv_offset); |
| 295 | } |
Ming Lin | 6904242 | 2016-04-25 14:33:20 -0700 | [diff] [blame] | 296 | } |
| 297 | |
Christoph Hellwig | 27fa9bc | 2017-04-20 16:02:57 +0200 | [diff] [blame] | 298 | static inline void nvme_end_request(struct request *req, __le16 status, |
| 299 | union nvme_result result) |
Christoph Hellwig | 15a190f7 | 2015-10-16 07:58:39 +0200 | [diff] [blame] | 300 | { |
Christoph Hellwig | 27fa9bc | 2017-04-20 16:02:57 +0200 | [diff] [blame] | 301 | struct nvme_request *rq = nvme_req(req); |
| 302 | |
| 303 | rq->status = le16_to_cpu(status) >> 1; |
| 304 | rq->result = result; |
Christoph Hellwig | 08e0029 | 2017-04-20 16:03:09 +0200 | [diff] [blame] | 305 | blk_mq_complete_request(req); |
Christoph Hellwig | 15a190f7 | 2015-10-16 07:58:39 +0200 | [diff] [blame] | 306 | } |
| 307 | |
Christoph Hellwig | d22524a | 2017-10-18 13:25:42 +0200 | [diff] [blame] | 308 | static inline void nvme_get_ctrl(struct nvme_ctrl *ctrl) |
| 309 | { |
| 310 | get_device(ctrl->device); |
| 311 | } |
| 312 | |
| 313 | static inline void nvme_put_ctrl(struct nvme_ctrl *ctrl) |
| 314 | { |
| 315 | put_device(ctrl->device); |
| 316 | } |
| 317 | |
Christoph Hellwig | 77f02a7 | 2017-03-30 13:41:32 +0200 | [diff] [blame] | 318 | void nvme_complete_rq(struct request *req); |
Ming Lin | c55a2fd | 2016-05-18 14:05:02 -0700 | [diff] [blame] | 319 | void nvme_cancel_request(struct request *req, void *data, bool reserved); |
Christoph Hellwig | bb8d261 | 2016-04-26 13:51:57 +0200 | [diff] [blame] | 320 | bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl, |
| 321 | enum nvme_ctrl_state new_state); |
Christoph Hellwig | 5fd4ce1 | 2015-11-28 15:03:49 +0100 | [diff] [blame] | 322 | int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap); |
| 323 | int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap); |
| 324 | int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl); |
Christoph Hellwig | f3ca80f | 2015-11-28 15:40:19 +0100 | [diff] [blame] | 325 | int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev, |
| 326 | const struct nvme_ctrl_ops *ops, unsigned long quirks); |
Keith Busch | 53029b0 | 2015-11-28 15:41:02 +0100 | [diff] [blame] | 327 | void nvme_uninit_ctrl(struct nvme_ctrl *ctrl); |
Sagi Grimberg | d09f2b4 | 2017-07-02 10:56:43 +0300 | [diff] [blame] | 328 | void nvme_start_ctrl(struct nvme_ctrl *ctrl); |
| 329 | void nvme_stop_ctrl(struct nvme_ctrl *ctrl); |
Christoph Hellwig | 1673f1f | 2015-11-26 10:54:19 +0100 | [diff] [blame] | 330 | void nvme_put_ctrl(struct nvme_ctrl *ctrl); |
Christoph Hellwig | 7fd8930 | 2015-11-28 15:37:52 +0100 | [diff] [blame] | 331 | int nvme_init_identify(struct nvme_ctrl *ctrl); |
Christoph Hellwig | 5bae7f7 | 2015-11-28 15:39:07 +0100 | [diff] [blame] | 332 | |
Christoph Hellwig | 5955be2 | 2016-04-26 13:51:59 +0200 | [diff] [blame] | 333 | void nvme_queue_scan(struct nvme_ctrl *ctrl); |
Christoph Hellwig | 5bae7f7 | 2015-11-28 15:39:07 +0100 | [diff] [blame] | 334 | void nvme_remove_namespaces(struct nvme_ctrl *ctrl); |
Christoph Hellwig | 1673f1f | 2015-11-26 10:54:19 +0100 | [diff] [blame] | 335 | |
Christoph Hellwig | 4f1244c | 2017-02-17 13:59:39 +0100 | [diff] [blame] | 336 | int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len, |
| 337 | bool send); |
Scott Bauer | a98e58e5 | 2017-02-03 12:50:32 -0700 | [diff] [blame] | 338 | |
Christoph Hellwig | 7bf5853 | 2016-11-10 07:32:34 -0800 | [diff] [blame] | 339 | void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status, |
| 340 | union nvme_result *res); |
Christoph Hellwig | f866fc42 | 2016-04-26 13:52:00 +0200 | [diff] [blame] | 341 | |
Keith Busch | 2564626 | 2016-01-04 09:10:57 -0700 | [diff] [blame] | 342 | void nvme_stop_queues(struct nvme_ctrl *ctrl); |
| 343 | void nvme_start_queues(struct nvme_ctrl *ctrl); |
Keith Busch | 69d9a99 | 2016-02-24 09:15:56 -0700 | [diff] [blame] | 344 | void nvme_kill_queues(struct nvme_ctrl *ctrl); |
Keith Busch | 302ad8c | 2017-03-01 14:22:12 -0500 | [diff] [blame] | 345 | void nvme_unfreeze(struct nvme_ctrl *ctrl); |
| 346 | void nvme_wait_freeze(struct nvme_ctrl *ctrl); |
| 347 | void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout); |
| 348 | void nvme_start_freeze(struct nvme_ctrl *ctrl); |
Sagi Grimberg | 31b8446 | 2017-10-11 12:53:07 +0300 | [diff] [blame] | 349 | int nvme_reinit_tagset(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set); |
Sagi Grimberg | 363c9aa | 2015-12-24 15:26:59 +0100 | [diff] [blame] | 350 | |
Christoph Hellwig | eb71f43 | 2016-06-13 16:45:23 +0200 | [diff] [blame] | 351 | #define NVME_QID_ANY -1 |
Christoph Hellwig | 4160982 | 2015-11-20 09:00:02 +0100 | [diff] [blame] | 352 | struct request *nvme_alloc_request(struct request_queue *q, |
Bart Van Assche | 9a95e4e | 2017-11-09 10:49:59 -0800 | [diff] [blame] | 353 | struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid); |
Christoph Hellwig | fc17b65 | 2017-06-03 09:38:05 +0200 | [diff] [blame] | 354 | blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req, |
Ming Lin | 8093f7c | 2016-04-12 13:10:14 -0600 | [diff] [blame] | 355 | struct nvme_command *cmd); |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 356 | int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
| 357 | void *buf, unsigned bufflen); |
| 358 | int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd, |
Christoph Hellwig | d49187e | 2016-11-10 07:32:33 -0800 | [diff] [blame] | 359 | union nvme_result *result, void *buffer, unsigned bufflen, |
Bart Van Assche | 9a95e4e | 2017-11-09 10:49:59 -0800 | [diff] [blame] | 360 | unsigned timeout, int qid, int at_head, |
| 361 | blk_mq_req_flags_t flags); |
Christoph Hellwig | 9a0be7a | 2015-11-26 11:09:06 +0100 | [diff] [blame] | 362 | int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count); |
Sagi Grimberg | 038bd4c | 2016-06-13 16:45:28 +0200 | [diff] [blame] | 363 | void nvme_start_keep_alive(struct nvme_ctrl *ctrl); |
| 364 | void nvme_stop_keep_alive(struct nvme_ctrl *ctrl); |
Christoph Hellwig | d86c4d8 | 2017-06-15 15:41:08 +0200 | [diff] [blame] | 365 | int nvme_reset_ctrl(struct nvme_ctrl *ctrl); |
Christoph Hellwig | c5017e8 | 2017-10-29 10:44:29 +0200 | [diff] [blame] | 366 | int nvme_delete_ctrl(struct nvme_ctrl *ctrl); |
| 367 | int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl); |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 368 | |
Keith Busch | c4699e7 | 2015-11-28 16:49:22 +0100 | [diff] [blame] | 369 | #ifdef CONFIG_NVM |
Matias Bjørling | 3dc87dd | 2016-11-28 22:38:53 +0100 | [diff] [blame] | 370 | int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, int node); |
Matias Bjørling | b0b4e09 | 2016-09-16 14:25:07 +0200 | [diff] [blame] | 371 | void nvme_nvm_unregister(struct nvme_ns *ns); |
Matias Bjørling | 3dc87dd | 2016-11-28 22:38:53 +0100 | [diff] [blame] | 372 | int nvme_nvm_register_sysfs(struct nvme_ns *ns); |
| 373 | void nvme_nvm_unregister_sysfs(struct nvme_ns *ns); |
Matias Bjørling | 84d4add | 2017-01-31 13:17:16 +0100 | [diff] [blame] | 374 | int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, unsigned long arg); |
Keith Busch | c4699e7 | 2015-11-28 16:49:22 +0100 | [diff] [blame] | 375 | #else |
Matias Bjørling | b0b4e09 | 2016-09-16 14:25:07 +0200 | [diff] [blame] | 376 | static inline int nvme_nvm_register(struct nvme_ns *ns, char *disk_name, |
Matias Bjørling | 3dc87dd | 2016-11-28 22:38:53 +0100 | [diff] [blame] | 377 | int node) |
Keith Busch | c4699e7 | 2015-11-28 16:49:22 +0100 | [diff] [blame] | 378 | { |
| 379 | return 0; |
| 380 | } |
| 381 | |
Matias Bjørling | b0b4e09 | 2016-09-16 14:25:07 +0200 | [diff] [blame] | 382 | static inline void nvme_nvm_unregister(struct nvme_ns *ns) {}; |
Matias Bjørling | 3dc87dd | 2016-11-28 22:38:53 +0100 | [diff] [blame] | 383 | static inline int nvme_nvm_register_sysfs(struct nvme_ns *ns) |
| 384 | { |
| 385 | return 0; |
| 386 | } |
| 387 | static inline void nvme_nvm_unregister_sysfs(struct nvme_ns *ns) {}; |
Matias Bjørling | 84d4add | 2017-01-31 13:17:16 +0100 | [diff] [blame] | 388 | static inline int nvme_nvm_ioctl(struct nvme_ns *ns, unsigned int cmd, |
| 389 | unsigned long arg) |
| 390 | { |
| 391 | return -ENOTTY; |
| 392 | } |
Matias Bjørling | 3dc87dd | 2016-11-28 22:38:53 +0100 | [diff] [blame] | 393 | #endif /* CONFIG_NVM */ |
| 394 | |
Simon A. F. Lund | 40267ef | 2016-09-16 14:25:08 +0200 | [diff] [blame] | 395 | static inline struct nvme_ns *nvme_get_ns_from_dev(struct device *dev) |
| 396 | { |
| 397 | return dev_to_disk(dev)->private_data; |
| 398 | } |
Matias Bjørling | ca06408 | 2015-10-29 17:57:29 +0900 | [diff] [blame] | 399 | |
Christoph Hellwig | 5bae7f7 | 2015-11-28 15:39:07 +0100 | [diff] [blame] | 400 | int __init nvme_core_init(void); |
| 401 | void nvme_core_exit(void); |
| 402 | |
Christoph Hellwig | f11bb3e | 2015-10-03 15:46:41 +0200 | [diff] [blame] | 403 | #endif /* _NVME_H */ |