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Jon Loeligeref82a302006-06-17 17:52:55 -05001/*
2 * Driver for Vitesse PHYs
3 *
4 * Author: Kriston Carson
5 *
Andy Flemingfddf86f2011-10-13 04:33:55 +00006 * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc.
Jon Loeligeref82a302006-06-17 17:52:55 -05007 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
Jon Loeligeref82a302006-06-17 17:52:55 -050015#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/mii.h>
18#include <linux/ethtool.h>
19#include <linux/phy.h>
20
21/* Vitesse Extended Control Register 1 */
22#define MII_VSC8244_EXT_CON1 0x17
23#define MII_VSC8244_EXTCON1_INIT 0x0000
Andy Flemingaf2d9402007-07-11 11:42:35 -050024#define MII_VSC8244_EXTCON1_TX_SKEW_MASK 0x0c00
25#define MII_VSC8244_EXTCON1_RX_SKEW_MASK 0x0300
26#define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
27#define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
Jon Loeligeref82a302006-06-17 17:52:55 -050028
29/* Vitesse Interrupt Mask Register */
30#define MII_VSC8244_IMASK 0x19
31#define MII_VSC8244_IMASK_IEN 0x8000
32#define MII_VSC8244_IMASK_SPEED 0x4000
33#define MII_VSC8244_IMASK_LINK 0x2000
34#define MII_VSC8244_IMASK_DUPLEX 0x1000
35#define MII_VSC8244_IMASK_MASK 0xf000
36
Trent Piepho11c6dd22008-11-25 01:00:47 -080037#define MII_VSC8221_IMASK_MASK 0xa000
38
Jon Loeligeref82a302006-06-17 17:52:55 -050039/* Vitesse Interrupt Status Register */
40#define MII_VSC8244_ISTAT 0x1a
41#define MII_VSC8244_ISTAT_STATUS 0x8000
42#define MII_VSC8244_ISTAT_SPEED 0x4000
43#define MII_VSC8244_ISTAT_LINK 0x2000
44#define MII_VSC8244_ISTAT_DUPLEX 0x1000
45
46/* Vitesse Auxiliary Control/Status Register */
Michal Simek2a8626d2013-05-30 20:08:23 +000047#define MII_VSC8244_AUX_CONSTAT 0x1c
48#define MII_VSC8244_AUXCONSTAT_INIT 0x0000
49#define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
50#define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
51#define MII_VSC8244_AUXCONSTAT_GBIT 0x0010
52#define MII_VSC8244_AUXCONSTAT_100 0x0008
Jon Loeligeref82a302006-06-17 17:52:55 -050053
Trent Piepho11c6dd22008-11-25 01:00:47 -080054#define MII_VSC8221_AUXCONSTAT_INIT 0x0004 /* need to set this bit? */
55#define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
56
Andy Fleming05080192013-11-20 16:38:16 -060057#define PHY_ID_VSC8234 0x000fc620
Trent Piepho11c6dd22008-11-25 01:00:47 -080058#define PHY_ID_VSC8244 0x000fc6c0
shaohui xiec2efef72013-11-20 16:38:17 -060059#define PHY_ID_VSC8574 0x000704a0
Trent Piepho11c6dd22008-11-25 01:00:47 -080060#define PHY_ID_VSC8221 0x000fc550
Michal Simek5a1cebd2013-05-30 20:08:24 +000061#define PHY_ID_VSC8211 0x000fc4b0
Trent Piepho11c6dd22008-11-25 01:00:47 -080062
Jon Loeligeref82a302006-06-17 17:52:55 -050063MODULE_DESCRIPTION("Vitesse PHY driver");
64MODULE_AUTHOR("Kriston Carson");
65MODULE_LICENSE("GPL");
66
stephen hemmingerbaec1262013-03-08 09:07:42 +000067static int vsc824x_add_skew(struct phy_device *phydev)
Andy Flemingfddf86f2011-10-13 04:33:55 +000068{
69 int err;
70 int extcon;
71
72 extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
73
74 if (extcon < 0)
75 return extcon;
76
77 extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK |
78 MII_VSC8244_EXTCON1_RX_SKEW_MASK);
79
80 extcon |= (MII_VSC8244_EXTCON1_TX_SKEW |
81 MII_VSC8244_EXTCON1_RX_SKEW);
82
83 err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
84
85 return err;
86}
Andy Flemingfddf86f2011-10-13 04:33:55 +000087
Jon Loeligeref82a302006-06-17 17:52:55 -050088static int vsc824x_config_init(struct phy_device *phydev)
89{
90 int err;
91
92 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
93 MII_VSC8244_AUXCONSTAT_INIT);
94 if (err < 0)
95 return err;
96
Andy Flemingaf2d9402007-07-11 11:42:35 -050097 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
Andy Flemingfddf86f2011-10-13 04:33:55 +000098 err = vsc824x_add_skew(phydev);
Andy Flemingaf2d9402007-07-11 11:42:35 -050099
Jon Loeligeref82a302006-06-17 17:52:55 -0500100 return err;
101}
102
103static int vsc824x_ack_interrupt(struct phy_device *phydev)
104{
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500105 int err = 0;
Michal Simek2a8626d2013-05-30 20:08:23 +0000106
107 /* Don't bother to ACK the interrupts if interrupts
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500108 * are disabled. The 824x cannot clear the interrupts
109 * if they are disabled.
110 */
111 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
112 err = phy_read(phydev, MII_VSC8244_ISTAT);
Jon Loeligeref82a302006-06-17 17:52:55 -0500113
114 return (err < 0) ? err : 0;
115}
116
Trent Piepho11c6dd22008-11-25 01:00:47 -0800117static int vsc82xx_config_intr(struct phy_device *phydev)
Jon Loeligeref82a302006-06-17 17:52:55 -0500118{
119 int err;
120
121 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
122 err = phy_write(phydev, MII_VSC8244_IMASK,
Andy Fleming05080192013-11-20 16:38:16 -0600123 (phydev->drv->phy_id == PHY_ID_VSC8234 ||
shaohui xiec2efef72013-11-20 16:38:17 -0600124 phydev->drv->phy_id == PHY_ID_VSC8244 ||
125 phydev->drv->phy_id == PHY_ID_VSC8574) ?
Trent Piepho11c6dd22008-11-25 01:00:47 -0800126 MII_VSC8244_IMASK_MASK :
127 MII_VSC8221_IMASK_MASK);
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500128 else {
Michal Simek2a8626d2013-05-30 20:08:23 +0000129 /* The Vitesse PHY cannot clear the interrupt
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500130 * once it has disabled them, so we clear them first
131 */
132 err = phy_read(phydev, MII_VSC8244_ISTAT);
133
Andy Fleming52cb1c22007-07-18 01:06:28 -0500134 if (err < 0)
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500135 return err;
136
Jon Loeligeref82a302006-06-17 17:52:55 -0500137 err = phy_write(phydev, MII_VSC8244_IMASK, 0);
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500138 }
139
Jon Loeligeref82a302006-06-17 17:52:55 -0500140 return err;
141}
142
Trent Piepho11c6dd22008-11-25 01:00:47 -0800143static int vsc8221_config_init(struct phy_device *phydev)
Jon Loeligeref82a302006-06-17 17:52:55 -0500144{
Trent Piepho11c6dd22008-11-25 01:00:47 -0800145 int err;
146
147 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
148 MII_VSC8221_AUXCONSTAT_INIT);
149 return err;
150
151 /* Perhaps we should set EXT_CON1 based on the interface?
Michal Simek2a8626d2013-05-30 20:08:23 +0000152 * Options are 802.3Z SerDes or SGMII
153 */
Jon Loeligeref82a302006-06-17 17:52:55 -0500154}
155
Andy Fleming05080192013-11-20 16:38:16 -0600156/* Vitesse 82xx */
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000157static struct phy_driver vsc82xx_driver[] = {
158{
Andy Fleming05080192013-11-20 16:38:16 -0600159 .phy_id = PHY_ID_VSC8234,
160 .name = "Vitesse VSC8234",
161 .phy_id_mask = 0x000ffff0,
162 .features = PHY_GBIT_FEATURES,
163 .flags = PHY_HAS_INTERRUPT,
164 .config_init = &vsc824x_config_init,
165 .config_aneg = &genphy_config_aneg,
166 .read_status = &genphy_read_status,
167 .ack_interrupt = &vsc824x_ack_interrupt,
168 .config_intr = &vsc82xx_config_intr,
169 .driver = { .owner = THIS_MODULE,},
170}, {
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000171 .phy_id = PHY_ID_VSC8244,
172 .name = "Vitesse VSC8244",
173 .phy_id_mask = 0x000fffc0,
174 .features = PHY_GBIT_FEATURES,
175 .flags = PHY_HAS_INTERRUPT,
176 .config_init = &vsc824x_config_init,
177 .config_aneg = &genphy_config_aneg,
178 .read_status = &genphy_read_status,
179 .ack_interrupt = &vsc824x_ack_interrupt,
180 .config_intr = &vsc82xx_config_intr,
181 .driver = { .owner = THIS_MODULE,},
182}, {
shaohui xiec2efef72013-11-20 16:38:17 -0600183 .phy_id = PHY_ID_VSC8574,
184 .name = "Vitesse VSC8574",
185 .phy_id_mask = 0x000ffff0,
186 .features = PHY_GBIT_FEATURES,
187 .flags = PHY_HAS_INTERRUPT,
188 .config_init = &vsc824x_config_init,
189 .config_aneg = &genphy_config_aneg,
190 .read_status = &genphy_read_status,
191 .ack_interrupt = &vsc824x_ack_interrupt,
192 .config_intr = &vsc82xx_config_intr,
193 .driver = { .owner = THIS_MODULE,},
194}, {
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000195 /* Vitesse 8221 */
Trent Piepho11c6dd22008-11-25 01:00:47 -0800196 .phy_id = PHY_ID_VSC8221,
197 .phy_id_mask = 0x000ffff0,
198 .name = "Vitesse VSC8221",
199 .features = PHY_GBIT_FEATURES,
200 .flags = PHY_HAS_INTERRUPT,
201 .config_init = &vsc8221_config_init,
202 .config_aneg = &genphy_config_aneg,
203 .read_status = &genphy_read_status,
204 .ack_interrupt = &vsc824x_ack_interrupt,
205 .config_intr = &vsc82xx_config_intr,
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000206 .driver = { .owner = THIS_MODULE,},
Michal Simek5a1cebd2013-05-30 20:08:24 +0000207}, {
208 /* Vitesse 8211 */
209 .phy_id = PHY_ID_VSC8211,
210 .phy_id_mask = 0x000ffff0,
211 .name = "Vitesse VSC8211",
212 .features = PHY_GBIT_FEATURES,
213 .flags = PHY_HAS_INTERRUPT,
214 .config_init = &vsc8221_config_init,
215 .config_aneg = &genphy_config_aneg,
216 .read_status = &genphy_read_status,
217 .ack_interrupt = &vsc824x_ack_interrupt,
218 .config_intr = &vsc82xx_config_intr,
219 .driver = { .owner = THIS_MODULE,},
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000220} };
Trent Piepho11c6dd22008-11-25 01:00:47 -0800221
222static int __init vsc82xx_init(void)
223{
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000224 return phy_drivers_register(vsc82xx_driver,
225 ARRAY_SIZE(vsc82xx_driver));
Trent Piepho11c6dd22008-11-25 01:00:47 -0800226}
227
228static void __exit vsc82xx_exit(void)
Jon Loeligeref82a302006-06-17 17:52:55 -0500229{
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000230 return phy_drivers_unregister(vsc82xx_driver,
231 ARRAY_SIZE(vsc82xx_driver));
Jon Loeligeref82a302006-06-17 17:52:55 -0500232}
233
Trent Piepho11c6dd22008-11-25 01:00:47 -0800234module_init(vsc82xx_init);
235module_exit(vsc82xx_exit);
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000236
Uwe Kleine-Königcf93c942010-10-03 23:43:32 +0000237static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
Andy Fleming05080192013-11-20 16:38:16 -0600238 { PHY_ID_VSC8234, 0x000ffff0 },
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000239 { PHY_ID_VSC8244, 0x000fffc0 },
shaohui xiec2efef72013-11-20 16:38:17 -0600240 { PHY_ID_VSC8574, 0x000ffff0 },
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000241 { PHY_ID_VSC8221, 0x000ffff0 },
Michal Simek5a1cebd2013-05-30 20:08:24 +0000242 { PHY_ID_VSC8211, 0x000ffff0 },
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000243 { }
244};
245
246MODULE_DEVICE_TABLE(mdio, vitesse_tbl);