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Jon Loeligeref82a302006-06-17 17:52:55 -05001/*
2 * Driver for Vitesse PHYs
3 *
4 * Author: Kriston Carson
5 *
Andy Flemingfddf86f2011-10-13 04:33:55 +00006 * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc.
Jon Loeligeref82a302006-06-17 17:52:55 -05007 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
Jon Loeligeref82a302006-06-17 17:52:55 -050015#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/mii.h>
18#include <linux/ethtool.h>
19#include <linux/phy.h>
20
21/* Vitesse Extended Control Register 1 */
22#define MII_VSC8244_EXT_CON1 0x17
23#define MII_VSC8244_EXTCON1_INIT 0x0000
Andy Flemingaf2d9402007-07-11 11:42:35 -050024#define MII_VSC8244_EXTCON1_TX_SKEW_MASK 0x0c00
25#define MII_VSC8244_EXTCON1_RX_SKEW_MASK 0x0300
26#define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
27#define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
Jon Loeligeref82a302006-06-17 17:52:55 -050028
29/* Vitesse Interrupt Mask Register */
30#define MII_VSC8244_IMASK 0x19
31#define MII_VSC8244_IMASK_IEN 0x8000
32#define MII_VSC8244_IMASK_SPEED 0x4000
33#define MII_VSC8244_IMASK_LINK 0x2000
34#define MII_VSC8244_IMASK_DUPLEX 0x1000
35#define MII_VSC8244_IMASK_MASK 0xf000
36
Trent Piepho11c6dd22008-11-25 01:00:47 -080037#define MII_VSC8221_IMASK_MASK 0xa000
38
Jon Loeligeref82a302006-06-17 17:52:55 -050039/* Vitesse Interrupt Status Register */
40#define MII_VSC8244_ISTAT 0x1a
41#define MII_VSC8244_ISTAT_STATUS 0x8000
42#define MII_VSC8244_ISTAT_SPEED 0x4000
43#define MII_VSC8244_ISTAT_LINK 0x2000
44#define MII_VSC8244_ISTAT_DUPLEX 0x1000
45
46/* Vitesse Auxiliary Control/Status Register */
Michal Simek2a8626d2013-05-30 20:08:23 +000047#define MII_VSC8244_AUX_CONSTAT 0x1c
48#define MII_VSC8244_AUXCONSTAT_INIT 0x0000
49#define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
50#define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
51#define MII_VSC8244_AUXCONSTAT_GBIT 0x0010
52#define MII_VSC8244_AUXCONSTAT_100 0x0008
Jon Loeligeref82a302006-06-17 17:52:55 -050053
Trent Piepho11c6dd22008-11-25 01:00:47 -080054#define MII_VSC8221_AUXCONSTAT_INIT 0x0004 /* need to set this bit? */
55#define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
56
Andy Fleming05080192013-11-20 16:38:16 -060057#define PHY_ID_VSC8234 0x000fc620
Trent Piepho11c6dd22008-11-25 01:00:47 -080058#define PHY_ID_VSC8244 0x000fc6c0
59#define PHY_ID_VSC8221 0x000fc550
Michal Simek5a1cebd2013-05-30 20:08:24 +000060#define PHY_ID_VSC8211 0x000fc4b0
Trent Piepho11c6dd22008-11-25 01:00:47 -080061
Jon Loeligeref82a302006-06-17 17:52:55 -050062MODULE_DESCRIPTION("Vitesse PHY driver");
63MODULE_AUTHOR("Kriston Carson");
64MODULE_LICENSE("GPL");
65
stephen hemmingerbaec1262013-03-08 09:07:42 +000066static int vsc824x_add_skew(struct phy_device *phydev)
Andy Flemingfddf86f2011-10-13 04:33:55 +000067{
68 int err;
69 int extcon;
70
71 extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
72
73 if (extcon < 0)
74 return extcon;
75
76 extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK |
77 MII_VSC8244_EXTCON1_RX_SKEW_MASK);
78
79 extcon |= (MII_VSC8244_EXTCON1_TX_SKEW |
80 MII_VSC8244_EXTCON1_RX_SKEW);
81
82 err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
83
84 return err;
85}
Andy Flemingfddf86f2011-10-13 04:33:55 +000086
Jon Loeligeref82a302006-06-17 17:52:55 -050087static int vsc824x_config_init(struct phy_device *phydev)
88{
89 int err;
90
91 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
92 MII_VSC8244_AUXCONSTAT_INIT);
93 if (err < 0)
94 return err;
95
Andy Flemingaf2d9402007-07-11 11:42:35 -050096 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
Andy Flemingfddf86f2011-10-13 04:33:55 +000097 err = vsc824x_add_skew(phydev);
Andy Flemingaf2d9402007-07-11 11:42:35 -050098
Jon Loeligeref82a302006-06-17 17:52:55 -050099 return err;
100}
101
102static int vsc824x_ack_interrupt(struct phy_device *phydev)
103{
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500104 int err = 0;
Michal Simek2a8626d2013-05-30 20:08:23 +0000105
106 /* Don't bother to ACK the interrupts if interrupts
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500107 * are disabled. The 824x cannot clear the interrupts
108 * if they are disabled.
109 */
110 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
111 err = phy_read(phydev, MII_VSC8244_ISTAT);
Jon Loeligeref82a302006-06-17 17:52:55 -0500112
113 return (err < 0) ? err : 0;
114}
115
Trent Piepho11c6dd22008-11-25 01:00:47 -0800116static int vsc82xx_config_intr(struct phy_device *phydev)
Jon Loeligeref82a302006-06-17 17:52:55 -0500117{
118 int err;
119
120 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
121 err = phy_write(phydev, MII_VSC8244_IMASK,
Andy Fleming05080192013-11-20 16:38:16 -0600122 (phydev->drv->phy_id == PHY_ID_VSC8234 ||
123 phydev->drv->phy_id == PHY_ID_VSC8244) ?
Trent Piepho11c6dd22008-11-25 01:00:47 -0800124 MII_VSC8244_IMASK_MASK :
125 MII_VSC8221_IMASK_MASK);
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500126 else {
Michal Simek2a8626d2013-05-30 20:08:23 +0000127 /* The Vitesse PHY cannot clear the interrupt
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500128 * once it has disabled them, so we clear them first
129 */
130 err = phy_read(phydev, MII_VSC8244_ISTAT);
131
Andy Fleming52cb1c22007-07-18 01:06:28 -0500132 if (err < 0)
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500133 return err;
134
Jon Loeligeref82a302006-06-17 17:52:55 -0500135 err = phy_write(phydev, MII_VSC8244_IMASK, 0);
Andy Fleming1d5e83a2007-07-10 16:42:04 -0500136 }
137
Jon Loeligeref82a302006-06-17 17:52:55 -0500138 return err;
139}
140
Trent Piepho11c6dd22008-11-25 01:00:47 -0800141static int vsc8221_config_init(struct phy_device *phydev)
Jon Loeligeref82a302006-06-17 17:52:55 -0500142{
Trent Piepho11c6dd22008-11-25 01:00:47 -0800143 int err;
144
145 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
146 MII_VSC8221_AUXCONSTAT_INIT);
147 return err;
148
149 /* Perhaps we should set EXT_CON1 based on the interface?
Michal Simek2a8626d2013-05-30 20:08:23 +0000150 * Options are 802.3Z SerDes or SGMII
151 */
Jon Loeligeref82a302006-06-17 17:52:55 -0500152}
153
Andy Fleming05080192013-11-20 16:38:16 -0600154/* Vitesse 82xx */
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000155static struct phy_driver vsc82xx_driver[] = {
156{
Andy Fleming05080192013-11-20 16:38:16 -0600157 .phy_id = PHY_ID_VSC8234,
158 .name = "Vitesse VSC8234",
159 .phy_id_mask = 0x000ffff0,
160 .features = PHY_GBIT_FEATURES,
161 .flags = PHY_HAS_INTERRUPT,
162 .config_init = &vsc824x_config_init,
163 .config_aneg = &genphy_config_aneg,
164 .read_status = &genphy_read_status,
165 .ack_interrupt = &vsc824x_ack_interrupt,
166 .config_intr = &vsc82xx_config_intr,
167 .driver = { .owner = THIS_MODULE,},
168}, {
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000169 .phy_id = PHY_ID_VSC8244,
170 .name = "Vitesse VSC8244",
171 .phy_id_mask = 0x000fffc0,
172 .features = PHY_GBIT_FEATURES,
173 .flags = PHY_HAS_INTERRUPT,
174 .config_init = &vsc824x_config_init,
175 .config_aneg = &genphy_config_aneg,
176 .read_status = &genphy_read_status,
177 .ack_interrupt = &vsc824x_ack_interrupt,
178 .config_intr = &vsc82xx_config_intr,
179 .driver = { .owner = THIS_MODULE,},
180}, {
181 /* Vitesse 8221 */
Trent Piepho11c6dd22008-11-25 01:00:47 -0800182 .phy_id = PHY_ID_VSC8221,
183 .phy_id_mask = 0x000ffff0,
184 .name = "Vitesse VSC8221",
185 .features = PHY_GBIT_FEATURES,
186 .flags = PHY_HAS_INTERRUPT,
187 .config_init = &vsc8221_config_init,
188 .config_aneg = &genphy_config_aneg,
189 .read_status = &genphy_read_status,
190 .ack_interrupt = &vsc824x_ack_interrupt,
191 .config_intr = &vsc82xx_config_intr,
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000192 .driver = { .owner = THIS_MODULE,},
Michal Simek5a1cebd2013-05-30 20:08:24 +0000193}, {
194 /* Vitesse 8211 */
195 .phy_id = PHY_ID_VSC8211,
196 .phy_id_mask = 0x000ffff0,
197 .name = "Vitesse VSC8211",
198 .features = PHY_GBIT_FEATURES,
199 .flags = PHY_HAS_INTERRUPT,
200 .config_init = &vsc8221_config_init,
201 .config_aneg = &genphy_config_aneg,
202 .read_status = &genphy_read_status,
203 .ack_interrupt = &vsc824x_ack_interrupt,
204 .config_intr = &vsc82xx_config_intr,
205 .driver = { .owner = THIS_MODULE,},
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000206} };
Trent Piepho11c6dd22008-11-25 01:00:47 -0800207
208static int __init vsc82xx_init(void)
209{
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000210 return phy_drivers_register(vsc82xx_driver,
211 ARRAY_SIZE(vsc82xx_driver));
Trent Piepho11c6dd22008-11-25 01:00:47 -0800212}
213
214static void __exit vsc82xx_exit(void)
Jon Loeligeref82a302006-06-17 17:52:55 -0500215{
Christian Hohnstaedtd5bf9072012-07-04 05:44:34 +0000216 return phy_drivers_unregister(vsc82xx_driver,
217 ARRAY_SIZE(vsc82xx_driver));
Jon Loeligeref82a302006-06-17 17:52:55 -0500218}
219
Trent Piepho11c6dd22008-11-25 01:00:47 -0800220module_init(vsc82xx_init);
221module_exit(vsc82xx_exit);
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000222
Uwe Kleine-Königcf93c942010-10-03 23:43:32 +0000223static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
Andy Fleming05080192013-11-20 16:38:16 -0600224 { PHY_ID_VSC8234, 0x000ffff0 },
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000225 { PHY_ID_VSC8244, 0x000fffc0 },
226 { PHY_ID_VSC8221, 0x000ffff0 },
Michal Simek5a1cebd2013-05-30 20:08:24 +0000227 { PHY_ID_VSC8211, 0x000ffff0 },
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000228 { }
229};
230
231MODULE_DEVICE_TABLE(mdio, vitesse_tbl);