Jon Loeliger | ef82a30 | 2006-06-17 17:52:55 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Driver for Vitesse PHYs |
| 3 | * |
| 4 | * Author: Kriston Carson |
| 5 | * |
Andy Fleming | fddf86f | 2011-10-13 04:33:55 +0000 | [diff] [blame] | 6 | * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc. |
Jon Loeliger | ef82a30 | 2006-06-17 17:52:55 -0500 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your |
| 11 | * option) any later version. |
| 12 | * |
| 13 | */ |
| 14 | |
Jon Loeliger | ef82a30 | 2006-06-17 17:52:55 -0500 | [diff] [blame] | 15 | #include <linux/kernel.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/mii.h> |
| 18 | #include <linux/ethtool.h> |
| 19 | #include <linux/phy.h> |
| 20 | |
| 21 | /* Vitesse Extended Control Register 1 */ |
| 22 | #define MII_VSC8244_EXT_CON1 0x17 |
| 23 | #define MII_VSC8244_EXTCON1_INIT 0x0000 |
Andy Fleming | af2d940 | 2007-07-11 11:42:35 -0500 | [diff] [blame] | 24 | #define MII_VSC8244_EXTCON1_TX_SKEW_MASK 0x0c00 |
| 25 | #define MII_VSC8244_EXTCON1_RX_SKEW_MASK 0x0300 |
| 26 | #define MII_VSC8244_EXTCON1_TX_SKEW 0x0800 |
| 27 | #define MII_VSC8244_EXTCON1_RX_SKEW 0x0200 |
Jon Loeliger | ef82a30 | 2006-06-17 17:52:55 -0500 | [diff] [blame] | 28 | |
| 29 | /* Vitesse Interrupt Mask Register */ |
| 30 | #define MII_VSC8244_IMASK 0x19 |
| 31 | #define MII_VSC8244_IMASK_IEN 0x8000 |
| 32 | #define MII_VSC8244_IMASK_SPEED 0x4000 |
| 33 | #define MII_VSC8244_IMASK_LINK 0x2000 |
| 34 | #define MII_VSC8244_IMASK_DUPLEX 0x1000 |
| 35 | #define MII_VSC8244_IMASK_MASK 0xf000 |
| 36 | |
Trent Piepho | 11c6dd2 | 2008-11-25 01:00:47 -0800 | [diff] [blame] | 37 | #define MII_VSC8221_IMASK_MASK 0xa000 |
| 38 | |
Jon Loeliger | ef82a30 | 2006-06-17 17:52:55 -0500 | [diff] [blame] | 39 | /* Vitesse Interrupt Status Register */ |
| 40 | #define MII_VSC8244_ISTAT 0x1a |
| 41 | #define MII_VSC8244_ISTAT_STATUS 0x8000 |
| 42 | #define MII_VSC8244_ISTAT_SPEED 0x4000 |
| 43 | #define MII_VSC8244_ISTAT_LINK 0x2000 |
| 44 | #define MII_VSC8244_ISTAT_DUPLEX 0x1000 |
| 45 | |
| 46 | /* Vitesse Auxiliary Control/Status Register */ |
Michal Simek | 2a8626d | 2013-05-30 20:08:23 +0000 | [diff] [blame] | 47 | #define MII_VSC8244_AUX_CONSTAT 0x1c |
| 48 | #define MII_VSC8244_AUXCONSTAT_INIT 0x0000 |
| 49 | #define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020 |
| 50 | #define MII_VSC8244_AUXCONSTAT_SPEED 0x0018 |
| 51 | #define MII_VSC8244_AUXCONSTAT_GBIT 0x0010 |
| 52 | #define MII_VSC8244_AUXCONSTAT_100 0x0008 |
Jon Loeliger | ef82a30 | 2006-06-17 17:52:55 -0500 | [diff] [blame] | 53 | |
Trent Piepho | 11c6dd2 | 2008-11-25 01:00:47 -0800 | [diff] [blame] | 54 | #define MII_VSC8221_AUXCONSTAT_INIT 0x0004 /* need to set this bit? */ |
| 55 | #define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004 |
| 56 | |
Andy Fleming | 0508019 | 2013-11-20 16:38:16 -0600 | [diff] [blame^] | 57 | #define PHY_ID_VSC8234 0x000fc620 |
Trent Piepho | 11c6dd2 | 2008-11-25 01:00:47 -0800 | [diff] [blame] | 58 | #define PHY_ID_VSC8244 0x000fc6c0 |
| 59 | #define PHY_ID_VSC8221 0x000fc550 |
Michal Simek | 5a1cebd | 2013-05-30 20:08:24 +0000 | [diff] [blame] | 60 | #define PHY_ID_VSC8211 0x000fc4b0 |
Trent Piepho | 11c6dd2 | 2008-11-25 01:00:47 -0800 | [diff] [blame] | 61 | |
Jon Loeliger | ef82a30 | 2006-06-17 17:52:55 -0500 | [diff] [blame] | 62 | MODULE_DESCRIPTION("Vitesse PHY driver"); |
| 63 | MODULE_AUTHOR("Kriston Carson"); |
| 64 | MODULE_LICENSE("GPL"); |
| 65 | |
stephen hemminger | baec126 | 2013-03-08 09:07:42 +0000 | [diff] [blame] | 66 | static int vsc824x_add_skew(struct phy_device *phydev) |
Andy Fleming | fddf86f | 2011-10-13 04:33:55 +0000 | [diff] [blame] | 67 | { |
| 68 | int err; |
| 69 | int extcon; |
| 70 | |
| 71 | extcon = phy_read(phydev, MII_VSC8244_EXT_CON1); |
| 72 | |
| 73 | if (extcon < 0) |
| 74 | return extcon; |
| 75 | |
| 76 | extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK | |
| 77 | MII_VSC8244_EXTCON1_RX_SKEW_MASK); |
| 78 | |
| 79 | extcon |= (MII_VSC8244_EXTCON1_TX_SKEW | |
| 80 | MII_VSC8244_EXTCON1_RX_SKEW); |
| 81 | |
| 82 | err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon); |
| 83 | |
| 84 | return err; |
| 85 | } |
Andy Fleming | fddf86f | 2011-10-13 04:33:55 +0000 | [diff] [blame] | 86 | |
Jon Loeliger | ef82a30 | 2006-06-17 17:52:55 -0500 | [diff] [blame] | 87 | static int vsc824x_config_init(struct phy_device *phydev) |
| 88 | { |
| 89 | int err; |
| 90 | |
| 91 | err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT, |
| 92 | MII_VSC8244_AUXCONSTAT_INIT); |
| 93 | if (err < 0) |
| 94 | return err; |
| 95 | |
Andy Fleming | af2d940 | 2007-07-11 11:42:35 -0500 | [diff] [blame] | 96 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) |
Andy Fleming | fddf86f | 2011-10-13 04:33:55 +0000 | [diff] [blame] | 97 | err = vsc824x_add_skew(phydev); |
Andy Fleming | af2d940 | 2007-07-11 11:42:35 -0500 | [diff] [blame] | 98 | |
Jon Loeliger | ef82a30 | 2006-06-17 17:52:55 -0500 | [diff] [blame] | 99 | return err; |
| 100 | } |
| 101 | |
| 102 | static int vsc824x_ack_interrupt(struct phy_device *phydev) |
| 103 | { |
Andy Fleming | 1d5e83a | 2007-07-10 16:42:04 -0500 | [diff] [blame] | 104 | int err = 0; |
Michal Simek | 2a8626d | 2013-05-30 20:08:23 +0000 | [diff] [blame] | 105 | |
| 106 | /* Don't bother to ACK the interrupts if interrupts |
Andy Fleming | 1d5e83a | 2007-07-10 16:42:04 -0500 | [diff] [blame] | 107 | * are disabled. The 824x cannot clear the interrupts |
| 108 | * if they are disabled. |
| 109 | */ |
| 110 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) |
| 111 | err = phy_read(phydev, MII_VSC8244_ISTAT); |
Jon Loeliger | ef82a30 | 2006-06-17 17:52:55 -0500 | [diff] [blame] | 112 | |
| 113 | return (err < 0) ? err : 0; |
| 114 | } |
| 115 | |
Trent Piepho | 11c6dd2 | 2008-11-25 01:00:47 -0800 | [diff] [blame] | 116 | static int vsc82xx_config_intr(struct phy_device *phydev) |
Jon Loeliger | ef82a30 | 2006-06-17 17:52:55 -0500 | [diff] [blame] | 117 | { |
| 118 | int err; |
| 119 | |
| 120 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) |
| 121 | err = phy_write(phydev, MII_VSC8244_IMASK, |
Andy Fleming | 0508019 | 2013-11-20 16:38:16 -0600 | [diff] [blame^] | 122 | (phydev->drv->phy_id == PHY_ID_VSC8234 || |
| 123 | phydev->drv->phy_id == PHY_ID_VSC8244) ? |
Trent Piepho | 11c6dd2 | 2008-11-25 01:00:47 -0800 | [diff] [blame] | 124 | MII_VSC8244_IMASK_MASK : |
| 125 | MII_VSC8221_IMASK_MASK); |
Andy Fleming | 1d5e83a | 2007-07-10 16:42:04 -0500 | [diff] [blame] | 126 | else { |
Michal Simek | 2a8626d | 2013-05-30 20:08:23 +0000 | [diff] [blame] | 127 | /* The Vitesse PHY cannot clear the interrupt |
Andy Fleming | 1d5e83a | 2007-07-10 16:42:04 -0500 | [diff] [blame] | 128 | * once it has disabled them, so we clear them first |
| 129 | */ |
| 130 | err = phy_read(phydev, MII_VSC8244_ISTAT); |
| 131 | |
Andy Fleming | 52cb1c2 | 2007-07-18 01:06:28 -0500 | [diff] [blame] | 132 | if (err < 0) |
Andy Fleming | 1d5e83a | 2007-07-10 16:42:04 -0500 | [diff] [blame] | 133 | return err; |
| 134 | |
Jon Loeliger | ef82a30 | 2006-06-17 17:52:55 -0500 | [diff] [blame] | 135 | err = phy_write(phydev, MII_VSC8244_IMASK, 0); |
Andy Fleming | 1d5e83a | 2007-07-10 16:42:04 -0500 | [diff] [blame] | 136 | } |
| 137 | |
Jon Loeliger | ef82a30 | 2006-06-17 17:52:55 -0500 | [diff] [blame] | 138 | return err; |
| 139 | } |
| 140 | |
Trent Piepho | 11c6dd2 | 2008-11-25 01:00:47 -0800 | [diff] [blame] | 141 | static int vsc8221_config_init(struct phy_device *phydev) |
Jon Loeliger | ef82a30 | 2006-06-17 17:52:55 -0500 | [diff] [blame] | 142 | { |
Trent Piepho | 11c6dd2 | 2008-11-25 01:00:47 -0800 | [diff] [blame] | 143 | int err; |
| 144 | |
| 145 | err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT, |
| 146 | MII_VSC8221_AUXCONSTAT_INIT); |
| 147 | return err; |
| 148 | |
| 149 | /* Perhaps we should set EXT_CON1 based on the interface? |
Michal Simek | 2a8626d | 2013-05-30 20:08:23 +0000 | [diff] [blame] | 150 | * Options are 802.3Z SerDes or SGMII |
| 151 | */ |
Jon Loeliger | ef82a30 | 2006-06-17 17:52:55 -0500 | [diff] [blame] | 152 | } |
| 153 | |
Andy Fleming | 0508019 | 2013-11-20 16:38:16 -0600 | [diff] [blame^] | 154 | /* Vitesse 82xx */ |
Christian Hohnstaedt | d5bf907 | 2012-07-04 05:44:34 +0000 | [diff] [blame] | 155 | static struct phy_driver vsc82xx_driver[] = { |
| 156 | { |
Andy Fleming | 0508019 | 2013-11-20 16:38:16 -0600 | [diff] [blame^] | 157 | .phy_id = PHY_ID_VSC8234, |
| 158 | .name = "Vitesse VSC8234", |
| 159 | .phy_id_mask = 0x000ffff0, |
| 160 | .features = PHY_GBIT_FEATURES, |
| 161 | .flags = PHY_HAS_INTERRUPT, |
| 162 | .config_init = &vsc824x_config_init, |
| 163 | .config_aneg = &genphy_config_aneg, |
| 164 | .read_status = &genphy_read_status, |
| 165 | .ack_interrupt = &vsc824x_ack_interrupt, |
| 166 | .config_intr = &vsc82xx_config_intr, |
| 167 | .driver = { .owner = THIS_MODULE,}, |
| 168 | }, { |
Christian Hohnstaedt | d5bf907 | 2012-07-04 05:44:34 +0000 | [diff] [blame] | 169 | .phy_id = PHY_ID_VSC8244, |
| 170 | .name = "Vitesse VSC8244", |
| 171 | .phy_id_mask = 0x000fffc0, |
| 172 | .features = PHY_GBIT_FEATURES, |
| 173 | .flags = PHY_HAS_INTERRUPT, |
| 174 | .config_init = &vsc824x_config_init, |
| 175 | .config_aneg = &genphy_config_aneg, |
| 176 | .read_status = &genphy_read_status, |
| 177 | .ack_interrupt = &vsc824x_ack_interrupt, |
| 178 | .config_intr = &vsc82xx_config_intr, |
| 179 | .driver = { .owner = THIS_MODULE,}, |
| 180 | }, { |
| 181 | /* Vitesse 8221 */ |
Trent Piepho | 11c6dd2 | 2008-11-25 01:00:47 -0800 | [diff] [blame] | 182 | .phy_id = PHY_ID_VSC8221, |
| 183 | .phy_id_mask = 0x000ffff0, |
| 184 | .name = "Vitesse VSC8221", |
| 185 | .features = PHY_GBIT_FEATURES, |
| 186 | .flags = PHY_HAS_INTERRUPT, |
| 187 | .config_init = &vsc8221_config_init, |
| 188 | .config_aneg = &genphy_config_aneg, |
| 189 | .read_status = &genphy_read_status, |
| 190 | .ack_interrupt = &vsc824x_ack_interrupt, |
| 191 | .config_intr = &vsc82xx_config_intr, |
Christian Hohnstaedt | d5bf907 | 2012-07-04 05:44:34 +0000 | [diff] [blame] | 192 | .driver = { .owner = THIS_MODULE,}, |
Michal Simek | 5a1cebd | 2013-05-30 20:08:24 +0000 | [diff] [blame] | 193 | }, { |
| 194 | /* Vitesse 8211 */ |
| 195 | .phy_id = PHY_ID_VSC8211, |
| 196 | .phy_id_mask = 0x000ffff0, |
| 197 | .name = "Vitesse VSC8211", |
| 198 | .features = PHY_GBIT_FEATURES, |
| 199 | .flags = PHY_HAS_INTERRUPT, |
| 200 | .config_init = &vsc8221_config_init, |
| 201 | .config_aneg = &genphy_config_aneg, |
| 202 | .read_status = &genphy_read_status, |
| 203 | .ack_interrupt = &vsc824x_ack_interrupt, |
| 204 | .config_intr = &vsc82xx_config_intr, |
| 205 | .driver = { .owner = THIS_MODULE,}, |
Christian Hohnstaedt | d5bf907 | 2012-07-04 05:44:34 +0000 | [diff] [blame] | 206 | } }; |
Trent Piepho | 11c6dd2 | 2008-11-25 01:00:47 -0800 | [diff] [blame] | 207 | |
| 208 | static int __init vsc82xx_init(void) |
| 209 | { |
Christian Hohnstaedt | d5bf907 | 2012-07-04 05:44:34 +0000 | [diff] [blame] | 210 | return phy_drivers_register(vsc82xx_driver, |
| 211 | ARRAY_SIZE(vsc82xx_driver)); |
Trent Piepho | 11c6dd2 | 2008-11-25 01:00:47 -0800 | [diff] [blame] | 212 | } |
| 213 | |
| 214 | static void __exit vsc82xx_exit(void) |
Jon Loeliger | ef82a30 | 2006-06-17 17:52:55 -0500 | [diff] [blame] | 215 | { |
Christian Hohnstaedt | d5bf907 | 2012-07-04 05:44:34 +0000 | [diff] [blame] | 216 | return phy_drivers_unregister(vsc82xx_driver, |
| 217 | ARRAY_SIZE(vsc82xx_driver)); |
Jon Loeliger | ef82a30 | 2006-06-17 17:52:55 -0500 | [diff] [blame] | 218 | } |
| 219 | |
Trent Piepho | 11c6dd2 | 2008-11-25 01:00:47 -0800 | [diff] [blame] | 220 | module_init(vsc82xx_init); |
| 221 | module_exit(vsc82xx_exit); |
David Woodhouse | 4e4f10f | 2010-04-02 01:05:56 +0000 | [diff] [blame] | 222 | |
Uwe Kleine-König | cf93c94 | 2010-10-03 23:43:32 +0000 | [diff] [blame] | 223 | static struct mdio_device_id __maybe_unused vitesse_tbl[] = { |
Andy Fleming | 0508019 | 2013-11-20 16:38:16 -0600 | [diff] [blame^] | 224 | { PHY_ID_VSC8234, 0x000ffff0 }, |
David Woodhouse | 4e4f10f | 2010-04-02 01:05:56 +0000 | [diff] [blame] | 225 | { PHY_ID_VSC8244, 0x000fffc0 }, |
| 226 | { PHY_ID_VSC8221, 0x000ffff0 }, |
Michal Simek | 5a1cebd | 2013-05-30 20:08:24 +0000 | [diff] [blame] | 227 | { PHY_ID_VSC8211, 0x000ffff0 }, |
David Woodhouse | 4e4f10f | 2010-04-02 01:05:56 +0000 | [diff] [blame] | 228 | { } |
| 229 | }; |
| 230 | |
| 231 | MODULE_DEVICE_TABLE(mdio, vitesse_tbl); |