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Michael Chanb6016b72005-05-26 13:03:09 -07001/* bnx2.c: Broadcom NX2 network driver.
2 *
Michael Chan8a56d242013-08-06 15:50:12 -07003 * Copyright (c) 2004-2013 Broadcom Corporation
Michael Chanb6016b72005-05-26 13:03:09 -07004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
Joe Perches3a9c6a42010-02-17 15:01:51 +000012#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
Michael Chanf2a4f052006-03-23 01:13:12 -080013
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16
Michael Chan555069d2012-06-16 15:45:41 +000017#include <linux/stringify.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080018#include <linux/kernel.h>
19#include <linux/timer.h>
20#include <linux/errno.h>
21#include <linux/ioport.h>
22#include <linux/slab.h>
23#include <linux/vmalloc.h>
24#include <linux/interrupt.h>
25#include <linux/pci.h>
26#include <linux/init.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/skbuff.h>
30#include <linux/dma-mapping.h>
Jiri Slaby1977f032007-10-18 23:40:25 -070031#include <linux/bitops.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080032#include <asm/io.h>
33#include <asm/irq.h>
34#include <linux/delay.h>
35#include <asm/byteorder.h>
Michael Chanc86a31f2006-06-13 15:03:47 -070036#include <asm/page.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080037#include <linux/time.h>
38#include <linux/ethtool.h>
39#include <linux/mii.h>
Jiri Pirko01789342011-08-16 06:29:00 +000040#include <linux/if.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080041#include <linux/if_vlan.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080042#include <net/ip.h>
Linus Torvaldsde081fa2007-07-12 16:40:08 -070043#include <net/tcp.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080044#include <net/checksum.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080045#include <linux/workqueue.h>
46#include <linux/crc32.h>
47#include <linux/prefetch.h>
Michael Chan29b12172006-03-23 01:13:43 -080048#include <linux/cache.h>
Michael Chan57579f72009-04-04 16:51:14 -070049#include <linux/firmware.h>
Benjamin Li706bf242008-07-18 17:55:11 -070050#include <linux/log2.h>
John Feeneycd709aa2010-08-22 17:45:53 +000051#include <linux/aer.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080052
Michael Chan4edd4732009-06-08 18:14:42 -070053#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
54#define BCM_CNIC 1
55#include "cnic_if.h"
56#endif
Michael Chanb6016b72005-05-26 13:03:09 -070057#include "bnx2.h"
58#include "bnx2_fw.h"
Denys Vlasenkob3448b02007-09-30 17:55:51 -070059
Michael Chanb6016b72005-05-26 13:03:09 -070060#define DRV_MODULE_NAME "bnx2"
Michael Chan8a56d242013-08-06 15:50:12 -070061#define DRV_MODULE_VERSION "2.2.4"
62#define DRV_MODULE_RELDATE "Aug 05, 2013"
Michael Chanc2c20ef2011-12-18 18:15:09 +000063#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.2.3.fw"
Michael Chan22fa1592010-10-11 16:12:00 -070064#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw"
Michael Chanc2c20ef2011-12-18 18:15:09 +000065#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.2.1b.fw"
Michael Chan22fa1592010-10-11 16:12:00 -070066#define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-6.0.17.fw"
67#define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-6.0.17.fw"
Michael Chanb6016b72005-05-26 13:03:09 -070068
69#define RUN_AT(x) (jiffies + (x))
70
71/* Time in jiffies before concluding the transmitter is hung. */
72#define TX_TIMEOUT (5*HZ)
73
Bill Pembertoncfd95a62012-12-03 09:22:58 -050074static char version[] =
Michael Chanb6016b72005-05-26 13:03:09 -070075 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
76
77MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
Benjamin Li453a9c62008-09-18 16:39:16 -070078MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
Michael Chanb6016b72005-05-26 13:03:09 -070079MODULE_LICENSE("GPL");
80MODULE_VERSION(DRV_MODULE_VERSION);
Michael Chan57579f72009-04-04 16:51:14 -070081MODULE_FIRMWARE(FW_MIPS_FILE_06);
82MODULE_FIRMWARE(FW_RV2P_FILE_06);
83MODULE_FIRMWARE(FW_MIPS_FILE_09);
84MODULE_FIRMWARE(FW_RV2P_FILE_09);
Michael Chan078b0732009-08-29 00:02:46 -070085MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
Michael Chanb6016b72005-05-26 13:03:09 -070086
87static int disable_msi = 0;
88
89module_param(disable_msi, int, 0);
90MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
91
92typedef enum {
93 BCM5706 = 0,
94 NC370T,
95 NC370I,
96 BCM5706S,
97 NC370F,
Michael Chan5b0c76a2005-11-04 08:45:49 -080098 BCM5708,
99 BCM5708S,
Michael Chanbac0dff2006-11-19 14:15:05 -0800100 BCM5709,
Michael Chan27a005b2007-05-03 13:23:41 -0700101 BCM5709S,
Michael Chan7bb0a042008-07-14 22:37:47 -0700102 BCM5716,
Michael Chan1caacec2008-11-12 16:01:12 -0800103 BCM5716S,
Michael Chanb6016b72005-05-26 13:03:09 -0700104} board_t;
105
106/* indexed by board_t, above */
Andrew Mortonfefa8642008-02-09 23:17:15 -0800107static struct {
Michael Chanb6016b72005-05-26 13:03:09 -0700108 char *name;
Bill Pembertoncfd95a62012-12-03 09:22:58 -0500109} board_info[] = {
Michael Chanb6016b72005-05-26 13:03:09 -0700110 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
111 { "HP NC370T Multifunction Gigabit Server Adapter" },
112 { "HP NC370i Multifunction Gigabit Server Adapter" },
113 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
114 { "HP NC370F Multifunction Gigabit Server Adapter" },
Michael Chan5b0c76a2005-11-04 08:45:49 -0800115 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
116 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
Michael Chanbac0dff2006-11-19 14:15:05 -0800117 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
Michael Chan27a005b2007-05-03 13:23:41 -0700118 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
Michael Chan7bb0a042008-07-14 22:37:47 -0700119 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
Michael Chan1caacec2008-11-12 16:01:12 -0800120 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
Michael Chanb6016b72005-05-26 13:03:09 -0700121 };
122
Michael Chan7bb0a042008-07-14 22:37:47 -0700123static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
Michael Chanb6016b72005-05-26 13:03:09 -0700124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
125 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
126 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
127 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
128 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
Michael Chan5b0c76a2005-11-04 08:45:49 -0800130 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
Michael Chanb6016b72005-05-26 13:03:09 -0700132 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
133 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
134 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
Michael Chan5b0c76a2005-11-04 08:45:49 -0800136 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
Michael Chanbac0dff2006-11-19 14:15:05 -0800138 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
Michael Chan27a005b2007-05-03 13:23:41 -0700140 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
Michael Chan7bb0a042008-07-14 22:37:47 -0700142 { PCI_VENDOR_ID_BROADCOM, 0x163b,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
Michael Chan1caacec2008-11-12 16:01:12 -0800144 { PCI_VENDOR_ID_BROADCOM, 0x163c,
Michael Chan1f2435e2008-12-16 20:28:13 -0800145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
Michael Chanb6016b72005-05-26 13:03:09 -0700146 { 0, }
147};
148
Michael Chan0ced9d02009-08-21 16:20:49 +0000149static const struct flash_spec flash_table[] =
Michael Chanb6016b72005-05-26 13:03:09 -0700150{
Michael Chane30372c2007-07-16 18:26:23 -0700151#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
152#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
Michael Chanb6016b72005-05-26 13:03:09 -0700153 /* Slow EEPROM */
Michael Chan37137702005-11-04 08:49:17 -0800154 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700155 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
Michael Chanb6016b72005-05-26 13:03:09 -0700156 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
157 "EEPROM - slow"},
Michael Chan37137702005-11-04 08:49:17 -0800158 /* Expansion entry 0001 */
159 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700160 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800161 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
162 "Entry 0001"},
Michael Chanb6016b72005-05-26 13:03:09 -0700163 /* Saifun SA25F010 (non-buffered flash) */
164 /* strap, cfg1, & write1 need updates */
Michael Chan37137702005-11-04 08:49:17 -0800165 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700166 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chanb6016b72005-05-26 13:03:09 -0700167 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
168 "Non-buffered flash (128kB)"},
169 /* Saifun SA25F020 (non-buffered flash) */
170 /* strap, cfg1, & write1 need updates */
Michael Chan37137702005-11-04 08:49:17 -0800171 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700172 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chanb6016b72005-05-26 13:03:09 -0700173 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
174 "Non-buffered flash (256kB)"},
Michael Chan37137702005-11-04 08:49:17 -0800175 /* Expansion entry 0100 */
176 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700177 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800178 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
179 "Entry 0100"},
180 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400181 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700182 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800183 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
184 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
185 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
186 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700187 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800188 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
189 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
190 /* Saifun SA25F005 (non-buffered flash) */
191 /* strap, cfg1, & write1 need updates */
192 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800194 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
195 "Non-buffered flash (64kB)"},
196 /* Fast EEPROM */
197 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700198 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800199 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
200 "EEPROM - fast"},
201 /* Expansion entry 1001 */
202 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1001"},
206 /* Expansion entry 1010 */
207 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700208 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800209 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1010"},
211 /* ATMEL AT45DB011B (buffered flash) */
212 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
215 "Buffered flash (128kB)"},
216 /* Expansion entry 1100 */
217 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700218 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
220 "Entry 1100"},
221 /* Expansion entry 1101 */
222 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700223 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800224 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
225 "Entry 1101"},
226 /* Ateml Expansion entry 1110 */
227 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700228 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800229 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
230 "Entry 1110 (Atmel)"},
231 /* ATMEL AT45DB021B (buffered flash) */
232 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700233 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800234 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
235 "Buffered flash (256kB)"},
Michael Chanb6016b72005-05-26 13:03:09 -0700236};
237
Michael Chan0ced9d02009-08-21 16:20:49 +0000238static const struct flash_spec flash_5709 = {
Michael Chane30372c2007-07-16 18:26:23 -0700239 .flags = BNX2_NV_BUFFERED,
240 .page_bits = BCM5709_FLASH_PAGE_BITS,
241 .page_size = BCM5709_FLASH_PAGE_SIZE,
242 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
243 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
244 .name = "5709 Buffered flash (256kB)",
245};
246
Michael Chanb6016b72005-05-26 13:03:09 -0700247MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
248
Benjamin Li4327ba42010-03-23 13:13:11 +0000249static void bnx2_init_napi(struct bnx2 *bp);
Michael Chanf048fa92010-06-01 15:05:36 +0000250static void bnx2_del_napi(struct bnx2 *bp);
Benjamin Li4327ba42010-03-23 13:13:11 +0000251
Michael Chan35e90102008-06-19 16:37:42 -0700252static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
Michael Chane89bbf12005-08-25 15:36:58 -0700253{
Michael Chan2f8af122006-08-15 01:39:10 -0700254 u32 diff;
Michael Chane89bbf12005-08-25 15:36:58 -0700255
Michael Chan11848b962010-07-19 14:15:04 +0000256 /* Tell compiler to fetch tx_prod and tx_cons from memory. */
257 barrier();
Michael Chanfaac9c42006-12-14 15:56:32 -0800258
259 /* The ring uses 256 indices for 255 entries, one of them
260 * needs to be skipped.
261 */
Michael Chan35e90102008-06-19 16:37:42 -0700262 diff = txr->tx_prod - txr->tx_cons;
Michael Chan2bc40782012-12-06 10:33:09 +0000263 if (unlikely(diff >= BNX2_TX_DESC_CNT)) {
Michael Chanfaac9c42006-12-14 15:56:32 -0800264 diff &= 0xffff;
Michael Chan2bc40782012-12-06 10:33:09 +0000265 if (diff == BNX2_TX_DESC_CNT)
266 diff = BNX2_MAX_TX_DESC_CNT;
Michael Chanfaac9c42006-12-14 15:56:32 -0800267 }
Eric Dumazet807540b2010-09-23 05:40:09 +0000268 return bp->tx_ring_size - diff;
Michael Chane89bbf12005-08-25 15:36:58 -0700269}
270
Michael Chanb6016b72005-05-26 13:03:09 -0700271static u32
272bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
273{
Michael Chan1b8227c2007-05-03 13:24:05 -0700274 u32 val;
275
276 spin_lock_bh(&bp->indirect_lock);
Michael Chane503e062012-12-06 10:33:08 +0000277 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
278 val = BNX2_RD(bp, BNX2_PCICFG_REG_WINDOW);
Michael Chan1b8227c2007-05-03 13:24:05 -0700279 spin_unlock_bh(&bp->indirect_lock);
280 return val;
Michael Chanb6016b72005-05-26 13:03:09 -0700281}
282
283static void
284bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
285{
Michael Chan1b8227c2007-05-03 13:24:05 -0700286 spin_lock_bh(&bp->indirect_lock);
Michael Chane503e062012-12-06 10:33:08 +0000287 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
288 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
Michael Chan1b8227c2007-05-03 13:24:05 -0700289 spin_unlock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700290}
291
292static void
Michael Chan2726d6e2008-01-29 21:35:05 -0800293bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
294{
295 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
296}
297
298static u32
299bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
300{
Eric Dumazet807540b2010-09-23 05:40:09 +0000301 return bnx2_reg_rd_ind(bp, bp->shmem_base + offset);
Michael Chan2726d6e2008-01-29 21:35:05 -0800302}
303
304static void
Michael Chanb6016b72005-05-26 13:03:09 -0700305bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
306{
307 offset += cid_addr;
Michael Chan1b8227c2007-05-03 13:24:05 -0700308 spin_lock_bh(&bp->indirect_lock);
Michael Chan4ce45e02012-12-06 10:33:10 +0000309 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
Michael Chan59b47d82006-11-19 14:10:45 -0800310 int i;
311
Michael Chane503e062012-12-06 10:33:08 +0000312 BNX2_WR(bp, BNX2_CTX_CTX_DATA, val);
313 BNX2_WR(bp, BNX2_CTX_CTX_CTRL,
314 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
Michael Chan59b47d82006-11-19 14:10:45 -0800315 for (i = 0; i < 5; i++) {
Michael Chane503e062012-12-06 10:33:08 +0000316 val = BNX2_RD(bp, BNX2_CTX_CTX_CTRL);
Michael Chan59b47d82006-11-19 14:10:45 -0800317 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
318 break;
319 udelay(5);
320 }
321 } else {
Michael Chane503e062012-12-06 10:33:08 +0000322 BNX2_WR(bp, BNX2_CTX_DATA_ADR, offset);
323 BNX2_WR(bp, BNX2_CTX_DATA, val);
Michael Chan59b47d82006-11-19 14:10:45 -0800324 }
Michael Chan1b8227c2007-05-03 13:24:05 -0700325 spin_unlock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700326}
327
Michael Chan4edd4732009-06-08 18:14:42 -0700328#ifdef BCM_CNIC
329static int
330bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
331{
332 struct bnx2 *bp = netdev_priv(dev);
333 struct drv_ctl_io *io = &info->data.io;
334
335 switch (info->cmd) {
336 case DRV_CTL_IO_WR_CMD:
337 bnx2_reg_wr_ind(bp, io->offset, io->data);
338 break;
339 case DRV_CTL_IO_RD_CMD:
340 io->data = bnx2_reg_rd_ind(bp, io->offset);
341 break;
342 case DRV_CTL_CTX_WR_CMD:
343 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
344 break;
345 default:
346 return -EINVAL;
347 }
348 return 0;
349}
350
351static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
352{
353 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
354 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
355 int sb_id;
356
357 if (bp->flags & BNX2_FLAG_USING_MSIX) {
358 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
359 bnapi->cnic_present = 0;
360 sb_id = bp->irq_nvecs;
361 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
362 } else {
363 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
364 bnapi->cnic_tag = bnapi->last_status_idx;
365 bnapi->cnic_present = 1;
366 sb_id = 0;
367 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
368 }
369
370 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
371 cp->irq_arr[0].status_blk = (void *)
372 ((unsigned long) bnapi->status_blk.msi +
373 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
374 cp->irq_arr[0].status_blk_num = sb_id;
375 cp->num_irq = 1;
376}
377
378static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
379 void *data)
380{
381 struct bnx2 *bp = netdev_priv(dev);
382 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
383
384 if (ops == NULL)
385 return -EINVAL;
386
387 if (cp->drv_state & CNIC_DRV_STATE_REGD)
388 return -EBUSY;
389
Michael Chan41c21782011-07-13 17:24:22 +0000390 if (!bnx2_reg_rd_ind(bp, BNX2_FW_MAX_ISCSI_CONN))
391 return -ENODEV;
392
Michael Chan4edd4732009-06-08 18:14:42 -0700393 bp->cnic_data = data;
394 rcu_assign_pointer(bp->cnic_ops, ops);
395
396 cp->num_irq = 0;
397 cp->drv_state = CNIC_DRV_STATE_REGD;
398
399 bnx2_setup_cnic_irq_info(bp);
400
401 return 0;
402}
403
404static int bnx2_unregister_cnic(struct net_device *dev)
405{
406 struct bnx2 *bp = netdev_priv(dev);
407 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
408 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
409
Michael Chanc5a88952009-08-14 15:49:45 +0000410 mutex_lock(&bp->cnic_lock);
Michael Chan4edd4732009-06-08 18:14:42 -0700411 cp->drv_state = 0;
412 bnapi->cnic_present = 0;
Eric Dumazet2cfa5a02011-11-23 07:09:32 +0000413 RCU_INIT_POINTER(bp->cnic_ops, NULL);
Michael Chanc5a88952009-08-14 15:49:45 +0000414 mutex_unlock(&bp->cnic_lock);
Michael Chan4edd4732009-06-08 18:14:42 -0700415 synchronize_rcu();
416 return 0;
417}
418
stephen hemminger61c2fc42013-04-10 10:53:40 +0000419static struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
Michael Chan4edd4732009-06-08 18:14:42 -0700420{
421 struct bnx2 *bp = netdev_priv(dev);
422 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
423
Michael Chan7625eb22011-06-08 19:29:36 +0000424 if (!cp->max_iscsi_conn)
425 return NULL;
426
Michael Chan4edd4732009-06-08 18:14:42 -0700427 cp->drv_owner = THIS_MODULE;
428 cp->chip_id = bp->chip_id;
429 cp->pdev = bp->pdev;
430 cp->io_base = bp->regview;
431 cp->drv_ctl = bnx2_drv_ctl;
432 cp->drv_register_cnic = bnx2_register_cnic;
433 cp->drv_unregister_cnic = bnx2_unregister_cnic;
434
435 return cp;
436}
Michael Chan4edd4732009-06-08 18:14:42 -0700437
438static void
439bnx2_cnic_stop(struct bnx2 *bp)
440{
441 struct cnic_ops *c_ops;
442 struct cnic_ctl_info info;
443
Michael Chanc5a88952009-08-14 15:49:45 +0000444 mutex_lock(&bp->cnic_lock);
Eric Dumazet13707f92011-01-26 19:28:23 +0000445 c_ops = rcu_dereference_protected(bp->cnic_ops,
446 lockdep_is_held(&bp->cnic_lock));
Michael Chan4edd4732009-06-08 18:14:42 -0700447 if (c_ops) {
448 info.cmd = CNIC_CTL_STOP_CMD;
449 c_ops->cnic_ctl(bp->cnic_data, &info);
450 }
Michael Chanc5a88952009-08-14 15:49:45 +0000451 mutex_unlock(&bp->cnic_lock);
Michael Chan4edd4732009-06-08 18:14:42 -0700452}
453
454static void
455bnx2_cnic_start(struct bnx2 *bp)
456{
457 struct cnic_ops *c_ops;
458 struct cnic_ctl_info info;
459
Michael Chanc5a88952009-08-14 15:49:45 +0000460 mutex_lock(&bp->cnic_lock);
Eric Dumazet13707f92011-01-26 19:28:23 +0000461 c_ops = rcu_dereference_protected(bp->cnic_ops,
462 lockdep_is_held(&bp->cnic_lock));
Michael Chan4edd4732009-06-08 18:14:42 -0700463 if (c_ops) {
464 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
465 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
466
467 bnapi->cnic_tag = bnapi->last_status_idx;
468 }
469 info.cmd = CNIC_CTL_START_CMD;
470 c_ops->cnic_ctl(bp->cnic_data, &info);
471 }
Michael Chanc5a88952009-08-14 15:49:45 +0000472 mutex_unlock(&bp->cnic_lock);
Michael Chan4edd4732009-06-08 18:14:42 -0700473}
474
475#else
476
477static void
478bnx2_cnic_stop(struct bnx2 *bp)
479{
480}
481
482static void
483bnx2_cnic_start(struct bnx2 *bp)
484{
485}
486
487#endif
488
Michael Chanb6016b72005-05-26 13:03:09 -0700489static int
490bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
491{
492 u32 val1;
493 int i, ret;
494
Michael Chan583c28e2008-01-21 19:51:35 -0800495 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chane503e062012-12-06 10:33:08 +0000496 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
Michael Chanb6016b72005-05-26 13:03:09 -0700497 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
498
Michael Chane503e062012-12-06 10:33:08 +0000499 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
500 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
Michael Chanb6016b72005-05-26 13:03:09 -0700501
502 udelay(40);
503 }
504
505 val1 = (bp->phy_addr << 21) | (reg << 16) |
506 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
507 BNX2_EMAC_MDIO_COMM_START_BUSY;
Michael Chane503e062012-12-06 10:33:08 +0000508 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
Michael Chanb6016b72005-05-26 13:03:09 -0700509
510 for (i = 0; i < 50; i++) {
511 udelay(10);
512
Michael Chane503e062012-12-06 10:33:08 +0000513 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
Michael Chanb6016b72005-05-26 13:03:09 -0700514 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
515 udelay(5);
516
Michael Chane503e062012-12-06 10:33:08 +0000517 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
Michael Chanb6016b72005-05-26 13:03:09 -0700518 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
519
520 break;
521 }
522 }
523
524 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
525 *val = 0x0;
526 ret = -EBUSY;
527 }
528 else {
529 *val = val1;
530 ret = 0;
531 }
532
Michael Chan583c28e2008-01-21 19:51:35 -0800533 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chane503e062012-12-06 10:33:08 +0000534 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
Michael Chanb6016b72005-05-26 13:03:09 -0700535 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
536
Michael Chane503e062012-12-06 10:33:08 +0000537 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
538 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
Michael Chanb6016b72005-05-26 13:03:09 -0700539
540 udelay(40);
541 }
542
543 return ret;
544}
545
546static int
547bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
548{
549 u32 val1;
550 int i, ret;
551
Michael Chan583c28e2008-01-21 19:51:35 -0800552 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chane503e062012-12-06 10:33:08 +0000553 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
Michael Chanb6016b72005-05-26 13:03:09 -0700554 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
555
Michael Chane503e062012-12-06 10:33:08 +0000556 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
557 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
Michael Chanb6016b72005-05-26 13:03:09 -0700558
559 udelay(40);
560 }
561
562 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
563 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
564 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
Michael Chane503e062012-12-06 10:33:08 +0000565 BNX2_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400566
Michael Chanb6016b72005-05-26 13:03:09 -0700567 for (i = 0; i < 50; i++) {
568 udelay(10);
569
Michael Chane503e062012-12-06 10:33:08 +0000570 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_COMM);
Michael Chanb6016b72005-05-26 13:03:09 -0700571 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
572 udelay(5);
573 break;
574 }
575 }
576
577 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
578 ret = -EBUSY;
579 else
580 ret = 0;
581
Michael Chan583c28e2008-01-21 19:51:35 -0800582 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chane503e062012-12-06 10:33:08 +0000583 val1 = BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
Michael Chanb6016b72005-05-26 13:03:09 -0700584 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
585
Michael Chane503e062012-12-06 10:33:08 +0000586 BNX2_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
587 BNX2_RD(bp, BNX2_EMAC_MDIO_MODE);
Michael Chanb6016b72005-05-26 13:03:09 -0700588
589 udelay(40);
590 }
591
592 return ret;
593}
594
595static void
596bnx2_disable_int(struct bnx2 *bp)
597{
Michael Chanb4b36042007-12-20 19:59:30 -0800598 int i;
599 struct bnx2_napi *bnapi;
600
601 for (i = 0; i < bp->irq_nvecs; i++) {
602 bnapi = &bp->bnx2_napi[i];
Michael Chane503e062012-12-06 10:33:08 +0000603 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
Michael Chanb4b36042007-12-20 19:59:30 -0800604 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
605 }
Michael Chane503e062012-12-06 10:33:08 +0000606 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
Michael Chanb6016b72005-05-26 13:03:09 -0700607}
608
609static void
610bnx2_enable_int(struct bnx2 *bp)
611{
Michael Chanb4b36042007-12-20 19:59:30 -0800612 int i;
613 struct bnx2_napi *bnapi;
Michael Chan1269a8a2006-01-23 16:11:03 -0800614
Michael Chanb4b36042007-12-20 19:59:30 -0800615 for (i = 0; i < bp->irq_nvecs; i++) {
616 bnapi = &bp->bnx2_napi[i];
Michael Chan35efa7c2007-12-20 19:56:37 -0800617
Michael Chane503e062012-12-06 10:33:08 +0000618 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
619 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
620 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
621 bnapi->last_status_idx);
Michael Chanb6016b72005-05-26 13:03:09 -0700622
Michael Chane503e062012-12-06 10:33:08 +0000623 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
624 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
625 bnapi->last_status_idx);
Michael Chanb4b36042007-12-20 19:59:30 -0800626 }
Michael Chane503e062012-12-06 10:33:08 +0000627 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
Michael Chanb6016b72005-05-26 13:03:09 -0700628}
629
630static void
631bnx2_disable_int_sync(struct bnx2 *bp)
632{
Michael Chanb4b36042007-12-20 19:59:30 -0800633 int i;
634
Michael Chanb6016b72005-05-26 13:03:09 -0700635 atomic_inc(&bp->intr_sem);
Michael Chan37675462009-08-21 16:20:44 +0000636 if (!netif_running(bp->dev))
637 return;
638
Michael Chanb6016b72005-05-26 13:03:09 -0700639 bnx2_disable_int(bp);
Michael Chanb4b36042007-12-20 19:59:30 -0800640 for (i = 0; i < bp->irq_nvecs; i++)
641 synchronize_irq(bp->irq_tbl[i].vector);
Michael Chanb6016b72005-05-26 13:03:09 -0700642}
643
644static void
Michael Chan35efa7c2007-12-20 19:56:37 -0800645bnx2_napi_disable(struct bnx2 *bp)
646{
Michael Chanb4b36042007-12-20 19:59:30 -0800647 int i;
648
649 for (i = 0; i < bp->irq_nvecs; i++)
650 napi_disable(&bp->bnx2_napi[i].napi);
Michael Chan35efa7c2007-12-20 19:56:37 -0800651}
652
653static void
654bnx2_napi_enable(struct bnx2 *bp)
655{
Michael Chanb4b36042007-12-20 19:59:30 -0800656 int i;
657
658 for (i = 0; i < bp->irq_nvecs; i++)
659 napi_enable(&bp->bnx2_napi[i].napi);
Michael Chan35efa7c2007-12-20 19:56:37 -0800660}
661
662static void
Michael Chan212f9932010-04-27 11:28:10 +0000663bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
Michael Chanb6016b72005-05-26 13:03:09 -0700664{
Michael Chan212f9932010-04-27 11:28:10 +0000665 if (stop_cnic)
666 bnx2_cnic_stop(bp);
Michael Chanb6016b72005-05-26 13:03:09 -0700667 if (netif_running(bp->dev)) {
Michael Chan35efa7c2007-12-20 19:56:37 -0800668 bnx2_napi_disable(bp);
Michael Chanb6016b72005-05-26 13:03:09 -0700669 netif_tx_disable(bp->dev);
Michael Chanb6016b72005-05-26 13:03:09 -0700670 }
Michael Chanb7466562009-12-20 18:40:18 -0800671 bnx2_disable_int_sync(bp);
Michael Chana0ba6762010-05-17 17:34:43 -0700672 netif_carrier_off(bp->dev); /* prevent tx timeout */
Michael Chanb6016b72005-05-26 13:03:09 -0700673}
674
675static void
Michael Chan212f9932010-04-27 11:28:10 +0000676bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
Michael Chanb6016b72005-05-26 13:03:09 -0700677{
678 if (atomic_dec_and_test(&bp->intr_sem)) {
679 if (netif_running(bp->dev)) {
Benjamin Li706bf242008-07-18 17:55:11 -0700680 netif_tx_wake_all_queues(bp->dev);
Michael Chana0ba6762010-05-17 17:34:43 -0700681 spin_lock_bh(&bp->phy_lock);
682 if (bp->link_up)
683 netif_carrier_on(bp->dev);
684 spin_unlock_bh(&bp->phy_lock);
Michael Chan35efa7c2007-12-20 19:56:37 -0800685 bnx2_napi_enable(bp);
Michael Chanb6016b72005-05-26 13:03:09 -0700686 bnx2_enable_int(bp);
Michael Chan212f9932010-04-27 11:28:10 +0000687 if (start_cnic)
688 bnx2_cnic_start(bp);
Michael Chanb6016b72005-05-26 13:03:09 -0700689 }
690 }
691}
692
693static void
Michael Chan35e90102008-06-19 16:37:42 -0700694bnx2_free_tx_mem(struct bnx2 *bp)
695{
696 int i;
697
698 for (i = 0; i < bp->num_tx_rings; i++) {
699 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
700 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
701
702 if (txr->tx_desc_ring) {
Stanislaw Gruszka36227e82010-07-15 04:25:50 +0000703 dma_free_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
704 txr->tx_desc_ring,
705 txr->tx_desc_mapping);
Michael Chan35e90102008-06-19 16:37:42 -0700706 txr->tx_desc_ring = NULL;
707 }
708 kfree(txr->tx_buf_ring);
709 txr->tx_buf_ring = NULL;
710 }
711}
712
Michael Chanbb4f98a2008-06-19 16:38:19 -0700713static void
714bnx2_free_rx_mem(struct bnx2 *bp)
715{
716 int i;
717
718 for (i = 0; i < bp->num_rx_rings; i++) {
719 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
720 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
721 int j;
722
723 for (j = 0; j < bp->rx_max_ring; j++) {
724 if (rxr->rx_desc_ring[j])
Stanislaw Gruszka36227e82010-07-15 04:25:50 +0000725 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
726 rxr->rx_desc_ring[j],
727 rxr->rx_desc_mapping[j]);
Michael Chanbb4f98a2008-06-19 16:38:19 -0700728 rxr->rx_desc_ring[j] = NULL;
729 }
Breno Leitao25b0b992009-06-08 10:30:19 +0000730 vfree(rxr->rx_buf_ring);
Michael Chanbb4f98a2008-06-19 16:38:19 -0700731 rxr->rx_buf_ring = NULL;
732
733 for (j = 0; j < bp->rx_max_pg_ring; j++) {
734 if (rxr->rx_pg_desc_ring[j])
Stanislaw Gruszka36227e82010-07-15 04:25:50 +0000735 dma_free_coherent(&bp->pdev->dev, RXBD_RING_SIZE,
736 rxr->rx_pg_desc_ring[j],
737 rxr->rx_pg_desc_mapping[j]);
Michael Chan3298a732008-12-17 19:06:08 -0800738 rxr->rx_pg_desc_ring[j] = NULL;
Michael Chanbb4f98a2008-06-19 16:38:19 -0700739 }
Breno Leitao25b0b992009-06-08 10:30:19 +0000740 vfree(rxr->rx_pg_ring);
Michael Chanbb4f98a2008-06-19 16:38:19 -0700741 rxr->rx_pg_ring = NULL;
742 }
743}
744
Michael Chan35e90102008-06-19 16:37:42 -0700745static int
746bnx2_alloc_tx_mem(struct bnx2 *bp)
747{
748 int i;
749
750 for (i = 0; i < bp->num_tx_rings; i++) {
751 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
752 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
753
754 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
755 if (txr->tx_buf_ring == NULL)
756 return -ENOMEM;
757
758 txr->tx_desc_ring =
Stanislaw Gruszka36227e82010-07-15 04:25:50 +0000759 dma_alloc_coherent(&bp->pdev->dev, TXBD_RING_SIZE,
760 &txr->tx_desc_mapping, GFP_KERNEL);
Michael Chan35e90102008-06-19 16:37:42 -0700761 if (txr->tx_desc_ring == NULL)
762 return -ENOMEM;
763 }
764 return 0;
765}
766
Michael Chanbb4f98a2008-06-19 16:38:19 -0700767static int
768bnx2_alloc_rx_mem(struct bnx2 *bp)
769{
770 int i;
771
772 for (i = 0; i < bp->num_rx_rings; i++) {
773 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
774 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
775 int j;
776
777 rxr->rx_buf_ring =
Eric Dumazet89bf67f2010-11-22 00:15:06 +0000778 vzalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
Michael Chanbb4f98a2008-06-19 16:38:19 -0700779 if (rxr->rx_buf_ring == NULL)
780 return -ENOMEM;
781
Michael Chanbb4f98a2008-06-19 16:38:19 -0700782 for (j = 0; j < bp->rx_max_ring; j++) {
783 rxr->rx_desc_ring[j] =
Stanislaw Gruszka36227e82010-07-15 04:25:50 +0000784 dma_alloc_coherent(&bp->pdev->dev,
785 RXBD_RING_SIZE,
786 &rxr->rx_desc_mapping[j],
787 GFP_KERNEL);
Michael Chanbb4f98a2008-06-19 16:38:19 -0700788 if (rxr->rx_desc_ring[j] == NULL)
789 return -ENOMEM;
790
791 }
792
793 if (bp->rx_pg_ring_size) {
Eric Dumazet89bf67f2010-11-22 00:15:06 +0000794 rxr->rx_pg_ring = vzalloc(SW_RXPG_RING_SIZE *
Michael Chanbb4f98a2008-06-19 16:38:19 -0700795 bp->rx_max_pg_ring);
796 if (rxr->rx_pg_ring == NULL)
797 return -ENOMEM;
798
Michael Chanbb4f98a2008-06-19 16:38:19 -0700799 }
800
801 for (j = 0; j < bp->rx_max_pg_ring; j++) {
802 rxr->rx_pg_desc_ring[j] =
Stanislaw Gruszka36227e82010-07-15 04:25:50 +0000803 dma_alloc_coherent(&bp->pdev->dev,
804 RXBD_RING_SIZE,
805 &rxr->rx_pg_desc_mapping[j],
806 GFP_KERNEL);
Michael Chanbb4f98a2008-06-19 16:38:19 -0700807 if (rxr->rx_pg_desc_ring[j] == NULL)
808 return -ENOMEM;
809
810 }
811 }
812 return 0;
813}
814
Michael Chan35e90102008-06-19 16:37:42 -0700815static void
Michael Chanb6016b72005-05-26 13:03:09 -0700816bnx2_free_mem(struct bnx2 *bp)
817{
Michael Chan13daffa2006-03-20 17:49:20 -0800818 int i;
Michael Chan43e80b82008-06-19 16:41:08 -0700819 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
Michael Chan13daffa2006-03-20 17:49:20 -0800820
Michael Chan35e90102008-06-19 16:37:42 -0700821 bnx2_free_tx_mem(bp);
Michael Chanbb4f98a2008-06-19 16:38:19 -0700822 bnx2_free_rx_mem(bp);
Michael Chan35e90102008-06-19 16:37:42 -0700823
Michael Chan59b47d82006-11-19 14:10:45 -0800824 for (i = 0; i < bp->ctx_pages; i++) {
825 if (bp->ctx_blk[i]) {
Michael Chan2bc40782012-12-06 10:33:09 +0000826 dma_free_coherent(&bp->pdev->dev, BNX2_PAGE_SIZE,
Stanislaw Gruszka36227e82010-07-15 04:25:50 +0000827 bp->ctx_blk[i],
828 bp->ctx_blk_mapping[i]);
Michael Chan59b47d82006-11-19 14:10:45 -0800829 bp->ctx_blk[i] = NULL;
830 }
831 }
Michael Chan43e80b82008-06-19 16:41:08 -0700832 if (bnapi->status_blk.msi) {
Stanislaw Gruszka36227e82010-07-15 04:25:50 +0000833 dma_free_coherent(&bp->pdev->dev, bp->status_stats_size,
834 bnapi->status_blk.msi,
835 bp->status_blk_mapping);
Michael Chan43e80b82008-06-19 16:41:08 -0700836 bnapi->status_blk.msi = NULL;
Michael Chan0f31f992006-03-23 01:12:38 -0800837 bp->stats_blk = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -0700838 }
Michael Chanb6016b72005-05-26 13:03:09 -0700839}
840
841static int
842bnx2_alloc_mem(struct bnx2 *bp)
843{
Michael Chan35e90102008-06-19 16:37:42 -0700844 int i, status_blk_size, err;
Michael Chan43e80b82008-06-19 16:41:08 -0700845 struct bnx2_napi *bnapi;
846 void *status_blk;
Michael Chanb6016b72005-05-26 13:03:09 -0700847
Michael Chan0f31f992006-03-23 01:12:38 -0800848 /* Combine status and statistics blocks into one allocation. */
849 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
David S. Millerf86e82f2008-01-21 17:15:40 -0800850 if (bp->flags & BNX2_FLAG_MSIX_CAP)
Michael Chanb4b36042007-12-20 19:59:30 -0800851 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
852 BNX2_SBLK_MSIX_ALIGN_SIZE);
Michael Chan0f31f992006-03-23 01:12:38 -0800853 bp->status_stats_size = status_blk_size +
854 sizeof(struct statistics_block);
855
Stanislaw Gruszka36227e82010-07-15 04:25:50 +0000856 status_blk = dma_alloc_coherent(&bp->pdev->dev, bp->status_stats_size,
Joe Perches1f9061d22013-03-15 07:23:58 +0000857 &bp->status_blk_mapping,
858 GFP_KERNEL | __GFP_ZERO);
Michael Chan43e80b82008-06-19 16:41:08 -0700859 if (status_blk == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -0700860 goto alloc_mem_err;
861
Michael Chan43e80b82008-06-19 16:41:08 -0700862 bnapi = &bp->bnx2_napi[0];
863 bnapi->status_blk.msi = status_blk;
864 bnapi->hw_tx_cons_ptr =
865 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
866 bnapi->hw_rx_cons_ptr =
867 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
David S. Millerf86e82f2008-01-21 17:15:40 -0800868 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
Michael Chan379b39a2010-07-19 14:15:03 +0000869 for (i = 1; i < bp->irq_nvecs; i++) {
Michael Chan43e80b82008-06-19 16:41:08 -0700870 struct status_block_msix *sblk;
Michael Chanb4b36042007-12-20 19:59:30 -0800871
Michael Chan43e80b82008-06-19 16:41:08 -0700872 bnapi = &bp->bnx2_napi[i];
873
Joe Perches64699332012-06-04 12:44:16 +0000874 sblk = (status_blk + BNX2_SBLK_MSIX_ALIGN_SIZE * i);
Michael Chan43e80b82008-06-19 16:41:08 -0700875 bnapi->status_blk.msix = sblk;
876 bnapi->hw_tx_cons_ptr =
877 &sblk->status_tx_quick_consumer_index;
878 bnapi->hw_rx_cons_ptr =
879 &sblk->status_rx_quick_consumer_index;
Michael Chanb4b36042007-12-20 19:59:30 -0800880 bnapi->int_num = i << 24;
881 }
882 }
Michael Chan35efa7c2007-12-20 19:56:37 -0800883
Michael Chan43e80b82008-06-19 16:41:08 -0700884 bp->stats_blk = status_blk + status_blk_size;
Michael Chanb6016b72005-05-26 13:03:09 -0700885
Michael Chan0f31f992006-03-23 01:12:38 -0800886 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
Michael Chanb6016b72005-05-26 13:03:09 -0700887
Michael Chan4ce45e02012-12-06 10:33:10 +0000888 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
Michael Chan2bc40782012-12-06 10:33:09 +0000889 bp->ctx_pages = 0x2000 / BNX2_PAGE_SIZE;
Michael Chan59b47d82006-11-19 14:10:45 -0800890 if (bp->ctx_pages == 0)
891 bp->ctx_pages = 1;
892 for (i = 0; i < bp->ctx_pages; i++) {
Stanislaw Gruszka36227e82010-07-15 04:25:50 +0000893 bp->ctx_blk[i] = dma_alloc_coherent(&bp->pdev->dev,
Michael Chan2bc40782012-12-06 10:33:09 +0000894 BNX2_PAGE_SIZE,
Stanislaw Gruszka36227e82010-07-15 04:25:50 +0000895 &bp->ctx_blk_mapping[i],
896 GFP_KERNEL);
Michael Chan59b47d82006-11-19 14:10:45 -0800897 if (bp->ctx_blk[i] == NULL)
898 goto alloc_mem_err;
899 }
900 }
Michael Chan35e90102008-06-19 16:37:42 -0700901
Michael Chanbb4f98a2008-06-19 16:38:19 -0700902 err = bnx2_alloc_rx_mem(bp);
903 if (err)
904 goto alloc_mem_err;
905
Michael Chan35e90102008-06-19 16:37:42 -0700906 err = bnx2_alloc_tx_mem(bp);
907 if (err)
908 goto alloc_mem_err;
909
Michael Chanb6016b72005-05-26 13:03:09 -0700910 return 0;
911
912alloc_mem_err:
913 bnx2_free_mem(bp);
914 return -ENOMEM;
915}
916
917static void
Michael Chane3648b32005-11-04 08:51:21 -0800918bnx2_report_fw_link(struct bnx2 *bp)
919{
920 u32 fw_link_status = 0;
921
Michael Chan583c28e2008-01-21 19:51:35 -0800922 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -0700923 return;
924
Michael Chane3648b32005-11-04 08:51:21 -0800925 if (bp->link_up) {
926 u32 bmsr;
927
928 switch (bp->line_speed) {
929 case SPEED_10:
930 if (bp->duplex == DUPLEX_HALF)
931 fw_link_status = BNX2_LINK_STATUS_10HALF;
932 else
933 fw_link_status = BNX2_LINK_STATUS_10FULL;
934 break;
935 case SPEED_100:
936 if (bp->duplex == DUPLEX_HALF)
937 fw_link_status = BNX2_LINK_STATUS_100HALF;
938 else
939 fw_link_status = BNX2_LINK_STATUS_100FULL;
940 break;
941 case SPEED_1000:
942 if (bp->duplex == DUPLEX_HALF)
943 fw_link_status = BNX2_LINK_STATUS_1000HALF;
944 else
945 fw_link_status = BNX2_LINK_STATUS_1000FULL;
946 break;
947 case SPEED_2500:
948 if (bp->duplex == DUPLEX_HALF)
949 fw_link_status = BNX2_LINK_STATUS_2500HALF;
950 else
951 fw_link_status = BNX2_LINK_STATUS_2500FULL;
952 break;
953 }
954
955 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
956
957 if (bp->autoneg) {
958 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
959
Michael Chanca58c3a2007-05-03 13:22:52 -0700960 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
961 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
Michael Chane3648b32005-11-04 08:51:21 -0800962
963 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
Michael Chan583c28e2008-01-21 19:51:35 -0800964 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
Michael Chane3648b32005-11-04 08:51:21 -0800965 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
966 else
967 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
968 }
969 }
970 else
971 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
972
Michael Chan2726d6e2008-01-29 21:35:05 -0800973 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
Michael Chane3648b32005-11-04 08:51:21 -0800974}
975
Michael Chan9b1084b2007-07-07 22:50:37 -0700976static char *
977bnx2_xceiver_str(struct bnx2 *bp)
978{
Eric Dumazet807540b2010-09-23 05:40:09 +0000979 return (bp->phy_port == PORT_FIBRE) ? "SerDes" :
Michael Chan583c28e2008-01-21 19:51:35 -0800980 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
Eric Dumazet807540b2010-09-23 05:40:09 +0000981 "Copper");
Michael Chan9b1084b2007-07-07 22:50:37 -0700982}
983
Michael Chane3648b32005-11-04 08:51:21 -0800984static void
Michael Chanb6016b72005-05-26 13:03:09 -0700985bnx2_report_link(struct bnx2 *bp)
986{
987 if (bp->link_up) {
988 netif_carrier_on(bp->dev);
Joe Perches3a9c6a42010-02-17 15:01:51 +0000989 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
990 bnx2_xceiver_str(bp),
991 bp->line_speed,
992 bp->duplex == DUPLEX_FULL ? "full" : "half");
Michael Chanb6016b72005-05-26 13:03:09 -0700993
994 if (bp->flow_ctrl) {
995 if (bp->flow_ctrl & FLOW_CTRL_RX) {
Joe Perches3a9c6a42010-02-17 15:01:51 +0000996 pr_cont(", receive ");
Michael Chanb6016b72005-05-26 13:03:09 -0700997 if (bp->flow_ctrl & FLOW_CTRL_TX)
Joe Perches3a9c6a42010-02-17 15:01:51 +0000998 pr_cont("& transmit ");
Michael Chanb6016b72005-05-26 13:03:09 -0700999 }
1000 else {
Joe Perches3a9c6a42010-02-17 15:01:51 +00001001 pr_cont(", transmit ");
Michael Chanb6016b72005-05-26 13:03:09 -07001002 }
Joe Perches3a9c6a42010-02-17 15:01:51 +00001003 pr_cont("flow control ON");
Michael Chanb6016b72005-05-26 13:03:09 -07001004 }
Joe Perches3a9c6a42010-02-17 15:01:51 +00001005 pr_cont("\n");
1006 } else {
Michael Chanb6016b72005-05-26 13:03:09 -07001007 netif_carrier_off(bp->dev);
Joe Perches3a9c6a42010-02-17 15:01:51 +00001008 netdev_err(bp->dev, "NIC %s Link is Down\n",
1009 bnx2_xceiver_str(bp));
Michael Chanb6016b72005-05-26 13:03:09 -07001010 }
Michael Chane3648b32005-11-04 08:51:21 -08001011
1012 bnx2_report_fw_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001013}
1014
1015static void
1016bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1017{
1018 u32 local_adv, remote_adv;
1019
1020 bp->flow_ctrl = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001021 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
Michael Chanb6016b72005-05-26 13:03:09 -07001022 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1023
1024 if (bp->duplex == DUPLEX_FULL) {
1025 bp->flow_ctrl = bp->req_flow_ctrl;
1026 }
1027 return;
1028 }
1029
1030 if (bp->duplex != DUPLEX_FULL) {
1031 return;
1032 }
1033
Michael Chan583c28e2008-01-21 19:51:35 -08001034 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan4ce45e02012-12-06 10:33:10 +00001035 (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001036 u32 val;
1037
1038 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1039 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1040 bp->flow_ctrl |= FLOW_CTRL_TX;
1041 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1042 bp->flow_ctrl |= FLOW_CTRL_RX;
1043 return;
1044 }
1045
Michael Chanca58c3a2007-05-03 13:22:52 -07001046 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1047 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
Michael Chanb6016b72005-05-26 13:03:09 -07001048
Michael Chan583c28e2008-01-21 19:51:35 -08001049 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -07001050 u32 new_local_adv = 0;
1051 u32 new_remote_adv = 0;
1052
1053 if (local_adv & ADVERTISE_1000XPAUSE)
1054 new_local_adv |= ADVERTISE_PAUSE_CAP;
1055 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1056 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1057 if (remote_adv & ADVERTISE_1000XPAUSE)
1058 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1059 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1060 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1061
1062 local_adv = new_local_adv;
1063 remote_adv = new_remote_adv;
1064 }
1065
1066 /* See Table 28B-3 of 802.3ab-1999 spec. */
1067 if (local_adv & ADVERTISE_PAUSE_CAP) {
1068 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1069 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1070 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1071 }
1072 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1073 bp->flow_ctrl = FLOW_CTRL_RX;
1074 }
1075 }
1076 else {
1077 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1078 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1079 }
1080 }
1081 }
1082 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1083 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1084 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1085
1086 bp->flow_ctrl = FLOW_CTRL_TX;
1087 }
1088 }
1089}
1090
1091static int
Michael Chan27a005b2007-05-03 13:23:41 -07001092bnx2_5709s_linkup(struct bnx2 *bp)
1093{
1094 u32 val, speed;
1095
1096 bp->link_up = 1;
1097
1098 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1099 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1100 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1101
1102 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1103 bp->line_speed = bp->req_line_speed;
1104 bp->duplex = bp->req_duplex;
1105 return 0;
1106 }
1107 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1108 switch (speed) {
1109 case MII_BNX2_GP_TOP_AN_SPEED_10:
1110 bp->line_speed = SPEED_10;
1111 break;
1112 case MII_BNX2_GP_TOP_AN_SPEED_100:
1113 bp->line_speed = SPEED_100;
1114 break;
1115 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1116 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1117 bp->line_speed = SPEED_1000;
1118 break;
1119 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1120 bp->line_speed = SPEED_2500;
1121 break;
1122 }
1123 if (val & MII_BNX2_GP_TOP_AN_FD)
1124 bp->duplex = DUPLEX_FULL;
1125 else
1126 bp->duplex = DUPLEX_HALF;
1127 return 0;
1128}
1129
1130static int
Michael Chan5b0c76a2005-11-04 08:45:49 -08001131bnx2_5708s_linkup(struct bnx2 *bp)
1132{
1133 u32 val;
1134
1135 bp->link_up = 1;
1136 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1137 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1138 case BCM5708S_1000X_STAT1_SPEED_10:
1139 bp->line_speed = SPEED_10;
1140 break;
1141 case BCM5708S_1000X_STAT1_SPEED_100:
1142 bp->line_speed = SPEED_100;
1143 break;
1144 case BCM5708S_1000X_STAT1_SPEED_1G:
1145 bp->line_speed = SPEED_1000;
1146 break;
1147 case BCM5708S_1000X_STAT1_SPEED_2G5:
1148 bp->line_speed = SPEED_2500;
1149 break;
1150 }
1151 if (val & BCM5708S_1000X_STAT1_FD)
1152 bp->duplex = DUPLEX_FULL;
1153 else
1154 bp->duplex = DUPLEX_HALF;
1155
1156 return 0;
1157}
1158
1159static int
1160bnx2_5706s_linkup(struct bnx2 *bp)
Michael Chanb6016b72005-05-26 13:03:09 -07001161{
1162 u32 bmcr, local_adv, remote_adv, common;
1163
1164 bp->link_up = 1;
1165 bp->line_speed = SPEED_1000;
1166
Michael Chanca58c3a2007-05-03 13:22:52 -07001167 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07001168 if (bmcr & BMCR_FULLDPLX) {
1169 bp->duplex = DUPLEX_FULL;
1170 }
1171 else {
1172 bp->duplex = DUPLEX_HALF;
1173 }
1174
1175 if (!(bmcr & BMCR_ANENABLE)) {
1176 return 0;
1177 }
1178
Michael Chanca58c3a2007-05-03 13:22:52 -07001179 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1180 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
Michael Chanb6016b72005-05-26 13:03:09 -07001181
1182 common = local_adv & remote_adv;
1183 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1184
1185 if (common & ADVERTISE_1000XFULL) {
1186 bp->duplex = DUPLEX_FULL;
1187 }
1188 else {
1189 bp->duplex = DUPLEX_HALF;
1190 }
1191 }
1192
1193 return 0;
1194}
1195
1196static int
1197bnx2_copper_linkup(struct bnx2 *bp)
1198{
1199 u32 bmcr;
1200
Michael Chanca58c3a2007-05-03 13:22:52 -07001201 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07001202 if (bmcr & BMCR_ANENABLE) {
1203 u32 local_adv, remote_adv, common;
1204
1205 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1206 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1207
1208 common = local_adv & (remote_adv >> 2);
1209 if (common & ADVERTISE_1000FULL) {
1210 bp->line_speed = SPEED_1000;
1211 bp->duplex = DUPLEX_FULL;
1212 }
1213 else if (common & ADVERTISE_1000HALF) {
1214 bp->line_speed = SPEED_1000;
1215 bp->duplex = DUPLEX_HALF;
1216 }
1217 else {
Michael Chanca58c3a2007-05-03 13:22:52 -07001218 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1219 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
Michael Chanb6016b72005-05-26 13:03:09 -07001220
1221 common = local_adv & remote_adv;
1222 if (common & ADVERTISE_100FULL) {
1223 bp->line_speed = SPEED_100;
1224 bp->duplex = DUPLEX_FULL;
1225 }
1226 else if (common & ADVERTISE_100HALF) {
1227 bp->line_speed = SPEED_100;
1228 bp->duplex = DUPLEX_HALF;
1229 }
1230 else if (common & ADVERTISE_10FULL) {
1231 bp->line_speed = SPEED_10;
1232 bp->duplex = DUPLEX_FULL;
1233 }
1234 else if (common & ADVERTISE_10HALF) {
1235 bp->line_speed = SPEED_10;
1236 bp->duplex = DUPLEX_HALF;
1237 }
1238 else {
1239 bp->line_speed = 0;
1240 bp->link_up = 0;
1241 }
1242 }
1243 }
1244 else {
1245 if (bmcr & BMCR_SPEED100) {
1246 bp->line_speed = SPEED_100;
1247 }
1248 else {
1249 bp->line_speed = SPEED_10;
1250 }
1251 if (bmcr & BMCR_FULLDPLX) {
1252 bp->duplex = DUPLEX_FULL;
1253 }
1254 else {
1255 bp->duplex = DUPLEX_HALF;
1256 }
1257 }
1258
1259 return 0;
1260}
1261
Michael Chan83e3fc82008-01-29 21:37:17 -08001262static void
Michael Chanbb4f98a2008-06-19 16:38:19 -07001263bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
Michael Chan83e3fc82008-01-29 21:37:17 -08001264{
Michael Chanbb4f98a2008-06-19 16:38:19 -07001265 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
Michael Chan83e3fc82008-01-29 21:37:17 -08001266
1267 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1268 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1269 val |= 0x02 << 8;
1270
Michael Chan22fa1592010-10-11 16:12:00 -07001271 if (bp->flow_ctrl & FLOW_CTRL_TX)
1272 val |= BNX2_L2CTX_FLOW_CTRL_ENABLE;
Michael Chan83e3fc82008-01-29 21:37:17 -08001273
Michael Chan83e3fc82008-01-29 21:37:17 -08001274 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1275}
1276
Michael Chanbb4f98a2008-06-19 16:38:19 -07001277static void
1278bnx2_init_all_rx_contexts(struct bnx2 *bp)
1279{
1280 int i;
1281 u32 cid;
1282
1283 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1284 if (i == 1)
1285 cid = RX_RSS_CID;
1286 bnx2_init_rx_context(bp, cid);
1287 }
1288}
1289
Benjamin Li344478d2008-09-18 16:38:24 -07001290static void
Michael Chanb6016b72005-05-26 13:03:09 -07001291bnx2_set_mac_link(struct bnx2 *bp)
1292{
1293 u32 val;
1294
Michael Chane503e062012-12-06 10:33:08 +00001295 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
Michael Chanb6016b72005-05-26 13:03:09 -07001296 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1297 (bp->duplex == DUPLEX_HALF)) {
Michael Chane503e062012-12-06 10:33:08 +00001298 BNX2_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
Michael Chanb6016b72005-05-26 13:03:09 -07001299 }
1300
1301 /* Configure the EMAC mode register. */
Michael Chane503e062012-12-06 10:33:08 +00001302 val = BNX2_RD(bp, BNX2_EMAC_MODE);
Michael Chanb6016b72005-05-26 13:03:09 -07001303
1304 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
Michael Chan5b0c76a2005-11-04 08:45:49 -08001305 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
Michael Chan59b47d82006-11-19 14:10:45 -08001306 BNX2_EMAC_MODE_25G_MODE);
Michael Chanb6016b72005-05-26 13:03:09 -07001307
1308 if (bp->link_up) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001309 switch (bp->line_speed) {
1310 case SPEED_10:
Michael Chan4ce45e02012-12-06 10:33:10 +00001311 if (BNX2_CHIP(bp) != BNX2_CHIP_5706) {
Michael Chan59b47d82006-11-19 14:10:45 -08001312 val |= BNX2_EMAC_MODE_PORT_MII_10M;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001313 break;
1314 }
1315 /* fall through */
1316 case SPEED_100:
1317 val |= BNX2_EMAC_MODE_PORT_MII;
1318 break;
1319 case SPEED_2500:
Michael Chan59b47d82006-11-19 14:10:45 -08001320 val |= BNX2_EMAC_MODE_25G_MODE;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001321 /* fall through */
1322 case SPEED_1000:
1323 val |= BNX2_EMAC_MODE_PORT_GMII;
1324 break;
1325 }
Michael Chanb6016b72005-05-26 13:03:09 -07001326 }
1327 else {
1328 val |= BNX2_EMAC_MODE_PORT_GMII;
1329 }
1330
1331 /* Set the MAC to operate in the appropriate duplex mode. */
1332 if (bp->duplex == DUPLEX_HALF)
1333 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
Michael Chane503e062012-12-06 10:33:08 +00001334 BNX2_WR(bp, BNX2_EMAC_MODE, val);
Michael Chanb6016b72005-05-26 13:03:09 -07001335
1336 /* Enable/disable rx PAUSE. */
1337 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1338
1339 if (bp->flow_ctrl & FLOW_CTRL_RX)
1340 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
Michael Chane503e062012-12-06 10:33:08 +00001341 BNX2_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
Michael Chanb6016b72005-05-26 13:03:09 -07001342
1343 /* Enable/disable tx PAUSE. */
Michael Chane503e062012-12-06 10:33:08 +00001344 val = BNX2_RD(bp, BNX2_EMAC_TX_MODE);
Michael Chanb6016b72005-05-26 13:03:09 -07001345 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1346
1347 if (bp->flow_ctrl & FLOW_CTRL_TX)
1348 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
Michael Chane503e062012-12-06 10:33:08 +00001349 BNX2_WR(bp, BNX2_EMAC_TX_MODE, val);
Michael Chanb6016b72005-05-26 13:03:09 -07001350
1351 /* Acknowledge the interrupt. */
Michael Chane503e062012-12-06 10:33:08 +00001352 BNX2_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
Michael Chanb6016b72005-05-26 13:03:09 -07001353
Michael Chan22fa1592010-10-11 16:12:00 -07001354 bnx2_init_all_rx_contexts(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001355}
1356
Michael Chan27a005b2007-05-03 13:23:41 -07001357static void
1358bnx2_enable_bmsr1(struct bnx2 *bp)
1359{
Michael Chan583c28e2008-01-21 19:51:35 -08001360 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan4ce45e02012-12-06 10:33:10 +00001361 (BNX2_CHIP(bp) == BNX2_CHIP_5709))
Michael Chan27a005b2007-05-03 13:23:41 -07001362 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1363 MII_BNX2_BLK_ADDR_GP_STATUS);
1364}
1365
1366static void
1367bnx2_disable_bmsr1(struct bnx2 *bp)
1368{
Michael Chan583c28e2008-01-21 19:51:35 -08001369 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan4ce45e02012-12-06 10:33:10 +00001370 (BNX2_CHIP(bp) == BNX2_CHIP_5709))
Michael Chan27a005b2007-05-03 13:23:41 -07001371 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1372 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1373}
1374
Michael Chanb6016b72005-05-26 13:03:09 -07001375static int
Michael Chan605a9e22007-05-03 13:23:13 -07001376bnx2_test_and_enable_2g5(struct bnx2 *bp)
1377{
1378 u32 up1;
1379 int ret = 1;
1380
Michael Chan583c28e2008-01-21 19:51:35 -08001381 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001382 return 0;
1383
1384 if (bp->autoneg & AUTONEG_SPEED)
1385 bp->advertising |= ADVERTISED_2500baseX_Full;
1386
Michael Chan4ce45e02012-12-06 10:33:10 +00001387 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
Michael Chan27a005b2007-05-03 13:23:41 -07001388 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1389
Michael Chan605a9e22007-05-03 13:23:13 -07001390 bnx2_read_phy(bp, bp->mii_up1, &up1);
1391 if (!(up1 & BCM5708S_UP1_2G5)) {
1392 up1 |= BCM5708S_UP1_2G5;
1393 bnx2_write_phy(bp, bp->mii_up1, up1);
1394 ret = 0;
1395 }
1396
Michael Chan4ce45e02012-12-06 10:33:10 +00001397 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
Michael Chan27a005b2007-05-03 13:23:41 -07001398 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1399 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1400
Michael Chan605a9e22007-05-03 13:23:13 -07001401 return ret;
1402}
1403
1404static int
1405bnx2_test_and_disable_2g5(struct bnx2 *bp)
1406{
1407 u32 up1;
1408 int ret = 0;
1409
Michael Chan583c28e2008-01-21 19:51:35 -08001410 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001411 return 0;
1412
Michael Chan4ce45e02012-12-06 10:33:10 +00001413 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
Michael Chan27a005b2007-05-03 13:23:41 -07001414 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1415
Michael Chan605a9e22007-05-03 13:23:13 -07001416 bnx2_read_phy(bp, bp->mii_up1, &up1);
1417 if (up1 & BCM5708S_UP1_2G5) {
1418 up1 &= ~BCM5708S_UP1_2G5;
1419 bnx2_write_phy(bp, bp->mii_up1, up1);
1420 ret = 1;
1421 }
1422
Michael Chan4ce45e02012-12-06 10:33:10 +00001423 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
Michael Chan27a005b2007-05-03 13:23:41 -07001424 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1425 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1426
Michael Chan605a9e22007-05-03 13:23:13 -07001427 return ret;
1428}
1429
1430static void
1431bnx2_enable_forced_2g5(struct bnx2 *bp)
1432{
Michael Chancbd68902010-06-08 07:21:30 +00001433 u32 uninitialized_var(bmcr);
1434 int err;
Michael Chan605a9e22007-05-03 13:23:13 -07001435
Michael Chan583c28e2008-01-21 19:51:35 -08001436 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001437 return;
1438
Michael Chan4ce45e02012-12-06 10:33:10 +00001439 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
Michael Chan27a005b2007-05-03 13:23:41 -07001440 u32 val;
1441
1442 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1443 MII_BNX2_BLK_ADDR_SERDES_DIG);
Michael Chancbd68902010-06-08 07:21:30 +00001444 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1445 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1446 val |= MII_BNX2_SD_MISC1_FORCE |
1447 MII_BNX2_SD_MISC1_FORCE_2_5G;
1448 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1449 }
Michael Chan27a005b2007-05-03 13:23:41 -07001450
1451 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1452 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
Michael Chancbd68902010-06-08 07:21:30 +00001453 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chan27a005b2007-05-03 13:23:41 -07001454
Michael Chan4ce45e02012-12-06 10:33:10 +00001455 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
Michael Chancbd68902010-06-08 07:21:30 +00001456 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1457 if (!err)
1458 bmcr |= BCM5708S_BMCR_FORCE_2500;
Eric Dumazetc70798572009-11-02 23:17:42 +00001459 } else {
1460 return;
Michael Chan605a9e22007-05-03 13:23:13 -07001461 }
1462
Michael Chancbd68902010-06-08 07:21:30 +00001463 if (err)
1464 return;
1465
Michael Chan605a9e22007-05-03 13:23:13 -07001466 if (bp->autoneg & AUTONEG_SPEED) {
1467 bmcr &= ~BMCR_ANENABLE;
1468 if (bp->req_duplex == DUPLEX_FULL)
1469 bmcr |= BMCR_FULLDPLX;
1470 }
1471 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1472}
1473
1474static void
1475bnx2_disable_forced_2g5(struct bnx2 *bp)
1476{
Michael Chancbd68902010-06-08 07:21:30 +00001477 u32 uninitialized_var(bmcr);
1478 int err;
Michael Chan605a9e22007-05-03 13:23:13 -07001479
Michael Chan583c28e2008-01-21 19:51:35 -08001480 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001481 return;
1482
Michael Chan4ce45e02012-12-06 10:33:10 +00001483 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
Michael Chan27a005b2007-05-03 13:23:41 -07001484 u32 val;
1485
1486 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1487 MII_BNX2_BLK_ADDR_SERDES_DIG);
Michael Chancbd68902010-06-08 07:21:30 +00001488 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1489 val &= ~MII_BNX2_SD_MISC1_FORCE;
1490 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1491 }
Michael Chan27a005b2007-05-03 13:23:41 -07001492
1493 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1494 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
Michael Chancbd68902010-06-08 07:21:30 +00001495 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chan27a005b2007-05-03 13:23:41 -07001496
Michael Chan4ce45e02012-12-06 10:33:10 +00001497 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
Michael Chancbd68902010-06-08 07:21:30 +00001498 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1499 if (!err)
1500 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
Eric Dumazetc70798572009-11-02 23:17:42 +00001501 } else {
1502 return;
Michael Chan605a9e22007-05-03 13:23:13 -07001503 }
1504
Michael Chancbd68902010-06-08 07:21:30 +00001505 if (err)
1506 return;
1507
Michael Chan605a9e22007-05-03 13:23:13 -07001508 if (bp->autoneg & AUTONEG_SPEED)
1509 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1510 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1511}
1512
Michael Chanb2fadea2008-01-21 17:07:06 -08001513static void
1514bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1515{
1516 u32 val;
1517
1518 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1519 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1520 if (start)
1521 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1522 else
1523 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1524}
1525
Michael Chan605a9e22007-05-03 13:23:13 -07001526static int
Michael Chanb6016b72005-05-26 13:03:09 -07001527bnx2_set_link(struct bnx2 *bp)
1528{
1529 u32 bmsr;
1530 u8 link_up;
1531
Michael Chan80be4432006-11-19 14:07:28 -08001532 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
Michael Chanb6016b72005-05-26 13:03:09 -07001533 bp->link_up = 1;
1534 return 0;
1535 }
1536
Michael Chan583c28e2008-01-21 19:51:35 -08001537 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07001538 return 0;
1539
Michael Chanb6016b72005-05-26 13:03:09 -07001540 link_up = bp->link_up;
1541
Michael Chan27a005b2007-05-03 13:23:41 -07001542 bnx2_enable_bmsr1(bp);
1543 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1544 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1545 bnx2_disable_bmsr1(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001546
Michael Chan583c28e2008-01-21 19:51:35 -08001547 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan4ce45e02012-12-06 10:33:10 +00001548 (BNX2_CHIP(bp) == BNX2_CHIP_5706)) {
Michael Chana2724e22008-02-23 19:47:44 -08001549 u32 val, an_dbg;
Michael Chanb6016b72005-05-26 13:03:09 -07001550
Michael Chan583c28e2008-01-21 19:51:35 -08001551 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
Michael Chanb2fadea2008-01-21 17:07:06 -08001552 bnx2_5706s_force_link_dn(bp, 0);
Michael Chan583c28e2008-01-21 19:51:35 -08001553 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
Michael Chanb2fadea2008-01-21 17:07:06 -08001554 }
Michael Chane503e062012-12-06 10:33:08 +00001555 val = BNX2_RD(bp, BNX2_EMAC_STATUS);
Michael Chana2724e22008-02-23 19:47:44 -08001556
1557 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1558 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1559 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1560
1561 if ((val & BNX2_EMAC_STATUS_LINK) &&
1562 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
Michael Chanb6016b72005-05-26 13:03:09 -07001563 bmsr |= BMSR_LSTATUS;
1564 else
1565 bmsr &= ~BMSR_LSTATUS;
1566 }
1567
1568 if (bmsr & BMSR_LSTATUS) {
1569 bp->link_up = 1;
1570
Michael Chan583c28e2008-01-21 19:51:35 -08001571 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan4ce45e02012-12-06 10:33:10 +00001572 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
Michael Chan5b0c76a2005-11-04 08:45:49 -08001573 bnx2_5706s_linkup(bp);
Michael Chan4ce45e02012-12-06 10:33:10 +00001574 else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
Michael Chan5b0c76a2005-11-04 08:45:49 -08001575 bnx2_5708s_linkup(bp);
Michael Chan4ce45e02012-12-06 10:33:10 +00001576 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
Michael Chan27a005b2007-05-03 13:23:41 -07001577 bnx2_5709s_linkup(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001578 }
1579 else {
1580 bnx2_copper_linkup(bp);
1581 }
1582 bnx2_resolve_flow_ctrl(bp);
1583 }
1584 else {
Michael Chan583c28e2008-01-21 19:51:35 -08001585 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan605a9e22007-05-03 13:23:13 -07001586 (bp->autoneg & AUTONEG_SPEED))
1587 bnx2_disable_forced_2g5(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001588
Michael Chan583c28e2008-01-21 19:51:35 -08001589 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
Michael Chanb2fadea2008-01-21 17:07:06 -08001590 u32 bmcr;
1591
1592 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1593 bmcr |= BMCR_ANENABLE;
1594 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1595
Michael Chan583c28e2008-01-21 19:51:35 -08001596 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chanb2fadea2008-01-21 17:07:06 -08001597 }
Michael Chanb6016b72005-05-26 13:03:09 -07001598 bp->link_up = 0;
1599 }
1600
1601 if (bp->link_up != link_up) {
1602 bnx2_report_link(bp);
1603 }
1604
1605 bnx2_set_mac_link(bp);
1606
1607 return 0;
1608}
1609
1610static int
1611bnx2_reset_phy(struct bnx2 *bp)
1612{
1613 int i;
1614 u32 reg;
1615
Michael Chanca58c3a2007-05-03 13:22:52 -07001616 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
Michael Chanb6016b72005-05-26 13:03:09 -07001617
1618#define PHY_RESET_MAX_WAIT 100
1619 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1620 udelay(10);
1621
Michael Chanca58c3a2007-05-03 13:22:52 -07001622 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
Michael Chanb6016b72005-05-26 13:03:09 -07001623 if (!(reg & BMCR_RESET)) {
1624 udelay(20);
1625 break;
1626 }
1627 }
1628 if (i == PHY_RESET_MAX_WAIT) {
1629 return -EBUSY;
1630 }
1631 return 0;
1632}
1633
1634static u32
1635bnx2_phy_get_pause_adv(struct bnx2 *bp)
1636{
1637 u32 adv = 0;
1638
1639 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1640 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1641
Michael Chan583c28e2008-01-21 19:51:35 -08001642 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -07001643 adv = ADVERTISE_1000XPAUSE;
1644 }
1645 else {
1646 adv = ADVERTISE_PAUSE_CAP;
1647 }
1648 }
1649 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
Michael Chan583c28e2008-01-21 19:51:35 -08001650 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -07001651 adv = ADVERTISE_1000XPSE_ASYM;
1652 }
1653 else {
1654 adv = ADVERTISE_PAUSE_ASYM;
1655 }
1656 }
1657 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
Michael Chan583c28e2008-01-21 19:51:35 -08001658 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -07001659 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1660 }
1661 else {
1662 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1663 }
1664 }
1665 return adv;
1666}
1667
Michael Chana2f13892008-07-14 22:38:23 -07001668static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
Michael Chan0d8a6572007-07-07 22:49:43 -07001669
Michael Chanb6016b72005-05-26 13:03:09 -07001670static int
Michael Chan0d8a6572007-07-07 22:49:43 -07001671bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
Harvey Harrison52d07b12009-01-19 17:27:06 -08001672__releases(&bp->phy_lock)
1673__acquires(&bp->phy_lock)
Michael Chan0d8a6572007-07-07 22:49:43 -07001674{
1675 u32 speed_arg = 0, pause_adv;
1676
1677 pause_adv = bnx2_phy_get_pause_adv(bp);
1678
1679 if (bp->autoneg & AUTONEG_SPEED) {
1680 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1681 if (bp->advertising & ADVERTISED_10baseT_Half)
1682 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1683 if (bp->advertising & ADVERTISED_10baseT_Full)
1684 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1685 if (bp->advertising & ADVERTISED_100baseT_Half)
1686 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1687 if (bp->advertising & ADVERTISED_100baseT_Full)
1688 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1689 if (bp->advertising & ADVERTISED_1000baseT_Full)
1690 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1691 if (bp->advertising & ADVERTISED_2500baseX_Full)
1692 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1693 } else {
1694 if (bp->req_line_speed == SPEED_2500)
1695 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1696 else if (bp->req_line_speed == SPEED_1000)
1697 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1698 else if (bp->req_line_speed == SPEED_100) {
1699 if (bp->req_duplex == DUPLEX_FULL)
1700 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1701 else
1702 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1703 } else if (bp->req_line_speed == SPEED_10) {
1704 if (bp->req_duplex == DUPLEX_FULL)
1705 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1706 else
1707 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1708 }
1709 }
1710
1711 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1712 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
Michael Chanc26736e2008-01-31 17:07:21 -08001713 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
Michael Chan0d8a6572007-07-07 22:49:43 -07001714 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1715
1716 if (port == PORT_TP)
1717 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1718 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1719
Michael Chan2726d6e2008-01-29 21:35:05 -08001720 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
Michael Chan0d8a6572007-07-07 22:49:43 -07001721
1722 spin_unlock_bh(&bp->phy_lock);
Michael Chana2f13892008-07-14 22:38:23 -07001723 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
Michael Chan0d8a6572007-07-07 22:49:43 -07001724 spin_lock_bh(&bp->phy_lock);
1725
1726 return 0;
1727}
1728
1729static int
1730bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
Harvey Harrison52d07b12009-01-19 17:27:06 -08001731__releases(&bp->phy_lock)
1732__acquires(&bp->phy_lock)
Michael Chanb6016b72005-05-26 13:03:09 -07001733{
Michael Chan605a9e22007-05-03 13:23:13 -07001734 u32 adv, bmcr;
Michael Chanb6016b72005-05-26 13:03:09 -07001735 u32 new_adv = 0;
1736
Michael Chan583c28e2008-01-21 19:51:35 -08001737 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Eric Dumazet807540b2010-09-23 05:40:09 +00001738 return bnx2_setup_remote_phy(bp, port);
Michael Chan0d8a6572007-07-07 22:49:43 -07001739
Michael Chanb6016b72005-05-26 13:03:09 -07001740 if (!(bp->autoneg & AUTONEG_SPEED)) {
1741 u32 new_bmcr;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001742 int force_link_down = 0;
1743
Michael Chan605a9e22007-05-03 13:23:13 -07001744 if (bp->req_line_speed == SPEED_2500) {
1745 if (!bnx2_test_and_enable_2g5(bp))
1746 force_link_down = 1;
1747 } else if (bp->req_line_speed == SPEED_1000) {
1748 if (bnx2_test_and_disable_2g5(bp))
1749 force_link_down = 1;
1750 }
Michael Chanca58c3a2007-05-03 13:22:52 -07001751 bnx2_read_phy(bp, bp->mii_adv, &adv);
Michael Chan80be4432006-11-19 14:07:28 -08001752 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1753
Michael Chanca58c3a2007-05-03 13:22:52 -07001754 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chan605a9e22007-05-03 13:23:13 -07001755 new_bmcr = bmcr & ~BMCR_ANENABLE;
Michael Chan80be4432006-11-19 14:07:28 -08001756 new_bmcr |= BMCR_SPEED1000;
Michael Chan605a9e22007-05-03 13:23:13 -07001757
Michael Chan4ce45e02012-12-06 10:33:10 +00001758 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
Michael Chan27a005b2007-05-03 13:23:41 -07001759 if (bp->req_line_speed == SPEED_2500)
1760 bnx2_enable_forced_2g5(bp);
1761 else if (bp->req_line_speed == SPEED_1000) {
1762 bnx2_disable_forced_2g5(bp);
1763 new_bmcr &= ~0x2000;
1764 }
1765
Michael Chan4ce45e02012-12-06 10:33:10 +00001766 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5708) {
Michael Chan605a9e22007-05-03 13:23:13 -07001767 if (bp->req_line_speed == SPEED_2500)
1768 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1769 else
1770 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001771 }
1772
Michael Chanb6016b72005-05-26 13:03:09 -07001773 if (bp->req_duplex == DUPLEX_FULL) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001774 adv |= ADVERTISE_1000XFULL;
Michael Chanb6016b72005-05-26 13:03:09 -07001775 new_bmcr |= BMCR_FULLDPLX;
1776 }
1777 else {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001778 adv |= ADVERTISE_1000XHALF;
Michael Chanb6016b72005-05-26 13:03:09 -07001779 new_bmcr &= ~BMCR_FULLDPLX;
1780 }
Michael Chan5b0c76a2005-11-04 08:45:49 -08001781 if ((new_bmcr != bmcr) || (force_link_down)) {
Michael Chanb6016b72005-05-26 13:03:09 -07001782 /* Force a link down visible on the other side */
1783 if (bp->link_up) {
Michael Chanca58c3a2007-05-03 13:22:52 -07001784 bnx2_write_phy(bp, bp->mii_adv, adv &
Michael Chan5b0c76a2005-11-04 08:45:49 -08001785 ~(ADVERTISE_1000XFULL |
1786 ADVERTISE_1000XHALF));
Michael Chanca58c3a2007-05-03 13:22:52 -07001787 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
Michael Chanb6016b72005-05-26 13:03:09 -07001788 BMCR_ANRESTART | BMCR_ANENABLE);
1789
1790 bp->link_up = 0;
1791 netif_carrier_off(bp->dev);
Michael Chanca58c3a2007-05-03 13:22:52 -07001792 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
Michael Chan80be4432006-11-19 14:07:28 -08001793 bnx2_report_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001794 }
Michael Chanca58c3a2007-05-03 13:22:52 -07001795 bnx2_write_phy(bp, bp->mii_adv, adv);
1796 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
Michael Chan605a9e22007-05-03 13:23:13 -07001797 } else {
1798 bnx2_resolve_flow_ctrl(bp);
1799 bnx2_set_mac_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001800 }
1801 return 0;
1802 }
1803
Michael Chan605a9e22007-05-03 13:23:13 -07001804 bnx2_test_and_enable_2g5(bp);
Michael Chan5b0c76a2005-11-04 08:45:49 -08001805
Michael Chanb6016b72005-05-26 13:03:09 -07001806 if (bp->advertising & ADVERTISED_1000baseT_Full)
1807 new_adv |= ADVERTISE_1000XFULL;
1808
1809 new_adv |= bnx2_phy_get_pause_adv(bp);
1810
Michael Chanca58c3a2007-05-03 13:22:52 -07001811 bnx2_read_phy(bp, bp->mii_adv, &adv);
1812 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07001813
1814 bp->serdes_an_pending = 0;
1815 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1816 /* Force a link down visible on the other side */
1817 if (bp->link_up) {
Michael Chanca58c3a2007-05-03 13:22:52 -07001818 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
Michael Chan80be4432006-11-19 14:07:28 -08001819 spin_unlock_bh(&bp->phy_lock);
1820 msleep(20);
1821 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07001822 }
1823
Michael Chanca58c3a2007-05-03 13:22:52 -07001824 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1825 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
Michael Chanb6016b72005-05-26 13:03:09 -07001826 BMCR_ANENABLE);
Michael Chanf8dd0642006-11-19 14:08:29 -08001827 /* Speed up link-up time when the link partner
1828 * does not autonegotiate which is very common
1829 * in blade servers. Some blade servers use
1830 * IPMI for kerboard input and it's important
1831 * to minimize link disruptions. Autoneg. involves
1832 * exchanging base pages plus 3 next pages and
1833 * normally completes in about 120 msec.
1834 */
Michael Chan40105c02008-11-12 16:02:45 -08001835 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
Michael Chanf8dd0642006-11-19 14:08:29 -08001836 bp->serdes_an_pending = 1;
1837 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chan605a9e22007-05-03 13:23:13 -07001838 } else {
1839 bnx2_resolve_flow_ctrl(bp);
1840 bnx2_set_mac_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001841 }
1842
1843 return 0;
1844}
1845
1846#define ETHTOOL_ALL_FIBRE_SPEED \
Michael Chan583c28e2008-01-21 19:51:35 -08001847 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
Michael Chandeaf3912007-07-07 22:48:00 -07001848 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1849 (ADVERTISED_1000baseT_Full)
Michael Chanb6016b72005-05-26 13:03:09 -07001850
1851#define ETHTOOL_ALL_COPPER_SPEED \
1852 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1853 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1854 ADVERTISED_1000baseT_Full)
1855
1856#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1857 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001858
Michael Chanb6016b72005-05-26 13:03:09 -07001859#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1860
Michael Chandeaf3912007-07-07 22:48:00 -07001861static void
Michael Chan0d8a6572007-07-07 22:49:43 -07001862bnx2_set_default_remote_link(struct bnx2 *bp)
1863{
1864 u32 link;
1865
1866 if (bp->phy_port == PORT_TP)
Michael Chan2726d6e2008-01-29 21:35:05 -08001867 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
Michael Chan0d8a6572007-07-07 22:49:43 -07001868 else
Michael Chan2726d6e2008-01-29 21:35:05 -08001869 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
Michael Chan0d8a6572007-07-07 22:49:43 -07001870
1871 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1872 bp->req_line_speed = 0;
1873 bp->autoneg |= AUTONEG_SPEED;
1874 bp->advertising = ADVERTISED_Autoneg;
1875 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1876 bp->advertising |= ADVERTISED_10baseT_Half;
1877 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1878 bp->advertising |= ADVERTISED_10baseT_Full;
1879 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1880 bp->advertising |= ADVERTISED_100baseT_Half;
1881 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1882 bp->advertising |= ADVERTISED_100baseT_Full;
1883 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1884 bp->advertising |= ADVERTISED_1000baseT_Full;
1885 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1886 bp->advertising |= ADVERTISED_2500baseX_Full;
1887 } else {
1888 bp->autoneg = 0;
1889 bp->advertising = 0;
1890 bp->req_duplex = DUPLEX_FULL;
1891 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1892 bp->req_line_speed = SPEED_10;
1893 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1894 bp->req_duplex = DUPLEX_HALF;
1895 }
1896 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1897 bp->req_line_speed = SPEED_100;
1898 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1899 bp->req_duplex = DUPLEX_HALF;
1900 }
1901 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1902 bp->req_line_speed = SPEED_1000;
1903 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1904 bp->req_line_speed = SPEED_2500;
1905 }
1906}
1907
1908static void
Michael Chandeaf3912007-07-07 22:48:00 -07001909bnx2_set_default_link(struct bnx2 *bp)
1910{
Harvey Harrisonab598592008-05-01 02:47:38 -07001911 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1912 bnx2_set_default_remote_link(bp);
1913 return;
1914 }
Michael Chan0d8a6572007-07-07 22:49:43 -07001915
Michael Chandeaf3912007-07-07 22:48:00 -07001916 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1917 bp->req_line_speed = 0;
Michael Chan583c28e2008-01-21 19:51:35 -08001918 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chandeaf3912007-07-07 22:48:00 -07001919 u32 reg;
1920
1921 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1922
Michael Chan2726d6e2008-01-29 21:35:05 -08001923 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
Michael Chandeaf3912007-07-07 22:48:00 -07001924 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1925 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1926 bp->autoneg = 0;
1927 bp->req_line_speed = bp->line_speed = SPEED_1000;
1928 bp->req_duplex = DUPLEX_FULL;
1929 }
1930 } else
1931 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1932}
1933
Michael Chan0d8a6572007-07-07 22:49:43 -07001934static void
Michael Chandf149d72007-07-07 22:51:36 -07001935bnx2_send_heart_beat(struct bnx2 *bp)
1936{
1937 u32 msg;
1938 u32 addr;
1939
1940 spin_lock(&bp->indirect_lock);
1941 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1942 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
Michael Chane503e062012-12-06 10:33:08 +00001943 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1944 BNX2_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
Michael Chandf149d72007-07-07 22:51:36 -07001945 spin_unlock(&bp->indirect_lock);
1946}
1947
1948static void
Michael Chan0d8a6572007-07-07 22:49:43 -07001949bnx2_remote_phy_event(struct bnx2 *bp)
1950{
1951 u32 msg;
1952 u8 link_up = bp->link_up;
1953 u8 old_port;
1954
Michael Chan2726d6e2008-01-29 21:35:05 -08001955 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
Michael Chan0d8a6572007-07-07 22:49:43 -07001956
Michael Chandf149d72007-07-07 22:51:36 -07001957 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1958 bnx2_send_heart_beat(bp);
1959
1960 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1961
Michael Chan0d8a6572007-07-07 22:49:43 -07001962 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1963 bp->link_up = 0;
1964 else {
1965 u32 speed;
1966
1967 bp->link_up = 1;
1968 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1969 bp->duplex = DUPLEX_FULL;
1970 switch (speed) {
1971 case BNX2_LINK_STATUS_10HALF:
1972 bp->duplex = DUPLEX_HALF;
Michael Chan7947c9c2012-06-27 15:08:23 +00001973 /* fall through */
Michael Chan0d8a6572007-07-07 22:49:43 -07001974 case BNX2_LINK_STATUS_10FULL:
1975 bp->line_speed = SPEED_10;
1976 break;
1977 case BNX2_LINK_STATUS_100HALF:
1978 bp->duplex = DUPLEX_HALF;
Michael Chan7947c9c2012-06-27 15:08:23 +00001979 /* fall through */
Michael Chan0d8a6572007-07-07 22:49:43 -07001980 case BNX2_LINK_STATUS_100BASE_T4:
1981 case BNX2_LINK_STATUS_100FULL:
1982 bp->line_speed = SPEED_100;
1983 break;
1984 case BNX2_LINK_STATUS_1000HALF:
1985 bp->duplex = DUPLEX_HALF;
Michael Chan7947c9c2012-06-27 15:08:23 +00001986 /* fall through */
Michael Chan0d8a6572007-07-07 22:49:43 -07001987 case BNX2_LINK_STATUS_1000FULL:
1988 bp->line_speed = SPEED_1000;
1989 break;
1990 case BNX2_LINK_STATUS_2500HALF:
1991 bp->duplex = DUPLEX_HALF;
Michael Chan7947c9c2012-06-27 15:08:23 +00001992 /* fall through */
Michael Chan0d8a6572007-07-07 22:49:43 -07001993 case BNX2_LINK_STATUS_2500FULL:
1994 bp->line_speed = SPEED_2500;
1995 break;
1996 default:
1997 bp->line_speed = 0;
1998 break;
1999 }
2000
Michael Chan0d8a6572007-07-07 22:49:43 -07002001 bp->flow_ctrl = 0;
2002 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2003 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2004 if (bp->duplex == DUPLEX_FULL)
2005 bp->flow_ctrl = bp->req_flow_ctrl;
2006 } else {
2007 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2008 bp->flow_ctrl |= FLOW_CTRL_TX;
2009 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2010 bp->flow_ctrl |= FLOW_CTRL_RX;
2011 }
2012
2013 old_port = bp->phy_port;
2014 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2015 bp->phy_port = PORT_FIBRE;
2016 else
2017 bp->phy_port = PORT_TP;
2018
2019 if (old_port != bp->phy_port)
2020 bnx2_set_default_link(bp);
2021
Michael Chan0d8a6572007-07-07 22:49:43 -07002022 }
2023 if (bp->link_up != link_up)
2024 bnx2_report_link(bp);
2025
2026 bnx2_set_mac_link(bp);
2027}
2028
2029static int
2030bnx2_set_remote_link(struct bnx2 *bp)
2031{
2032 u32 evt_code;
2033
Michael Chan2726d6e2008-01-29 21:35:05 -08002034 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
Michael Chan0d8a6572007-07-07 22:49:43 -07002035 switch (evt_code) {
2036 case BNX2_FW_EVT_CODE_LINK_EVENT:
2037 bnx2_remote_phy_event(bp);
2038 break;
2039 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2040 default:
Michael Chandf149d72007-07-07 22:51:36 -07002041 bnx2_send_heart_beat(bp);
Michael Chan0d8a6572007-07-07 22:49:43 -07002042 break;
2043 }
2044 return 0;
2045}
2046
Michael Chanb6016b72005-05-26 13:03:09 -07002047static int
2048bnx2_setup_copper_phy(struct bnx2 *bp)
Harvey Harrison52d07b12009-01-19 17:27:06 -08002049__releases(&bp->phy_lock)
2050__acquires(&bp->phy_lock)
Michael Chanb6016b72005-05-26 13:03:09 -07002051{
2052 u32 bmcr;
2053 u32 new_bmcr;
2054
Michael Chanca58c3a2007-05-03 13:22:52 -07002055 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07002056
2057 if (bp->autoneg & AUTONEG_SPEED) {
2058 u32 adv_reg, adv1000_reg;
Matt Carlson37f07022011-11-17 14:30:55 +00002059 u32 new_adv = 0;
2060 u32 new_adv1000 = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07002061
Michael Chanca58c3a2007-05-03 13:22:52 -07002062 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
Michael Chanb6016b72005-05-26 13:03:09 -07002063 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2064 ADVERTISE_PAUSE_ASYM);
2065
2066 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2067 adv1000_reg &= PHY_ALL_1000_SPEED;
2068
Matt Carlson37f07022011-11-17 14:30:55 +00002069 new_adv = ethtool_adv_to_mii_adv_t(bp->advertising);
2070 new_adv |= ADVERTISE_CSMA;
2071 new_adv |= bnx2_phy_get_pause_adv(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07002072
Matt Carlson37f07022011-11-17 14:30:55 +00002073 new_adv1000 |= ethtool_adv_to_mii_ctrl1000_t(bp->advertising);
Matt Carlson28011cf2011-11-16 18:36:59 -05002074
Matt Carlson37f07022011-11-17 14:30:55 +00002075 if ((adv1000_reg != new_adv1000) ||
2076 (adv_reg != new_adv) ||
Michael Chanb6016b72005-05-26 13:03:09 -07002077 ((bmcr & BMCR_ANENABLE) == 0)) {
2078
Matt Carlson37f07022011-11-17 14:30:55 +00002079 bnx2_write_phy(bp, bp->mii_adv, new_adv);
2080 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000);
Michael Chanca58c3a2007-05-03 13:22:52 -07002081 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
Michael Chanb6016b72005-05-26 13:03:09 -07002082 BMCR_ANENABLE);
2083 }
2084 else if (bp->link_up) {
2085 /* Flow ctrl may have changed from auto to forced */
2086 /* or vice-versa. */
2087
2088 bnx2_resolve_flow_ctrl(bp);
2089 bnx2_set_mac_link(bp);
2090 }
2091 return 0;
2092 }
2093
2094 new_bmcr = 0;
2095 if (bp->req_line_speed == SPEED_100) {
2096 new_bmcr |= BMCR_SPEED100;
2097 }
2098 if (bp->req_duplex == DUPLEX_FULL) {
2099 new_bmcr |= BMCR_FULLDPLX;
2100 }
2101 if (new_bmcr != bmcr) {
2102 u32 bmsr;
Michael Chanb6016b72005-05-26 13:03:09 -07002103
Michael Chanca58c3a2007-05-03 13:22:52 -07002104 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2105 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04002106
Michael Chanb6016b72005-05-26 13:03:09 -07002107 if (bmsr & BMSR_LSTATUS) {
2108 /* Force link down */
Michael Chanca58c3a2007-05-03 13:22:52 -07002109 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
Michael Chana16dda02006-11-19 14:08:56 -08002110 spin_unlock_bh(&bp->phy_lock);
2111 msleep(50);
2112 spin_lock_bh(&bp->phy_lock);
2113
Michael Chanca58c3a2007-05-03 13:22:52 -07002114 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2115 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
Michael Chanb6016b72005-05-26 13:03:09 -07002116 }
2117
Michael Chanca58c3a2007-05-03 13:22:52 -07002118 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07002119
2120 /* Normally, the new speed is setup after the link has
2121 * gone down and up again. In some cases, link will not go
2122 * down so we need to set up the new speed here.
2123 */
2124 if (bmsr & BMSR_LSTATUS) {
2125 bp->line_speed = bp->req_line_speed;
2126 bp->duplex = bp->req_duplex;
2127 bnx2_resolve_flow_ctrl(bp);
2128 bnx2_set_mac_link(bp);
2129 }
Michael Chan27a005b2007-05-03 13:23:41 -07002130 } else {
2131 bnx2_resolve_flow_ctrl(bp);
2132 bnx2_set_mac_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07002133 }
2134 return 0;
2135}
2136
2137static int
Michael Chan0d8a6572007-07-07 22:49:43 -07002138bnx2_setup_phy(struct bnx2 *bp, u8 port)
Harvey Harrison52d07b12009-01-19 17:27:06 -08002139__releases(&bp->phy_lock)
2140__acquires(&bp->phy_lock)
Michael Chanb6016b72005-05-26 13:03:09 -07002141{
2142 if (bp->loopback == MAC_LOOPBACK)
2143 return 0;
2144
Michael Chan583c28e2008-01-21 19:51:35 -08002145 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Eric Dumazet807540b2010-09-23 05:40:09 +00002146 return bnx2_setup_serdes_phy(bp, port);
Michael Chanb6016b72005-05-26 13:03:09 -07002147 }
2148 else {
Eric Dumazet807540b2010-09-23 05:40:09 +00002149 return bnx2_setup_copper_phy(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07002150 }
2151}
2152
2153static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002154bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
Michael Chan27a005b2007-05-03 13:23:41 -07002155{
2156 u32 val;
2157
2158 bp->mii_bmcr = MII_BMCR + 0x10;
2159 bp->mii_bmsr = MII_BMSR + 0x10;
2160 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2161 bp->mii_adv = MII_ADVERTISE + 0x10;
2162 bp->mii_lpa = MII_LPA + 0x10;
2163 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2164
2165 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2166 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2167
2168 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
Michael Chan9a120bc2008-05-16 22:17:45 -07002169 if (reset_phy)
2170 bnx2_reset_phy(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07002171
2172 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2173
2174 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2175 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2176 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2177 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2178
2179 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2180 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
Michael Chan583c28e2008-01-21 19:51:35 -08002181 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
Michael Chan27a005b2007-05-03 13:23:41 -07002182 val |= BCM5708S_UP1_2G5;
2183 else
2184 val &= ~BCM5708S_UP1_2G5;
2185 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2186
2187 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2188 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2189 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2190 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2191
2192 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2193
2194 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2195 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2196 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2197
2198 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2199
2200 return 0;
2201}
2202
2203static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002204bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
Michael Chan5b0c76a2005-11-04 08:45:49 -08002205{
2206 u32 val;
2207
Michael Chan9a120bc2008-05-16 22:17:45 -07002208 if (reset_phy)
2209 bnx2_reset_phy(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07002210
2211 bp->mii_up1 = BCM5708S_UP1;
2212
Michael Chan5b0c76a2005-11-04 08:45:49 -08002213 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2214 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2215 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2216
2217 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2218 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2219 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2220
2221 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2222 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2223 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2224
Michael Chan583c28e2008-01-21 19:51:35 -08002225 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08002226 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2227 val |= BCM5708S_UP1_2G5;
2228 bnx2_write_phy(bp, BCM5708S_UP1, val);
2229 }
2230
Michael Chan4ce45e02012-12-06 10:33:10 +00002231 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||
2232 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||
2233 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1)) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08002234 /* increase tx signal amplitude */
2235 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2236 BCM5708S_BLK_ADDR_TX_MISC);
2237 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2238 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2239 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2240 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2241 }
2242
Michael Chan2726d6e2008-01-29 21:35:05 -08002243 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
Michael Chan5b0c76a2005-11-04 08:45:49 -08002244 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2245
2246 if (val) {
2247 u32 is_backplane;
2248
Michael Chan2726d6e2008-01-29 21:35:05 -08002249 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
Michael Chan5b0c76a2005-11-04 08:45:49 -08002250 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2251 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2252 BCM5708S_BLK_ADDR_TX_MISC);
2253 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2254 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2255 BCM5708S_BLK_ADDR_DIG);
2256 }
2257 }
2258 return 0;
2259}
2260
2261static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002262bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
Michael Chanb6016b72005-05-26 13:03:09 -07002263{
Michael Chan9a120bc2008-05-16 22:17:45 -07002264 if (reset_phy)
2265 bnx2_reset_phy(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07002266
Michael Chan583c28e2008-01-21 19:51:35 -08002267 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chanb6016b72005-05-26 13:03:09 -07002268
Michael Chan4ce45e02012-12-06 10:33:10 +00002269 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
Michael Chane503e062012-12-06 10:33:08 +00002270 BNX2_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
Michael Chanb6016b72005-05-26 13:03:09 -07002271
2272 if (bp->dev->mtu > 1500) {
2273 u32 val;
2274
2275 /* Set extended packet length bit */
2276 bnx2_write_phy(bp, 0x18, 0x7);
2277 bnx2_read_phy(bp, 0x18, &val);
2278 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2279
2280 bnx2_write_phy(bp, 0x1c, 0x6c00);
2281 bnx2_read_phy(bp, 0x1c, &val);
2282 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2283 }
2284 else {
2285 u32 val;
2286
2287 bnx2_write_phy(bp, 0x18, 0x7);
2288 bnx2_read_phy(bp, 0x18, &val);
2289 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2290
2291 bnx2_write_phy(bp, 0x1c, 0x6c00);
2292 bnx2_read_phy(bp, 0x1c, &val);
2293 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2294 }
2295
2296 return 0;
2297}
2298
2299static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002300bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
Michael Chanb6016b72005-05-26 13:03:09 -07002301{
Michael Chan5b0c76a2005-11-04 08:45:49 -08002302 u32 val;
2303
Michael Chan9a120bc2008-05-16 22:17:45 -07002304 if (reset_phy)
2305 bnx2_reset_phy(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07002306
Michael Chan583c28e2008-01-21 19:51:35 -08002307 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
Michael Chanb6016b72005-05-26 13:03:09 -07002308 bnx2_write_phy(bp, 0x18, 0x0c00);
2309 bnx2_write_phy(bp, 0x17, 0x000a);
2310 bnx2_write_phy(bp, 0x15, 0x310b);
2311 bnx2_write_phy(bp, 0x17, 0x201f);
2312 bnx2_write_phy(bp, 0x15, 0x9506);
2313 bnx2_write_phy(bp, 0x17, 0x401f);
2314 bnx2_write_phy(bp, 0x15, 0x14e2);
2315 bnx2_write_phy(bp, 0x18, 0x0400);
2316 }
2317
Michael Chan583c28e2008-01-21 19:51:35 -08002318 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
Michael Chanb659f442007-02-02 00:46:35 -08002319 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2320 MII_BNX2_DSP_EXPAND_REG | 0x8);
2321 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2322 val &= ~(1 << 8);
2323 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2324 }
2325
Michael Chanb6016b72005-05-26 13:03:09 -07002326 if (bp->dev->mtu > 1500) {
Michael Chanb6016b72005-05-26 13:03:09 -07002327 /* Set extended packet length bit */
2328 bnx2_write_phy(bp, 0x18, 0x7);
2329 bnx2_read_phy(bp, 0x18, &val);
2330 bnx2_write_phy(bp, 0x18, val | 0x4000);
2331
2332 bnx2_read_phy(bp, 0x10, &val);
2333 bnx2_write_phy(bp, 0x10, val | 0x1);
2334 }
2335 else {
Michael Chanb6016b72005-05-26 13:03:09 -07002336 bnx2_write_phy(bp, 0x18, 0x7);
2337 bnx2_read_phy(bp, 0x18, &val);
2338 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2339
2340 bnx2_read_phy(bp, 0x10, &val);
2341 bnx2_write_phy(bp, 0x10, val & ~0x1);
2342 }
2343
Michael Chan5b0c76a2005-11-04 08:45:49 -08002344 /* ethernet@wirespeed */
2345 bnx2_write_phy(bp, 0x18, 0x7007);
2346 bnx2_read_phy(bp, 0x18, &val);
2347 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
Michael Chanb6016b72005-05-26 13:03:09 -07002348 return 0;
2349}
2350
2351
2352static int
Michael Chan9a120bc2008-05-16 22:17:45 -07002353bnx2_init_phy(struct bnx2 *bp, int reset_phy)
Harvey Harrison52d07b12009-01-19 17:27:06 -08002354__releases(&bp->phy_lock)
2355__acquires(&bp->phy_lock)
Michael Chanb6016b72005-05-26 13:03:09 -07002356{
2357 u32 val;
2358 int rc = 0;
2359
Michael Chan583c28e2008-01-21 19:51:35 -08002360 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2361 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
Michael Chanb6016b72005-05-26 13:03:09 -07002362
Michael Chanca58c3a2007-05-03 13:22:52 -07002363 bp->mii_bmcr = MII_BMCR;
2364 bp->mii_bmsr = MII_BMSR;
Michael Chan27a005b2007-05-03 13:23:41 -07002365 bp->mii_bmsr1 = MII_BMSR;
Michael Chanca58c3a2007-05-03 13:22:52 -07002366 bp->mii_adv = MII_ADVERTISE;
2367 bp->mii_lpa = MII_LPA;
2368
Michael Chane503e062012-12-06 10:33:08 +00002369 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
Michael Chanb6016b72005-05-26 13:03:09 -07002370
Michael Chan583c28e2008-01-21 19:51:35 -08002371 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07002372 goto setup_phy;
2373
Michael Chanb6016b72005-05-26 13:03:09 -07002374 bnx2_read_phy(bp, MII_PHYSID1, &val);
2375 bp->phy_id = val << 16;
2376 bnx2_read_phy(bp, MII_PHYSID2, &val);
2377 bp->phy_id |= val & 0xffff;
2378
Michael Chan583c28e2008-01-21 19:51:35 -08002379 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan4ce45e02012-12-06 10:33:10 +00002380 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
Michael Chan9a120bc2008-05-16 22:17:45 -07002381 rc = bnx2_init_5706s_phy(bp, reset_phy);
Michael Chan4ce45e02012-12-06 10:33:10 +00002382 else if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
Michael Chan9a120bc2008-05-16 22:17:45 -07002383 rc = bnx2_init_5708s_phy(bp, reset_phy);
Michael Chan4ce45e02012-12-06 10:33:10 +00002384 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
Michael Chan9a120bc2008-05-16 22:17:45 -07002385 rc = bnx2_init_5709s_phy(bp, reset_phy);
Michael Chanb6016b72005-05-26 13:03:09 -07002386 }
2387 else {
Michael Chan9a120bc2008-05-16 22:17:45 -07002388 rc = bnx2_init_copper_phy(bp, reset_phy);
Michael Chanb6016b72005-05-26 13:03:09 -07002389 }
2390
Michael Chan0d8a6572007-07-07 22:49:43 -07002391setup_phy:
2392 if (!rc)
2393 rc = bnx2_setup_phy(bp, bp->phy_port);
Michael Chanb6016b72005-05-26 13:03:09 -07002394
2395 return rc;
2396}
2397
2398static int
2399bnx2_set_mac_loopback(struct bnx2 *bp)
2400{
2401 u32 mac_mode;
2402
Michael Chane503e062012-12-06 10:33:08 +00002403 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
Michael Chanb6016b72005-05-26 13:03:09 -07002404 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2405 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
Michael Chane503e062012-12-06 10:33:08 +00002406 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
Michael Chanb6016b72005-05-26 13:03:09 -07002407 bp->link_up = 1;
2408 return 0;
2409}
2410
Michael Chanbc5a0692006-01-23 16:13:22 -08002411static int bnx2_test_link(struct bnx2 *);
2412
2413static int
2414bnx2_set_phy_loopback(struct bnx2 *bp)
2415{
2416 u32 mac_mode;
2417 int rc, i;
2418
2419 spin_lock_bh(&bp->phy_lock);
Michael Chanca58c3a2007-05-03 13:22:52 -07002420 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
Michael Chanbc5a0692006-01-23 16:13:22 -08002421 BMCR_SPEED1000);
2422 spin_unlock_bh(&bp->phy_lock);
2423 if (rc)
2424 return rc;
2425
2426 for (i = 0; i < 10; i++) {
2427 if (bnx2_test_link(bp) == 0)
2428 break;
Michael Chan80be4432006-11-19 14:07:28 -08002429 msleep(100);
Michael Chanbc5a0692006-01-23 16:13:22 -08002430 }
2431
Michael Chane503e062012-12-06 10:33:08 +00002432 mac_mode = BNX2_RD(bp, BNX2_EMAC_MODE);
Michael Chanbc5a0692006-01-23 16:13:22 -08002433 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2434 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
Michael Chan59b47d82006-11-19 14:10:45 -08002435 BNX2_EMAC_MODE_25G_MODE);
Michael Chanbc5a0692006-01-23 16:13:22 -08002436
2437 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
Michael Chane503e062012-12-06 10:33:08 +00002438 BNX2_WR(bp, BNX2_EMAC_MODE, mac_mode);
Michael Chanbc5a0692006-01-23 16:13:22 -08002439 bp->link_up = 1;
2440 return 0;
2441}
2442
Jeffrey Huangecdbf6e2011-07-13 17:24:21 +00002443static void
2444bnx2_dump_mcp_state(struct bnx2 *bp)
2445{
2446 struct net_device *dev = bp->dev;
2447 u32 mcp_p0, mcp_p1;
2448
2449 netdev_err(dev, "<--- start MCP states dump --->\n");
Michael Chan4ce45e02012-12-06 10:33:10 +00002450 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
Jeffrey Huangecdbf6e2011-07-13 17:24:21 +00002451 mcp_p0 = BNX2_MCP_STATE_P0;
2452 mcp_p1 = BNX2_MCP_STATE_P1;
2453 } else {
2454 mcp_p0 = BNX2_MCP_STATE_P0_5708;
2455 mcp_p1 = BNX2_MCP_STATE_P1_5708;
2456 }
2457 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
2458 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
2459 netdev_err(dev, "DEBUG: MCP mode[%08x] state[%08x] evt_mask[%08x]\n",
2460 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_MODE),
2461 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_STATE),
2462 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_EVENT_MASK));
2463 netdev_err(dev, "DEBUG: pc[%08x] pc[%08x] instr[%08x]\n",
2464 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2465 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_PROGRAM_COUNTER),
2466 bnx2_reg_rd_ind(bp, BNX2_MCP_CPU_INSTRUCTION));
2467 netdev_err(dev, "DEBUG: shmem states:\n");
2468 netdev_err(dev, "DEBUG: drv_mb[%08x] fw_mb[%08x] link_status[%08x]",
2469 bnx2_shmem_rd(bp, BNX2_DRV_MB),
2470 bnx2_shmem_rd(bp, BNX2_FW_MB),
2471 bnx2_shmem_rd(bp, BNX2_LINK_STATUS));
2472 pr_cont(" drv_pulse_mb[%08x]\n", bnx2_shmem_rd(bp, BNX2_DRV_PULSE_MB));
2473 netdev_err(dev, "DEBUG: dev_info_signature[%08x] reset_type[%08x]",
2474 bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE),
2475 bnx2_shmem_rd(bp, BNX2_BC_STATE_RESET_TYPE));
2476 pr_cont(" condition[%08x]\n",
2477 bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION));
Michael Chan13e63512012-06-16 15:45:42 +00002478 DP_SHMEM_LINE(bp, BNX2_BC_RESET_TYPE);
Jeffrey Huangecdbf6e2011-07-13 17:24:21 +00002479 DP_SHMEM_LINE(bp, 0x3cc);
2480 DP_SHMEM_LINE(bp, 0x3dc);
2481 DP_SHMEM_LINE(bp, 0x3ec);
2482 netdev_err(dev, "DEBUG: 0x3fc[%08x]\n", bnx2_shmem_rd(bp, 0x3fc));
2483 netdev_err(dev, "<--- end MCP states dump --->\n");
2484}
2485
Michael Chanb6016b72005-05-26 13:03:09 -07002486static int
Michael Chana2f13892008-07-14 22:38:23 -07002487bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
Michael Chanb6016b72005-05-26 13:03:09 -07002488{
2489 int i;
2490 u32 val;
2491
Michael Chanb6016b72005-05-26 13:03:09 -07002492 bp->fw_wr_seq++;
2493 msg_data |= bp->fw_wr_seq;
2494
Michael Chan2726d6e2008-01-29 21:35:05 -08002495 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
Michael Chanb6016b72005-05-26 13:03:09 -07002496
Michael Chana2f13892008-07-14 22:38:23 -07002497 if (!ack)
2498 return 0;
2499
Michael Chanb6016b72005-05-26 13:03:09 -07002500 /* wait for an acknowledgement. */
Michael Chan40105c02008-11-12 16:02:45 -08002501 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
Michael Chanb090ae22006-01-23 16:07:10 -08002502 msleep(10);
Michael Chanb6016b72005-05-26 13:03:09 -07002503
Michael Chan2726d6e2008-01-29 21:35:05 -08002504 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
Michael Chanb6016b72005-05-26 13:03:09 -07002505
2506 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2507 break;
2508 }
Michael Chanb090ae22006-01-23 16:07:10 -08002509 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2510 return 0;
Michael Chanb6016b72005-05-26 13:03:09 -07002511
2512 /* If we timed out, inform the firmware that this is the case. */
Michael Chanb090ae22006-01-23 16:07:10 -08002513 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
Michael Chanb6016b72005-05-26 13:03:09 -07002514 msg_data &= ~BNX2_DRV_MSG_CODE;
2515 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2516
Michael Chan2726d6e2008-01-29 21:35:05 -08002517 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
Jeffrey Huangecdbf6e2011-07-13 17:24:21 +00002518 if (!silent) {
2519 pr_err("fw sync timeout, reset code = %x\n", msg_data);
2520 bnx2_dump_mcp_state(bp);
2521 }
Michael Chanb6016b72005-05-26 13:03:09 -07002522
Michael Chanb6016b72005-05-26 13:03:09 -07002523 return -EBUSY;
2524 }
2525
Michael Chanb090ae22006-01-23 16:07:10 -08002526 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2527 return -EIO;
2528
Michael Chanb6016b72005-05-26 13:03:09 -07002529 return 0;
2530}
2531
Michael Chan59b47d82006-11-19 14:10:45 -08002532static int
2533bnx2_init_5709_context(struct bnx2 *bp)
2534{
2535 int i, ret = 0;
2536 u32 val;
2537
2538 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
Michael Chan2bc40782012-12-06 10:33:09 +00002539 val |= (BNX2_PAGE_BITS - 8) << 16;
Michael Chane503e062012-12-06 10:33:08 +00002540 BNX2_WR(bp, BNX2_CTX_COMMAND, val);
Michael Chan641bdcd2007-06-04 21:22:24 -07002541 for (i = 0; i < 10; i++) {
Michael Chane503e062012-12-06 10:33:08 +00002542 val = BNX2_RD(bp, BNX2_CTX_COMMAND);
Michael Chan641bdcd2007-06-04 21:22:24 -07002543 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2544 break;
2545 udelay(2);
2546 }
2547 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2548 return -EBUSY;
2549
Michael Chan59b47d82006-11-19 14:10:45 -08002550 for (i = 0; i < bp->ctx_pages; i++) {
2551 int j;
2552
Michael Chan352f7682008-05-02 16:57:26 -07002553 if (bp->ctx_blk[i])
Michael Chan2bc40782012-12-06 10:33:09 +00002554 memset(bp->ctx_blk[i], 0, BNX2_PAGE_SIZE);
Michael Chan352f7682008-05-02 16:57:26 -07002555 else
2556 return -ENOMEM;
2557
Michael Chane503e062012-12-06 10:33:08 +00002558 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2559 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2560 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2561 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2562 (u64) bp->ctx_blk_mapping[i] >> 32);
2563 BNX2_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2564 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
Michael Chan59b47d82006-11-19 14:10:45 -08002565 for (j = 0; j < 10; j++) {
2566
Michael Chane503e062012-12-06 10:33:08 +00002567 val = BNX2_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
Michael Chan59b47d82006-11-19 14:10:45 -08002568 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2569 break;
2570 udelay(5);
2571 }
2572 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2573 ret = -EBUSY;
2574 break;
2575 }
2576 }
2577 return ret;
2578}
2579
Michael Chanb6016b72005-05-26 13:03:09 -07002580static void
2581bnx2_init_context(struct bnx2 *bp)
2582{
2583 u32 vcid;
2584
2585 vcid = 96;
2586 while (vcid) {
2587 u32 vcid_addr, pcid_addr, offset;
Michael Chan7947b202007-06-04 21:17:10 -07002588 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07002589
2590 vcid--;
2591
Michael Chan4ce45e02012-12-06 10:33:10 +00002592 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
Michael Chanb6016b72005-05-26 13:03:09 -07002593 u32 new_vcid;
2594
2595 vcid_addr = GET_PCID_ADDR(vcid);
2596 if (vcid & 0x8) {
2597 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2598 }
2599 else {
2600 new_vcid = vcid;
2601 }
2602 pcid_addr = GET_PCID_ADDR(new_vcid);
2603 }
2604 else {
2605 vcid_addr = GET_CID_ADDR(vcid);
2606 pcid_addr = vcid_addr;
2607 }
2608
Michael Chan7947b202007-06-04 21:17:10 -07002609 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2610 vcid_addr += (i << PHY_CTX_SHIFT);
2611 pcid_addr += (i << PHY_CTX_SHIFT);
Michael Chanb6016b72005-05-26 13:03:09 -07002612
Michael Chane503e062012-12-06 10:33:08 +00002613 BNX2_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2614 BNX2_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
Michael Chan7947b202007-06-04 21:17:10 -07002615
2616 /* Zero out the context. */
2617 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
Michael Chan62a83132008-01-29 21:35:40 -08002618 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07002619 }
Michael Chanb6016b72005-05-26 13:03:09 -07002620 }
2621}
2622
2623static int
2624bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2625{
2626 u16 *good_mbuf;
2627 u32 good_mbuf_cnt;
2628 u32 val;
2629
2630 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
Joe Perchese404dec2012-01-29 12:56:23 +00002631 if (good_mbuf == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -07002632 return -ENOMEM;
Michael Chanb6016b72005-05-26 13:03:09 -07002633
Michael Chane503e062012-12-06 10:33:08 +00002634 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
Michael Chanb6016b72005-05-26 13:03:09 -07002635 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2636
2637 good_mbuf_cnt = 0;
2638
2639 /* Allocate a bunch of mbufs and save the good ones in an array. */
Michael Chan2726d6e2008-01-29 21:35:05 -08002640 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
Michael Chanb6016b72005-05-26 13:03:09 -07002641 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
Michael Chan2726d6e2008-01-29 21:35:05 -08002642 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2643 BNX2_RBUF_COMMAND_ALLOC_REQ);
Michael Chanb6016b72005-05-26 13:03:09 -07002644
Michael Chan2726d6e2008-01-29 21:35:05 -08002645 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
Michael Chanb6016b72005-05-26 13:03:09 -07002646
2647 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2648
2649 /* The addresses with Bit 9 set are bad memory blocks. */
2650 if (!(val & (1 << 9))) {
2651 good_mbuf[good_mbuf_cnt] = (u16) val;
2652 good_mbuf_cnt++;
2653 }
2654
Michael Chan2726d6e2008-01-29 21:35:05 -08002655 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
Michael Chanb6016b72005-05-26 13:03:09 -07002656 }
2657
2658 /* Free the good ones back to the mbuf pool thus discarding
2659 * all the bad ones. */
2660 while (good_mbuf_cnt) {
2661 good_mbuf_cnt--;
2662
2663 val = good_mbuf[good_mbuf_cnt];
2664 val = (val << 9) | val | 1;
2665
Michael Chan2726d6e2008-01-29 21:35:05 -08002666 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
Michael Chanb6016b72005-05-26 13:03:09 -07002667 }
2668 kfree(good_mbuf);
2669 return 0;
2670}
2671
2672static void
Benjamin Li5fcaed02008-07-14 22:39:52 -07002673bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
Michael Chanb6016b72005-05-26 13:03:09 -07002674{
2675 u32 val;
Michael Chanb6016b72005-05-26 13:03:09 -07002676
2677 val = (mac_addr[0] << 8) | mac_addr[1];
2678
Michael Chane503e062012-12-06 10:33:08 +00002679 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
Michael Chanb6016b72005-05-26 13:03:09 -07002680
Jeff Garzik6aa20a22006-09-13 13:24:59 -04002681 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
Michael Chanb6016b72005-05-26 13:03:09 -07002682 (mac_addr[4] << 8) | mac_addr[5];
2683
Michael Chane503e062012-12-06 10:33:08 +00002684 BNX2_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
Michael Chanb6016b72005-05-26 13:03:09 -07002685}
2686
2687static inline int
Stanislaw Gruszkaa2df00a2010-07-15 22:55:40 +00002688bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
Michael Chan47bf4242007-12-12 11:19:12 -08002689{
2690 dma_addr_t mapping;
Michael Chan2bc40782012-12-06 10:33:09 +00002691 struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2692 struct bnx2_rx_bd *rxbd =
2693 &rxr->rx_pg_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)];
Stanislaw Gruszkaa2df00a2010-07-15 22:55:40 +00002694 struct page *page = alloc_page(gfp);
Michael Chan47bf4242007-12-12 11:19:12 -08002695
2696 if (!page)
2697 return -ENOMEM;
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00002698 mapping = dma_map_page(&bp->pdev->dev, page, 0, PAGE_SIZE,
Michael Chan47bf4242007-12-12 11:19:12 -08002699 PCI_DMA_FROMDEVICE);
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00002700 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
Benjamin Li3d16af82008-10-09 12:26:41 -07002701 __free_page(page);
2702 return -EIO;
2703 }
2704
Michael Chan47bf4242007-12-12 11:19:12 -08002705 rx_pg->page = page;
FUJITA Tomonori1a4ccc22010-04-01 16:56:57 +00002706 dma_unmap_addr_set(rx_pg, mapping, mapping);
Michael Chan47bf4242007-12-12 11:19:12 -08002707 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2708 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2709 return 0;
2710}
2711
2712static void
Michael Chanbb4f98a2008-06-19 16:38:19 -07002713bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
Michael Chan47bf4242007-12-12 11:19:12 -08002714{
Michael Chan2bc40782012-12-06 10:33:09 +00002715 struct bnx2_sw_pg *rx_pg = &rxr->rx_pg_ring[index];
Michael Chan47bf4242007-12-12 11:19:12 -08002716 struct page *page = rx_pg->page;
2717
2718 if (!page)
2719 return;
2720
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00002721 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(rx_pg, mapping),
2722 PAGE_SIZE, PCI_DMA_FROMDEVICE);
Michael Chan47bf4242007-12-12 11:19:12 -08002723
2724 __free_page(page);
2725 rx_pg->page = NULL;
2726}
2727
2728static inline int
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00002729bnx2_alloc_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index, gfp_t gfp)
Michael Chanb6016b72005-05-26 13:03:09 -07002730{
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00002731 u8 *data;
Michael Chan2bc40782012-12-06 10:33:09 +00002732 struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[index];
Michael Chanb6016b72005-05-26 13:03:09 -07002733 dma_addr_t mapping;
Michael Chan2bc40782012-12-06 10:33:09 +00002734 struct bnx2_rx_bd *rxbd =
2735 &rxr->rx_desc_ring[BNX2_RX_RING(index)][BNX2_RX_IDX(index)];
Michael Chanb6016b72005-05-26 13:03:09 -07002736
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00002737 data = kmalloc(bp->rx_buf_size, gfp);
2738 if (!data)
Michael Chanb6016b72005-05-26 13:03:09 -07002739 return -ENOMEM;
Michael Chanb6016b72005-05-26 13:03:09 -07002740
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00002741 mapping = dma_map_single(&bp->pdev->dev,
2742 get_l2_fhdr(data),
2743 bp->rx_buf_use_size,
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00002744 PCI_DMA_FROMDEVICE);
2745 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00002746 kfree(data);
Benjamin Li3d16af82008-10-09 12:26:41 -07002747 return -EIO;
2748 }
Michael Chanb6016b72005-05-26 13:03:09 -07002749
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00002750 rx_buf->data = data;
FUJITA Tomonori1a4ccc22010-04-01 16:56:57 +00002751 dma_unmap_addr_set(rx_buf, mapping, mapping);
Michael Chanb6016b72005-05-26 13:03:09 -07002752
2753 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2754 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2755
Michael Chanbb4f98a2008-06-19 16:38:19 -07002756 rxr->rx_prod_bseq += bp->rx_buf_use_size;
Michael Chanb6016b72005-05-26 13:03:09 -07002757
2758 return 0;
2759}
2760
Michael Chanda3e4fb2007-05-03 13:24:23 -07002761static int
Michael Chan35efa7c2007-12-20 19:56:37 -08002762bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
Michael Chanda3e4fb2007-05-03 13:24:23 -07002763{
Michael Chan43e80b82008-06-19 16:41:08 -07002764 struct status_block *sblk = bnapi->status_blk.msi;
Michael Chanda3e4fb2007-05-03 13:24:23 -07002765 u32 new_link_state, old_link_state;
2766 int is_set = 1;
2767
2768 new_link_state = sblk->status_attn_bits & event;
2769 old_link_state = sblk->status_attn_bits_ack & event;
2770 if (new_link_state != old_link_state) {
2771 if (new_link_state)
Michael Chane503e062012-12-06 10:33:08 +00002772 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
Michael Chanda3e4fb2007-05-03 13:24:23 -07002773 else
Michael Chane503e062012-12-06 10:33:08 +00002774 BNX2_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
Michael Chanda3e4fb2007-05-03 13:24:23 -07002775 } else
2776 is_set = 0;
2777
2778 return is_set;
2779}
2780
Michael Chanb6016b72005-05-26 13:03:09 -07002781static void
Michael Chan35efa7c2007-12-20 19:56:37 -08002782bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
Michael Chanb6016b72005-05-26 13:03:09 -07002783{
Michael Chan74ecc62d2008-05-02 16:56:16 -07002784 spin_lock(&bp->phy_lock);
2785
2786 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
Michael Chanb6016b72005-05-26 13:03:09 -07002787 bnx2_set_link(bp);
Michael Chan35efa7c2007-12-20 19:56:37 -08002788 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
Michael Chan0d8a6572007-07-07 22:49:43 -07002789 bnx2_set_remote_link(bp);
2790
Michael Chan74ecc62d2008-05-02 16:56:16 -07002791 spin_unlock(&bp->phy_lock);
2792
Michael Chanb6016b72005-05-26 13:03:09 -07002793}
2794
Michael Chanead72702007-12-20 19:55:39 -08002795static inline u16
Michael Chan35efa7c2007-12-20 19:56:37 -08002796bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
Michael Chanead72702007-12-20 19:55:39 -08002797{
2798 u16 cons;
2799
Michael Chan43e80b82008-06-19 16:41:08 -07002800 /* Tell compiler that status block fields can change. */
2801 barrier();
2802 cons = *bnapi->hw_tx_cons_ptr;
Michael Chan581daf72009-05-06 16:46:47 -07002803 barrier();
Michael Chan2bc40782012-12-06 10:33:09 +00002804 if (unlikely((cons & BNX2_MAX_TX_DESC_CNT) == BNX2_MAX_TX_DESC_CNT))
Michael Chanead72702007-12-20 19:55:39 -08002805 cons++;
2806 return cons;
2807}
2808
Michael Chan57851d82007-12-20 20:01:44 -08002809static int
2810bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
Michael Chanb6016b72005-05-26 13:03:09 -07002811{
Michael Chan35e90102008-06-19 16:37:42 -07002812 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
Michael Chanb6016b72005-05-26 13:03:09 -07002813 u16 hw_cons, sw_cons, sw_ring_cons;
Benjamin Li706bf242008-07-18 17:55:11 -07002814 int tx_pkt = 0, index;
Eric Dumazete9831902011-11-29 11:53:05 +00002815 unsigned int tx_bytes = 0;
Benjamin Li706bf242008-07-18 17:55:11 -07002816 struct netdev_queue *txq;
2817
2818 index = (bnapi - bp->bnx2_napi);
2819 txq = netdev_get_tx_queue(bp->dev, index);
Michael Chanb6016b72005-05-26 13:03:09 -07002820
Michael Chan35efa7c2007-12-20 19:56:37 -08002821 hw_cons = bnx2_get_hw_tx_cons(bnapi);
Michael Chan35e90102008-06-19 16:37:42 -07002822 sw_cons = txr->tx_cons;
Michael Chanb6016b72005-05-26 13:03:09 -07002823
2824 while (sw_cons != hw_cons) {
Michael Chan2bc40782012-12-06 10:33:09 +00002825 struct bnx2_sw_tx_bd *tx_buf;
Michael Chanb6016b72005-05-26 13:03:09 -07002826 struct sk_buff *skb;
2827 int i, last;
2828
Michael Chan2bc40782012-12-06 10:33:09 +00002829 sw_ring_cons = BNX2_TX_RING_IDX(sw_cons);
Michael Chanb6016b72005-05-26 13:03:09 -07002830
Michael Chan35e90102008-06-19 16:37:42 -07002831 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
Michael Chanb6016b72005-05-26 13:03:09 -07002832 skb = tx_buf->skb;
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01002833
Eric Dumazetd62fda02009-05-12 20:48:02 +00002834 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2835 prefetch(&skb->end);
2836
Michael Chanb6016b72005-05-26 13:03:09 -07002837 /* partial BD completions possible with TSO packets */
Eric Dumazetd62fda02009-05-12 20:48:02 +00002838 if (tx_buf->is_gso) {
Michael Chanb6016b72005-05-26 13:03:09 -07002839 u16 last_idx, last_ring_idx;
2840
Eric Dumazetd62fda02009-05-12 20:48:02 +00002841 last_idx = sw_cons + tx_buf->nr_frags + 1;
2842 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
Michael Chan2bc40782012-12-06 10:33:09 +00002843 if (unlikely(last_ring_idx >= BNX2_MAX_TX_DESC_CNT)) {
Michael Chanb6016b72005-05-26 13:03:09 -07002844 last_idx++;
2845 }
2846 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2847 break;
2848 }
2849 }
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01002850
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00002851 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
Alexander Duycke95524a2009-12-02 16:47:57 +00002852 skb_headlen(skb), PCI_DMA_TODEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07002853
2854 tx_buf->skb = NULL;
Eric Dumazetd62fda02009-05-12 20:48:02 +00002855 last = tx_buf->nr_frags;
Michael Chanb6016b72005-05-26 13:03:09 -07002856
2857 for (i = 0; i < last; i++) {
Michael Chan2bc40782012-12-06 10:33:09 +00002858 struct bnx2_sw_tx_bd *tx_buf;
Alexander Duycke95524a2009-12-02 16:47:57 +00002859
Michael Chan2bc40782012-12-06 10:33:09 +00002860 sw_cons = BNX2_NEXT_TX_BD(sw_cons);
2861
2862 tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(sw_cons)];
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00002863 dma_unmap_page(&bp->pdev->dev,
Michael Chan2bc40782012-12-06 10:33:09 +00002864 dma_unmap_addr(tx_buf, mapping),
Eric Dumazet9e903e02011-10-18 21:00:24 +00002865 skb_frag_size(&skb_shinfo(skb)->frags[i]),
Alexander Duycke95524a2009-12-02 16:47:57 +00002866 PCI_DMA_TODEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07002867 }
2868
Michael Chan2bc40782012-12-06 10:33:09 +00002869 sw_cons = BNX2_NEXT_TX_BD(sw_cons);
Michael Chanb6016b72005-05-26 13:03:09 -07002870
Eric Dumazete9831902011-11-29 11:53:05 +00002871 tx_bytes += skb->len;
Michael Chan745720e2006-06-29 12:37:41 -07002872 dev_kfree_skb(skb);
Michael Chan57851d82007-12-20 20:01:44 -08002873 tx_pkt++;
2874 if (tx_pkt == budget)
2875 break;
Michael Chanb6016b72005-05-26 13:03:09 -07002876
Eric Dumazetd62fda02009-05-12 20:48:02 +00002877 if (hw_cons == sw_cons)
2878 hw_cons = bnx2_get_hw_tx_cons(bnapi);
Michael Chanb6016b72005-05-26 13:03:09 -07002879 }
2880
Eric Dumazete9831902011-11-29 11:53:05 +00002881 netdev_tx_completed_queue(txq, tx_pkt, tx_bytes);
Michael Chan35e90102008-06-19 16:37:42 -07002882 txr->hw_tx_cons = hw_cons;
2883 txr->tx_cons = sw_cons;
Benjamin Li706bf242008-07-18 17:55:11 -07002884
Michael Chan2f8af122006-08-15 01:39:10 -07002885 /* Need to make the tx_cons update visible to bnx2_start_xmit()
Benjamin Li706bf242008-07-18 17:55:11 -07002886 * before checking for netif_tx_queue_stopped(). Without the
Michael Chan2f8af122006-08-15 01:39:10 -07002887 * memory barrier, there is a small possibility that bnx2_start_xmit()
2888 * will miss it and cause the queue to be stopped forever.
2889 */
2890 smp_mb();
Michael Chanb6016b72005-05-26 13:03:09 -07002891
Benjamin Li706bf242008-07-18 17:55:11 -07002892 if (unlikely(netif_tx_queue_stopped(txq)) &&
Michael Chan35e90102008-06-19 16:37:42 -07002893 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
Benjamin Li706bf242008-07-18 17:55:11 -07002894 __netif_tx_lock(txq, smp_processor_id());
2895 if ((netif_tx_queue_stopped(txq)) &&
Michael Chan35e90102008-06-19 16:37:42 -07002896 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
Benjamin Li706bf242008-07-18 17:55:11 -07002897 netif_tx_wake_queue(txq);
2898 __netif_tx_unlock(txq);
Michael Chanb6016b72005-05-26 13:03:09 -07002899 }
Benjamin Li706bf242008-07-18 17:55:11 -07002900
Michael Chan57851d82007-12-20 20:01:44 -08002901 return tx_pkt;
Michael Chanb6016b72005-05-26 13:03:09 -07002902}
2903
Michael Chan1db82f22007-12-12 11:19:35 -08002904static void
Michael Chanbb4f98a2008-06-19 16:38:19 -07002905bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
Michael Chana1f60192007-12-20 19:57:19 -08002906 struct sk_buff *skb, int count)
Michael Chan1db82f22007-12-12 11:19:35 -08002907{
Michael Chan2bc40782012-12-06 10:33:09 +00002908 struct bnx2_sw_pg *cons_rx_pg, *prod_rx_pg;
2909 struct bnx2_rx_bd *cons_bd, *prod_bd;
Michael Chan1db82f22007-12-12 11:19:35 -08002910 int i;
Benjamin Li3d16af82008-10-09 12:26:41 -07002911 u16 hw_prod, prod;
Michael Chanbb4f98a2008-06-19 16:38:19 -07002912 u16 cons = rxr->rx_pg_cons;
Michael Chan1db82f22007-12-12 11:19:35 -08002913
Benjamin Li3d16af82008-10-09 12:26:41 -07002914 cons_rx_pg = &rxr->rx_pg_ring[cons];
2915
2916 /* The caller was unable to allocate a new page to replace the
2917 * last one in the frags array, so we need to recycle that page
2918 * and then free the skb.
2919 */
2920 if (skb) {
2921 struct page *page;
2922 struct skb_shared_info *shinfo;
2923
2924 shinfo = skb_shinfo(skb);
2925 shinfo->nr_frags--;
Ian Campbellb7b6a682011-08-24 22:28:12 +00002926 page = skb_frag_page(&shinfo->frags[shinfo->nr_frags]);
2927 __skb_frag_set_page(&shinfo->frags[shinfo->nr_frags], NULL);
Benjamin Li3d16af82008-10-09 12:26:41 -07002928
2929 cons_rx_pg->page = page;
2930 dev_kfree_skb(skb);
2931 }
2932
2933 hw_prod = rxr->rx_pg_prod;
2934
Michael Chan1db82f22007-12-12 11:19:35 -08002935 for (i = 0; i < count; i++) {
Michael Chan2bc40782012-12-06 10:33:09 +00002936 prod = BNX2_RX_PG_RING_IDX(hw_prod);
Michael Chan1db82f22007-12-12 11:19:35 -08002937
Michael Chanbb4f98a2008-06-19 16:38:19 -07002938 prod_rx_pg = &rxr->rx_pg_ring[prod];
2939 cons_rx_pg = &rxr->rx_pg_ring[cons];
Michael Chan2bc40782012-12-06 10:33:09 +00002940 cons_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(cons)]
2941 [BNX2_RX_IDX(cons)];
2942 prod_bd = &rxr->rx_pg_desc_ring[BNX2_RX_RING(prod)]
2943 [BNX2_RX_IDX(prod)];
Michael Chan1db82f22007-12-12 11:19:35 -08002944
Michael Chan1db82f22007-12-12 11:19:35 -08002945 if (prod != cons) {
2946 prod_rx_pg->page = cons_rx_pg->page;
2947 cons_rx_pg->page = NULL;
FUJITA Tomonori1a4ccc22010-04-01 16:56:57 +00002948 dma_unmap_addr_set(prod_rx_pg, mapping,
2949 dma_unmap_addr(cons_rx_pg, mapping));
Michael Chan1db82f22007-12-12 11:19:35 -08002950
2951 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2952 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2953
2954 }
Michael Chan2bc40782012-12-06 10:33:09 +00002955 cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(cons));
2956 hw_prod = BNX2_NEXT_RX_BD(hw_prod);
Michael Chan1db82f22007-12-12 11:19:35 -08002957 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07002958 rxr->rx_pg_prod = hw_prod;
2959 rxr->rx_pg_cons = cons;
Michael Chan1db82f22007-12-12 11:19:35 -08002960}
2961
Michael Chanb6016b72005-05-26 13:03:09 -07002962static inline void
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00002963bnx2_reuse_rx_data(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2964 u8 *data, u16 cons, u16 prod)
Michael Chanb6016b72005-05-26 13:03:09 -07002965{
Michael Chan2bc40782012-12-06 10:33:09 +00002966 struct bnx2_sw_bd *cons_rx_buf, *prod_rx_buf;
2967 struct bnx2_rx_bd *cons_bd, *prod_bd;
Michael Chan236b6392006-03-20 17:49:02 -08002968
Michael Chanbb4f98a2008-06-19 16:38:19 -07002969 cons_rx_buf = &rxr->rx_buf_ring[cons];
2970 prod_rx_buf = &rxr->rx_buf_ring[prod];
Michael Chanb6016b72005-05-26 13:03:09 -07002971
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00002972 dma_sync_single_for_device(&bp->pdev->dev,
FUJITA Tomonori1a4ccc22010-04-01 16:56:57 +00002973 dma_unmap_addr(cons_rx_buf, mapping),
Benjamin Li601d3d12008-05-16 22:19:35 -07002974 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07002975
Michael Chanbb4f98a2008-06-19 16:38:19 -07002976 rxr->rx_prod_bseq += bp->rx_buf_use_size;
Michael Chan236b6392006-03-20 17:49:02 -08002977
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00002978 prod_rx_buf->data = data;
Michael Chan236b6392006-03-20 17:49:02 -08002979
2980 if (cons == prod)
2981 return;
2982
FUJITA Tomonori1a4ccc22010-04-01 16:56:57 +00002983 dma_unmap_addr_set(prod_rx_buf, mapping,
2984 dma_unmap_addr(cons_rx_buf, mapping));
Michael Chanb6016b72005-05-26 13:03:09 -07002985
Michael Chan2bc40782012-12-06 10:33:09 +00002986 cons_bd = &rxr->rx_desc_ring[BNX2_RX_RING(cons)][BNX2_RX_IDX(cons)];
2987 prod_bd = &rxr->rx_desc_ring[BNX2_RX_RING(prod)][BNX2_RX_IDX(prod)];
Michael Chan236b6392006-03-20 17:49:02 -08002988 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2989 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
Michael Chanb6016b72005-05-26 13:03:09 -07002990}
2991
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00002992static struct sk_buff *
2993bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u8 *data,
Michael Chana1f60192007-12-20 19:57:19 -08002994 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2995 u32 ring_idx)
Michael Chan85833c62007-12-12 11:17:01 -08002996{
2997 int err;
2998 u16 prod = ring_idx & 0xffff;
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00002999 struct sk_buff *skb;
Michael Chan85833c62007-12-12 11:17:01 -08003000
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00003001 err = bnx2_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
Michael Chan85833c62007-12-12 11:17:01 -08003002 if (unlikely(err)) {
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00003003 bnx2_reuse_rx_data(bp, rxr, data, (u16) (ring_idx >> 16), prod);
3004error:
Michael Chan1db82f22007-12-12 11:19:35 -08003005 if (hdr_len) {
3006 unsigned int raw_len = len + 4;
3007 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
3008
Michael Chanbb4f98a2008-06-19 16:38:19 -07003009 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
Michael Chan1db82f22007-12-12 11:19:35 -08003010 }
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00003011 return NULL;
Michael Chan85833c62007-12-12 11:17:01 -08003012 }
3013
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00003014 dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
Michael Chan85833c62007-12-12 11:17:01 -08003015 PCI_DMA_FROMDEVICE);
Eric Dumazetd3836f22012-04-27 00:33:38 +00003016 skb = build_skb(data, 0);
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00003017 if (!skb) {
3018 kfree(data);
3019 goto error;
3020 }
3021 skb_reserve(skb, ((u8 *)get_l2_fhdr(data) - data) + BNX2_RX_OFFSET);
Michael Chan1db82f22007-12-12 11:19:35 -08003022 if (hdr_len == 0) {
3023 skb_put(skb, len);
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00003024 return skb;
Michael Chan1db82f22007-12-12 11:19:35 -08003025 } else {
3026 unsigned int i, frag_len, frag_size, pages;
Michael Chan2bc40782012-12-06 10:33:09 +00003027 struct bnx2_sw_pg *rx_pg;
Michael Chanbb4f98a2008-06-19 16:38:19 -07003028 u16 pg_cons = rxr->rx_pg_cons;
3029 u16 pg_prod = rxr->rx_pg_prod;
Michael Chan1db82f22007-12-12 11:19:35 -08003030
3031 frag_size = len + 4 - hdr_len;
3032 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
3033 skb_put(skb, hdr_len);
3034
3035 for (i = 0; i < pages; i++) {
Benjamin Li3d16af82008-10-09 12:26:41 -07003036 dma_addr_t mapping_old;
3037
Michael Chan1db82f22007-12-12 11:19:35 -08003038 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
3039 if (unlikely(frag_len <= 4)) {
3040 unsigned int tail = 4 - frag_len;
3041
Michael Chanbb4f98a2008-06-19 16:38:19 -07003042 rxr->rx_pg_cons = pg_cons;
3043 rxr->rx_pg_prod = pg_prod;
3044 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
Michael Chana1f60192007-12-20 19:57:19 -08003045 pages - i);
Michael Chan1db82f22007-12-12 11:19:35 -08003046 skb->len -= tail;
3047 if (i == 0) {
3048 skb->tail -= tail;
3049 } else {
3050 skb_frag_t *frag =
3051 &skb_shinfo(skb)->frags[i - 1];
Eric Dumazet9e903e02011-10-18 21:00:24 +00003052 skb_frag_size_sub(frag, tail);
Michael Chan1db82f22007-12-12 11:19:35 -08003053 skb->data_len -= tail;
Michael Chan1db82f22007-12-12 11:19:35 -08003054 }
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00003055 return skb;
Michael Chan1db82f22007-12-12 11:19:35 -08003056 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07003057 rx_pg = &rxr->rx_pg_ring[pg_cons];
Michael Chan1db82f22007-12-12 11:19:35 -08003058
Benjamin Li3d16af82008-10-09 12:26:41 -07003059 /* Don't unmap yet. If we're unable to allocate a new
3060 * page, we need to recycle the page and the DMA addr.
3061 */
FUJITA Tomonori1a4ccc22010-04-01 16:56:57 +00003062 mapping_old = dma_unmap_addr(rx_pg, mapping);
Michael Chan1db82f22007-12-12 11:19:35 -08003063 if (i == pages - 1)
3064 frag_len -= 4;
3065
3066 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3067 rx_pg->page = NULL;
3068
Michael Chanbb4f98a2008-06-19 16:38:19 -07003069 err = bnx2_alloc_rx_page(bp, rxr,
Michael Chan2bc40782012-12-06 10:33:09 +00003070 BNX2_RX_PG_RING_IDX(pg_prod),
Stanislaw Gruszkaa2df00a2010-07-15 22:55:40 +00003071 GFP_ATOMIC);
Michael Chan1db82f22007-12-12 11:19:35 -08003072 if (unlikely(err)) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07003073 rxr->rx_pg_cons = pg_cons;
3074 rxr->rx_pg_prod = pg_prod;
3075 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
Michael Chana1f60192007-12-20 19:57:19 -08003076 pages - i);
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00003077 return NULL;
Michael Chan1db82f22007-12-12 11:19:35 -08003078 }
3079
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00003080 dma_unmap_page(&bp->pdev->dev, mapping_old,
Benjamin Li3d16af82008-10-09 12:26:41 -07003081 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3082
Michael Chan1db82f22007-12-12 11:19:35 -08003083 frag_size -= frag_len;
3084 skb->data_len += frag_len;
Eric Dumazeta1f4e8b2011-10-13 07:50:19 +00003085 skb->truesize += PAGE_SIZE;
Michael Chan1db82f22007-12-12 11:19:35 -08003086 skb->len += frag_len;
3087
Michael Chan2bc40782012-12-06 10:33:09 +00003088 pg_prod = BNX2_NEXT_RX_BD(pg_prod);
3089 pg_cons = BNX2_RX_PG_RING_IDX(BNX2_NEXT_RX_BD(pg_cons));
Michael Chan1db82f22007-12-12 11:19:35 -08003090 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07003091 rxr->rx_pg_prod = pg_prod;
3092 rxr->rx_pg_cons = pg_cons;
Michael Chan1db82f22007-12-12 11:19:35 -08003093 }
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00003094 return skb;
Michael Chan85833c62007-12-12 11:17:01 -08003095}
3096
Michael Chanc09c2622007-12-10 17:18:37 -08003097static inline u16
Michael Chan35efa7c2007-12-20 19:56:37 -08003098bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
Michael Chanc09c2622007-12-10 17:18:37 -08003099{
Michael Chanbb4f98a2008-06-19 16:38:19 -07003100 u16 cons;
3101
Michael Chan43e80b82008-06-19 16:41:08 -07003102 /* Tell compiler that status block fields can change. */
3103 barrier();
3104 cons = *bnapi->hw_rx_cons_ptr;
Michael Chan581daf72009-05-06 16:46:47 -07003105 barrier();
Michael Chan2bc40782012-12-06 10:33:09 +00003106 if (unlikely((cons & BNX2_MAX_RX_DESC_CNT) == BNX2_MAX_RX_DESC_CNT))
Michael Chanc09c2622007-12-10 17:18:37 -08003107 cons++;
3108 return cons;
3109}
3110
Michael Chanb6016b72005-05-26 13:03:09 -07003111static int
Michael Chan35efa7c2007-12-20 19:56:37 -08003112bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
Michael Chanb6016b72005-05-26 13:03:09 -07003113{
Michael Chanbb4f98a2008-06-19 16:38:19 -07003114 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
Michael Chanb6016b72005-05-26 13:03:09 -07003115 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3116 struct l2_fhdr *rx_hdr;
Michael Chan1db82f22007-12-12 11:19:35 -08003117 int rx_pkt = 0, pg_ring_used = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07003118
Michael Chan35efa7c2007-12-20 19:56:37 -08003119 hw_cons = bnx2_get_hw_rx_cons(bnapi);
Michael Chanbb4f98a2008-06-19 16:38:19 -07003120 sw_cons = rxr->rx_cons;
3121 sw_prod = rxr->rx_prod;
Michael Chanb6016b72005-05-26 13:03:09 -07003122
3123 /* Memory barrier necessary as speculative reads of the rx
3124 * buffer can be ahead of the index in the status block
3125 */
3126 rmb();
3127 while (sw_cons != hw_cons) {
Michael Chan1db82f22007-12-12 11:19:35 -08003128 unsigned int len, hdr_len;
Michael Chanade2bfe2006-01-23 16:09:51 -08003129 u32 status;
Michael Chan2bc40782012-12-06 10:33:09 +00003130 struct bnx2_sw_bd *rx_buf, *next_rx_buf;
Michael Chanb6016b72005-05-26 13:03:09 -07003131 struct sk_buff *skb;
Michael Chan236b6392006-03-20 17:49:02 -08003132 dma_addr_t dma_addr;
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00003133 u8 *data;
Michael Chan2bc40782012-12-06 10:33:09 +00003134 u16 next_ring_idx;
Michael Chanb6016b72005-05-26 13:03:09 -07003135
Michael Chan2bc40782012-12-06 10:33:09 +00003136 sw_ring_cons = BNX2_RX_RING_IDX(sw_cons);
3137 sw_ring_prod = BNX2_RX_RING_IDX(sw_prod);
Michael Chanb6016b72005-05-26 13:03:09 -07003138
Michael Chanbb4f98a2008-06-19 16:38:19 -07003139 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00003140 data = rx_buf->data;
3141 rx_buf->data = NULL;
Michael Chan236b6392006-03-20 17:49:02 -08003142
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00003143 rx_hdr = get_l2_fhdr(data);
3144 prefetch(rx_hdr);
Michael Chan236b6392006-03-20 17:49:02 -08003145
FUJITA Tomonori1a4ccc22010-04-01 16:56:57 +00003146 dma_addr = dma_unmap_addr(rx_buf, mapping);
Michael Chan236b6392006-03-20 17:49:02 -08003147
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00003148 dma_sync_single_for_cpu(&bp->pdev->dev, dma_addr,
Benjamin Li601d3d12008-05-16 22:19:35 -07003149 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3150 PCI_DMA_FROMDEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07003151
Michael Chan2bc40782012-12-06 10:33:09 +00003152 next_ring_idx = BNX2_RX_RING_IDX(BNX2_NEXT_RX_BD(sw_cons));
3153 next_rx_buf = &rxr->rx_buf_ring[next_ring_idx];
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00003154 prefetch(get_l2_fhdr(next_rx_buf->data));
3155
Michael Chan1db82f22007-12-12 11:19:35 -08003156 len = rx_hdr->l2_fhdr_pkt_len;
Michael Chan990ec382009-02-12 16:54:13 -08003157 status = rx_hdr->l2_fhdr_status;
Michael Chanb6016b72005-05-26 13:03:09 -07003158
Michael Chan1db82f22007-12-12 11:19:35 -08003159 hdr_len = 0;
3160 if (status & L2_FHDR_STATUS_SPLIT) {
3161 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3162 pg_ring_used = 1;
3163 } else if (len > bp->rx_jumbo_thresh) {
3164 hdr_len = bp->rx_jumbo_thresh;
3165 pg_ring_used = 1;
3166 }
3167
Michael Chan990ec382009-02-12 16:54:13 -08003168 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3169 L2_FHDR_ERRORS_PHY_DECODE |
3170 L2_FHDR_ERRORS_ALIGNMENT |
3171 L2_FHDR_ERRORS_TOO_SHORT |
3172 L2_FHDR_ERRORS_GIANT_FRAME))) {
3173
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00003174 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
Michael Chan990ec382009-02-12 16:54:13 -08003175 sw_ring_prod);
3176 if (pg_ring_used) {
3177 int pages;
3178
3179 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3180
3181 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3182 }
3183 goto next_rx;
3184 }
3185
Michael Chan1db82f22007-12-12 11:19:35 -08003186 len -= 4;
Michael Chanb6016b72005-05-26 13:03:09 -07003187
Michael Chan5d5d0012007-12-12 11:17:43 -08003188 if (len <= bp->rx_copy_thresh) {
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00003189 skb = netdev_alloc_skb(bp->dev, len + 6);
3190 if (skb == NULL) {
3191 bnx2_reuse_rx_data(bp, rxr, data, sw_ring_cons,
Michael Chan85833c62007-12-12 11:17:01 -08003192 sw_ring_prod);
3193 goto next_rx;
3194 }
Michael Chanb6016b72005-05-26 13:03:09 -07003195
3196 /* aligned copy */
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00003197 memcpy(skb->data,
3198 (u8 *)rx_hdr + BNX2_RX_OFFSET - 6,
3199 len + 6);
3200 skb_reserve(skb, 6);
3201 skb_put(skb, len);
Michael Chanb6016b72005-05-26 13:03:09 -07003202
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00003203 bnx2_reuse_rx_data(bp, rxr, data,
Michael Chanb6016b72005-05-26 13:03:09 -07003204 sw_ring_cons, sw_ring_prod);
3205
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00003206 } else {
3207 skb = bnx2_rx_skb(bp, rxr, data, len, hdr_len, dma_addr,
3208 (sw_ring_cons << 16) | sw_ring_prod);
3209 if (!skb)
3210 goto next_rx;
3211 }
Michael Chanf22828e2008-08-14 15:30:14 -07003212 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
Jesse Gross7d0fd212010-10-20 13:56:09 +00003213 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG))
Patrick McHardy86a9bad2013-04-19 02:04:30 +00003214 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rx_hdr->l2_fhdr_vlan_tag);
Michael Chanf22828e2008-08-14 15:30:14 -07003215
Michael Chanb6016b72005-05-26 13:03:09 -07003216 skb->protocol = eth_type_trans(skb, bp->dev);
3217
3218 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
Alexey Dobriyand1e100b2006-06-11 20:57:17 -07003219 (ntohs(skb->protocol) != 0x8100)) {
Michael Chanb6016b72005-05-26 13:03:09 -07003220
Michael Chan745720e2006-06-29 12:37:41 -07003221 dev_kfree_skb(skb);
Michael Chanb6016b72005-05-26 13:03:09 -07003222 goto next_rx;
3223
3224 }
3225
Eric Dumazetbc8acf22010-09-02 13:07:41 -07003226 skb_checksum_none_assert(skb);
Michał Mirosław8d7dfc22011-04-10 04:47:46 +00003227 if ((bp->dev->features & NETIF_F_RXCSUM) &&
Michael Chanb6016b72005-05-26 13:03:09 -07003228 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3229 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3230
Michael Chanade2bfe2006-01-23 16:09:51 -08003231 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3232 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
Michael Chanb6016b72005-05-26 13:03:09 -07003233 skb->ip_summed = CHECKSUM_UNNECESSARY;
3234 }
Michael Chanfdc85412010-07-03 20:42:16 +00003235 if ((bp->dev->features & NETIF_F_RXHASH) &&
3236 ((status & L2_FHDR_STATUS_USE_RXHASH) ==
3237 L2_FHDR_STATUS_USE_RXHASH))
3238 skb->rxhash = rx_hdr->l2_fhdr_hash;
Michael Chanb6016b72005-05-26 13:03:09 -07003239
David S. Miller0c8dfc82009-01-27 16:22:32 -08003240 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
Jesse Gross7d0fd212010-10-20 13:56:09 +00003241 napi_gro_receive(&bnapi->napi, skb);
Michael Chanb6016b72005-05-26 13:03:09 -07003242 rx_pkt++;
3243
3244next_rx:
Michael Chan2bc40782012-12-06 10:33:09 +00003245 sw_cons = BNX2_NEXT_RX_BD(sw_cons);
3246 sw_prod = BNX2_NEXT_RX_BD(sw_prod);
Michael Chanb6016b72005-05-26 13:03:09 -07003247
3248 if ((rx_pkt == budget))
3249 break;
Michael Chanf4e418f2005-11-04 08:53:48 -08003250
3251 /* Refresh hw_cons to see if there is new work */
3252 if (sw_cons == hw_cons) {
Michael Chan35efa7c2007-12-20 19:56:37 -08003253 hw_cons = bnx2_get_hw_rx_cons(bnapi);
Michael Chanf4e418f2005-11-04 08:53:48 -08003254 rmb();
3255 }
Michael Chanb6016b72005-05-26 13:03:09 -07003256 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07003257 rxr->rx_cons = sw_cons;
3258 rxr->rx_prod = sw_prod;
Michael Chanb6016b72005-05-26 13:03:09 -07003259
Michael Chan1db82f22007-12-12 11:19:35 -08003260 if (pg_ring_used)
Michael Chane503e062012-12-06 10:33:08 +00003261 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
Michael Chan1db82f22007-12-12 11:19:35 -08003262
Michael Chane503e062012-12-06 10:33:08 +00003263 BNX2_WR16(bp, rxr->rx_bidx_addr, sw_prod);
Michael Chanb6016b72005-05-26 13:03:09 -07003264
Michael Chane503e062012-12-06 10:33:08 +00003265 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07003266
3267 mmiowb();
3268
3269 return rx_pkt;
3270
3271}
3272
3273/* MSI ISR - The only difference between this and the INTx ISR
3274 * is that the MSI interrupt is always serviced.
3275 */
3276static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01003277bnx2_msi(int irq, void *dev_instance)
Michael Chanb6016b72005-05-26 13:03:09 -07003278{
Michael Chanf0ea2e62008-06-19 16:41:57 -07003279 struct bnx2_napi *bnapi = dev_instance;
3280 struct bnx2 *bp = bnapi->bp;
Michael Chanb6016b72005-05-26 13:03:09 -07003281
Michael Chan43e80b82008-06-19 16:41:08 -07003282 prefetch(bnapi->status_blk.msi);
Michael Chane503e062012-12-06 10:33:08 +00003283 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
Michael Chanb6016b72005-05-26 13:03:09 -07003284 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3285 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3286
3287 /* Return here if interrupt is disabled. */
Michael Chan73eef4c2005-08-25 15:39:15 -07003288 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3289 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07003290
Ben Hutchings288379f2009-01-19 16:43:59 -08003291 napi_schedule(&bnapi->napi);
Michael Chanb6016b72005-05-26 13:03:09 -07003292
Michael Chan73eef4c2005-08-25 15:39:15 -07003293 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07003294}
3295
3296static irqreturn_t
Michael Chan8e6a72c2007-05-03 13:24:48 -07003297bnx2_msi_1shot(int irq, void *dev_instance)
3298{
Michael Chanf0ea2e62008-06-19 16:41:57 -07003299 struct bnx2_napi *bnapi = dev_instance;
3300 struct bnx2 *bp = bnapi->bp;
Michael Chan8e6a72c2007-05-03 13:24:48 -07003301
Michael Chan43e80b82008-06-19 16:41:08 -07003302 prefetch(bnapi->status_blk.msi);
Michael Chan8e6a72c2007-05-03 13:24:48 -07003303
3304 /* Return here if interrupt is disabled. */
3305 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3306 return IRQ_HANDLED;
3307
Ben Hutchings288379f2009-01-19 16:43:59 -08003308 napi_schedule(&bnapi->napi);
Michael Chan8e6a72c2007-05-03 13:24:48 -07003309
3310 return IRQ_HANDLED;
3311}
3312
3313static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01003314bnx2_interrupt(int irq, void *dev_instance)
Michael Chanb6016b72005-05-26 13:03:09 -07003315{
Michael Chanf0ea2e62008-06-19 16:41:57 -07003316 struct bnx2_napi *bnapi = dev_instance;
3317 struct bnx2 *bp = bnapi->bp;
Michael Chan43e80b82008-06-19 16:41:08 -07003318 struct status_block *sblk = bnapi->status_blk.msi;
Michael Chanb6016b72005-05-26 13:03:09 -07003319
3320 /* When using INTx, it is possible for the interrupt to arrive
3321 * at the CPU before the status block posted prior to the
3322 * interrupt. Reading a register will flush the status block.
3323 * When using MSI, the MSI message will always complete after
3324 * the status block write.
3325 */
Michael Chan35efa7c2007-12-20 19:56:37 -08003326 if ((sblk->status_idx == bnapi->last_status_idx) &&
Michael Chane503e062012-12-06 10:33:08 +00003327 (BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS) &
Michael Chanb6016b72005-05-26 13:03:09 -07003328 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
Michael Chan73eef4c2005-08-25 15:39:15 -07003329 return IRQ_NONE;
Michael Chanb6016b72005-05-26 13:03:09 -07003330
Michael Chane503e062012-12-06 10:33:08 +00003331 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
Michael Chanb6016b72005-05-26 13:03:09 -07003332 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3333 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3334
Michael Chanb8a7ce72007-07-07 22:51:03 -07003335 /* Read back to deassert IRQ immediately to avoid too many
3336 * spurious interrupts.
3337 */
Michael Chane503e062012-12-06 10:33:08 +00003338 BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
Michael Chanb8a7ce72007-07-07 22:51:03 -07003339
Michael Chanb6016b72005-05-26 13:03:09 -07003340 /* Return here if interrupt is shared and is disabled. */
Michael Chan73eef4c2005-08-25 15:39:15 -07003341 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3342 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07003343
Ben Hutchings288379f2009-01-19 16:43:59 -08003344 if (napi_schedule_prep(&bnapi->napi)) {
Michael Chan35efa7c2007-12-20 19:56:37 -08003345 bnapi->last_status_idx = sblk->status_idx;
Ben Hutchings288379f2009-01-19 16:43:59 -08003346 __napi_schedule(&bnapi->napi);
Michael Chanb8a7ce72007-07-07 22:51:03 -07003347 }
Michael Chanb6016b72005-05-26 13:03:09 -07003348
Michael Chan73eef4c2005-08-25 15:39:15 -07003349 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07003350}
3351
Michael Chan43e80b82008-06-19 16:41:08 -07003352static inline int
3353bnx2_has_fast_work(struct bnx2_napi *bnapi)
3354{
3355 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3356 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3357
3358 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3359 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3360 return 1;
3361 return 0;
3362}
3363
Michael Chan0d8a6572007-07-07 22:49:43 -07003364#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3365 STATUS_ATTN_BITS_TIMER_ABORT)
Michael Chanda3e4fb2007-05-03 13:24:23 -07003366
Michael Chanf4e418f2005-11-04 08:53:48 -08003367static inline int
Michael Chan35efa7c2007-12-20 19:56:37 -08003368bnx2_has_work(struct bnx2_napi *bnapi)
Michael Chanf4e418f2005-11-04 08:53:48 -08003369{
Michael Chan43e80b82008-06-19 16:41:08 -07003370 struct status_block *sblk = bnapi->status_blk.msi;
Michael Chanf4e418f2005-11-04 08:53:48 -08003371
Michael Chan43e80b82008-06-19 16:41:08 -07003372 if (bnx2_has_fast_work(bnapi))
Michael Chanf4e418f2005-11-04 08:53:48 -08003373 return 1;
3374
Michael Chan4edd4732009-06-08 18:14:42 -07003375#ifdef BCM_CNIC
3376 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3377 return 1;
3378#endif
3379
Michael Chanda3e4fb2007-05-03 13:24:23 -07003380 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3381 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
Michael Chanf4e418f2005-11-04 08:53:48 -08003382 return 1;
3383
3384 return 0;
3385}
3386
Michael Chanefba0182008-12-03 00:36:15 -08003387static void
3388bnx2_chk_missed_msi(struct bnx2 *bp)
3389{
3390 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3391 u32 msi_ctrl;
3392
3393 if (bnx2_has_work(bnapi)) {
Michael Chane503e062012-12-06 10:33:08 +00003394 msi_ctrl = BNX2_RD(bp, BNX2_PCICFG_MSI_CONTROL);
Michael Chanefba0182008-12-03 00:36:15 -08003395 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3396 return;
3397
3398 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
Michael Chane503e062012-12-06 10:33:08 +00003399 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3400 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3401 BNX2_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
Michael Chanefba0182008-12-03 00:36:15 -08003402 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3403 }
3404 }
3405
3406 bp->idle_chk_status_idx = bnapi->last_status_idx;
3407}
3408
Michael Chan4edd4732009-06-08 18:14:42 -07003409#ifdef BCM_CNIC
3410static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3411{
3412 struct cnic_ops *c_ops;
3413
3414 if (!bnapi->cnic_present)
3415 return;
3416
3417 rcu_read_lock();
3418 c_ops = rcu_dereference(bp->cnic_ops);
3419 if (c_ops)
3420 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3421 bnapi->status_blk.msi);
3422 rcu_read_unlock();
3423}
3424#endif
3425
Michael Chan43e80b82008-06-19 16:41:08 -07003426static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
Michael Chanb6016b72005-05-26 13:03:09 -07003427{
Michael Chan43e80b82008-06-19 16:41:08 -07003428 struct status_block *sblk = bnapi->status_blk.msi;
Michael Chanda3e4fb2007-05-03 13:24:23 -07003429 u32 status_attn_bits = sblk->status_attn_bits;
3430 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
Michael Chanb6016b72005-05-26 13:03:09 -07003431
Michael Chanda3e4fb2007-05-03 13:24:23 -07003432 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3433 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
Michael Chanb6016b72005-05-26 13:03:09 -07003434
Michael Chan35efa7c2007-12-20 19:56:37 -08003435 bnx2_phy_int(bp, bnapi);
Michael Chanbf5295b2006-03-23 01:11:56 -08003436
3437 /* This is needed to take care of transient status
3438 * during link changes.
3439 */
Michael Chane503e062012-12-06 10:33:08 +00003440 BNX2_WR(bp, BNX2_HC_COMMAND,
3441 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3442 BNX2_RD(bp, BNX2_HC_COMMAND);
Michael Chanb6016b72005-05-26 13:03:09 -07003443 }
Michael Chan43e80b82008-06-19 16:41:08 -07003444}
3445
3446static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3447 int work_done, int budget)
3448{
3449 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3450 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
Michael Chanb6016b72005-05-26 13:03:09 -07003451
Michael Chan35e90102008-06-19 16:37:42 -07003452 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
Michael Chan57851d82007-12-20 20:01:44 -08003453 bnx2_tx_int(bp, bnapi, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07003454
Michael Chanbb4f98a2008-06-19 16:38:19 -07003455 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
Michael Chan35efa7c2007-12-20 19:56:37 -08003456 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003457
David S. Miller6f535762007-10-11 18:08:29 -07003458 return work_done;
3459}
Michael Chanf4e418f2005-11-04 08:53:48 -08003460
Michael Chanf0ea2e62008-06-19 16:41:57 -07003461static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3462{
3463 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3464 struct bnx2 *bp = bnapi->bp;
3465 int work_done = 0;
3466 struct status_block_msix *sblk = bnapi->status_blk.msix;
3467
3468 while (1) {
3469 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3470 if (unlikely(work_done >= budget))
3471 break;
3472
3473 bnapi->last_status_idx = sblk->status_idx;
3474 /* status idx must be read before checking for more work. */
3475 rmb();
3476 if (likely(!bnx2_has_fast_work(bnapi))) {
3477
Ben Hutchings288379f2009-01-19 16:43:59 -08003478 napi_complete(napi);
Michael Chane503e062012-12-06 10:33:08 +00003479 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3480 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3481 bnapi->last_status_idx);
Michael Chanf0ea2e62008-06-19 16:41:57 -07003482 break;
3483 }
3484 }
3485 return work_done;
3486}
3487
David S. Miller6f535762007-10-11 18:08:29 -07003488static int bnx2_poll(struct napi_struct *napi, int budget)
3489{
Michael Chan35efa7c2007-12-20 19:56:37 -08003490 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3491 struct bnx2 *bp = bnapi->bp;
David S. Miller6f535762007-10-11 18:08:29 -07003492 int work_done = 0;
Michael Chan43e80b82008-06-19 16:41:08 -07003493 struct status_block *sblk = bnapi->status_blk.msi;
David S. Miller6f535762007-10-11 18:08:29 -07003494
3495 while (1) {
Michael Chan43e80b82008-06-19 16:41:08 -07003496 bnx2_poll_link(bp, bnapi);
3497
Michael Chan35efa7c2007-12-20 19:56:37 -08003498 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
David S. Miller6f535762007-10-11 18:08:29 -07003499
Michael Chan4edd4732009-06-08 18:14:42 -07003500#ifdef BCM_CNIC
3501 bnx2_poll_cnic(bp, bnapi);
3502#endif
3503
Michael Chan35efa7c2007-12-20 19:56:37 -08003504 /* bnapi->last_status_idx is used below to tell the hw how
Michael Chan6dee6422007-10-12 01:40:38 -07003505 * much work has been processed, so we must read it before
3506 * checking for more work.
3507 */
Michael Chan35efa7c2007-12-20 19:56:37 -08003508 bnapi->last_status_idx = sblk->status_idx;
Michael Chanefba0182008-12-03 00:36:15 -08003509
3510 if (unlikely(work_done >= budget))
3511 break;
3512
Michael Chan6dee6422007-10-12 01:40:38 -07003513 rmb();
Michael Chan35efa7c2007-12-20 19:56:37 -08003514 if (likely(!bnx2_has_work(bnapi))) {
Ben Hutchings288379f2009-01-19 16:43:59 -08003515 napi_complete(napi);
David S. Millerf86e82f2008-01-21 17:15:40 -08003516 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
Michael Chane503e062012-12-06 10:33:08 +00003517 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3518 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3519 bnapi->last_status_idx);
Michael Chan6dee6422007-10-12 01:40:38 -07003520 break;
David S. Miller6f535762007-10-11 18:08:29 -07003521 }
Michael Chane503e062012-12-06 10:33:08 +00003522 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3523 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3524 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3525 bnapi->last_status_idx);
David S. Miller6f535762007-10-11 18:08:29 -07003526
Michael Chane503e062012-12-06 10:33:08 +00003527 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3528 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3529 bnapi->last_status_idx);
David S. Miller6f535762007-10-11 18:08:29 -07003530 break;
Michael Chan1269a8a2006-01-23 16:11:03 -08003531 }
Michael Chanb6016b72005-05-26 13:03:09 -07003532 }
3533
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003534 return work_done;
Michael Chanb6016b72005-05-26 13:03:09 -07003535}
3536
Herbert Xu932ff272006-06-09 12:20:56 -07003537/* Called with rtnl_lock from vlan functions and also netif_tx_lock
Michael Chanb6016b72005-05-26 13:03:09 -07003538 * from set_multicast.
3539 */
3540static void
3541bnx2_set_rx_mode(struct net_device *dev)
3542{
Michael Chan972ec0d2006-01-23 16:12:43 -08003543 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07003544 u32 rx_mode, sort_mode;
Jiri Pirkoccffad252009-05-22 23:22:17 +00003545 struct netdev_hw_addr *ha;
Michael Chanb6016b72005-05-26 13:03:09 -07003546 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07003547
Michael Chan9f52b562008-10-09 12:21:46 -07003548 if (!netif_running(dev))
3549 return;
3550
Michael Chanc770a652005-08-25 15:38:39 -07003551 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07003552
3553 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3554 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3555 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
Patrick McHardyf6469682013-04-19 02:04:27 +00003556 if (!(dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
Jesse Gross7d0fd212010-10-20 13:56:09 +00003557 (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
Michael Chanb6016b72005-05-26 13:03:09 -07003558 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
Michael Chanb6016b72005-05-26 13:03:09 -07003559 if (dev->flags & IFF_PROMISC) {
3560 /* Promiscuous mode. */
3561 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
Michael Chan75108732006-11-19 14:06:40 -08003562 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3563 BNX2_RPM_SORT_USER0_PROM_VLAN;
Michael Chanb6016b72005-05-26 13:03:09 -07003564 }
3565 else if (dev->flags & IFF_ALLMULTI) {
3566 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
Michael Chane503e062012-12-06 10:33:08 +00003567 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3568 0xffffffff);
Michael Chanb6016b72005-05-26 13:03:09 -07003569 }
3570 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3571 }
3572 else {
3573 /* Accept one or more multicast(s). */
Michael Chanb6016b72005-05-26 13:03:09 -07003574 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3575 u32 regidx;
3576 u32 bit;
3577 u32 crc;
3578
3579 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3580
Jiri Pirko22bedad32010-04-01 21:22:57 +00003581 netdev_for_each_mc_addr(ha, dev) {
3582 crc = ether_crc_le(ETH_ALEN, ha->addr);
Michael Chanb6016b72005-05-26 13:03:09 -07003583 bit = crc & 0xff;
3584 regidx = (bit & 0xe0) >> 5;
3585 bit &= 0x1f;
3586 mc_filter[regidx] |= (1 << bit);
3587 }
3588
3589 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
Michael Chane503e062012-12-06 10:33:08 +00003590 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3591 mc_filter[i]);
Michael Chanb6016b72005-05-26 13:03:09 -07003592 }
3593
3594 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3595 }
3596
Jiri Pirko32e7bfc2010-01-25 13:36:10 -08003597 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
Benjamin Li5fcaed02008-07-14 22:39:52 -07003598 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3599 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3600 BNX2_RPM_SORT_USER0_PROM_VLAN;
3601 } else if (!(dev->flags & IFF_PROMISC)) {
Benjamin Li5fcaed02008-07-14 22:39:52 -07003602 /* Add all entries into to the match filter list */
Jiri Pirkoccffad252009-05-22 23:22:17 +00003603 i = 0;
Jiri Pirko32e7bfc2010-01-25 13:36:10 -08003604 netdev_for_each_uc_addr(ha, dev) {
Jiri Pirkoccffad252009-05-22 23:22:17 +00003605 bnx2_set_mac_addr(bp, ha->addr,
Benjamin Li5fcaed02008-07-14 22:39:52 -07003606 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3607 sort_mode |= (1 <<
3608 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
Jiri Pirkoccffad252009-05-22 23:22:17 +00003609 i++;
Benjamin Li5fcaed02008-07-14 22:39:52 -07003610 }
3611
3612 }
3613
Michael Chanb6016b72005-05-26 13:03:09 -07003614 if (rx_mode != bp->rx_mode) {
3615 bp->rx_mode = rx_mode;
Michael Chane503e062012-12-06 10:33:08 +00003616 BNX2_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
Michael Chanb6016b72005-05-26 13:03:09 -07003617 }
3618
Michael Chane503e062012-12-06 10:33:08 +00003619 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3620 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3621 BNX2_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
Michael Chanb6016b72005-05-26 13:03:09 -07003622
Michael Chanc770a652005-08-25 15:38:39 -07003623 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07003624}
3625
françois romieu7880b722011-09-30 00:36:52 +00003626static int
Michael Chan57579f72009-04-04 16:51:14 -07003627check_fw_section(const struct firmware *fw,
3628 const struct bnx2_fw_file_section *section,
3629 u32 alignment, bool non_empty)
Michael Chanb6016b72005-05-26 13:03:09 -07003630{
Michael Chan57579f72009-04-04 16:51:14 -07003631 u32 offset = be32_to_cpu(section->offset);
3632 u32 len = be32_to_cpu(section->len);
Michael Chanb6016b72005-05-26 13:03:09 -07003633
Michael Chan57579f72009-04-04 16:51:14 -07003634 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3635 return -EINVAL;
3636 if ((non_empty && len == 0) || len > fw->size - offset ||
3637 len & (alignment - 1))
3638 return -EINVAL;
3639 return 0;
3640}
3641
françois romieu7880b722011-09-30 00:36:52 +00003642static int
Michael Chan57579f72009-04-04 16:51:14 -07003643check_mips_fw_entry(const struct firmware *fw,
3644 const struct bnx2_mips_fw_file_entry *entry)
3645{
3646 if (check_fw_section(fw, &entry->text, 4, true) ||
3647 check_fw_section(fw, &entry->data, 4, false) ||
3648 check_fw_section(fw, &entry->rodata, 4, false))
3649 return -EINVAL;
3650 return 0;
3651}
3652
françois romieu7880b722011-09-30 00:36:52 +00003653static void bnx2_release_firmware(struct bnx2 *bp)
3654{
3655 if (bp->rv2p_firmware) {
3656 release_firmware(bp->mips_firmware);
3657 release_firmware(bp->rv2p_firmware);
3658 bp->rv2p_firmware = NULL;
3659 }
3660}
3661
3662static int bnx2_request_uncached_firmware(struct bnx2 *bp)
Michael Chan57579f72009-04-04 16:51:14 -07003663{
3664 const char *mips_fw_file, *rv2p_fw_file;
Bastian Blank5ee1c322009-04-08 15:50:07 -07003665 const struct bnx2_mips_fw_file *mips_fw;
3666 const struct bnx2_rv2p_fw_file *rv2p_fw;
Michael Chan57579f72009-04-04 16:51:14 -07003667 int rc;
3668
Michael Chan4ce45e02012-12-06 10:33:10 +00003669 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
Michael Chan57579f72009-04-04 16:51:14 -07003670 mips_fw_file = FW_MIPS_FILE_09;
Michael Chan4ce45e02012-12-06 10:33:10 +00003671 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A0) ||
3672 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5709_A1))
Michael Chan078b0732009-08-29 00:02:46 -07003673 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3674 else
3675 rv2p_fw_file = FW_RV2P_FILE_09;
Michael Chan57579f72009-04-04 16:51:14 -07003676 } else {
3677 mips_fw_file = FW_MIPS_FILE_06;
3678 rv2p_fw_file = FW_RV2P_FILE_06;
3679 }
3680
3681 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3682 if (rc) {
Joe Perches3a9c6a42010-02-17 15:01:51 +00003683 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
françois romieu7880b722011-09-30 00:36:52 +00003684 goto out;
Michael Chan57579f72009-04-04 16:51:14 -07003685 }
3686
3687 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3688 if (rc) {
Joe Perches3a9c6a42010-02-17 15:01:51 +00003689 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
françois romieu7880b722011-09-30 00:36:52 +00003690 goto err_release_mips_firmware;
Michael Chan57579f72009-04-04 16:51:14 -07003691 }
Bastian Blank5ee1c322009-04-08 15:50:07 -07003692 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3693 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3694 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3695 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3696 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3697 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3698 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3699 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
Joe Perches3a9c6a42010-02-17 15:01:51 +00003700 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
françois romieu7880b722011-09-30 00:36:52 +00003701 rc = -EINVAL;
3702 goto err_release_firmware;
Michael Chan57579f72009-04-04 16:51:14 -07003703 }
Bastian Blank5ee1c322009-04-08 15:50:07 -07003704 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3705 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3706 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
Joe Perches3a9c6a42010-02-17 15:01:51 +00003707 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
françois romieu7880b722011-09-30 00:36:52 +00003708 rc = -EINVAL;
3709 goto err_release_firmware;
Michael Chan57579f72009-04-04 16:51:14 -07003710 }
françois romieu7880b722011-09-30 00:36:52 +00003711out:
3712 return rc;
Michael Chan57579f72009-04-04 16:51:14 -07003713
françois romieu7880b722011-09-30 00:36:52 +00003714err_release_firmware:
3715 release_firmware(bp->rv2p_firmware);
3716 bp->rv2p_firmware = NULL;
3717err_release_mips_firmware:
3718 release_firmware(bp->mips_firmware);
3719 goto out;
3720}
3721
3722static int bnx2_request_firmware(struct bnx2 *bp)
3723{
3724 return bp->rv2p_firmware ? 0 : bnx2_request_uncached_firmware(bp);
Michael Chan57579f72009-04-04 16:51:14 -07003725}
3726
3727static u32
3728rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3729{
3730 switch (idx) {
3731 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3732 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3733 rv2p_code |= RV2P_BD_PAGE_SIZE;
3734 break;
3735 }
3736 return rv2p_code;
3737}
3738
3739static int
3740load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3741 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3742{
3743 u32 rv2p_code_len, file_offset;
3744 __be32 *rv2p_code;
3745 int i;
3746 u32 val, cmd, addr;
3747
3748 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3749 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3750
3751 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3752
3753 if (rv2p_proc == RV2P_PROC1) {
3754 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3755 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3756 } else {
3757 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3758 addr = BNX2_RV2P_PROC2_ADDR_CMD;
Michael Chand25be1d2008-05-02 16:57:59 -07003759 }
Michael Chanb6016b72005-05-26 13:03:09 -07003760
3761 for (i = 0; i < rv2p_code_len; i += 8) {
Michael Chane503e062012-12-06 10:33:08 +00003762 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
Michael Chanb6016b72005-05-26 13:03:09 -07003763 rv2p_code++;
Michael Chane503e062012-12-06 10:33:08 +00003764 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
Michael Chanb6016b72005-05-26 13:03:09 -07003765 rv2p_code++;
3766
Michael Chan57579f72009-04-04 16:51:14 -07003767 val = (i / 8) | cmd;
Michael Chane503e062012-12-06 10:33:08 +00003768 BNX2_WR(bp, addr, val);
Michael Chan57579f72009-04-04 16:51:14 -07003769 }
3770
3771 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3772 for (i = 0; i < 8; i++) {
3773 u32 loc, code;
3774
3775 loc = be32_to_cpu(fw_entry->fixup[i]);
3776 if (loc && ((loc * 4) < rv2p_code_len)) {
3777 code = be32_to_cpu(*(rv2p_code + loc - 1));
Michael Chane503e062012-12-06 10:33:08 +00003778 BNX2_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
Michael Chan57579f72009-04-04 16:51:14 -07003779 code = be32_to_cpu(*(rv2p_code + loc));
3780 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
Michael Chane503e062012-12-06 10:33:08 +00003781 BNX2_WR(bp, BNX2_RV2P_INSTR_LOW, code);
Michael Chan57579f72009-04-04 16:51:14 -07003782
3783 val = (loc / 2) | cmd;
Michael Chane503e062012-12-06 10:33:08 +00003784 BNX2_WR(bp, addr, val);
Michael Chanb6016b72005-05-26 13:03:09 -07003785 }
3786 }
3787
3788 /* Reset the processor, un-stall is done later. */
3789 if (rv2p_proc == RV2P_PROC1) {
Michael Chane503e062012-12-06 10:33:08 +00003790 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
Michael Chanb6016b72005-05-26 13:03:09 -07003791 }
3792 else {
Michael Chane503e062012-12-06 10:33:08 +00003793 BNX2_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
Michael Chanb6016b72005-05-26 13:03:09 -07003794 }
Michael Chan57579f72009-04-04 16:51:14 -07003795
3796 return 0;
Michael Chanb6016b72005-05-26 13:03:09 -07003797}
3798
Michael Chanaf3ee512006-11-19 14:09:25 -08003799static int
Michael Chan57579f72009-04-04 16:51:14 -07003800load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3801 const struct bnx2_mips_fw_file_entry *fw_entry)
Michael Chanb6016b72005-05-26 13:03:09 -07003802{
Michael Chan57579f72009-04-04 16:51:14 -07003803 u32 addr, len, file_offset;
3804 __be32 *data;
Michael Chanb6016b72005-05-26 13:03:09 -07003805 u32 offset;
3806 u32 val;
3807
3808 /* Halt the CPU. */
Michael Chan2726d6e2008-01-29 21:35:05 -08003809 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
Michael Chanb6016b72005-05-26 13:03:09 -07003810 val |= cpu_reg->mode_value_halt;
Michael Chan2726d6e2008-01-29 21:35:05 -08003811 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3812 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
Michael Chanb6016b72005-05-26 13:03:09 -07003813
3814 /* Load the Text area. */
Michael Chan57579f72009-04-04 16:51:14 -07003815 addr = be32_to_cpu(fw_entry->text.addr);
3816 len = be32_to_cpu(fw_entry->text.len);
3817 file_offset = be32_to_cpu(fw_entry->text.offset);
3818 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3819
3820 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3821 if (len) {
Michael Chanb6016b72005-05-26 13:03:09 -07003822 int j;
3823
Michael Chan57579f72009-04-04 16:51:14 -07003824 for (j = 0; j < (len / 4); j++, offset += 4)
3825 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
Michael Chanb6016b72005-05-26 13:03:09 -07003826 }
3827
3828 /* Load the Data area. */
Michael Chan57579f72009-04-04 16:51:14 -07003829 addr = be32_to_cpu(fw_entry->data.addr);
3830 len = be32_to_cpu(fw_entry->data.len);
3831 file_offset = be32_to_cpu(fw_entry->data.offset);
3832 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3833
3834 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3835 if (len) {
Michael Chanb6016b72005-05-26 13:03:09 -07003836 int j;
3837
Michael Chan57579f72009-04-04 16:51:14 -07003838 for (j = 0; j < (len / 4); j++, offset += 4)
3839 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
Michael Chanb6016b72005-05-26 13:03:09 -07003840 }
3841
3842 /* Load the Read-Only area. */
Michael Chan57579f72009-04-04 16:51:14 -07003843 addr = be32_to_cpu(fw_entry->rodata.addr);
3844 len = be32_to_cpu(fw_entry->rodata.len);
3845 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3846 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3847
3848 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3849 if (len) {
Michael Chanb6016b72005-05-26 13:03:09 -07003850 int j;
3851
Michael Chan57579f72009-04-04 16:51:14 -07003852 for (j = 0; j < (len / 4); j++, offset += 4)
3853 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
Michael Chanb6016b72005-05-26 13:03:09 -07003854 }
3855
3856 /* Clear the pre-fetch instruction. */
Michael Chan2726d6e2008-01-29 21:35:05 -08003857 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
Michael Chan57579f72009-04-04 16:51:14 -07003858
3859 val = be32_to_cpu(fw_entry->start_addr);
3860 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
Michael Chanb6016b72005-05-26 13:03:09 -07003861
3862 /* Start the CPU. */
Michael Chan2726d6e2008-01-29 21:35:05 -08003863 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
Michael Chanb6016b72005-05-26 13:03:09 -07003864 val &= ~cpu_reg->mode_value_halt;
Michael Chan2726d6e2008-01-29 21:35:05 -08003865 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3866 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
Michael Chanaf3ee512006-11-19 14:09:25 -08003867
3868 return 0;
Michael Chanb6016b72005-05-26 13:03:09 -07003869}
3870
Michael Chanfba9fe92006-06-12 22:21:25 -07003871static int
Michael Chanb6016b72005-05-26 13:03:09 -07003872bnx2_init_cpus(struct bnx2 *bp)
3873{
Michael Chan57579f72009-04-04 16:51:14 -07003874 const struct bnx2_mips_fw_file *mips_fw =
3875 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3876 const struct bnx2_rv2p_fw_file *rv2p_fw =
3877 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3878 int rc;
Michael Chanb6016b72005-05-26 13:03:09 -07003879
3880 /* Initialize the RV2P processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003881 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3882 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
Michael Chanb6016b72005-05-26 13:03:09 -07003883
3884 /* Initialize the RX Processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003885 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
Michael Chanfba9fe92006-06-12 22:21:25 -07003886 if (rc)
3887 goto init_cpu_err;
3888
Michael Chanb6016b72005-05-26 13:03:09 -07003889 /* Initialize the TX Processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003890 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
Michael Chanfba9fe92006-06-12 22:21:25 -07003891 if (rc)
3892 goto init_cpu_err;
3893
Michael Chanb6016b72005-05-26 13:03:09 -07003894 /* Initialize the TX Patch-up Processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003895 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
Michael Chanfba9fe92006-06-12 22:21:25 -07003896 if (rc)
3897 goto init_cpu_err;
3898
Michael Chanb6016b72005-05-26 13:03:09 -07003899 /* Initialize the Completion Processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003900 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
Michael Chanfba9fe92006-06-12 22:21:25 -07003901 if (rc)
3902 goto init_cpu_err;
3903
Michael Chand43584c2006-11-19 14:14:35 -08003904 /* Initialize the Command Processor. */
Michael Chan57579f72009-04-04 16:51:14 -07003905 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
Michael Chan110d0ef2007-12-12 11:18:34 -08003906
Michael Chanfba9fe92006-06-12 22:21:25 -07003907init_cpu_err:
Michael Chanfba9fe92006-06-12 22:21:25 -07003908 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07003909}
3910
Michael Chanb6a23e92013-08-06 15:50:09 -07003911static void
3912bnx2_setup_wol(struct bnx2 *bp)
3913{
3914 int i;
3915 u32 val, wol_msg;
3916
3917 if (bp->wol) {
3918 u32 advertising;
3919 u8 autoneg;
3920
3921 autoneg = bp->autoneg;
3922 advertising = bp->advertising;
3923
3924 if (bp->phy_port == PORT_TP) {
3925 bp->autoneg = AUTONEG_SPEED;
3926 bp->advertising = ADVERTISED_10baseT_Half |
3927 ADVERTISED_10baseT_Full |
3928 ADVERTISED_100baseT_Half |
3929 ADVERTISED_100baseT_Full |
3930 ADVERTISED_Autoneg;
3931 }
3932
3933 spin_lock_bh(&bp->phy_lock);
3934 bnx2_setup_phy(bp, bp->phy_port);
3935 spin_unlock_bh(&bp->phy_lock);
3936
3937 bp->autoneg = autoneg;
3938 bp->advertising = advertising;
3939
3940 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3941
3942 val = BNX2_RD(bp, BNX2_EMAC_MODE);
3943
3944 /* Enable port mode. */
3945 val &= ~BNX2_EMAC_MODE_PORT;
3946 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3947 BNX2_EMAC_MODE_ACPI_RCVD |
3948 BNX2_EMAC_MODE_MPKT;
3949 if (bp->phy_port == PORT_TP) {
3950 val |= BNX2_EMAC_MODE_PORT_MII;
3951 } else {
3952 val |= BNX2_EMAC_MODE_PORT_GMII;
3953 if (bp->line_speed == SPEED_2500)
3954 val |= BNX2_EMAC_MODE_25G_MODE;
3955 }
3956
3957 BNX2_WR(bp, BNX2_EMAC_MODE, val);
3958
3959 /* receive all multicast */
3960 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3961 BNX2_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3962 0xffffffff);
3963 }
3964 BNX2_WR(bp, BNX2_EMAC_RX_MODE, BNX2_EMAC_RX_MODE_SORT_MODE);
3965
3966 val = 1 | BNX2_RPM_SORT_USER0_BC_EN | BNX2_RPM_SORT_USER0_MC_EN;
3967 BNX2_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3968 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val);
3969 BNX2_WR(bp, BNX2_RPM_SORT_USER0, val | BNX2_RPM_SORT_USER0_ENA);
3970
3971 /* Need to enable EMAC and RPM for WOL. */
3972 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3973 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3974 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3975 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3976
3977 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
3978 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3979 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
3980
3981 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3982 } else {
3983 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3984 }
3985
3986 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3987 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 1, 0);
3988
3989}
3990
Michael Chanb6016b72005-05-26 13:03:09 -07003991static int
Pavel Machek829ca9a2005-09-03 15:56:56 -07003992bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
Michael Chanb6016b72005-05-26 13:03:09 -07003993{
Michael Chanb6016b72005-05-26 13:03:09 -07003994 switch (state) {
Pavel Machek829ca9a2005-09-03 15:56:56 -07003995 case PCI_D0: {
Michael Chanb6016b72005-05-26 13:03:09 -07003996 u32 val;
3997
Michael Chan6d5e85c2013-08-06 15:50:08 -07003998 pci_enable_wake(bp->pdev, PCI_D0, false);
3999 pci_set_power_state(bp->pdev, PCI_D0);
Michael Chanb6016b72005-05-26 13:03:09 -07004000
Michael Chane503e062012-12-06 10:33:08 +00004001 val = BNX2_RD(bp, BNX2_EMAC_MODE);
Michael Chanb6016b72005-05-26 13:03:09 -07004002 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
4003 val &= ~BNX2_EMAC_MODE_MPKT;
Michael Chane503e062012-12-06 10:33:08 +00004004 BNX2_WR(bp, BNX2_EMAC_MODE, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004005
Michael Chane503e062012-12-06 10:33:08 +00004006 val = BNX2_RD(bp, BNX2_RPM_CONFIG);
Michael Chanb6016b72005-05-26 13:03:09 -07004007 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
Michael Chane503e062012-12-06 10:33:08 +00004008 BNX2_WR(bp, BNX2_RPM_CONFIG, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004009 break;
4010 }
Pavel Machek829ca9a2005-09-03 15:56:56 -07004011 case PCI_D3hot: {
Michael Chanb6a23e92013-08-06 15:50:09 -07004012 bnx2_setup_wol(bp);
Michael Chan6d5e85c2013-08-06 15:50:08 -07004013 pci_wake_from_d3(bp->pdev, bp->wol);
Michael Chan4ce45e02012-12-06 10:33:10 +00004014 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
4015 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)) {
Michael Chanb6016b72005-05-26 13:03:09 -07004016
4017 if (bp->wol)
Michael Chan6d5e85c2013-08-06 15:50:08 -07004018 pci_set_power_state(bp->pdev, PCI_D3hot);
4019 } else {
4020 pci_set_power_state(bp->pdev, PCI_D3hot);
Michael Chanb6016b72005-05-26 13:03:09 -07004021 }
Michael Chanb6016b72005-05-26 13:03:09 -07004022
4023 /* No more memory access after this point until
4024 * device is brought back to D0.
4025 */
Michael Chanb6016b72005-05-26 13:03:09 -07004026 break;
4027 }
4028 default:
4029 return -EINVAL;
4030 }
4031 return 0;
4032}
4033
4034static int
4035bnx2_acquire_nvram_lock(struct bnx2 *bp)
4036{
4037 u32 val;
4038 int j;
4039
4040 /* Request access to the flash interface. */
Michael Chane503e062012-12-06 10:33:08 +00004041 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
Michael Chanb6016b72005-05-26 13:03:09 -07004042 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
Michael Chane503e062012-12-06 10:33:08 +00004043 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
Michael Chanb6016b72005-05-26 13:03:09 -07004044 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4045 break;
4046
4047 udelay(5);
4048 }
4049
4050 if (j >= NVRAM_TIMEOUT_COUNT)
4051 return -EBUSY;
4052
4053 return 0;
4054}
4055
4056static int
4057bnx2_release_nvram_lock(struct bnx2 *bp)
4058{
4059 int j;
4060 u32 val;
4061
4062 /* Relinquish nvram interface. */
Michael Chane503e062012-12-06 10:33:08 +00004063 BNX2_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
Michael Chanb6016b72005-05-26 13:03:09 -07004064
4065 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
Michael Chane503e062012-12-06 10:33:08 +00004066 val = BNX2_RD(bp, BNX2_NVM_SW_ARB);
Michael Chanb6016b72005-05-26 13:03:09 -07004067 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4068 break;
4069
4070 udelay(5);
4071 }
4072
4073 if (j >= NVRAM_TIMEOUT_COUNT)
4074 return -EBUSY;
4075
4076 return 0;
4077}
4078
4079
4080static int
4081bnx2_enable_nvram_write(struct bnx2 *bp)
4082{
4083 u32 val;
4084
Michael Chane503e062012-12-06 10:33:08 +00004085 val = BNX2_RD(bp, BNX2_MISC_CFG);
4086 BNX2_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
Michael Chanb6016b72005-05-26 13:03:09 -07004087
Michael Chane30372c2007-07-16 18:26:23 -07004088 if (bp->flash_info->flags & BNX2_NV_WREN) {
Michael Chanb6016b72005-05-26 13:03:09 -07004089 int j;
4090
Michael Chane503e062012-12-06 10:33:08 +00004091 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4092 BNX2_WR(bp, BNX2_NVM_COMMAND,
4093 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
Michael Chanb6016b72005-05-26 13:03:09 -07004094
4095 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4096 udelay(5);
4097
Michael Chane503e062012-12-06 10:33:08 +00004098 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
Michael Chanb6016b72005-05-26 13:03:09 -07004099 if (val & BNX2_NVM_COMMAND_DONE)
4100 break;
4101 }
4102
4103 if (j >= NVRAM_TIMEOUT_COUNT)
4104 return -EBUSY;
4105 }
4106 return 0;
4107}
4108
4109static void
4110bnx2_disable_nvram_write(struct bnx2 *bp)
4111{
4112 u32 val;
4113
Michael Chane503e062012-12-06 10:33:08 +00004114 val = BNX2_RD(bp, BNX2_MISC_CFG);
4115 BNX2_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
Michael Chanb6016b72005-05-26 13:03:09 -07004116}
4117
4118
4119static void
4120bnx2_enable_nvram_access(struct bnx2 *bp)
4121{
4122 u32 val;
4123
Michael Chane503e062012-12-06 10:33:08 +00004124 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
Michael Chanb6016b72005-05-26 13:03:09 -07004125 /* Enable both bits, even on read. */
Michael Chane503e062012-12-06 10:33:08 +00004126 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4127 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
Michael Chanb6016b72005-05-26 13:03:09 -07004128}
4129
4130static void
4131bnx2_disable_nvram_access(struct bnx2 *bp)
4132{
4133 u32 val;
4134
Michael Chane503e062012-12-06 10:33:08 +00004135 val = BNX2_RD(bp, BNX2_NVM_ACCESS_ENABLE);
Michael Chanb6016b72005-05-26 13:03:09 -07004136 /* Disable both bits, even after read. */
Michael Chane503e062012-12-06 10:33:08 +00004137 BNX2_WR(bp, BNX2_NVM_ACCESS_ENABLE,
Michael Chanb6016b72005-05-26 13:03:09 -07004138 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4139 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4140}
4141
4142static int
4143bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4144{
4145 u32 cmd;
4146 int j;
4147
Michael Chane30372c2007-07-16 18:26:23 -07004148 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
Michael Chanb6016b72005-05-26 13:03:09 -07004149 /* Buffered flash, no erase needed */
4150 return 0;
4151
4152 /* Build an erase command */
4153 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4154 BNX2_NVM_COMMAND_DOIT;
4155
4156 /* Need to clear DONE bit separately. */
Michael Chane503e062012-12-06 10:33:08 +00004157 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
Michael Chanb6016b72005-05-26 13:03:09 -07004158
4159 /* Address of the NVRAM to read from. */
Michael Chane503e062012-12-06 10:33:08 +00004160 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
Michael Chanb6016b72005-05-26 13:03:09 -07004161
4162 /* Issue an erase command. */
Michael Chane503e062012-12-06 10:33:08 +00004163 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
Michael Chanb6016b72005-05-26 13:03:09 -07004164
4165 /* Wait for completion. */
4166 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4167 u32 val;
4168
4169 udelay(5);
4170
Michael Chane503e062012-12-06 10:33:08 +00004171 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
Michael Chanb6016b72005-05-26 13:03:09 -07004172 if (val & BNX2_NVM_COMMAND_DONE)
4173 break;
4174 }
4175
4176 if (j >= NVRAM_TIMEOUT_COUNT)
4177 return -EBUSY;
4178
4179 return 0;
4180}
4181
4182static int
4183bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4184{
4185 u32 cmd;
4186 int j;
4187
4188 /* Build the command word. */
4189 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4190
Michael Chane30372c2007-07-16 18:26:23 -07004191 /* Calculate an offset of a buffered flash, not needed for 5709. */
4192 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
Michael Chanb6016b72005-05-26 13:03:09 -07004193 offset = ((offset / bp->flash_info->page_size) <<
4194 bp->flash_info->page_bits) +
4195 (offset % bp->flash_info->page_size);
4196 }
4197
4198 /* Need to clear DONE bit separately. */
Michael Chane503e062012-12-06 10:33:08 +00004199 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
Michael Chanb6016b72005-05-26 13:03:09 -07004200
4201 /* Address of the NVRAM to read from. */
Michael Chane503e062012-12-06 10:33:08 +00004202 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
Michael Chanb6016b72005-05-26 13:03:09 -07004203
4204 /* Issue a read command. */
Michael Chane503e062012-12-06 10:33:08 +00004205 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
Michael Chanb6016b72005-05-26 13:03:09 -07004206
4207 /* Wait for completion. */
4208 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4209 u32 val;
4210
4211 udelay(5);
4212
Michael Chane503e062012-12-06 10:33:08 +00004213 val = BNX2_RD(bp, BNX2_NVM_COMMAND);
Michael Chanb6016b72005-05-26 13:03:09 -07004214 if (val & BNX2_NVM_COMMAND_DONE) {
Michael Chane503e062012-12-06 10:33:08 +00004215 __be32 v = cpu_to_be32(BNX2_RD(bp, BNX2_NVM_READ));
Al Virob491edd2007-12-22 19:44:51 +00004216 memcpy(ret_val, &v, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07004217 break;
4218 }
4219 }
4220 if (j >= NVRAM_TIMEOUT_COUNT)
4221 return -EBUSY;
4222
4223 return 0;
4224}
4225
4226
4227static int
4228bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4229{
Al Virob491edd2007-12-22 19:44:51 +00004230 u32 cmd;
4231 __be32 val32;
Michael Chanb6016b72005-05-26 13:03:09 -07004232 int j;
4233
4234 /* Build the command word. */
4235 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4236
Michael Chane30372c2007-07-16 18:26:23 -07004237 /* Calculate an offset of a buffered flash, not needed for 5709. */
4238 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
Michael Chanb6016b72005-05-26 13:03:09 -07004239 offset = ((offset / bp->flash_info->page_size) <<
4240 bp->flash_info->page_bits) +
4241 (offset % bp->flash_info->page_size);
4242 }
4243
4244 /* Need to clear DONE bit separately. */
Michael Chane503e062012-12-06 10:33:08 +00004245 BNX2_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
Michael Chanb6016b72005-05-26 13:03:09 -07004246
4247 memcpy(&val32, val, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07004248
4249 /* Write the data. */
Michael Chane503e062012-12-06 10:33:08 +00004250 BNX2_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
Michael Chanb6016b72005-05-26 13:03:09 -07004251
4252 /* Address of the NVRAM to write to. */
Michael Chane503e062012-12-06 10:33:08 +00004253 BNX2_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
Michael Chanb6016b72005-05-26 13:03:09 -07004254
4255 /* Issue the write command. */
Michael Chane503e062012-12-06 10:33:08 +00004256 BNX2_WR(bp, BNX2_NVM_COMMAND, cmd);
Michael Chanb6016b72005-05-26 13:03:09 -07004257
4258 /* Wait for completion. */
4259 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4260 udelay(5);
4261
Michael Chane503e062012-12-06 10:33:08 +00004262 if (BNX2_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
Michael Chanb6016b72005-05-26 13:03:09 -07004263 break;
4264 }
4265 if (j >= NVRAM_TIMEOUT_COUNT)
4266 return -EBUSY;
4267
4268 return 0;
4269}
4270
4271static int
4272bnx2_init_nvram(struct bnx2 *bp)
4273{
4274 u32 val;
Michael Chane30372c2007-07-16 18:26:23 -07004275 int j, entry_count, rc = 0;
Michael Chan0ced9d02009-08-21 16:20:49 +00004276 const struct flash_spec *flash;
Michael Chanb6016b72005-05-26 13:03:09 -07004277
Michael Chan4ce45e02012-12-06 10:33:10 +00004278 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
Michael Chane30372c2007-07-16 18:26:23 -07004279 bp->flash_info = &flash_5709;
4280 goto get_flash_size;
4281 }
4282
Michael Chanb6016b72005-05-26 13:03:09 -07004283 /* Determine the selected interface. */
Michael Chane503e062012-12-06 10:33:08 +00004284 val = BNX2_RD(bp, BNX2_NVM_CFG1);
Michael Chanb6016b72005-05-26 13:03:09 -07004285
Denis Chengff8ac602007-09-02 18:30:18 +08004286 entry_count = ARRAY_SIZE(flash_table);
Michael Chanb6016b72005-05-26 13:03:09 -07004287
Michael Chanb6016b72005-05-26 13:03:09 -07004288 if (val & 0x40000000) {
4289
4290 /* Flash interface has been reconfigured */
4291 for (j = 0, flash = &flash_table[0]; j < entry_count;
Michael Chan37137702005-11-04 08:49:17 -08004292 j++, flash++) {
4293 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4294 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
Michael Chanb6016b72005-05-26 13:03:09 -07004295 bp->flash_info = flash;
4296 break;
4297 }
4298 }
4299 }
4300 else {
Michael Chan37137702005-11-04 08:49:17 -08004301 u32 mask;
Michael Chanb6016b72005-05-26 13:03:09 -07004302 /* Not yet been reconfigured */
4303
Michael Chan37137702005-11-04 08:49:17 -08004304 if (val & (1 << 23))
4305 mask = FLASH_BACKUP_STRAP_MASK;
4306 else
4307 mask = FLASH_STRAP_MASK;
4308
Michael Chanb6016b72005-05-26 13:03:09 -07004309 for (j = 0, flash = &flash_table[0]; j < entry_count;
4310 j++, flash++) {
4311
Michael Chan37137702005-11-04 08:49:17 -08004312 if ((val & mask) == (flash->strapping & mask)) {
Michael Chanb6016b72005-05-26 13:03:09 -07004313 bp->flash_info = flash;
4314
4315 /* Request access to the flash interface. */
4316 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4317 return rc;
4318
4319 /* Enable access to flash interface */
4320 bnx2_enable_nvram_access(bp);
4321
4322 /* Reconfigure the flash interface */
Michael Chane503e062012-12-06 10:33:08 +00004323 BNX2_WR(bp, BNX2_NVM_CFG1, flash->config1);
4324 BNX2_WR(bp, BNX2_NVM_CFG2, flash->config2);
4325 BNX2_WR(bp, BNX2_NVM_CFG3, flash->config3);
4326 BNX2_WR(bp, BNX2_NVM_WRITE1, flash->write1);
Michael Chanb6016b72005-05-26 13:03:09 -07004327
4328 /* Disable access to flash interface */
4329 bnx2_disable_nvram_access(bp);
4330 bnx2_release_nvram_lock(bp);
4331
4332 break;
4333 }
4334 }
4335 } /* if (val & 0x40000000) */
4336
4337 if (j == entry_count) {
4338 bp->flash_info = NULL;
Joe Perches3a9c6a42010-02-17 15:01:51 +00004339 pr_alert("Unknown flash/EEPROM type\n");
Michael Chan1122db72006-01-23 16:11:42 -08004340 return -ENODEV;
Michael Chanb6016b72005-05-26 13:03:09 -07004341 }
4342
Michael Chane30372c2007-07-16 18:26:23 -07004343get_flash_size:
Michael Chan2726d6e2008-01-29 21:35:05 -08004344 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
Michael Chan1122db72006-01-23 16:11:42 -08004345 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4346 if (val)
4347 bp->flash_size = val;
4348 else
4349 bp->flash_size = bp->flash_info->total_size;
4350
Michael Chanb6016b72005-05-26 13:03:09 -07004351 return rc;
4352}
4353
4354static int
4355bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4356 int buf_size)
4357{
4358 int rc = 0;
4359 u32 cmd_flags, offset32, len32, extra;
4360
4361 if (buf_size == 0)
4362 return 0;
4363
4364 /* Request access to the flash interface. */
4365 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4366 return rc;
4367
4368 /* Enable access to flash interface */
4369 bnx2_enable_nvram_access(bp);
4370
4371 len32 = buf_size;
4372 offset32 = offset;
4373 extra = 0;
4374
4375 cmd_flags = 0;
4376
4377 if (offset32 & 3) {
4378 u8 buf[4];
4379 u32 pre_len;
4380
4381 offset32 &= ~3;
4382 pre_len = 4 - (offset & 3);
4383
4384 if (pre_len >= len32) {
4385 pre_len = len32;
4386 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4387 BNX2_NVM_COMMAND_LAST;
4388 }
4389 else {
4390 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4391 }
4392
4393 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4394
4395 if (rc)
4396 return rc;
4397
4398 memcpy(ret_buf, buf + (offset & 3), pre_len);
4399
4400 offset32 += 4;
4401 ret_buf += pre_len;
4402 len32 -= pre_len;
4403 }
4404 if (len32 & 3) {
4405 extra = 4 - (len32 & 3);
4406 len32 = (len32 + 4) & ~3;
4407 }
4408
4409 if (len32 == 4) {
4410 u8 buf[4];
4411
4412 if (cmd_flags)
4413 cmd_flags = BNX2_NVM_COMMAND_LAST;
4414 else
4415 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4416 BNX2_NVM_COMMAND_LAST;
4417
4418 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4419
4420 memcpy(ret_buf, buf, 4 - extra);
4421 }
4422 else if (len32 > 0) {
4423 u8 buf[4];
4424
4425 /* Read the first word. */
4426 if (cmd_flags)
4427 cmd_flags = 0;
4428 else
4429 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4430
4431 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4432
4433 /* Advance to the next dword. */
4434 offset32 += 4;
4435 ret_buf += 4;
4436 len32 -= 4;
4437
4438 while (len32 > 4 && rc == 0) {
4439 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4440
4441 /* Advance to the next dword. */
4442 offset32 += 4;
4443 ret_buf += 4;
4444 len32 -= 4;
4445 }
4446
4447 if (rc)
4448 return rc;
4449
4450 cmd_flags = BNX2_NVM_COMMAND_LAST;
4451 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4452
4453 memcpy(ret_buf, buf, 4 - extra);
4454 }
4455
4456 /* Disable access to flash interface */
4457 bnx2_disable_nvram_access(bp);
4458
4459 bnx2_release_nvram_lock(bp);
4460
4461 return rc;
4462}
4463
4464static int
4465bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4466 int buf_size)
4467{
4468 u32 written, offset32, len32;
Michael Chane6be7632007-01-08 19:56:13 -08004469 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07004470 int rc = 0;
4471 int align_start, align_end;
4472
4473 buf = data_buf;
4474 offset32 = offset;
4475 len32 = buf_size;
4476 align_start = align_end = 0;
4477
4478 if ((align_start = (offset32 & 3))) {
4479 offset32 &= ~3;
Michael Chanc8738792007-03-30 14:53:06 -07004480 len32 += align_start;
4481 if (len32 < 4)
4482 len32 = 4;
Michael Chanb6016b72005-05-26 13:03:09 -07004483 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4484 return rc;
4485 }
4486
4487 if (len32 & 3) {
Michael Chanc8738792007-03-30 14:53:06 -07004488 align_end = 4 - (len32 & 3);
4489 len32 += align_end;
4490 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4491 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07004492 }
4493
4494 if (align_start || align_end) {
Michael Chane6be7632007-01-08 19:56:13 -08004495 align_buf = kmalloc(len32, GFP_KERNEL);
4496 if (align_buf == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -07004497 return -ENOMEM;
4498 if (align_start) {
Michael Chane6be7632007-01-08 19:56:13 -08004499 memcpy(align_buf, start, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07004500 }
4501 if (align_end) {
Michael Chane6be7632007-01-08 19:56:13 -08004502 memcpy(align_buf + len32 - 4, end, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07004503 }
Michael Chane6be7632007-01-08 19:56:13 -08004504 memcpy(align_buf + align_start, data_buf, buf_size);
4505 buf = align_buf;
Michael Chanb6016b72005-05-26 13:03:09 -07004506 }
4507
Michael Chane30372c2007-07-16 18:26:23 -07004508 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanae181bc2006-05-22 16:39:20 -07004509 flash_buffer = kmalloc(264, GFP_KERNEL);
4510 if (flash_buffer == NULL) {
4511 rc = -ENOMEM;
4512 goto nvram_write_end;
4513 }
4514 }
4515
Michael Chanb6016b72005-05-26 13:03:09 -07004516 written = 0;
4517 while ((written < len32) && (rc == 0)) {
4518 u32 page_start, page_end, data_start, data_end;
4519 u32 addr, cmd_flags;
4520 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07004521
4522 /* Find the page_start addr */
4523 page_start = offset32 + written;
4524 page_start -= (page_start % bp->flash_info->page_size);
4525 /* Find the page_end addr */
4526 page_end = page_start + bp->flash_info->page_size;
4527 /* Find the data_start addr */
4528 data_start = (written == 0) ? offset32 : page_start;
4529 /* Find the data_end addr */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004530 data_end = (page_end > offset32 + len32) ?
Michael Chanb6016b72005-05-26 13:03:09 -07004531 (offset32 + len32) : page_end;
4532
4533 /* Request access to the flash interface. */
4534 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4535 goto nvram_write_end;
4536
4537 /* Enable access to flash interface */
4538 bnx2_enable_nvram_access(bp);
4539
4540 cmd_flags = BNX2_NVM_COMMAND_FIRST;
Michael Chane30372c2007-07-16 18:26:23 -07004541 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanb6016b72005-05-26 13:03:09 -07004542 int j;
4543
4544 /* Read the whole page into the buffer
4545 * (non-buffer flash only) */
4546 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4547 if (j == (bp->flash_info->page_size - 4)) {
4548 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4549 }
4550 rc = bnx2_nvram_read_dword(bp,
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004551 page_start + j,
4552 &flash_buffer[j],
Michael Chanb6016b72005-05-26 13:03:09 -07004553 cmd_flags);
4554
4555 if (rc)
4556 goto nvram_write_end;
4557
4558 cmd_flags = 0;
4559 }
4560 }
4561
4562 /* Enable writes to flash interface (unlock write-protect) */
4563 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4564 goto nvram_write_end;
4565
Michael Chanb6016b72005-05-26 13:03:09 -07004566 /* Loop to write back the buffer data from page_start to
4567 * data_start */
4568 i = 0;
Michael Chane30372c2007-07-16 18:26:23 -07004569 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanc8738792007-03-30 14:53:06 -07004570 /* Erase the page */
4571 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4572 goto nvram_write_end;
4573
4574 /* Re-enable the write again for the actual write */
4575 bnx2_enable_nvram_write(bp);
4576
Michael Chanb6016b72005-05-26 13:03:09 -07004577 for (addr = page_start; addr < data_start;
4578 addr += 4, i += 4) {
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004579
Michael Chanb6016b72005-05-26 13:03:09 -07004580 rc = bnx2_nvram_write_dword(bp, addr,
4581 &flash_buffer[i], cmd_flags);
4582
4583 if (rc != 0)
4584 goto nvram_write_end;
4585
4586 cmd_flags = 0;
4587 }
4588 }
4589
4590 /* Loop to write the new data from data_start to data_end */
Michael Chanbae25762006-05-22 16:38:38 -07004591 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
Michael Chanb6016b72005-05-26 13:03:09 -07004592 if ((addr == page_end - 4) ||
Michael Chane30372c2007-07-16 18:26:23 -07004593 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
Michael Chanb6016b72005-05-26 13:03:09 -07004594 (addr == data_end - 4))) {
4595
4596 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4597 }
4598 rc = bnx2_nvram_write_dword(bp, addr, buf,
4599 cmd_flags);
4600
4601 if (rc != 0)
4602 goto nvram_write_end;
4603
4604 cmd_flags = 0;
4605 buf += 4;
4606 }
4607
4608 /* Loop to write back the buffer data from data_end
4609 * to page_end */
Michael Chane30372c2007-07-16 18:26:23 -07004610 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanb6016b72005-05-26 13:03:09 -07004611 for (addr = data_end; addr < page_end;
4612 addr += 4, i += 4) {
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004613
Michael Chanb6016b72005-05-26 13:03:09 -07004614 if (addr == page_end-4) {
4615 cmd_flags = BNX2_NVM_COMMAND_LAST;
4616 }
4617 rc = bnx2_nvram_write_dword(bp, addr,
4618 &flash_buffer[i], cmd_flags);
4619
4620 if (rc != 0)
4621 goto nvram_write_end;
4622
4623 cmd_flags = 0;
4624 }
4625 }
4626
4627 /* Disable writes to flash interface (lock write-protect) */
4628 bnx2_disable_nvram_write(bp);
4629
4630 /* Disable access to flash interface */
4631 bnx2_disable_nvram_access(bp);
4632 bnx2_release_nvram_lock(bp);
4633
4634 /* Increment written */
4635 written += data_end - data_start;
4636 }
4637
4638nvram_write_end:
Michael Chane6be7632007-01-08 19:56:13 -08004639 kfree(flash_buffer);
4640 kfree(align_buf);
Michael Chanb6016b72005-05-26 13:03:09 -07004641 return rc;
4642}
4643
Michael Chan0d8a6572007-07-07 22:49:43 -07004644static void
Michael Chan7c62e832008-07-14 22:39:03 -07004645bnx2_init_fw_cap(struct bnx2 *bp)
Michael Chan0d8a6572007-07-07 22:49:43 -07004646{
Michael Chan7c62e832008-07-14 22:39:03 -07004647 u32 val, sig = 0;
Michael Chan0d8a6572007-07-07 22:49:43 -07004648
Michael Chan583c28e2008-01-21 19:51:35 -08004649 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
Michael Chan7c62e832008-07-14 22:39:03 -07004650 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4651
4652 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4653 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
Michael Chan0d8a6572007-07-07 22:49:43 -07004654
Michael Chan2726d6e2008-01-29 21:35:05 -08004655 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
Michael Chan0d8a6572007-07-07 22:49:43 -07004656 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4657 return;
4658
Michael Chan7c62e832008-07-14 22:39:03 -07004659 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4660 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4661 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4662 }
4663
4664 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4665 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4666 u32 link;
4667
Michael Chan583c28e2008-01-21 19:51:35 -08004668 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
Michael Chan0d8a6572007-07-07 22:49:43 -07004669
Michael Chan7c62e832008-07-14 22:39:03 -07004670 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4671 if (link & BNX2_LINK_STATUS_SERDES_LINK)
Michael Chan0d8a6572007-07-07 22:49:43 -07004672 bp->phy_port = PORT_FIBRE;
4673 else
4674 bp->phy_port = PORT_TP;
Michael Chan489310a2007-10-10 16:16:31 -07004675
Michael Chan7c62e832008-07-14 22:39:03 -07004676 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4677 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
Michael Chan0d8a6572007-07-07 22:49:43 -07004678 }
Michael Chan7c62e832008-07-14 22:39:03 -07004679
4680 if (netif_running(bp->dev) && sig)
4681 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
Michael Chan0d8a6572007-07-07 22:49:43 -07004682}
4683
Michael Chanb4b36042007-12-20 19:59:30 -08004684static void
4685bnx2_setup_msix_tbl(struct bnx2 *bp)
4686{
Michael Chane503e062012-12-06 10:33:08 +00004687 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
Michael Chanb4b36042007-12-20 19:59:30 -08004688
Michael Chane503e062012-12-06 10:33:08 +00004689 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4690 BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
Michael Chanb4b36042007-12-20 19:59:30 -08004691}
4692
Michael Chanb6016b72005-05-26 13:03:09 -07004693static int
4694bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4695{
4696 u32 val;
4697 int i, rc = 0;
Michael Chan489310a2007-10-10 16:16:31 -07004698 u8 old_port;
Michael Chanb6016b72005-05-26 13:03:09 -07004699
4700 /* Wait for the current PCI transaction to complete before
4701 * issuing a reset. */
Michael Chan4ce45e02012-12-06 10:33:10 +00004702 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||
4703 (BNX2_CHIP(bp) == BNX2_CHIP_5708)) {
Michael Chane503e062012-12-06 10:33:08 +00004704 BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4705 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4706 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4707 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4708 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4709 val = BNX2_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
Eddie Waia5dac102010-11-24 13:48:54 +00004710 udelay(5);
4711 } else { /* 5709 */
Michael Chane503e062012-12-06 10:33:08 +00004712 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
Eddie Waia5dac102010-11-24 13:48:54 +00004713 val &= ~BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
Michael Chane503e062012-12-06 10:33:08 +00004714 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4715 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
Eddie Waia5dac102010-11-24 13:48:54 +00004716
4717 for (i = 0; i < 100; i++) {
4718 msleep(1);
Michael Chane503e062012-12-06 10:33:08 +00004719 val = BNX2_RD(bp, BNX2_PCICFG_DEVICE_CONTROL);
Eddie Waia5dac102010-11-24 13:48:54 +00004720 if (!(val & BNX2_PCICFG_DEVICE_STATUS_NO_PEND))
4721 break;
4722 }
4723 }
Michael Chanb6016b72005-05-26 13:03:09 -07004724
Michael Chanb090ae22006-01-23 16:07:10 -08004725 /* Wait for the firmware to tell us it is ok to issue a reset. */
Michael Chana2f13892008-07-14 22:38:23 -07004726 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
Michael Chanb090ae22006-01-23 16:07:10 -08004727
Michael Chanb6016b72005-05-26 13:03:09 -07004728 /* Deposit a driver reset signature so the firmware knows that
4729 * this is a soft reset. */
Michael Chan2726d6e2008-01-29 21:35:05 -08004730 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4731 BNX2_DRV_RESET_SIGNATURE_MAGIC);
Michael Chanb6016b72005-05-26 13:03:09 -07004732
Michael Chanb6016b72005-05-26 13:03:09 -07004733 /* Do a dummy read to force the chip to complete all current transaction
4734 * before we issue a reset. */
Michael Chane503e062012-12-06 10:33:08 +00004735 val = BNX2_RD(bp, BNX2_MISC_ID);
Michael Chanb6016b72005-05-26 13:03:09 -07004736
Michael Chan4ce45e02012-12-06 10:33:10 +00004737 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
Michael Chane503e062012-12-06 10:33:08 +00004738 BNX2_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4739 BNX2_RD(bp, BNX2_MISC_COMMAND);
Michael Chan234754d2006-11-19 14:11:41 -08004740 udelay(5);
Michael Chanb6016b72005-05-26 13:03:09 -07004741
Michael Chan234754d2006-11-19 14:11:41 -08004742 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4743 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
Michael Chanb6016b72005-05-26 13:03:09 -07004744
Michael Chane503e062012-12-06 10:33:08 +00004745 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004746
Michael Chan234754d2006-11-19 14:11:41 -08004747 } else {
4748 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4749 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4750 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4751
4752 /* Chip reset. */
Michael Chane503e062012-12-06 10:33:08 +00004753 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
Michael Chan234754d2006-11-19 14:11:41 -08004754
Michael Chan594a9df2007-08-28 15:39:42 -07004755 /* Reading back any register after chip reset will hang the
4756 * bus on 5706 A0 and A1. The msleep below provides plenty
4757 * of margin for write posting.
4758 */
Michael Chan4ce45e02012-12-06 10:33:10 +00004759 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
4760 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1))
Arjan van de Ven8e545882007-08-28 14:34:43 -07004761 msleep(20);
Michael Chanb6016b72005-05-26 13:03:09 -07004762
Michael Chan234754d2006-11-19 14:11:41 -08004763 /* Reset takes approximate 30 usec */
4764 for (i = 0; i < 10; i++) {
Michael Chane503e062012-12-06 10:33:08 +00004765 val = BNX2_RD(bp, BNX2_PCICFG_MISC_CONFIG);
Michael Chan234754d2006-11-19 14:11:41 -08004766 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4767 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4768 break;
4769 udelay(10);
4770 }
4771
4772 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4773 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
Joe Perches3a9c6a42010-02-17 15:01:51 +00004774 pr_err("Chip reset did not complete\n");
Michael Chan234754d2006-11-19 14:11:41 -08004775 return -EBUSY;
4776 }
Michael Chanb6016b72005-05-26 13:03:09 -07004777 }
4778
4779 /* Make sure byte swapping is properly configured. */
Michael Chane503e062012-12-06 10:33:08 +00004780 val = BNX2_RD(bp, BNX2_PCI_SWAP_DIAG0);
Michael Chanb6016b72005-05-26 13:03:09 -07004781 if (val != 0x01020304) {
Joe Perches3a9c6a42010-02-17 15:01:51 +00004782 pr_err("Chip not in correct endian mode\n");
Michael Chanb6016b72005-05-26 13:03:09 -07004783 return -ENODEV;
4784 }
4785
Michael Chanb6016b72005-05-26 13:03:09 -07004786 /* Wait for the firmware to finish its initialization. */
Michael Chana2f13892008-07-14 22:38:23 -07004787 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
Michael Chanb090ae22006-01-23 16:07:10 -08004788 if (rc)
4789 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07004790
Michael Chan0d8a6572007-07-07 22:49:43 -07004791 spin_lock_bh(&bp->phy_lock);
Michael Chan489310a2007-10-10 16:16:31 -07004792 old_port = bp->phy_port;
Michael Chan7c62e832008-07-14 22:39:03 -07004793 bnx2_init_fw_cap(bp);
Michael Chan583c28e2008-01-21 19:51:35 -08004794 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4795 old_port != bp->phy_port)
Michael Chan0d8a6572007-07-07 22:49:43 -07004796 bnx2_set_default_remote_link(bp);
4797 spin_unlock_bh(&bp->phy_lock);
4798
Michael Chan4ce45e02012-12-06 10:33:10 +00004799 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
Michael Chanb6016b72005-05-26 13:03:09 -07004800 /* Adjust the voltage regular to two steps lower. The default
4801 * of this register is 0x0000000e. */
Michael Chane503e062012-12-06 10:33:08 +00004802 BNX2_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
Michael Chanb6016b72005-05-26 13:03:09 -07004803
4804 /* Remove bad rbuf memory from the free pool. */
4805 rc = bnx2_alloc_bad_rbuf(bp);
4806 }
4807
Michael Chanc441b8d2010-04-27 11:28:09 +00004808 if (bp->flags & BNX2_FLAG_USING_MSIX) {
Michael Chanb4b36042007-12-20 19:59:30 -08004809 bnx2_setup_msix_tbl(bp);
Michael Chanc441b8d2010-04-27 11:28:09 +00004810 /* Prevent MSIX table reads and write from timing out */
Michael Chane503e062012-12-06 10:33:08 +00004811 BNX2_WR(bp, BNX2_MISC_ECO_HW_CTL,
Michael Chanc441b8d2010-04-27 11:28:09 +00004812 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4813 }
Michael Chanb4b36042007-12-20 19:59:30 -08004814
Michael Chanb6016b72005-05-26 13:03:09 -07004815 return rc;
4816}
4817
4818static int
4819bnx2_init_chip(struct bnx2 *bp)
4820{
Michael Chand8026d92008-11-12 16:02:20 -08004821 u32 val, mtu;
Michael Chanb4b36042007-12-20 19:59:30 -08004822 int rc, i;
Michael Chanb6016b72005-05-26 13:03:09 -07004823
4824 /* Make sure the interrupt is not active. */
Michael Chane503e062012-12-06 10:33:08 +00004825 BNX2_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
Michael Chanb6016b72005-05-26 13:03:09 -07004826
4827 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4828 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4829#ifdef __BIG_ENDIAN
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004830 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
Michael Chanb6016b72005-05-26 13:03:09 -07004831#endif
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004832 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
Michael Chanb6016b72005-05-26 13:03:09 -07004833 DMA_READ_CHANS << 12 |
4834 DMA_WRITE_CHANS << 16;
4835
4836 val |= (0x2 << 20) | (1 << 11);
4837
David S. Millerf86e82f2008-01-21 17:15:40 -08004838 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
Michael Chanb6016b72005-05-26 13:03:09 -07004839 val |= (1 << 23);
4840
Michael Chan4ce45e02012-12-06 10:33:10 +00004841 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) &&
4842 (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0) &&
4843 !(bp->flags & BNX2_FLAG_PCIX))
Michael Chanb6016b72005-05-26 13:03:09 -07004844 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4845
Michael Chane503e062012-12-06 10:33:08 +00004846 BNX2_WR(bp, BNX2_DMA_CONFIG, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004847
Michael Chan4ce45e02012-12-06 10:33:10 +00004848 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
Michael Chane503e062012-12-06 10:33:08 +00004849 val = BNX2_RD(bp, BNX2_TDMA_CONFIG);
Michael Chanb6016b72005-05-26 13:03:09 -07004850 val |= BNX2_TDMA_CONFIG_ONE_DMA;
Michael Chane503e062012-12-06 10:33:08 +00004851 BNX2_WR(bp, BNX2_TDMA_CONFIG, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004852 }
4853
David S. Millerf86e82f2008-01-21 17:15:40 -08004854 if (bp->flags & BNX2_FLAG_PCIX) {
Michael Chanb6016b72005-05-26 13:03:09 -07004855 u16 val16;
4856
4857 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4858 &val16);
4859 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4860 val16 & ~PCI_X_CMD_ERO);
4861 }
4862
Michael Chane503e062012-12-06 10:33:08 +00004863 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4864 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4865 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4866 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
Michael Chanb6016b72005-05-26 13:03:09 -07004867
4868 /* Initialize context mapping and zero out the quick contexts. The
4869 * context block must have already been enabled. */
Michael Chan4ce45e02012-12-06 10:33:10 +00004870 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
Michael Chan641bdcd2007-06-04 21:22:24 -07004871 rc = bnx2_init_5709_context(bp);
4872 if (rc)
4873 return rc;
4874 } else
Michael Chan59b47d82006-11-19 14:10:45 -08004875 bnx2_init_context(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07004876
Michael Chanfba9fe92006-06-12 22:21:25 -07004877 if ((rc = bnx2_init_cpus(bp)) != 0)
4878 return rc;
4879
Michael Chanb6016b72005-05-26 13:03:09 -07004880 bnx2_init_nvram(bp);
4881
Benjamin Li5fcaed02008-07-14 22:39:52 -07004882 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07004883
Michael Chane503e062012-12-06 10:33:08 +00004884 val = BNX2_RD(bp, BNX2_MQ_CONFIG);
Michael Chanb6016b72005-05-26 13:03:09 -07004885 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4886 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
Michael Chan4ce45e02012-12-06 10:33:10 +00004887 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
Michael Chan4edd4732009-06-08 18:14:42 -07004888 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
Michael Chan4ce45e02012-12-06 10:33:10 +00004889 if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)
Michael Chan4edd4732009-06-08 18:14:42 -07004890 val |= BNX2_MQ_CONFIG_HALT_DIS;
4891 }
Michael Chan68c9f752007-04-24 15:35:53 -07004892
Michael Chane503e062012-12-06 10:33:08 +00004893 BNX2_WR(bp, BNX2_MQ_CONFIG, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004894
4895 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
Michael Chane503e062012-12-06 10:33:08 +00004896 BNX2_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4897 BNX2_WR(bp, BNX2_MQ_KNL_WIND_END, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004898
Michael Chan2bc40782012-12-06 10:33:09 +00004899 val = (BNX2_PAGE_BITS - 8) << 24;
Michael Chane503e062012-12-06 10:33:08 +00004900 BNX2_WR(bp, BNX2_RV2P_CONFIG, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004901
4902 /* Configure page size. */
Michael Chane503e062012-12-06 10:33:08 +00004903 val = BNX2_RD(bp, BNX2_TBDR_CONFIG);
Michael Chanb6016b72005-05-26 13:03:09 -07004904 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
Michael Chan2bc40782012-12-06 10:33:09 +00004905 val |= (BNX2_PAGE_BITS - 8) << 24 | 0x40;
Michael Chane503e062012-12-06 10:33:08 +00004906 BNX2_WR(bp, BNX2_TBDR_CONFIG, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004907
4908 val = bp->mac_addr[0] +
4909 (bp->mac_addr[1] << 8) +
4910 (bp->mac_addr[2] << 16) +
4911 bp->mac_addr[3] +
4912 (bp->mac_addr[4] << 8) +
4913 (bp->mac_addr[5] << 16);
Michael Chane503e062012-12-06 10:33:08 +00004914 BNX2_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004915
4916 /* Program the MTU. Also include 4 bytes for CRC32. */
Michael Chand8026d92008-11-12 16:02:20 -08004917 mtu = bp->dev->mtu;
4918 val = mtu + ETH_HLEN + ETH_FCS_LEN;
Michael Chanb6016b72005-05-26 13:03:09 -07004919 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4920 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
Michael Chane503e062012-12-06 10:33:08 +00004921 BNX2_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004922
Michael Chand8026d92008-11-12 16:02:20 -08004923 if (mtu < 1500)
4924 mtu = 1500;
4925
4926 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4927 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4928 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4929
Michael Chan155d5562009-08-21 16:20:43 +00004930 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
Michael Chanb4b36042007-12-20 19:59:30 -08004931 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4932 bp->bnx2_napi[i].last_status_idx = 0;
4933
Michael Chanefba0182008-12-03 00:36:15 -08004934 bp->idle_chk_status_idx = 0xffff;
4935
Michael Chanb6016b72005-05-26 13:03:09 -07004936 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4937
4938 /* Set up how to generate a link change interrupt. */
Michael Chane503e062012-12-06 10:33:08 +00004939 BNX2_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
Michael Chanb6016b72005-05-26 13:03:09 -07004940
Michael Chane503e062012-12-06 10:33:08 +00004941 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_L,
4942 (u64) bp->status_blk_mapping & 0xffffffff);
4943 BNX2_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
Michael Chanb6016b72005-05-26 13:03:09 -07004944
Michael Chane503e062012-12-06 10:33:08 +00004945 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4946 (u64) bp->stats_blk_mapping & 0xffffffff);
4947 BNX2_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4948 (u64) bp->stats_blk_mapping >> 32);
Michael Chanb6016b72005-05-26 13:03:09 -07004949
Michael Chane503e062012-12-06 10:33:08 +00004950 BNX2_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4951 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
Michael Chanb6016b72005-05-26 13:03:09 -07004952
Michael Chane503e062012-12-06 10:33:08 +00004953 BNX2_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4954 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
Michael Chanb6016b72005-05-26 13:03:09 -07004955
Michael Chane503e062012-12-06 10:33:08 +00004956 BNX2_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4957 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
Michael Chanb6016b72005-05-26 13:03:09 -07004958
Michael Chane503e062012-12-06 10:33:08 +00004959 BNX2_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
Michael Chanb6016b72005-05-26 13:03:09 -07004960
Michael Chane503e062012-12-06 10:33:08 +00004961 BNX2_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
Michael Chanb6016b72005-05-26 13:03:09 -07004962
Michael Chane503e062012-12-06 10:33:08 +00004963 BNX2_WR(bp, BNX2_HC_COM_TICKS,
4964 (bp->com_ticks_int << 16) | bp->com_ticks);
Michael Chanb6016b72005-05-26 13:03:09 -07004965
Michael Chane503e062012-12-06 10:33:08 +00004966 BNX2_WR(bp, BNX2_HC_CMD_TICKS,
4967 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
Michael Chanb6016b72005-05-26 13:03:09 -07004968
Michael Chan61d9e3f2009-08-21 16:20:46 +00004969 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
Michael Chane503e062012-12-06 10:33:08 +00004970 BNX2_WR(bp, BNX2_HC_STATS_TICKS, 0);
Michael Chan02537b062007-06-04 21:24:07 -07004971 else
Michael Chane503e062012-12-06 10:33:08 +00004972 BNX2_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4973 BNX2_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
Michael Chanb6016b72005-05-26 13:03:09 -07004974
Michael Chan4ce45e02012-12-06 10:33:10 +00004975 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1)
Michael Chan8e6a72c2007-05-03 13:24:48 -07004976 val = BNX2_HC_CONFIG_COLLECT_STATS;
Michael Chanb6016b72005-05-26 13:03:09 -07004977 else {
Michael Chan8e6a72c2007-05-03 13:24:48 -07004978 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4979 BNX2_HC_CONFIG_COLLECT_STATS;
Michael Chanb6016b72005-05-26 13:03:09 -07004980 }
4981
Michael Chanefde73a2010-02-15 19:42:07 +00004982 if (bp->flags & BNX2_FLAG_USING_MSIX) {
Michael Chane503e062012-12-06 10:33:08 +00004983 BNX2_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4984 BNX2_HC_MSIX_BIT_VECTOR_VAL);
Michael Chanc76c0472007-12-20 20:01:19 -08004985
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004986 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4987 }
4988
4989 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
Michael Chancf7474a2009-08-21 16:20:48 +00004990 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004991
Michael Chane503e062012-12-06 10:33:08 +00004992 BNX2_WR(bp, BNX2_HC_CONFIG, val);
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004993
Michael Chan22fa1592010-10-11 16:12:00 -07004994 if (bp->rx_ticks < 25)
4995 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 1);
4996 else
4997 bnx2_reg_wr_ind(bp, BNX2_FW_RX_LOW_LATENCY, 0);
4998
Michael Chan5e9ad9e2008-06-19 16:43:17 -07004999 for (i = 1; i < bp->irq_nvecs; i++) {
5000 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
5001 BNX2_HC_SB_CONFIG_1;
5002
Michael Chane503e062012-12-06 10:33:08 +00005003 BNX2_WR(bp, base,
Michael Chanc76c0472007-12-20 20:01:19 -08005004 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005005 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
Michael Chanc76c0472007-12-20 20:01:19 -08005006 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
5007
Michael Chane503e062012-12-06 10:33:08 +00005008 BNX2_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
Michael Chanc76c0472007-12-20 20:01:19 -08005009 (bp->tx_quick_cons_trip_int << 16) |
5010 bp->tx_quick_cons_trip);
5011
Michael Chane503e062012-12-06 10:33:08 +00005012 BNX2_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
Michael Chanc76c0472007-12-20 20:01:19 -08005013 (bp->tx_ticks_int << 16) | bp->tx_ticks);
5014
Michael Chane503e062012-12-06 10:33:08 +00005015 BNX2_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
5016 (bp->rx_quick_cons_trip_int << 16) |
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005017 bp->rx_quick_cons_trip);
5018
Michael Chane503e062012-12-06 10:33:08 +00005019 BNX2_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005020 (bp->rx_ticks_int << 16) | bp->rx_ticks);
Michael Chanc76c0472007-12-20 20:01:19 -08005021 }
5022
Michael Chanb6016b72005-05-26 13:03:09 -07005023 /* Clear internal stats counters. */
Michael Chane503e062012-12-06 10:33:08 +00005024 BNX2_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
Michael Chanb6016b72005-05-26 13:03:09 -07005025
Michael Chane503e062012-12-06 10:33:08 +00005026 BNX2_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
Michael Chanb6016b72005-05-26 13:03:09 -07005027
5028 /* Initialize the receive filter. */
5029 bnx2_set_rx_mode(bp->dev);
5030
Michael Chan4ce45e02012-12-06 10:33:10 +00005031 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
Michael Chane503e062012-12-06 10:33:08 +00005032 val = BNX2_RD(bp, BNX2_MISC_NEW_CORE_CTL);
Michael Chan0aa38df2007-06-04 21:23:06 -07005033 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
Michael Chane503e062012-12-06 10:33:08 +00005034 BNX2_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
Michael Chan0aa38df2007-06-04 21:23:06 -07005035 }
Michael Chanb090ae22006-01-23 16:07:10 -08005036 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
Michael Chana2f13892008-07-14 22:38:23 -07005037 1, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07005038
Michael Chane503e062012-12-06 10:33:08 +00005039 BNX2_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
5040 BNX2_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
Michael Chanb6016b72005-05-26 13:03:09 -07005041
5042 udelay(20);
5043
Michael Chane503e062012-12-06 10:33:08 +00005044 bp->hc_cmd = BNX2_RD(bp, BNX2_HC_COMMAND);
Michael Chanbf5295b2006-03-23 01:11:56 -08005045
Michael Chanb090ae22006-01-23 16:07:10 -08005046 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07005047}
5048
Michael Chan59b47d82006-11-19 14:10:45 -08005049static void
Michael Chanc76c0472007-12-20 20:01:19 -08005050bnx2_clear_ring_states(struct bnx2 *bp)
5051{
5052 struct bnx2_napi *bnapi;
Michael Chan35e90102008-06-19 16:37:42 -07005053 struct bnx2_tx_ring_info *txr;
Michael Chanbb4f98a2008-06-19 16:38:19 -07005054 struct bnx2_rx_ring_info *rxr;
Michael Chanc76c0472007-12-20 20:01:19 -08005055 int i;
5056
5057 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5058 bnapi = &bp->bnx2_napi[i];
Michael Chan35e90102008-06-19 16:37:42 -07005059 txr = &bnapi->tx_ring;
Michael Chanbb4f98a2008-06-19 16:38:19 -07005060 rxr = &bnapi->rx_ring;
Michael Chanc76c0472007-12-20 20:01:19 -08005061
Michael Chan35e90102008-06-19 16:37:42 -07005062 txr->tx_cons = 0;
5063 txr->hw_tx_cons = 0;
Michael Chanbb4f98a2008-06-19 16:38:19 -07005064 rxr->rx_prod_bseq = 0;
5065 rxr->rx_prod = 0;
5066 rxr->rx_cons = 0;
5067 rxr->rx_pg_prod = 0;
5068 rxr->rx_pg_cons = 0;
Michael Chanc76c0472007-12-20 20:01:19 -08005069 }
5070}
5071
5072static void
Michael Chan35e90102008-06-19 16:37:42 -07005073bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
Michael Chan59b47d82006-11-19 14:10:45 -08005074{
5075 u32 val, offset0, offset1, offset2, offset3;
Michael Chan62a83132008-01-29 21:35:40 -08005076 u32 cid_addr = GET_CID_ADDR(cid);
Michael Chan59b47d82006-11-19 14:10:45 -08005077
Michael Chan4ce45e02012-12-06 10:33:10 +00005078 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
Michael Chan59b47d82006-11-19 14:10:45 -08005079 offset0 = BNX2_L2CTX_TYPE_XI;
5080 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5081 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5082 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5083 } else {
5084 offset0 = BNX2_L2CTX_TYPE;
5085 offset1 = BNX2_L2CTX_CMD_TYPE;
5086 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5087 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5088 }
5089 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
Michael Chan62a83132008-01-29 21:35:40 -08005090 bnx2_ctx_wr(bp, cid_addr, offset0, val);
Michael Chan59b47d82006-11-19 14:10:45 -08005091
5092 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
Michael Chan62a83132008-01-29 21:35:40 -08005093 bnx2_ctx_wr(bp, cid_addr, offset1, val);
Michael Chan59b47d82006-11-19 14:10:45 -08005094
Michael Chan35e90102008-06-19 16:37:42 -07005095 val = (u64) txr->tx_desc_mapping >> 32;
Michael Chan62a83132008-01-29 21:35:40 -08005096 bnx2_ctx_wr(bp, cid_addr, offset2, val);
Michael Chan59b47d82006-11-19 14:10:45 -08005097
Michael Chan35e90102008-06-19 16:37:42 -07005098 val = (u64) txr->tx_desc_mapping & 0xffffffff;
Michael Chan62a83132008-01-29 21:35:40 -08005099 bnx2_ctx_wr(bp, cid_addr, offset3, val);
Michael Chan59b47d82006-11-19 14:10:45 -08005100}
Michael Chanb6016b72005-05-26 13:03:09 -07005101
5102static void
Michael Chan35e90102008-06-19 16:37:42 -07005103bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
Michael Chanb6016b72005-05-26 13:03:09 -07005104{
Michael Chan2bc40782012-12-06 10:33:09 +00005105 struct bnx2_tx_bd *txbd;
Michael Chanc76c0472007-12-20 20:01:19 -08005106 u32 cid = TX_CID;
5107 struct bnx2_napi *bnapi;
Michael Chan35e90102008-06-19 16:37:42 -07005108 struct bnx2_tx_ring_info *txr;
Michael Chanc76c0472007-12-20 20:01:19 -08005109
Michael Chan35e90102008-06-19 16:37:42 -07005110 bnapi = &bp->bnx2_napi[ring_num];
5111 txr = &bnapi->tx_ring;
5112
5113 if (ring_num == 0)
5114 cid = TX_CID;
5115 else
5116 cid = TX_TSS_CID + ring_num - 1;
Michael Chanb6016b72005-05-26 13:03:09 -07005117
Michael Chan2f8af122006-08-15 01:39:10 -07005118 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5119
Michael Chan2bc40782012-12-06 10:33:09 +00005120 txbd = &txr->tx_desc_ring[BNX2_MAX_TX_DESC_CNT];
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005121
Michael Chan35e90102008-06-19 16:37:42 -07005122 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5123 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
Michael Chanb6016b72005-05-26 13:03:09 -07005124
Michael Chan35e90102008-06-19 16:37:42 -07005125 txr->tx_prod = 0;
5126 txr->tx_prod_bseq = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005127
Michael Chan35e90102008-06-19 16:37:42 -07005128 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5129 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
Michael Chanb6016b72005-05-26 13:03:09 -07005130
Michael Chan35e90102008-06-19 16:37:42 -07005131 bnx2_init_tx_context(bp, cid, txr);
Michael Chanb6016b72005-05-26 13:03:09 -07005132}
5133
5134static void
Michael Chan2bc40782012-12-06 10:33:09 +00005135bnx2_init_rxbd_rings(struct bnx2_rx_bd *rx_ring[], dma_addr_t dma[],
5136 u32 buf_size, int num_rings)
Michael Chanb6016b72005-05-26 13:03:09 -07005137{
Michael Chanb6016b72005-05-26 13:03:09 -07005138 int i;
Michael Chan2bc40782012-12-06 10:33:09 +00005139 struct bnx2_rx_bd *rxbd;
Michael Chanb6016b72005-05-26 13:03:09 -07005140
Michael Chan5d5d0012007-12-12 11:17:43 -08005141 for (i = 0; i < num_rings; i++) {
Michael Chan13daffa2006-03-20 17:49:20 -08005142 int j;
Michael Chanb6016b72005-05-26 13:03:09 -07005143
Michael Chan5d5d0012007-12-12 11:17:43 -08005144 rxbd = &rx_ring[i][0];
Michael Chan2bc40782012-12-06 10:33:09 +00005145 for (j = 0; j < BNX2_MAX_RX_DESC_CNT; j++, rxbd++) {
Michael Chan5d5d0012007-12-12 11:17:43 -08005146 rxbd->rx_bd_len = buf_size;
Michael Chan13daffa2006-03-20 17:49:20 -08005147 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5148 }
Michael Chan5d5d0012007-12-12 11:17:43 -08005149 if (i == (num_rings - 1))
Michael Chan13daffa2006-03-20 17:49:20 -08005150 j = 0;
5151 else
5152 j = i + 1;
Michael Chan5d5d0012007-12-12 11:17:43 -08005153 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5154 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
Michael Chan13daffa2006-03-20 17:49:20 -08005155 }
Michael Chan5d5d0012007-12-12 11:17:43 -08005156}
5157
5158static void
Michael Chanbb4f98a2008-06-19 16:38:19 -07005159bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
Michael Chan5d5d0012007-12-12 11:17:43 -08005160{
5161 int i;
5162 u16 prod, ring_prod;
Michael Chanbb4f98a2008-06-19 16:38:19 -07005163 u32 cid, rx_cid_addr, val;
5164 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5165 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
Michael Chan5d5d0012007-12-12 11:17:43 -08005166
Michael Chanbb4f98a2008-06-19 16:38:19 -07005167 if (ring_num == 0)
5168 cid = RX_CID;
5169 else
5170 cid = RX_RSS_CID + ring_num - 1;
5171
5172 rx_cid_addr = GET_CID_ADDR(cid);
5173
5174 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
Michael Chan5d5d0012007-12-12 11:17:43 -08005175 bp->rx_buf_use_size, bp->rx_max_ring);
5176
Michael Chanbb4f98a2008-06-19 16:38:19 -07005177 bnx2_init_rx_context(bp, cid);
Michael Chan83e3fc82008-01-29 21:37:17 -08005178
Michael Chan4ce45e02012-12-06 10:33:10 +00005179 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
Michael Chane503e062012-12-06 10:33:08 +00005180 val = BNX2_RD(bp, BNX2_MQ_MAP_L2_5);
5181 BNX2_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
Michael Chan83e3fc82008-01-29 21:37:17 -08005182 }
5183
Michael Chan62a83132008-01-29 21:35:40 -08005184 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
Michael Chan47bf4242007-12-12 11:19:12 -08005185 if (bp->rx_pg_ring_size) {
Michael Chanbb4f98a2008-06-19 16:38:19 -07005186 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5187 rxr->rx_pg_desc_mapping,
Michael Chan47bf4242007-12-12 11:19:12 -08005188 PAGE_SIZE, bp->rx_max_pg_ring);
5189 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
Michael Chan62a83132008-01-29 21:35:40 -08005190 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5191 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005192 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
Michael Chan47bf4242007-12-12 11:19:12 -08005193
Michael Chanbb4f98a2008-06-19 16:38:19 -07005194 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
Michael Chan62a83132008-01-29 21:35:40 -08005195 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
Michael Chan47bf4242007-12-12 11:19:12 -08005196
Michael Chanbb4f98a2008-06-19 16:38:19 -07005197 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
Michael Chan62a83132008-01-29 21:35:40 -08005198 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
Michael Chan47bf4242007-12-12 11:19:12 -08005199
Michael Chan4ce45e02012-12-06 10:33:10 +00005200 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
Michael Chane503e062012-12-06 10:33:08 +00005201 BNX2_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
Michael Chan47bf4242007-12-12 11:19:12 -08005202 }
Michael Chanb6016b72005-05-26 13:03:09 -07005203
Michael Chanbb4f98a2008-06-19 16:38:19 -07005204 val = (u64) rxr->rx_desc_mapping[0] >> 32;
Michael Chan62a83132008-01-29 21:35:40 -08005205 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
Michael Chanb6016b72005-05-26 13:03:09 -07005206
Michael Chanbb4f98a2008-06-19 16:38:19 -07005207 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
Michael Chan62a83132008-01-29 21:35:40 -08005208 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
Michael Chanb6016b72005-05-26 13:03:09 -07005209
Michael Chanbb4f98a2008-06-19 16:38:19 -07005210 ring_prod = prod = rxr->rx_pg_prod;
Michael Chan47bf4242007-12-12 11:19:12 -08005211 for (i = 0; i < bp->rx_pg_ring_size; i++) {
Stanislaw Gruszkaa2df00a2010-07-15 22:55:40 +00005212 if (bnx2_alloc_rx_page(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
Joe Perches3a9c6a42010-02-17 15:01:51 +00005213 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5214 ring_num, i, bp->rx_pg_ring_size);
Michael Chan47bf4242007-12-12 11:19:12 -08005215 break;
Michael Chanb929e532009-12-03 09:46:33 +00005216 }
Michael Chan2bc40782012-12-06 10:33:09 +00005217 prod = BNX2_NEXT_RX_BD(prod);
5218 ring_prod = BNX2_RX_PG_RING_IDX(prod);
Michael Chan47bf4242007-12-12 11:19:12 -08005219 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07005220 rxr->rx_pg_prod = prod;
Michael Chan47bf4242007-12-12 11:19:12 -08005221
Michael Chanbb4f98a2008-06-19 16:38:19 -07005222 ring_prod = prod = rxr->rx_prod;
Michael Chan236b6392006-03-20 17:49:02 -08005223 for (i = 0; i < bp->rx_ring_size; i++) {
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00005224 if (bnx2_alloc_rx_data(bp, rxr, ring_prod, GFP_KERNEL) < 0) {
Joe Perches3a9c6a42010-02-17 15:01:51 +00005225 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5226 ring_num, i, bp->rx_ring_size);
Michael Chanb6016b72005-05-26 13:03:09 -07005227 break;
Michael Chanb929e532009-12-03 09:46:33 +00005228 }
Michael Chan2bc40782012-12-06 10:33:09 +00005229 prod = BNX2_NEXT_RX_BD(prod);
5230 ring_prod = BNX2_RX_RING_IDX(prod);
Michael Chanb6016b72005-05-26 13:03:09 -07005231 }
Michael Chanbb4f98a2008-06-19 16:38:19 -07005232 rxr->rx_prod = prod;
Michael Chanb6016b72005-05-26 13:03:09 -07005233
Michael Chanbb4f98a2008-06-19 16:38:19 -07005234 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5235 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5236 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
Michael Chanb6016b72005-05-26 13:03:09 -07005237
Michael Chane503e062012-12-06 10:33:08 +00005238 BNX2_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5239 BNX2_WR16(bp, rxr->rx_bidx_addr, prod);
Michael Chanbb4f98a2008-06-19 16:38:19 -07005240
Michael Chane503e062012-12-06 10:33:08 +00005241 BNX2_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07005242}
5243
Michael Chan35e90102008-06-19 16:37:42 -07005244static void
5245bnx2_init_all_rings(struct bnx2 *bp)
5246{
5247 int i;
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005248 u32 val;
Michael Chan35e90102008-06-19 16:37:42 -07005249
5250 bnx2_clear_ring_states(bp);
5251
Michael Chane503e062012-12-06 10:33:08 +00005252 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, 0);
Michael Chan35e90102008-06-19 16:37:42 -07005253 for (i = 0; i < bp->num_tx_rings; i++)
5254 bnx2_init_tx_ring(bp, i);
5255
5256 if (bp->num_tx_rings > 1)
Michael Chane503e062012-12-06 10:33:08 +00005257 BNX2_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5258 (TX_TSS_CID << 7));
Michael Chan35e90102008-06-19 16:37:42 -07005259
Michael Chane503e062012-12-06 10:33:08 +00005260 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005261 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5262
Michael Chanbb4f98a2008-06-19 16:38:19 -07005263 for (i = 0; i < bp->num_rx_rings; i++)
5264 bnx2_init_rx_ring(bp, i);
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005265
5266 if (bp->num_rx_rings > 1) {
Michael Chan22fa1592010-10-11 16:12:00 -07005267 u32 tbl_32 = 0;
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005268
5269 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
Michael Chan22fa1592010-10-11 16:12:00 -07005270 int shift = (i % 8) << 2;
5271
5272 tbl_32 |= (i % (bp->num_rx_rings - 1)) << shift;
5273 if ((i % 8) == 7) {
Michael Chane503e062012-12-06 10:33:08 +00005274 BNX2_WR(bp, BNX2_RLUP_RSS_DATA, tbl_32);
5275 BNX2_WR(bp, BNX2_RLUP_RSS_COMMAND, (i >> 3) |
Michael Chan22fa1592010-10-11 16:12:00 -07005276 BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK |
5277 BNX2_RLUP_RSS_COMMAND_WRITE |
5278 BNX2_RLUP_RSS_COMMAND_HASH_MASK);
5279 tbl_32 = 0;
5280 }
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005281 }
5282
5283 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5284 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5285
Michael Chane503e062012-12-06 10:33:08 +00005286 BNX2_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
Michael Chan5e9ad9e2008-06-19 16:43:17 -07005287
5288 }
Michael Chan35e90102008-06-19 16:37:42 -07005289}
5290
Michael Chan5d5d0012007-12-12 11:17:43 -08005291static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
Michael Chan13daffa2006-03-20 17:49:20 -08005292{
Michael Chan5d5d0012007-12-12 11:17:43 -08005293 u32 max, num_rings = 1;
Michael Chan13daffa2006-03-20 17:49:20 -08005294
Michael Chan2bc40782012-12-06 10:33:09 +00005295 while (ring_size > BNX2_MAX_RX_DESC_CNT) {
5296 ring_size -= BNX2_MAX_RX_DESC_CNT;
Michael Chan13daffa2006-03-20 17:49:20 -08005297 num_rings++;
5298 }
5299 /* round to next power of 2 */
Michael Chan5d5d0012007-12-12 11:17:43 -08005300 max = max_size;
Michael Chan13daffa2006-03-20 17:49:20 -08005301 while ((max & num_rings) == 0)
5302 max >>= 1;
5303
5304 if (num_rings != max)
5305 max <<= 1;
5306
Michael Chan5d5d0012007-12-12 11:17:43 -08005307 return max;
5308}
5309
5310static void
5311bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5312{
Michael Chan84eaa182007-12-12 11:19:57 -08005313 u32 rx_size, rx_space, jumbo_size;
Michael Chan5d5d0012007-12-12 11:17:43 -08005314
5315 /* 8 for CRC and VLAN */
Benjamin Lid89cb6a2008-05-16 22:18:57 -07005316 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
Michael Chan5d5d0012007-12-12 11:17:43 -08005317
Michael Chan84eaa182007-12-12 11:19:57 -08005318 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00005319 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
Michael Chan84eaa182007-12-12 11:19:57 -08005320
Benjamin Li601d3d12008-05-16 22:19:35 -07005321 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
Michael Chan47bf4242007-12-12 11:19:12 -08005322 bp->rx_pg_ring_size = 0;
5323 bp->rx_max_pg_ring = 0;
5324 bp->rx_max_pg_ring_idx = 0;
David S. Millerf86e82f2008-01-21 17:15:40 -08005325 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
Michael Chan84eaa182007-12-12 11:19:57 -08005326 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5327
5328 jumbo_size = size * pages;
Michael Chan2bc40782012-12-06 10:33:09 +00005329 if (jumbo_size > BNX2_MAX_TOTAL_RX_PG_DESC_CNT)
5330 jumbo_size = BNX2_MAX_TOTAL_RX_PG_DESC_CNT;
Michael Chan84eaa182007-12-12 11:19:57 -08005331
5332 bp->rx_pg_ring_size = jumbo_size;
5333 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
Michael Chan2bc40782012-12-06 10:33:09 +00005334 BNX2_MAX_RX_PG_RINGS);
5335 bp->rx_max_pg_ring_idx =
5336 (bp->rx_max_pg_ring * BNX2_RX_DESC_CNT) - 1;
Benjamin Li601d3d12008-05-16 22:19:35 -07005337 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
Michael Chan84eaa182007-12-12 11:19:57 -08005338 bp->rx_copy_thresh = 0;
5339 }
Michael Chan5d5d0012007-12-12 11:17:43 -08005340
5341 bp->rx_buf_use_size = rx_size;
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00005342 /* hw alignment + build_skb() overhead*/
5343 bp->rx_buf_size = SKB_DATA_ALIGN(bp->rx_buf_use_size + BNX2_RX_ALIGN) +
5344 NET_SKB_PAD + SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
Benjamin Lid89cb6a2008-05-16 22:18:57 -07005345 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
Michael Chan5d5d0012007-12-12 11:17:43 -08005346 bp->rx_ring_size = size;
Michael Chan2bc40782012-12-06 10:33:09 +00005347 bp->rx_max_ring = bnx2_find_max_ring(size, BNX2_MAX_RX_RINGS);
5348 bp->rx_max_ring_idx = (bp->rx_max_ring * BNX2_RX_DESC_CNT) - 1;
Michael Chan13daffa2006-03-20 17:49:20 -08005349}
5350
5351static void
Michael Chanb6016b72005-05-26 13:03:09 -07005352bnx2_free_tx_skbs(struct bnx2 *bp)
5353{
5354 int i;
5355
Michael Chan35e90102008-06-19 16:37:42 -07005356 for (i = 0; i < bp->num_tx_rings; i++) {
5357 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5358 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5359 int j;
Michael Chanb6016b72005-05-26 13:03:09 -07005360
Michael Chan35e90102008-06-19 16:37:42 -07005361 if (txr->tx_buf_ring == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -07005362 continue;
Michael Chanb6016b72005-05-26 13:03:09 -07005363
Michael Chan2bc40782012-12-06 10:33:09 +00005364 for (j = 0; j < BNX2_TX_DESC_CNT; ) {
5365 struct bnx2_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
Michael Chan35e90102008-06-19 16:37:42 -07005366 struct sk_buff *skb = tx_buf->skb;
Alexander Duycke95524a2009-12-02 16:47:57 +00005367 int k, last;
Michael Chan35e90102008-06-19 16:37:42 -07005368
5369 if (skb == NULL) {
Michael Chan2bc40782012-12-06 10:33:09 +00005370 j = BNX2_NEXT_TX_BD(j);
Michael Chan35e90102008-06-19 16:37:42 -07005371 continue;
5372 }
5373
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00005374 dma_unmap_single(&bp->pdev->dev,
FUJITA Tomonori1a4ccc22010-04-01 16:56:57 +00005375 dma_unmap_addr(tx_buf, mapping),
Alexander Duycke95524a2009-12-02 16:47:57 +00005376 skb_headlen(skb),
5377 PCI_DMA_TODEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07005378
Michael Chan35e90102008-06-19 16:37:42 -07005379 tx_buf->skb = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07005380
Alexander Duycke95524a2009-12-02 16:47:57 +00005381 last = tx_buf->nr_frags;
Michael Chan2bc40782012-12-06 10:33:09 +00005382 j = BNX2_NEXT_TX_BD(j);
5383 for (k = 0; k < last; k++, j = BNX2_NEXT_TX_BD(j)) {
5384 tx_buf = &txr->tx_buf_ring[BNX2_TX_RING_IDX(j)];
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00005385 dma_unmap_page(&bp->pdev->dev,
FUJITA Tomonori1a4ccc22010-04-01 16:56:57 +00005386 dma_unmap_addr(tx_buf, mapping),
Eric Dumazet9e903e02011-10-18 21:00:24 +00005387 skb_frag_size(&skb_shinfo(skb)->frags[k]),
Alexander Duycke95524a2009-12-02 16:47:57 +00005388 PCI_DMA_TODEVICE);
5389 }
Michael Chan35e90102008-06-19 16:37:42 -07005390 dev_kfree_skb(skb);
Michael Chanb6016b72005-05-26 13:03:09 -07005391 }
Eric Dumazete9831902011-11-29 11:53:05 +00005392 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
Michael Chanb6016b72005-05-26 13:03:09 -07005393 }
Michael Chanb6016b72005-05-26 13:03:09 -07005394}
5395
5396static void
5397bnx2_free_rx_skbs(struct bnx2 *bp)
5398{
5399 int i;
5400
Michael Chanbb4f98a2008-06-19 16:38:19 -07005401 for (i = 0; i < bp->num_rx_rings; i++) {
5402 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5403 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5404 int j;
Michael Chanb6016b72005-05-26 13:03:09 -07005405
Michael Chanbb4f98a2008-06-19 16:38:19 -07005406 if (rxr->rx_buf_ring == NULL)
5407 return;
Michael Chanb6016b72005-05-26 13:03:09 -07005408
Michael Chanbb4f98a2008-06-19 16:38:19 -07005409 for (j = 0; j < bp->rx_max_ring_idx; j++) {
Michael Chan2bc40782012-12-06 10:33:09 +00005410 struct bnx2_sw_bd *rx_buf = &rxr->rx_buf_ring[j];
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00005411 u8 *data = rx_buf->data;
Michael Chanb6016b72005-05-26 13:03:09 -07005412
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00005413 if (data == NULL)
Michael Chanbb4f98a2008-06-19 16:38:19 -07005414 continue;
Michael Chanb6016b72005-05-26 13:03:09 -07005415
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00005416 dma_unmap_single(&bp->pdev->dev,
FUJITA Tomonori1a4ccc22010-04-01 16:56:57 +00005417 dma_unmap_addr(rx_buf, mapping),
Michael Chanbb4f98a2008-06-19 16:38:19 -07005418 bp->rx_buf_use_size,
5419 PCI_DMA_FROMDEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07005420
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00005421 rx_buf->data = NULL;
Michael Chanbb4f98a2008-06-19 16:38:19 -07005422
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00005423 kfree(data);
Michael Chanbb4f98a2008-06-19 16:38:19 -07005424 }
5425 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5426 bnx2_free_rx_page(bp, rxr, j);
Michael Chanb6016b72005-05-26 13:03:09 -07005427 }
5428}
5429
5430static void
5431bnx2_free_skbs(struct bnx2 *bp)
5432{
5433 bnx2_free_tx_skbs(bp);
5434 bnx2_free_rx_skbs(bp);
5435}
5436
5437static int
5438bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5439{
5440 int rc;
5441
5442 rc = bnx2_reset_chip(bp, reset_code);
5443 bnx2_free_skbs(bp);
5444 if (rc)
5445 return rc;
5446
Michael Chanfba9fe92006-06-12 22:21:25 -07005447 if ((rc = bnx2_init_chip(bp)) != 0)
5448 return rc;
5449
Michael Chan35e90102008-06-19 16:37:42 -07005450 bnx2_init_all_rings(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07005451 return 0;
5452}
5453
5454static int
Michael Chan9a120bc2008-05-16 22:17:45 -07005455bnx2_init_nic(struct bnx2 *bp, int reset_phy)
Michael Chanb6016b72005-05-26 13:03:09 -07005456{
5457 int rc;
5458
5459 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5460 return rc;
5461
Michael Chan80be4432006-11-19 14:07:28 -08005462 spin_lock_bh(&bp->phy_lock);
Michael Chan9a120bc2008-05-16 22:17:45 -07005463 bnx2_init_phy(bp, reset_phy);
Michael Chanb6016b72005-05-26 13:03:09 -07005464 bnx2_set_link(bp);
Michael Chan543a8272008-05-02 16:56:44 -07005465 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5466 bnx2_remote_phy_event(bp);
Michael Chan0d8a6572007-07-07 22:49:43 -07005467 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07005468 return 0;
5469}
5470
5471static int
Michael Chan74bf4ba2008-10-09 12:21:08 -07005472bnx2_shutdown_chip(struct bnx2 *bp)
5473{
5474 u32 reset_code;
5475
5476 if (bp->flags & BNX2_FLAG_NO_WOL)
5477 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5478 else if (bp->wol)
5479 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5480 else
5481 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5482
5483 return bnx2_reset_chip(bp, reset_code);
5484}
5485
5486static int
Michael Chanb6016b72005-05-26 13:03:09 -07005487bnx2_test_registers(struct bnx2 *bp)
5488{
5489 int ret;
Michael Chan5bae30c2007-05-03 13:18:46 -07005490 int i, is_5709;
Arjan van de Venf71e1302006-03-03 21:33:57 -05005491 static const struct {
Michael Chanb6016b72005-05-26 13:03:09 -07005492 u16 offset;
5493 u16 flags;
Michael Chan5bae30c2007-05-03 13:18:46 -07005494#define BNX2_FL_NOT_5709 1
Michael Chanb6016b72005-05-26 13:03:09 -07005495 u32 rw_mask;
5496 u32 ro_mask;
5497 } reg_tbl[] = {
5498 { 0x006c, 0, 0x00000000, 0x0000003f },
5499 { 0x0090, 0, 0xffffffff, 0x00000000 },
5500 { 0x0094, 0, 0x00000000, 0x00000000 },
5501
Michael Chan5bae30c2007-05-03 13:18:46 -07005502 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5503 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5504 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5505 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5506 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5507 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5508 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5509 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5510 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
Michael Chanb6016b72005-05-26 13:03:09 -07005511
Michael Chan5bae30c2007-05-03 13:18:46 -07005512 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5513 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5514 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5515 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5516 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5517 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
Michael Chanb6016b72005-05-26 13:03:09 -07005518
Michael Chan5bae30c2007-05-03 13:18:46 -07005519 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5520 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5521 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005522
5523 { 0x1000, 0, 0x00000000, 0x00000001 },
Michael Chan15b169c2008-05-02 16:57:08 -07005524 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
Michael Chanb6016b72005-05-26 13:03:09 -07005525
5526 { 0x1408, 0, 0x01c00800, 0x00000000 },
5527 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5528 { 0x14a8, 0, 0x00000000, 0x000001ff },
Michael Chan5b0c76a2005-11-04 08:45:49 -08005529 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005530 { 0x14b0, 0, 0x00000002, 0x00000001 },
5531 { 0x14b8, 0, 0x00000000, 0x00000000 },
5532 { 0x14c0, 0, 0x00000000, 0x00000009 },
5533 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5534 { 0x14cc, 0, 0x00000000, 0x00000001 },
5535 { 0x14d0, 0, 0xffffffff, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005536
5537 { 0x1800, 0, 0x00000000, 0x00000001 },
5538 { 0x1804, 0, 0x00000000, 0x00000003 },
Michael Chanb6016b72005-05-26 13:03:09 -07005539
5540 { 0x2800, 0, 0x00000000, 0x00000001 },
5541 { 0x2804, 0, 0x00000000, 0x00003f01 },
5542 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5543 { 0x2810, 0, 0xffff0000, 0x00000000 },
5544 { 0x2814, 0, 0xffff0000, 0x00000000 },
5545 { 0x2818, 0, 0xffff0000, 0x00000000 },
5546 { 0x281c, 0, 0xffff0000, 0x00000000 },
5547 { 0x2834, 0, 0xffffffff, 0x00000000 },
5548 { 0x2840, 0, 0x00000000, 0xffffffff },
5549 { 0x2844, 0, 0x00000000, 0xffffffff },
5550 { 0x2848, 0, 0xffffffff, 0x00000000 },
5551 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5552
5553 { 0x2c00, 0, 0x00000000, 0x00000011 },
5554 { 0x2c04, 0, 0x00000000, 0x00030007 },
5555
Michael Chanb6016b72005-05-26 13:03:09 -07005556 { 0x3c00, 0, 0x00000000, 0x00000001 },
5557 { 0x3c04, 0, 0x00000000, 0x00070000 },
5558 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5559 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5560 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5561 { 0x3c14, 0, 0x00000000, 0xffffffff },
5562 { 0x3c18, 0, 0x00000000, 0xffffffff },
5563 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5564 { 0x3c20, 0, 0xffffff00, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005565
5566 { 0x5004, 0, 0x00000000, 0x0000007f },
5567 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005568
Michael Chanb6016b72005-05-26 13:03:09 -07005569 { 0x5c00, 0, 0x00000000, 0x00000001 },
5570 { 0x5c04, 0, 0x00000000, 0x0003000f },
5571 { 0x5c08, 0, 0x00000003, 0x00000000 },
5572 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5573 { 0x5c10, 0, 0x00000000, 0xffffffff },
5574 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5575 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5576 { 0x5c88, 0, 0x00000000, 0x00077373 },
5577 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5578
5579 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5580 { 0x680c, 0, 0xffffffff, 0x00000000 },
5581 { 0x6810, 0, 0xffffffff, 0x00000000 },
5582 { 0x6814, 0, 0xffffffff, 0x00000000 },
5583 { 0x6818, 0, 0xffffffff, 0x00000000 },
5584 { 0x681c, 0, 0xffffffff, 0x00000000 },
5585 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5586 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5587 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5588 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5589 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5590 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5591 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5592 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5593 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5594 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5595 { 0x684c, 0, 0xffffffff, 0x00000000 },
5596 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5597 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5598 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5599 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5600 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5601 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5602
5603 { 0xffff, 0, 0x00000000, 0x00000000 },
5604 };
5605
5606 ret = 0;
Michael Chan5bae30c2007-05-03 13:18:46 -07005607 is_5709 = 0;
Michael Chan4ce45e02012-12-06 10:33:10 +00005608 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
Michael Chan5bae30c2007-05-03 13:18:46 -07005609 is_5709 = 1;
5610
Michael Chanb6016b72005-05-26 13:03:09 -07005611 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5612 u32 offset, rw_mask, ro_mask, save_val, val;
Michael Chan5bae30c2007-05-03 13:18:46 -07005613 u16 flags = reg_tbl[i].flags;
5614
5615 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5616 continue;
Michael Chanb6016b72005-05-26 13:03:09 -07005617
5618 offset = (u32) reg_tbl[i].offset;
5619 rw_mask = reg_tbl[i].rw_mask;
5620 ro_mask = reg_tbl[i].ro_mask;
5621
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005622 save_val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005623
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005624 writel(0, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005625
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005626 val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005627 if ((val & rw_mask) != 0) {
5628 goto reg_test_err;
5629 }
5630
5631 if ((val & ro_mask) != (save_val & ro_mask)) {
5632 goto reg_test_err;
5633 }
5634
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005635 writel(0xffffffff, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005636
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005637 val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005638 if ((val & rw_mask) != rw_mask) {
5639 goto reg_test_err;
5640 }
5641
5642 if ((val & ro_mask) != (save_val & ro_mask)) {
5643 goto reg_test_err;
5644 }
5645
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005646 writel(save_val, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005647 continue;
5648
5649reg_test_err:
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005650 writel(save_val, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005651 ret = -ENODEV;
5652 break;
5653 }
5654 return ret;
5655}
5656
5657static int
5658bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5659{
Arjan van de Venf71e1302006-03-03 21:33:57 -05005660 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
Michael Chanb6016b72005-05-26 13:03:09 -07005661 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5662 int i;
5663
5664 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5665 u32 offset;
5666
5667 for (offset = 0; offset < size; offset += 4) {
5668
Michael Chan2726d6e2008-01-29 21:35:05 -08005669 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
Michael Chanb6016b72005-05-26 13:03:09 -07005670
Michael Chan2726d6e2008-01-29 21:35:05 -08005671 if (bnx2_reg_rd_ind(bp, start + offset) !=
Michael Chanb6016b72005-05-26 13:03:09 -07005672 test_pattern[i]) {
5673 return -ENODEV;
5674 }
5675 }
5676 }
5677 return 0;
5678}
5679
5680static int
5681bnx2_test_memory(struct bnx2 *bp)
5682{
5683 int ret = 0;
5684 int i;
Michael Chan5bae30c2007-05-03 13:18:46 -07005685 static struct mem_entry {
Michael Chanb6016b72005-05-26 13:03:09 -07005686 u32 offset;
5687 u32 len;
Michael Chan5bae30c2007-05-03 13:18:46 -07005688 } mem_tbl_5706[] = {
Michael Chanb6016b72005-05-26 13:03:09 -07005689 { 0x60000, 0x4000 },
Michael Chan5b0c76a2005-11-04 08:45:49 -08005690 { 0xa0000, 0x3000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005691 { 0xe0000, 0x4000 },
5692 { 0x120000, 0x4000 },
5693 { 0x1a0000, 0x4000 },
5694 { 0x160000, 0x4000 },
5695 { 0xffffffff, 0 },
Michael Chan5bae30c2007-05-03 13:18:46 -07005696 },
5697 mem_tbl_5709[] = {
5698 { 0x60000, 0x4000 },
5699 { 0xa0000, 0x3000 },
5700 { 0xe0000, 0x4000 },
5701 { 0x120000, 0x4000 },
5702 { 0x1a0000, 0x4000 },
5703 { 0xffffffff, 0 },
Michael Chanb6016b72005-05-26 13:03:09 -07005704 };
Michael Chan5bae30c2007-05-03 13:18:46 -07005705 struct mem_entry *mem_tbl;
5706
Michael Chan4ce45e02012-12-06 10:33:10 +00005707 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
Michael Chan5bae30c2007-05-03 13:18:46 -07005708 mem_tbl = mem_tbl_5709;
5709 else
5710 mem_tbl = mem_tbl_5706;
Michael Chanb6016b72005-05-26 13:03:09 -07005711
5712 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5713 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5714 mem_tbl[i].len)) != 0) {
5715 return ret;
5716 }
5717 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005718
Michael Chanb6016b72005-05-26 13:03:09 -07005719 return ret;
5720}
5721
Michael Chanbc5a0692006-01-23 16:13:22 -08005722#define BNX2_MAC_LOOPBACK 0
5723#define BNX2_PHY_LOOPBACK 1
5724
Michael Chanb6016b72005-05-26 13:03:09 -07005725static int
Michael Chanbc5a0692006-01-23 16:13:22 -08005726bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
Michael Chanb6016b72005-05-26 13:03:09 -07005727{
5728 unsigned int pkt_size, num_pkts, i;
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00005729 struct sk_buff *skb;
5730 u8 *data;
Michael Chanb6016b72005-05-26 13:03:09 -07005731 unsigned char *packet;
Michael Chanbc5a0692006-01-23 16:13:22 -08005732 u16 rx_start_idx, rx_idx;
Michael Chanb6016b72005-05-26 13:03:09 -07005733 dma_addr_t map;
Michael Chan2bc40782012-12-06 10:33:09 +00005734 struct bnx2_tx_bd *txbd;
5735 struct bnx2_sw_bd *rx_buf;
Michael Chanb6016b72005-05-26 13:03:09 -07005736 struct l2_fhdr *rx_hdr;
5737 int ret = -ENODEV;
Michael Chanc76c0472007-12-20 20:01:19 -08005738 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
Michael Chan35e90102008-06-19 16:37:42 -07005739 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
Michael Chanbb4f98a2008-06-19 16:38:19 -07005740 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
Michael Chanc76c0472007-12-20 20:01:19 -08005741
5742 tx_napi = bnapi;
Michael Chanb6016b72005-05-26 13:03:09 -07005743
Michael Chan35e90102008-06-19 16:37:42 -07005744 txr = &tx_napi->tx_ring;
Michael Chanbb4f98a2008-06-19 16:38:19 -07005745 rxr = &bnapi->rx_ring;
Michael Chanbc5a0692006-01-23 16:13:22 -08005746 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5747 bp->loopback = MAC_LOOPBACK;
5748 bnx2_set_mac_loopback(bp);
5749 }
5750 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
Michael Chan583c28e2008-01-21 19:51:35 -08005751 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan489310a2007-10-10 16:16:31 -07005752 return 0;
5753
Michael Chan80be4432006-11-19 14:07:28 -08005754 bp->loopback = PHY_LOOPBACK;
Michael Chanbc5a0692006-01-23 16:13:22 -08005755 bnx2_set_phy_loopback(bp);
5756 }
5757 else
5758 return -EINVAL;
Michael Chanb6016b72005-05-26 13:03:09 -07005759
Michael Chan84eaa182007-12-12 11:19:57 -08005760 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
Michael Chan932f3772006-08-15 01:39:36 -07005761 skb = netdev_alloc_skb(bp->dev, pkt_size);
John W. Linvilleb6cbc3b62005-11-10 12:58:00 -08005762 if (!skb)
5763 return -ENOMEM;
Michael Chanb6016b72005-05-26 13:03:09 -07005764 packet = skb_put(skb, pkt_size);
Michael Chan66342922006-12-14 15:57:04 -08005765 memcpy(packet, bp->dev->dev_addr, 6);
Michael Chanb6016b72005-05-26 13:03:09 -07005766 memset(packet + 6, 0x0, 8);
5767 for (i = 14; i < pkt_size; i++)
5768 packet[i] = (unsigned char) (i & 0xff);
5769
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00005770 map = dma_map_single(&bp->pdev->dev, skb->data, pkt_size,
5771 PCI_DMA_TODEVICE);
5772 if (dma_mapping_error(&bp->pdev->dev, map)) {
Benjamin Li3d16af82008-10-09 12:26:41 -07005773 dev_kfree_skb(skb);
5774 return -EIO;
5775 }
Michael Chanb6016b72005-05-26 13:03:09 -07005776
Michael Chane503e062012-12-06 10:33:08 +00005777 BNX2_WR(bp, BNX2_HC_COMMAND,
5778 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
Michael Chanbf5295b2006-03-23 01:11:56 -08005779
Michael Chane503e062012-12-06 10:33:08 +00005780 BNX2_RD(bp, BNX2_HC_COMMAND);
Michael Chanb6016b72005-05-26 13:03:09 -07005781
5782 udelay(5);
Michael Chan35efa7c2007-12-20 19:56:37 -08005783 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
Michael Chanb6016b72005-05-26 13:03:09 -07005784
Michael Chanb6016b72005-05-26 13:03:09 -07005785 num_pkts = 0;
5786
Michael Chan2bc40782012-12-06 10:33:09 +00005787 txbd = &txr->tx_desc_ring[BNX2_TX_RING_IDX(txr->tx_prod)];
Michael Chanb6016b72005-05-26 13:03:09 -07005788
5789 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5790 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5791 txbd->tx_bd_mss_nbytes = pkt_size;
5792 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5793
5794 num_pkts++;
Michael Chan2bc40782012-12-06 10:33:09 +00005795 txr->tx_prod = BNX2_NEXT_TX_BD(txr->tx_prod);
Michael Chan35e90102008-06-19 16:37:42 -07005796 txr->tx_prod_bseq += pkt_size;
Michael Chanb6016b72005-05-26 13:03:09 -07005797
Michael Chane503e062012-12-06 10:33:08 +00005798 BNX2_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5799 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07005800
5801 udelay(100);
5802
Michael Chane503e062012-12-06 10:33:08 +00005803 BNX2_WR(bp, BNX2_HC_COMMAND,
5804 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
Michael Chanbf5295b2006-03-23 01:11:56 -08005805
Michael Chane503e062012-12-06 10:33:08 +00005806 BNX2_RD(bp, BNX2_HC_COMMAND);
Michael Chanb6016b72005-05-26 13:03:09 -07005807
5808 udelay(5);
5809
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00005810 dma_unmap_single(&bp->pdev->dev, map, pkt_size, PCI_DMA_TODEVICE);
Michael Chan745720e2006-06-29 12:37:41 -07005811 dev_kfree_skb(skb);
Michael Chanb6016b72005-05-26 13:03:09 -07005812
Michael Chan35e90102008-06-19 16:37:42 -07005813 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
Michael Chanb6016b72005-05-26 13:03:09 -07005814 goto loopback_test_done;
Michael Chanb6016b72005-05-26 13:03:09 -07005815
Michael Chan35efa7c2007-12-20 19:56:37 -08005816 rx_idx = bnx2_get_hw_rx_cons(bnapi);
Michael Chanb6016b72005-05-26 13:03:09 -07005817 if (rx_idx != rx_start_idx + num_pkts) {
5818 goto loopback_test_done;
5819 }
5820
Michael Chanbb4f98a2008-06-19 16:38:19 -07005821 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00005822 data = rx_buf->data;
Michael Chanb6016b72005-05-26 13:03:09 -07005823
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00005824 rx_hdr = get_l2_fhdr(data);
5825 data = (u8 *)rx_hdr + BNX2_RX_OFFSET;
Michael Chanb6016b72005-05-26 13:03:09 -07005826
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00005827 dma_sync_single_for_cpu(&bp->pdev->dev,
FUJITA Tomonori1a4ccc22010-04-01 16:56:57 +00005828 dma_unmap_addr(rx_buf, mapping),
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00005829 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
Michael Chanb6016b72005-05-26 13:03:09 -07005830
Michael Chanade2bfe2006-01-23 16:09:51 -08005831 if (rx_hdr->l2_fhdr_status &
Michael Chanb6016b72005-05-26 13:03:09 -07005832 (L2_FHDR_ERRORS_BAD_CRC |
5833 L2_FHDR_ERRORS_PHY_DECODE |
5834 L2_FHDR_ERRORS_ALIGNMENT |
5835 L2_FHDR_ERRORS_TOO_SHORT |
5836 L2_FHDR_ERRORS_GIANT_FRAME)) {
5837
5838 goto loopback_test_done;
5839 }
5840
5841 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5842 goto loopback_test_done;
5843 }
5844
5845 for (i = 14; i < pkt_size; i++) {
Eric Dumazetdd2bc8e2011-11-15 07:30:05 +00005846 if (*(data + i) != (unsigned char) (i & 0xff)) {
Michael Chanb6016b72005-05-26 13:03:09 -07005847 goto loopback_test_done;
5848 }
5849 }
5850
5851 ret = 0;
5852
5853loopback_test_done:
5854 bp->loopback = 0;
5855 return ret;
5856}
5857
Michael Chanbc5a0692006-01-23 16:13:22 -08005858#define BNX2_MAC_LOOPBACK_FAILED 1
5859#define BNX2_PHY_LOOPBACK_FAILED 2
5860#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5861 BNX2_PHY_LOOPBACK_FAILED)
5862
5863static int
5864bnx2_test_loopback(struct bnx2 *bp)
5865{
5866 int rc = 0;
5867
5868 if (!netif_running(bp->dev))
5869 return BNX2_LOOPBACK_FAILED;
5870
5871 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5872 spin_lock_bh(&bp->phy_lock);
Michael Chan9a120bc2008-05-16 22:17:45 -07005873 bnx2_init_phy(bp, 1);
Michael Chanbc5a0692006-01-23 16:13:22 -08005874 spin_unlock_bh(&bp->phy_lock);
5875 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5876 rc |= BNX2_MAC_LOOPBACK_FAILED;
5877 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5878 rc |= BNX2_PHY_LOOPBACK_FAILED;
5879 return rc;
5880}
5881
Michael Chanb6016b72005-05-26 13:03:09 -07005882#define NVRAM_SIZE 0x200
5883#define CRC32_RESIDUAL 0xdebb20e3
5884
5885static int
5886bnx2_test_nvram(struct bnx2 *bp)
5887{
Al Virob491edd2007-12-22 19:44:51 +00005888 __be32 buf[NVRAM_SIZE / 4];
Michael Chanb6016b72005-05-26 13:03:09 -07005889 u8 *data = (u8 *) buf;
5890 int rc = 0;
5891 u32 magic, csum;
5892
5893 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5894 goto test_nvram_done;
5895
5896 magic = be32_to_cpu(buf[0]);
5897 if (magic != 0x669955aa) {
5898 rc = -ENODEV;
5899 goto test_nvram_done;
5900 }
5901
5902 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5903 goto test_nvram_done;
5904
5905 csum = ether_crc_le(0x100, data);
5906 if (csum != CRC32_RESIDUAL) {
5907 rc = -ENODEV;
5908 goto test_nvram_done;
5909 }
5910
5911 csum = ether_crc_le(0x100, data + 0x100);
5912 if (csum != CRC32_RESIDUAL) {
5913 rc = -ENODEV;
5914 }
5915
5916test_nvram_done:
5917 return rc;
5918}
5919
5920static int
5921bnx2_test_link(struct bnx2 *bp)
5922{
5923 u32 bmsr;
5924
Michael Chan9f52b562008-10-09 12:21:46 -07005925 if (!netif_running(bp->dev))
5926 return -ENODEV;
5927
Michael Chan583c28e2008-01-21 19:51:35 -08005928 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
Michael Chan489310a2007-10-10 16:16:31 -07005929 if (bp->link_up)
5930 return 0;
5931 return -ENODEV;
5932 }
Michael Chanc770a652005-08-25 15:38:39 -07005933 spin_lock_bh(&bp->phy_lock);
Michael Chan27a005b2007-05-03 13:23:41 -07005934 bnx2_enable_bmsr1(bp);
5935 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5936 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5937 bnx2_disable_bmsr1(bp);
Michael Chanc770a652005-08-25 15:38:39 -07005938 spin_unlock_bh(&bp->phy_lock);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005939
Michael Chanb6016b72005-05-26 13:03:09 -07005940 if (bmsr & BMSR_LSTATUS) {
5941 return 0;
5942 }
5943 return -ENODEV;
5944}
5945
5946static int
5947bnx2_test_intr(struct bnx2 *bp)
5948{
5949 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07005950 u16 status_idx;
5951
5952 if (!netif_running(bp->dev))
5953 return -ENODEV;
5954
Michael Chane503e062012-12-06 10:33:08 +00005955 status_idx = BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
Michael Chanb6016b72005-05-26 13:03:09 -07005956
5957 /* This register is not touched during run-time. */
Michael Chane503e062012-12-06 10:33:08 +00005958 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5959 BNX2_RD(bp, BNX2_HC_COMMAND);
Michael Chanb6016b72005-05-26 13:03:09 -07005960
5961 for (i = 0; i < 10; i++) {
Michael Chane503e062012-12-06 10:33:08 +00005962 if ((BNX2_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
Michael Chanb6016b72005-05-26 13:03:09 -07005963 status_idx) {
5964
5965 break;
5966 }
5967
5968 msleep_interruptible(10);
5969 }
5970 if (i < 10)
5971 return 0;
5972
5973 return -ENODEV;
5974}
5975
Michael Chan38ea3682008-02-23 19:48:57 -08005976/* Determining link for parallel detection. */
Michael Chanb2fadea2008-01-21 17:07:06 -08005977static int
5978bnx2_5706_serdes_has_link(struct bnx2 *bp)
5979{
5980 u32 mode_ctl, an_dbg, exp;
5981
Michael Chan38ea3682008-02-23 19:48:57 -08005982 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5983 return 0;
5984
Michael Chanb2fadea2008-01-21 17:07:06 -08005985 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5986 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5987
5988 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5989 return 0;
5990
5991 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5992 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5993 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5994
Michael Chanf3014c0c2008-01-29 21:33:03 -08005995 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
Michael Chanb2fadea2008-01-21 17:07:06 -08005996 return 0;
5997
5998 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5999 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6000 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
6001
6002 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
6003 return 0;
6004
6005 return 1;
6006}
6007
Michael Chanb6016b72005-05-26 13:03:09 -07006008static void
Michael Chan48b01e22006-11-19 14:08:00 -08006009bnx2_5706_serdes_timer(struct bnx2 *bp)
6010{
Michael Chanb2fadea2008-01-21 17:07:06 -08006011 int check_link = 1;
6012
Michael Chan48b01e22006-11-19 14:08:00 -08006013 spin_lock(&bp->phy_lock);
Michael Chanb2fadea2008-01-21 17:07:06 -08006014 if (bp->serdes_an_pending) {
Michael Chan48b01e22006-11-19 14:08:00 -08006015 bp->serdes_an_pending--;
Michael Chanb2fadea2008-01-21 17:07:06 -08006016 check_link = 0;
6017 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
Michael Chan48b01e22006-11-19 14:08:00 -08006018 u32 bmcr;
6019
Benjamin Liac392ab2008-09-18 16:40:49 -07006020 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chan48b01e22006-11-19 14:08:00 -08006021
Michael Chanca58c3a2007-05-03 13:22:52 -07006022 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chan48b01e22006-11-19 14:08:00 -08006023
6024 if (bmcr & BMCR_ANENABLE) {
Michael Chanb2fadea2008-01-21 17:07:06 -08006025 if (bnx2_5706_serdes_has_link(bp)) {
Michael Chan48b01e22006-11-19 14:08:00 -08006026 bmcr &= ~BMCR_ANENABLE;
6027 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
Michael Chanca58c3a2007-05-03 13:22:52 -07006028 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
Michael Chan583c28e2008-01-21 19:51:35 -08006029 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chan48b01e22006-11-19 14:08:00 -08006030 }
6031 }
6032 }
6033 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
Michael Chan583c28e2008-01-21 19:51:35 -08006034 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
Michael Chan48b01e22006-11-19 14:08:00 -08006035 u32 phy2;
6036
6037 bnx2_write_phy(bp, 0x17, 0x0f01);
6038 bnx2_read_phy(bp, 0x15, &phy2);
6039 if (phy2 & 0x20) {
6040 u32 bmcr;
6041
Michael Chanca58c3a2007-05-03 13:22:52 -07006042 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chan48b01e22006-11-19 14:08:00 -08006043 bmcr |= BMCR_ANENABLE;
Michael Chanca58c3a2007-05-03 13:22:52 -07006044 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
Michael Chan48b01e22006-11-19 14:08:00 -08006045
Michael Chan583c28e2008-01-21 19:51:35 -08006046 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chan48b01e22006-11-19 14:08:00 -08006047 }
6048 } else
Benjamin Liac392ab2008-09-18 16:40:49 -07006049 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chan48b01e22006-11-19 14:08:00 -08006050
Michael Chana2724e22008-02-23 19:47:44 -08006051 if (check_link) {
Michael Chanb2fadea2008-01-21 17:07:06 -08006052 u32 val;
6053
6054 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6055 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6056 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6057
Michael Chana2724e22008-02-23 19:47:44 -08006058 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6059 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6060 bnx2_5706s_force_link_dn(bp, 1);
6061 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6062 } else
6063 bnx2_set_link(bp);
6064 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6065 bnx2_set_link(bp);
Michael Chanb2fadea2008-01-21 17:07:06 -08006066 }
Michael Chan48b01e22006-11-19 14:08:00 -08006067 spin_unlock(&bp->phy_lock);
6068}
6069
6070static void
Michael Chanf8dd0642006-11-19 14:08:29 -08006071bnx2_5708_serdes_timer(struct bnx2 *bp)
6072{
Michael Chan583c28e2008-01-21 19:51:35 -08006073 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07006074 return;
6075
Michael Chan583c28e2008-01-21 19:51:35 -08006076 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
Michael Chanf8dd0642006-11-19 14:08:29 -08006077 bp->serdes_an_pending = 0;
6078 return;
6079 }
6080
6081 spin_lock(&bp->phy_lock);
6082 if (bp->serdes_an_pending)
6083 bp->serdes_an_pending--;
6084 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6085 u32 bmcr;
6086
Michael Chanca58c3a2007-05-03 13:22:52 -07006087 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanf8dd0642006-11-19 14:08:29 -08006088 if (bmcr & BMCR_ANENABLE) {
Michael Chan605a9e22007-05-03 13:23:13 -07006089 bnx2_enable_forced_2g5(bp);
Michael Chan40105c02008-11-12 16:02:45 -08006090 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
Michael Chanf8dd0642006-11-19 14:08:29 -08006091 } else {
Michael Chan605a9e22007-05-03 13:23:13 -07006092 bnx2_disable_forced_2g5(bp);
Michael Chanf8dd0642006-11-19 14:08:29 -08006093 bp->serdes_an_pending = 2;
Benjamin Liac392ab2008-09-18 16:40:49 -07006094 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chanf8dd0642006-11-19 14:08:29 -08006095 }
6096
6097 } else
Benjamin Liac392ab2008-09-18 16:40:49 -07006098 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chanf8dd0642006-11-19 14:08:29 -08006099
6100 spin_unlock(&bp->phy_lock);
6101}
6102
6103static void
Michael Chanb6016b72005-05-26 13:03:09 -07006104bnx2_timer(unsigned long data)
6105{
6106 struct bnx2 *bp = (struct bnx2 *) data;
Michael Chanb6016b72005-05-26 13:03:09 -07006107
Michael Chancd339a02005-08-25 15:35:24 -07006108 if (!netif_running(bp->dev))
6109 return;
6110
Michael Chanb6016b72005-05-26 13:03:09 -07006111 if (atomic_read(&bp->intr_sem) != 0)
6112 goto bnx2_restart_timer;
6113
Michael Chanefba0182008-12-03 00:36:15 -08006114 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6115 BNX2_FLAG_USING_MSI)
6116 bnx2_chk_missed_msi(bp);
6117
Michael Chandf149d72007-07-07 22:51:36 -07006118 bnx2_send_heart_beat(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07006119
Michael Chan2726d6e2008-01-29 21:35:05 -08006120 bp->stats_blk->stat_FwRxDrop =
6121 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
Michael Chancea94db2006-06-12 22:16:13 -07006122
Michael Chan02537b062007-06-04 21:24:07 -07006123 /* workaround occasional corrupted counters */
Michael Chan61d9e3f2009-08-21 16:20:46 +00006124 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
Michael Chane503e062012-12-06 10:33:08 +00006125 BNX2_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6126 BNX2_HC_COMMAND_STATS_NOW);
Michael Chan02537b062007-06-04 21:24:07 -07006127
Michael Chan583c28e2008-01-21 19:51:35 -08006128 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan4ce45e02012-12-06 10:33:10 +00006129 if (BNX2_CHIP(bp) == BNX2_CHIP_5706)
Michael Chanf8dd0642006-11-19 14:08:29 -08006130 bnx2_5706_serdes_timer(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07006131 else
Michael Chanf8dd0642006-11-19 14:08:29 -08006132 bnx2_5708_serdes_timer(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07006133 }
6134
6135bnx2_restart_timer:
Michael Chancd339a02005-08-25 15:35:24 -07006136 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -07006137}
6138
Michael Chan8e6a72c2007-05-03 13:24:48 -07006139static int
6140bnx2_request_irq(struct bnx2 *bp)
6141{
Michael Chan6d866ff2007-12-20 19:56:09 -08006142 unsigned long flags;
Michael Chanb4b36042007-12-20 19:59:30 -08006143 struct bnx2_irq *irq;
6144 int rc = 0, i;
Michael Chan8e6a72c2007-05-03 13:24:48 -07006145
David S. Millerf86e82f2008-01-21 17:15:40 -08006146 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
Michael Chan6d866ff2007-12-20 19:56:09 -08006147 flags = 0;
6148 else
6149 flags = IRQF_SHARED;
Michael Chanb4b36042007-12-20 19:59:30 -08006150
6151 for (i = 0; i < bp->irq_nvecs; i++) {
6152 irq = &bp->irq_tbl[i];
Michael Chanc76c0472007-12-20 20:01:19 -08006153 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
Michael Chanf0ea2e62008-06-19 16:41:57 -07006154 &bp->bnx2_napi[i]);
Michael Chanb4b36042007-12-20 19:59:30 -08006155 if (rc)
6156 break;
6157 irq->requested = 1;
6158 }
Michael Chan8e6a72c2007-05-03 13:24:48 -07006159 return rc;
6160}
6161
6162static void
Michael Chana29ba9d2010-12-31 11:03:14 -08006163__bnx2_free_irq(struct bnx2 *bp)
Michael Chan8e6a72c2007-05-03 13:24:48 -07006164{
Michael Chanb4b36042007-12-20 19:59:30 -08006165 struct bnx2_irq *irq;
6166 int i;
Michael Chan8e6a72c2007-05-03 13:24:48 -07006167
Michael Chanb4b36042007-12-20 19:59:30 -08006168 for (i = 0; i < bp->irq_nvecs; i++) {
6169 irq = &bp->irq_tbl[i];
6170 if (irq->requested)
Michael Chanf0ea2e62008-06-19 16:41:57 -07006171 free_irq(irq->vector, &bp->bnx2_napi[i]);
Michael Chanb4b36042007-12-20 19:59:30 -08006172 irq->requested = 0;
Michael Chan6d866ff2007-12-20 19:56:09 -08006173 }
Michael Chana29ba9d2010-12-31 11:03:14 -08006174}
6175
6176static void
6177bnx2_free_irq(struct bnx2 *bp)
6178{
6179
6180 __bnx2_free_irq(bp);
David S. Millerf86e82f2008-01-21 17:15:40 -08006181 if (bp->flags & BNX2_FLAG_USING_MSI)
Michael Chanb4b36042007-12-20 19:59:30 -08006182 pci_disable_msi(bp->pdev);
David S. Millerf86e82f2008-01-21 17:15:40 -08006183 else if (bp->flags & BNX2_FLAG_USING_MSIX)
Michael Chanb4b36042007-12-20 19:59:30 -08006184 pci_disable_msix(bp->pdev);
6185
David S. Millerf86e82f2008-01-21 17:15:40 -08006186 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
Michael Chanb4b36042007-12-20 19:59:30 -08006187}
6188
6189static void
Michael Chan5e9ad9e2008-06-19 16:43:17 -07006190bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
Michael Chanb4b36042007-12-20 19:59:30 -08006191{
Michael Chan379b39a2010-07-19 14:15:03 +00006192 int i, total_vecs, rc;
Michael Chan57851d82007-12-20 20:01:44 -08006193 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
Michael Chan4e1d0de2008-12-16 20:27:45 -08006194 struct net_device *dev = bp->dev;
6195 const int len = sizeof(bp->irq_tbl[0].name);
Michael Chan57851d82007-12-20 20:01:44 -08006196
Michael Chanb4b36042007-12-20 19:59:30 -08006197 bnx2_setup_msix_tbl(bp);
Michael Chane503e062012-12-06 10:33:08 +00006198 BNX2_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6199 BNX2_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6200 BNX2_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
Michael Chan57851d82007-12-20 20:01:44 -08006201
Benjamin Lie2eb8e32010-01-08 00:51:21 -08006202 /* Need to flush the previous three writes to ensure MSI-X
6203 * is setup properly */
Michael Chane503e062012-12-06 10:33:08 +00006204 BNX2_RD(bp, BNX2_PCI_MSIX_CONTROL);
Benjamin Lie2eb8e32010-01-08 00:51:21 -08006205
Michael Chan57851d82007-12-20 20:01:44 -08006206 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6207 msix_ent[i].entry = i;
6208 msix_ent[i].vector = 0;
6209 }
6210
Michael Chan379b39a2010-07-19 14:15:03 +00006211 total_vecs = msix_vecs;
6212#ifdef BCM_CNIC
6213 total_vecs++;
6214#endif
6215 rc = -ENOSPC;
6216 while (total_vecs >= BNX2_MIN_MSIX_VEC) {
6217 rc = pci_enable_msix(bp->pdev, msix_ent, total_vecs);
6218 if (rc <= 0)
6219 break;
6220 if (rc > 0)
6221 total_vecs = rc;
6222 }
6223
Michael Chan57851d82007-12-20 20:01:44 -08006224 if (rc != 0)
6225 return;
6226
Michael Chan379b39a2010-07-19 14:15:03 +00006227 msix_vecs = total_vecs;
6228#ifdef BCM_CNIC
6229 msix_vecs--;
6230#endif
Michael Chan5e9ad9e2008-06-19 16:43:17 -07006231 bp->irq_nvecs = msix_vecs;
David S. Millerf86e82f2008-01-21 17:15:40 -08006232 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
Michael Chan379b39a2010-07-19 14:15:03 +00006233 for (i = 0; i < total_vecs; i++) {
Michael Chan57851d82007-12-20 20:01:44 -08006234 bp->irq_tbl[i].vector = msix_ent[i].vector;
Michael Chan69010312009-03-18 18:11:51 -07006235 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6236 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6237 }
Michael Chan6d866ff2007-12-20 19:56:09 -08006238}
6239
Ben Hutchings657d92f2010-09-27 08:25:16 +00006240static int
Michael Chan6d866ff2007-12-20 19:56:09 -08006241bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6242{
Yuval Mintz0a742122012-07-01 03:18:58 +00006243 int cpus = netif_get_num_default_rss_queues();
Michael Chanb0332812012-02-05 15:24:38 +00006244 int msix_vecs;
6245
6246 if (!bp->num_req_rx_rings)
6247 msix_vecs = max(cpus + 1, bp->num_req_tx_rings);
6248 else if (!bp->num_req_tx_rings)
6249 msix_vecs = max(cpus, bp->num_req_rx_rings);
6250 else
6251 msix_vecs = max(bp->num_req_rx_rings, bp->num_req_tx_rings);
6252
6253 msix_vecs = min(msix_vecs, RX_MAX_RINGS);
Michael Chan5e9ad9e2008-06-19 16:43:17 -07006254
Michael Chan6d866ff2007-12-20 19:56:09 -08006255 bp->irq_tbl[0].handler = bnx2_interrupt;
6256 strcpy(bp->irq_tbl[0].name, bp->dev->name);
Michael Chanb4b36042007-12-20 19:59:30 -08006257 bp->irq_nvecs = 1;
6258 bp->irq_tbl[0].vector = bp->pdev->irq;
Michael Chan6d866ff2007-12-20 19:56:09 -08006259
Michael Chan3d5f3a72010-07-03 20:42:15 +00006260 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
Michael Chan5e9ad9e2008-06-19 16:43:17 -07006261 bnx2_enable_msix(bp, msix_vecs);
Michael Chanb4b36042007-12-20 19:59:30 -08006262
David S. Millerf86e82f2008-01-21 17:15:40 -08006263 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6264 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
Michael Chan6d866ff2007-12-20 19:56:09 -08006265 if (pci_enable_msi(bp->pdev) == 0) {
David S. Millerf86e82f2008-01-21 17:15:40 -08006266 bp->flags |= BNX2_FLAG_USING_MSI;
Michael Chan4ce45e02012-12-06 10:33:10 +00006267 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
David S. Millerf86e82f2008-01-21 17:15:40 -08006268 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
Michael Chan6d866ff2007-12-20 19:56:09 -08006269 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6270 } else
6271 bp->irq_tbl[0].handler = bnx2_msi;
Michael Chanb4b36042007-12-20 19:59:30 -08006272
6273 bp->irq_tbl[0].vector = bp->pdev->irq;
Michael Chan6d866ff2007-12-20 19:56:09 -08006274 }
6275 }
Benjamin Li706bf242008-07-18 17:55:11 -07006276
Michael Chanb0332812012-02-05 15:24:38 +00006277 if (!bp->num_req_tx_rings)
6278 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6279 else
6280 bp->num_tx_rings = min(bp->irq_nvecs, bp->num_req_tx_rings);
6281
6282 if (!bp->num_req_rx_rings)
6283 bp->num_rx_rings = bp->irq_nvecs;
6284 else
6285 bp->num_rx_rings = min(bp->irq_nvecs, bp->num_req_rx_rings);
6286
Ben Hutchings657d92f2010-09-27 08:25:16 +00006287 netif_set_real_num_tx_queues(bp->dev, bp->num_tx_rings);
Benjamin Li706bf242008-07-18 17:55:11 -07006288
Ben Hutchings657d92f2010-09-27 08:25:16 +00006289 return netif_set_real_num_rx_queues(bp->dev, bp->num_rx_rings);
Michael Chan8e6a72c2007-05-03 13:24:48 -07006290}
6291
Michael Chanb6016b72005-05-26 13:03:09 -07006292/* Called with rtnl_lock */
6293static int
6294bnx2_open(struct net_device *dev)
6295{
Michael Chan972ec0d2006-01-23 16:12:43 -08006296 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006297 int rc;
6298
françois romieu7880b722011-09-30 00:36:52 +00006299 rc = bnx2_request_firmware(bp);
6300 if (rc < 0)
6301 goto out;
6302
Michael Chan1b2f9222007-05-03 13:20:19 -07006303 netif_carrier_off(dev);
6304
Michael Chanb6016b72005-05-26 13:03:09 -07006305 bnx2_disable_int(bp);
6306
Ben Hutchings657d92f2010-09-27 08:25:16 +00006307 rc = bnx2_setup_int_mode(bp, disable_msi);
6308 if (rc)
6309 goto open_err;
Benjamin Li4327ba42010-03-23 13:13:11 +00006310 bnx2_init_napi(bp);
Michael Chan35efa7c2007-12-20 19:56:37 -08006311 bnx2_napi_enable(bp);
Michael Chan35e90102008-06-19 16:37:42 -07006312 rc = bnx2_alloc_mem(bp);
Michael Chan2739a8b2008-06-19 16:44:10 -07006313 if (rc)
6314 goto open_err;
Michael Chan35e90102008-06-19 16:37:42 -07006315
Michael Chan8e6a72c2007-05-03 13:24:48 -07006316 rc = bnx2_request_irq(bp);
Michael Chan2739a8b2008-06-19 16:44:10 -07006317 if (rc)
6318 goto open_err;
Michael Chanb6016b72005-05-26 13:03:09 -07006319
Michael Chan9a120bc2008-05-16 22:17:45 -07006320 rc = bnx2_init_nic(bp, 1);
Michael Chan2739a8b2008-06-19 16:44:10 -07006321 if (rc)
6322 goto open_err;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006323
Michael Chancd339a02005-08-25 15:35:24 -07006324 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -07006325
6326 atomic_set(&bp->intr_sem, 0);
6327
Michael Chan354fcd72010-01-17 07:30:44 +00006328 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6329
Michael Chanb6016b72005-05-26 13:03:09 -07006330 bnx2_enable_int(bp);
6331
David S. Millerf86e82f2008-01-21 17:15:40 -08006332 if (bp->flags & BNX2_FLAG_USING_MSI) {
Michael Chanb6016b72005-05-26 13:03:09 -07006333 /* Test MSI to make sure it is working
6334 * If MSI test fails, go back to INTx mode
6335 */
6336 if (bnx2_test_intr(bp) != 0) {
Joe Perches3a9c6a42010-02-17 15:01:51 +00006337 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07006338
6339 bnx2_disable_int(bp);
Michael Chan8e6a72c2007-05-03 13:24:48 -07006340 bnx2_free_irq(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07006341
Michael Chan6d866ff2007-12-20 19:56:09 -08006342 bnx2_setup_int_mode(bp, 1);
6343
Michael Chan9a120bc2008-05-16 22:17:45 -07006344 rc = bnx2_init_nic(bp, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07006345
Michael Chan8e6a72c2007-05-03 13:24:48 -07006346 if (!rc)
6347 rc = bnx2_request_irq(bp);
6348
Michael Chanb6016b72005-05-26 13:03:09 -07006349 if (rc) {
Michael Chanb6016b72005-05-26 13:03:09 -07006350 del_timer_sync(&bp->timer);
Michael Chan2739a8b2008-06-19 16:44:10 -07006351 goto open_err;
Michael Chanb6016b72005-05-26 13:03:09 -07006352 }
6353 bnx2_enable_int(bp);
6354 }
6355 }
David S. Millerf86e82f2008-01-21 17:15:40 -08006356 if (bp->flags & BNX2_FLAG_USING_MSI)
Joe Perches3a9c6a42010-02-17 15:01:51 +00006357 netdev_info(dev, "using MSI\n");
David S. Millerf86e82f2008-01-21 17:15:40 -08006358 else if (bp->flags & BNX2_FLAG_USING_MSIX)
Joe Perches3a9c6a42010-02-17 15:01:51 +00006359 netdev_info(dev, "using MSIX\n");
Michael Chanb6016b72005-05-26 13:03:09 -07006360
Benjamin Li706bf242008-07-18 17:55:11 -07006361 netif_tx_start_all_queues(dev);
françois romieu7880b722011-09-30 00:36:52 +00006362out:
6363 return rc;
Michael Chan2739a8b2008-06-19 16:44:10 -07006364
6365open_err:
6366 bnx2_napi_disable(bp);
6367 bnx2_free_skbs(bp);
6368 bnx2_free_irq(bp);
6369 bnx2_free_mem(bp);
Michael Chanf048fa92010-06-01 15:05:36 +00006370 bnx2_del_napi(bp);
françois romieu7880b722011-09-30 00:36:52 +00006371 bnx2_release_firmware(bp);
6372 goto out;
Michael Chanb6016b72005-05-26 13:03:09 -07006373}
6374
6375static void
David Howellsc4028952006-11-22 14:57:56 +00006376bnx2_reset_task(struct work_struct *work)
Michael Chanb6016b72005-05-26 13:03:09 -07006377{
David Howellsc4028952006-11-22 14:57:56 +00006378 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
Michael Chancd634012011-07-15 06:53:58 +00006379 int rc;
Michael Chanefdfad32012-07-16 14:25:56 +00006380 u16 pcicmd;
Michael Chanb6016b72005-05-26 13:03:09 -07006381
Michael Chan51bf6bb2009-12-03 09:46:31 +00006382 rtnl_lock();
6383 if (!netif_running(bp->dev)) {
6384 rtnl_unlock();
Michael Chanafdc08b2005-08-25 15:34:29 -07006385 return;
Michael Chan51bf6bb2009-12-03 09:46:31 +00006386 }
Michael Chanafdc08b2005-08-25 15:34:29 -07006387
Michael Chan212f9932010-04-27 11:28:10 +00006388 bnx2_netif_stop(bp, true);
Michael Chanb6016b72005-05-26 13:03:09 -07006389
Michael Chanefdfad32012-07-16 14:25:56 +00006390 pci_read_config_word(bp->pdev, PCI_COMMAND, &pcicmd);
6391 if (!(pcicmd & PCI_COMMAND_MEMORY)) {
6392 /* in case PCI block has reset */
6393 pci_restore_state(bp->pdev);
6394 pci_save_state(bp->pdev);
6395 }
Michael Chancd634012011-07-15 06:53:58 +00006396 rc = bnx2_init_nic(bp, 1);
6397 if (rc) {
6398 netdev_err(bp->dev, "failed to reset NIC, closing\n");
6399 bnx2_napi_enable(bp);
6400 dev_close(bp->dev);
6401 rtnl_unlock();
6402 return;
6403 }
Michael Chanb6016b72005-05-26 13:03:09 -07006404
6405 atomic_set(&bp->intr_sem, 1);
Michael Chan212f9932010-04-27 11:28:10 +00006406 bnx2_netif_start(bp, true);
Michael Chan51bf6bb2009-12-03 09:46:31 +00006407 rtnl_unlock();
Michael Chanb6016b72005-05-26 13:03:09 -07006408}
6409
Michael Chan555069d2012-06-16 15:45:41 +00006410#define BNX2_FTQ_ENTRY(ftq) { __stringify(ftq##FTQ_CTL), BNX2_##ftq##FTQ_CTL }
6411
6412static void
6413bnx2_dump_ftq(struct bnx2 *bp)
6414{
6415 int i;
6416 u32 reg, bdidx, cid, valid;
6417 struct net_device *dev = bp->dev;
6418 static const struct ftq_reg {
6419 char *name;
6420 u32 off;
6421 } ftq_arr[] = {
6422 BNX2_FTQ_ENTRY(RV2P_P),
6423 BNX2_FTQ_ENTRY(RV2P_T),
6424 BNX2_FTQ_ENTRY(RV2P_M),
6425 BNX2_FTQ_ENTRY(TBDR_),
6426 BNX2_FTQ_ENTRY(TDMA_),
6427 BNX2_FTQ_ENTRY(TXP_),
6428 BNX2_FTQ_ENTRY(TXP_),
6429 BNX2_FTQ_ENTRY(TPAT_),
6430 BNX2_FTQ_ENTRY(RXP_C),
6431 BNX2_FTQ_ENTRY(RXP_),
6432 BNX2_FTQ_ENTRY(COM_COMXQ_),
6433 BNX2_FTQ_ENTRY(COM_COMTQ_),
6434 BNX2_FTQ_ENTRY(COM_COMQ_),
6435 BNX2_FTQ_ENTRY(CP_CPQ_),
6436 };
6437
6438 netdev_err(dev, "<--- start FTQ dump --->\n");
6439 for (i = 0; i < ARRAY_SIZE(ftq_arr); i++)
6440 netdev_err(dev, "%s %08x\n", ftq_arr[i].name,
6441 bnx2_reg_rd_ind(bp, ftq_arr[i].off));
6442
6443 netdev_err(dev, "CPU states:\n");
6444 for (reg = BNX2_TXP_CPU_MODE; reg <= BNX2_CP_CPU_MODE; reg += 0x40000)
6445 netdev_err(dev, "%06x mode %x state %x evt_mask %x pc %x pc %x instr %x\n",
6446 reg, bnx2_reg_rd_ind(bp, reg),
6447 bnx2_reg_rd_ind(bp, reg + 4),
6448 bnx2_reg_rd_ind(bp, reg + 8),
6449 bnx2_reg_rd_ind(bp, reg + 0x1c),
6450 bnx2_reg_rd_ind(bp, reg + 0x1c),
6451 bnx2_reg_rd_ind(bp, reg + 0x20));
6452
6453 netdev_err(dev, "<--- end FTQ dump --->\n");
6454 netdev_err(dev, "<--- start TBDC dump --->\n");
6455 netdev_err(dev, "TBDC free cnt: %ld\n",
Michael Chane503e062012-12-06 10:33:08 +00006456 BNX2_RD(bp, BNX2_TBDC_STATUS) & BNX2_TBDC_STATUS_FREE_CNT);
Michael Chan555069d2012-06-16 15:45:41 +00006457 netdev_err(dev, "LINE CID BIDX CMD VALIDS\n");
6458 for (i = 0; i < 0x20; i++) {
6459 int j = 0;
6460
Michael Chane503e062012-12-06 10:33:08 +00006461 BNX2_WR(bp, BNX2_TBDC_BD_ADDR, i);
6462 BNX2_WR(bp, BNX2_TBDC_CAM_OPCODE,
6463 BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ);
6464 BNX2_WR(bp, BNX2_TBDC_COMMAND, BNX2_TBDC_COMMAND_CMD_REG_ARB);
6465 while ((BNX2_RD(bp, BNX2_TBDC_COMMAND) &
Michael Chan555069d2012-06-16 15:45:41 +00006466 BNX2_TBDC_COMMAND_CMD_REG_ARB) && j < 100)
6467 j++;
6468
Michael Chane503e062012-12-06 10:33:08 +00006469 cid = BNX2_RD(bp, BNX2_TBDC_CID);
6470 bdidx = BNX2_RD(bp, BNX2_TBDC_BIDX);
6471 valid = BNX2_RD(bp, BNX2_TBDC_CAM_OPCODE);
Michael Chan555069d2012-06-16 15:45:41 +00006472 netdev_err(dev, "%02x %06x %04lx %02x [%x]\n",
6473 i, cid, bdidx & BNX2_TBDC_BDIDX_BDIDX,
6474 bdidx >> 24, (valid >> 8) & 0x0ff);
6475 }
6476 netdev_err(dev, "<--- end TBDC dump --->\n");
6477}
6478
Michael Chanb6016b72005-05-26 13:03:09 -07006479static void
Michael Chan20175c52009-12-03 09:46:32 +00006480bnx2_dump_state(struct bnx2 *bp)
6481{
6482 struct net_device *dev = bp->dev;
Jeffrey Huangecdbf6e2011-07-13 17:24:21 +00006483 u32 val1, val2;
Michael Chan20175c52009-12-03 09:46:32 +00006484
Michael Chan5804a8f2010-07-03 20:42:17 +00006485 pci_read_config_dword(bp->pdev, PCI_COMMAND, &val1);
6486 netdev_err(dev, "DEBUG: intr_sem[%x] PCI_CMD[%08x]\n",
6487 atomic_read(&bp->intr_sem), val1);
6488 pci_read_config_dword(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &val1);
6489 pci_read_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, &val2);
6490 netdev_err(dev, "DEBUG: PCI_PM[%08x] PCI_MISC_CFG[%08x]\n", val1, val2);
Eddie Waib98eba52010-05-17 17:32:56 -07006491 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
Michael Chane503e062012-12-06 10:33:08 +00006492 BNX2_RD(bp, BNX2_EMAC_TX_STATUS),
6493 BNX2_RD(bp, BNX2_EMAC_RX_STATUS));
Eddie Waib98eba52010-05-17 17:32:56 -07006494 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
Michael Chane503e062012-12-06 10:33:08 +00006495 BNX2_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
Joe Perches3a9c6a42010-02-17 15:01:51 +00006496 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
Michael Chane503e062012-12-06 10:33:08 +00006497 BNX2_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
Michael Chan20175c52009-12-03 09:46:32 +00006498 if (bp->flags & BNX2_FLAG_USING_MSIX)
Joe Perches3a9c6a42010-02-17 15:01:51 +00006499 netdev_err(dev, "DEBUG: PBA[%08x]\n",
Michael Chane503e062012-12-06 10:33:08 +00006500 BNX2_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
Michael Chan20175c52009-12-03 09:46:32 +00006501}
6502
6503static void
Michael Chanb6016b72005-05-26 13:03:09 -07006504bnx2_tx_timeout(struct net_device *dev)
6505{
Michael Chan972ec0d2006-01-23 16:12:43 -08006506 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006507
Michael Chan555069d2012-06-16 15:45:41 +00006508 bnx2_dump_ftq(bp);
Michael Chan20175c52009-12-03 09:46:32 +00006509 bnx2_dump_state(bp);
Jeffrey Huangecdbf6e2011-07-13 17:24:21 +00006510 bnx2_dump_mcp_state(bp);
Michael Chan20175c52009-12-03 09:46:32 +00006511
Michael Chanb6016b72005-05-26 13:03:09 -07006512 /* This allows the netif to be shutdown gracefully before resetting */
6513 schedule_work(&bp->reset_task);
6514}
6515
Herbert Xu932ff272006-06-09 12:20:56 -07006516/* Called with netif_tx_lock.
Michael Chan2f8af122006-08-15 01:39:10 -07006517 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6518 * netif_wake_queue().
Michael Chanb6016b72005-05-26 13:03:09 -07006519 */
Stephen Hemminger613573252009-08-31 19:50:58 +00006520static netdev_tx_t
Michael Chanb6016b72005-05-26 13:03:09 -07006521bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6522{
Michael Chan972ec0d2006-01-23 16:12:43 -08006523 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006524 dma_addr_t mapping;
Michael Chan2bc40782012-12-06 10:33:09 +00006525 struct bnx2_tx_bd *txbd;
6526 struct bnx2_sw_tx_bd *tx_buf;
Michael Chanb6016b72005-05-26 13:03:09 -07006527 u32 len, vlan_tag_flags, last_frag, mss;
6528 u16 prod, ring_prod;
6529 int i;
Benjamin Li706bf242008-07-18 17:55:11 -07006530 struct bnx2_napi *bnapi;
6531 struct bnx2_tx_ring_info *txr;
6532 struct netdev_queue *txq;
6533
6534 /* Determine which tx ring we will be placed on */
6535 i = skb_get_queue_mapping(skb);
6536 bnapi = &bp->bnx2_napi[i];
6537 txr = &bnapi->tx_ring;
6538 txq = netdev_get_tx_queue(dev, i);
Michael Chanb6016b72005-05-26 13:03:09 -07006539
Michael Chan35e90102008-06-19 16:37:42 -07006540 if (unlikely(bnx2_tx_avail(bp, txr) <
Michael Chana550c992007-12-20 19:56:59 -08006541 (skb_shinfo(skb)->nr_frags + 1))) {
Benjamin Li706bf242008-07-18 17:55:11 -07006542 netif_tx_stop_queue(txq);
Joe Perches3a9c6a42010-02-17 15:01:51 +00006543 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
Michael Chanb6016b72005-05-26 13:03:09 -07006544
6545 return NETDEV_TX_BUSY;
6546 }
6547 len = skb_headlen(skb);
Michael Chan35e90102008-06-19 16:37:42 -07006548 prod = txr->tx_prod;
Michael Chan2bc40782012-12-06 10:33:09 +00006549 ring_prod = BNX2_TX_RING_IDX(prod);
Michael Chanb6016b72005-05-26 13:03:09 -07006550
6551 vlan_tag_flags = 0;
Patrick McHardy84fa7932006-08-29 16:44:56 -07006552 if (skb->ip_summed == CHECKSUM_PARTIAL) {
Michael Chanb6016b72005-05-26 13:03:09 -07006553 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6554 }
6555
Jesse Grosseab6d182010-10-20 13:56:03 +00006556 if (vlan_tx_tag_present(skb)) {
Michael Chanb6016b72005-05-26 13:03:09 -07006557 vlan_tag_flags |=
6558 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6559 }
Jesse Gross7d0fd212010-10-20 13:56:09 +00006560
Michael Chanfde82052007-05-03 17:23:35 -07006561 if ((mss = skb_shinfo(skb)->gso_size)) {
Michael Chana1efb4b2008-10-09 12:24:39 -07006562 u32 tcp_opt_len;
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07006563 struct iphdr *iph;
Michael Chanb6016b72005-05-26 13:03:09 -07006564
Michael Chanb6016b72005-05-26 13:03:09 -07006565 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6566
Michael Chan4666f872007-05-03 13:22:28 -07006567 tcp_opt_len = tcp_optlen(skb);
Arnaldo Carvalho de Meloab6a5bb2007-03-18 17:43:48 -07006568
Michael Chan4666f872007-05-03 13:22:28 -07006569 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6570 u32 tcp_off = skb_transport_offset(skb) -
6571 sizeof(struct ipv6hdr) - ETH_HLEN;
Michael Chanb6016b72005-05-26 13:03:09 -07006572
Michael Chan4666f872007-05-03 13:22:28 -07006573 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6574 TX_BD_FLAGS_SW_FLAGS;
6575 if (likely(tcp_off == 0))
6576 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6577 else {
6578 tcp_off >>= 3;
6579 vlan_tag_flags |= ((tcp_off & 0x3) <<
6580 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6581 ((tcp_off & 0x10) <<
6582 TX_BD_FLAGS_TCP6_OFF4_SHL);
6583 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6584 }
6585 } else {
Michael Chan4666f872007-05-03 13:22:28 -07006586 iph = ip_hdr(skb);
Michael Chan4666f872007-05-03 13:22:28 -07006587 if (tcp_opt_len || (iph->ihl > 5)) {
6588 vlan_tag_flags |= ((iph->ihl - 5) +
6589 (tcp_opt_len >> 2)) << 8;
6590 }
Michael Chanb6016b72005-05-26 13:03:09 -07006591 }
Michael Chan4666f872007-05-03 13:22:28 -07006592 } else
Michael Chanb6016b72005-05-26 13:03:09 -07006593 mss = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07006594
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00006595 mapping = dma_map_single(&bp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
6596 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
Benjamin Li3d16af82008-10-09 12:26:41 -07006597 dev_kfree_skb(skb);
6598 return NETDEV_TX_OK;
6599 }
6600
Michael Chan35e90102008-06-19 16:37:42 -07006601 tx_buf = &txr->tx_buf_ring[ring_prod];
Michael Chanb6016b72005-05-26 13:03:09 -07006602 tx_buf->skb = skb;
FUJITA Tomonori1a4ccc22010-04-01 16:56:57 +00006603 dma_unmap_addr_set(tx_buf, mapping, mapping);
Michael Chanb6016b72005-05-26 13:03:09 -07006604
Michael Chan35e90102008-06-19 16:37:42 -07006605 txbd = &txr->tx_desc_ring[ring_prod];
Michael Chanb6016b72005-05-26 13:03:09 -07006606
6607 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6608 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6609 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6610 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6611
6612 last_frag = skb_shinfo(skb)->nr_frags;
Eric Dumazetd62fda02009-05-12 20:48:02 +00006613 tx_buf->nr_frags = last_frag;
6614 tx_buf->is_gso = skb_is_gso(skb);
Michael Chanb6016b72005-05-26 13:03:09 -07006615
6616 for (i = 0; i < last_frag; i++) {
Eric Dumazet9e903e02011-10-18 21:00:24 +00006617 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
Michael Chanb6016b72005-05-26 13:03:09 -07006618
Michael Chan2bc40782012-12-06 10:33:09 +00006619 prod = BNX2_NEXT_TX_BD(prod);
6620 ring_prod = BNX2_TX_RING_IDX(prod);
Michael Chan35e90102008-06-19 16:37:42 -07006621 txbd = &txr->tx_desc_ring[ring_prod];
Michael Chanb6016b72005-05-26 13:03:09 -07006622
Eric Dumazet9e903e02011-10-18 21:00:24 +00006623 len = skb_frag_size(frag);
Ian Campbellb7b6a682011-08-24 22:28:12 +00006624 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, len,
Ian Campbell5d6bcdf2011-10-06 11:10:48 +01006625 DMA_TO_DEVICE);
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00006626 if (dma_mapping_error(&bp->pdev->dev, mapping))
Alexander Duycke95524a2009-12-02 16:47:57 +00006627 goto dma_error;
FUJITA Tomonori1a4ccc22010-04-01 16:56:57 +00006628 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
Alexander Duycke95524a2009-12-02 16:47:57 +00006629 mapping);
Michael Chanb6016b72005-05-26 13:03:09 -07006630
6631 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6632 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6633 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6634 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6635
6636 }
6637 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6638
Vlad Zolotarov94bf91b2012-02-05 15:24:39 +00006639 /* Sync BD data before updating TX mailbox */
6640 wmb();
6641
Eric Dumazete9831902011-11-29 11:53:05 +00006642 netdev_tx_sent_queue(txq, skb->len);
6643
Michael Chan2bc40782012-12-06 10:33:09 +00006644 prod = BNX2_NEXT_TX_BD(prod);
Michael Chan35e90102008-06-19 16:37:42 -07006645 txr->tx_prod_bseq += skb->len;
Michael Chanb6016b72005-05-26 13:03:09 -07006646
Michael Chane503e062012-12-06 10:33:08 +00006647 BNX2_WR16(bp, txr->tx_bidx_addr, prod);
6648 BNX2_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07006649
6650 mmiowb();
6651
Michael Chan35e90102008-06-19 16:37:42 -07006652 txr->tx_prod = prod;
Michael Chanb6016b72005-05-26 13:03:09 -07006653
Michael Chan35e90102008-06-19 16:37:42 -07006654 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
Benjamin Li706bf242008-07-18 17:55:11 -07006655 netif_tx_stop_queue(txq);
Michael Chan11848b962010-07-19 14:15:04 +00006656
6657 /* netif_tx_stop_queue() must be done before checking
6658 * tx index in bnx2_tx_avail() below, because in
6659 * bnx2_tx_int(), we update tx index before checking for
6660 * netif_tx_queue_stopped().
6661 */
6662 smp_mb();
Michael Chan35e90102008-06-19 16:37:42 -07006663 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
Benjamin Li706bf242008-07-18 17:55:11 -07006664 netif_tx_wake_queue(txq);
Michael Chanb6016b72005-05-26 13:03:09 -07006665 }
6666
6667 return NETDEV_TX_OK;
Alexander Duycke95524a2009-12-02 16:47:57 +00006668dma_error:
6669 /* save value of frag that failed */
6670 last_frag = i;
6671
6672 /* start back at beginning and unmap skb */
6673 prod = txr->tx_prod;
Michael Chan2bc40782012-12-06 10:33:09 +00006674 ring_prod = BNX2_TX_RING_IDX(prod);
Alexander Duycke95524a2009-12-02 16:47:57 +00006675 tx_buf = &txr->tx_buf_ring[ring_prod];
6676 tx_buf->skb = NULL;
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00006677 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
Alexander Duycke95524a2009-12-02 16:47:57 +00006678 skb_headlen(skb), PCI_DMA_TODEVICE);
6679
6680 /* unmap remaining mapped pages */
6681 for (i = 0; i < last_frag; i++) {
Michael Chan2bc40782012-12-06 10:33:09 +00006682 prod = BNX2_NEXT_TX_BD(prod);
6683 ring_prod = BNX2_TX_RING_IDX(prod);
Alexander Duycke95524a2009-12-02 16:47:57 +00006684 tx_buf = &txr->tx_buf_ring[ring_prod];
Stanislaw Gruszka36227e82010-07-15 04:25:50 +00006685 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(tx_buf, mapping),
Eric Dumazet9e903e02011-10-18 21:00:24 +00006686 skb_frag_size(&skb_shinfo(skb)->frags[i]),
Alexander Duycke95524a2009-12-02 16:47:57 +00006687 PCI_DMA_TODEVICE);
6688 }
6689
6690 dev_kfree_skb(skb);
6691 return NETDEV_TX_OK;
Michael Chanb6016b72005-05-26 13:03:09 -07006692}
6693
6694/* Called with rtnl_lock */
6695static int
6696bnx2_close(struct net_device *dev)
6697{
Michael Chan972ec0d2006-01-23 16:12:43 -08006698 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006699
Stephen Hemmingerbea33482007-10-03 16:41:36 -07006700 bnx2_disable_int_sync(bp);
Michael Chan35efa7c2007-12-20 19:56:37 -08006701 bnx2_napi_disable(bp);
Michael Chand2e553b2012-06-27 15:08:24 +00006702 netif_tx_disable(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006703 del_timer_sync(&bp->timer);
Michael Chan74bf4ba2008-10-09 12:21:08 -07006704 bnx2_shutdown_chip(bp);
Michael Chan8e6a72c2007-05-03 13:24:48 -07006705 bnx2_free_irq(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07006706 bnx2_free_skbs(bp);
6707 bnx2_free_mem(bp);
Michael Chanf048fa92010-06-01 15:05:36 +00006708 bnx2_del_napi(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07006709 bp->link_up = 0;
6710 netif_carrier_off(bp->dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006711 return 0;
6712}
6713
Michael Chan354fcd72010-01-17 07:30:44 +00006714static void
6715bnx2_save_stats(struct bnx2 *bp)
6716{
6717 u32 *hw_stats = (u32 *) bp->stats_blk;
6718 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6719 int i;
6720
6721 /* The 1st 10 counters are 64-bit counters */
6722 for (i = 0; i < 20; i += 2) {
6723 u32 hi;
6724 u64 lo;
6725
Patrick Rabauc9885fe2010-02-15 19:42:11 +00006726 hi = temp_stats[i] + hw_stats[i];
6727 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
Michael Chan354fcd72010-01-17 07:30:44 +00006728 if (lo > 0xffffffff)
6729 hi++;
Patrick Rabauc9885fe2010-02-15 19:42:11 +00006730 temp_stats[i] = hi;
6731 temp_stats[i + 1] = lo & 0xffffffff;
Michael Chan354fcd72010-01-17 07:30:44 +00006732 }
6733
6734 for ( ; i < sizeof(struct statistics_block) / 4; i++)
Patrick Rabauc9885fe2010-02-15 19:42:11 +00006735 temp_stats[i] += hw_stats[i];
Michael Chan354fcd72010-01-17 07:30:44 +00006736}
6737
Eric Dumazet5d07bf22010-07-08 04:08:43 +00006738#define GET_64BIT_NET_STATS64(ctr) \
6739 (((u64) (ctr##_hi) << 32) + (u64) (ctr##_lo))
Michael Chanb6016b72005-05-26 13:03:09 -07006740
Michael Chana4743052010-01-17 07:30:43 +00006741#define GET_64BIT_NET_STATS(ctr) \
Michael Chan354fcd72010-01-17 07:30:44 +00006742 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6743 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
Michael Chanb6016b72005-05-26 13:03:09 -07006744
Michael Chana4743052010-01-17 07:30:43 +00006745#define GET_32BIT_NET_STATS(ctr) \
Michael Chan354fcd72010-01-17 07:30:44 +00006746 (unsigned long) (bp->stats_blk->ctr + \
6747 bp->temp_stats_blk->ctr)
Michael Chana4743052010-01-17 07:30:43 +00006748
Eric Dumazet5d07bf22010-07-08 04:08:43 +00006749static struct rtnl_link_stats64 *
6750bnx2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *net_stats)
Michael Chanb6016b72005-05-26 13:03:09 -07006751{
Michael Chan972ec0d2006-01-23 16:12:43 -08006752 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006753
Eric Dumazet5d07bf22010-07-08 04:08:43 +00006754 if (bp->stats_blk == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -07006755 return net_stats;
Eric Dumazet5d07bf22010-07-08 04:08:43 +00006756
Michael Chanb6016b72005-05-26 13:03:09 -07006757 net_stats->rx_packets =
Michael Chana4743052010-01-17 07:30:43 +00006758 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6759 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6760 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
Michael Chanb6016b72005-05-26 13:03:09 -07006761
6762 net_stats->tx_packets =
Michael Chana4743052010-01-17 07:30:43 +00006763 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6764 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6765 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
Michael Chanb6016b72005-05-26 13:03:09 -07006766
6767 net_stats->rx_bytes =
Michael Chana4743052010-01-17 07:30:43 +00006768 GET_64BIT_NET_STATS(stat_IfHCInOctets);
Michael Chanb6016b72005-05-26 13:03:09 -07006769
6770 net_stats->tx_bytes =
Michael Chana4743052010-01-17 07:30:43 +00006771 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
Michael Chanb6016b72005-05-26 13:03:09 -07006772
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006773 net_stats->multicast =
Michael Chan6fdae9952010-07-19 14:15:02 +00006774 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts);
Michael Chanb6016b72005-05-26 13:03:09 -07006775
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006776 net_stats->collisions =
Michael Chana4743052010-01-17 07:30:43 +00006777 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
Michael Chanb6016b72005-05-26 13:03:09 -07006778
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006779 net_stats->rx_length_errors =
Michael Chana4743052010-01-17 07:30:43 +00006780 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6781 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
Michael Chanb6016b72005-05-26 13:03:09 -07006782
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006783 net_stats->rx_over_errors =
Michael Chana4743052010-01-17 07:30:43 +00006784 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6785 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
Michael Chanb6016b72005-05-26 13:03:09 -07006786
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006787 net_stats->rx_frame_errors =
Michael Chana4743052010-01-17 07:30:43 +00006788 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
Michael Chanb6016b72005-05-26 13:03:09 -07006789
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006790 net_stats->rx_crc_errors =
Michael Chana4743052010-01-17 07:30:43 +00006791 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
Michael Chanb6016b72005-05-26 13:03:09 -07006792
6793 net_stats->rx_errors = net_stats->rx_length_errors +
6794 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6795 net_stats->rx_crc_errors;
6796
6797 net_stats->tx_aborted_errors =
Michael Chana4743052010-01-17 07:30:43 +00006798 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6799 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
Michael Chanb6016b72005-05-26 13:03:09 -07006800
Michael Chan4ce45e02012-12-06 10:33:10 +00006801 if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||
6802 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))
Michael Chanb6016b72005-05-26 13:03:09 -07006803 net_stats->tx_carrier_errors = 0;
6804 else {
6805 net_stats->tx_carrier_errors =
Michael Chana4743052010-01-17 07:30:43 +00006806 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
Michael Chanb6016b72005-05-26 13:03:09 -07006807 }
6808
6809 net_stats->tx_errors =
Michael Chana4743052010-01-17 07:30:43 +00006810 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
Michael Chanb6016b72005-05-26 13:03:09 -07006811 net_stats->tx_aborted_errors +
6812 net_stats->tx_carrier_errors;
6813
Michael Chancea94db2006-06-12 22:16:13 -07006814 net_stats->rx_missed_errors =
Michael Chana4743052010-01-17 07:30:43 +00006815 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6816 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6817 GET_32BIT_NET_STATS(stat_FwRxDrop);
Michael Chancea94db2006-06-12 22:16:13 -07006818
Michael Chanb6016b72005-05-26 13:03:09 -07006819 return net_stats;
6820}
6821
6822/* All ethtool functions called with rtnl_lock */
6823
6824static int
6825bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6826{
Michael Chan972ec0d2006-01-23 16:12:43 -08006827 struct bnx2 *bp = netdev_priv(dev);
Michael Chan7b6b8342007-07-07 22:50:15 -07006828 int support_serdes = 0, support_copper = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07006829
6830 cmd->supported = SUPPORTED_Autoneg;
Michael Chan583c28e2008-01-21 19:51:35 -08006831 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
Michael Chan7b6b8342007-07-07 22:50:15 -07006832 support_serdes = 1;
6833 support_copper = 1;
6834 } else if (bp->phy_port == PORT_FIBRE)
6835 support_serdes = 1;
6836 else
6837 support_copper = 1;
6838
6839 if (support_serdes) {
Michael Chanb6016b72005-05-26 13:03:09 -07006840 cmd->supported |= SUPPORTED_1000baseT_Full |
6841 SUPPORTED_FIBRE;
Michael Chan583c28e2008-01-21 19:51:35 -08006842 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
Michael Chan605a9e22007-05-03 13:23:13 -07006843 cmd->supported |= SUPPORTED_2500baseX_Full;
Michael Chanb6016b72005-05-26 13:03:09 -07006844
Michael Chanb6016b72005-05-26 13:03:09 -07006845 }
Michael Chan7b6b8342007-07-07 22:50:15 -07006846 if (support_copper) {
Michael Chanb6016b72005-05-26 13:03:09 -07006847 cmd->supported |= SUPPORTED_10baseT_Half |
6848 SUPPORTED_10baseT_Full |
6849 SUPPORTED_100baseT_Half |
6850 SUPPORTED_100baseT_Full |
6851 SUPPORTED_1000baseT_Full |
6852 SUPPORTED_TP;
6853
Michael Chanb6016b72005-05-26 13:03:09 -07006854 }
6855
Michael Chan7b6b8342007-07-07 22:50:15 -07006856 spin_lock_bh(&bp->phy_lock);
6857 cmd->port = bp->phy_port;
Michael Chanb6016b72005-05-26 13:03:09 -07006858 cmd->advertising = bp->advertising;
6859
6860 if (bp->autoneg & AUTONEG_SPEED) {
6861 cmd->autoneg = AUTONEG_ENABLE;
David Decotigny70739492011-04-27 18:32:40 +00006862 } else {
Michael Chanb6016b72005-05-26 13:03:09 -07006863 cmd->autoneg = AUTONEG_DISABLE;
6864 }
6865
6866 if (netif_carrier_ok(dev)) {
David Decotigny70739492011-04-27 18:32:40 +00006867 ethtool_cmd_speed_set(cmd, bp->line_speed);
Michael Chanb6016b72005-05-26 13:03:09 -07006868 cmd->duplex = bp->duplex;
6869 }
6870 else {
David Decotigny70739492011-04-27 18:32:40 +00006871 ethtool_cmd_speed_set(cmd, -1);
Michael Chanb6016b72005-05-26 13:03:09 -07006872 cmd->duplex = -1;
6873 }
Michael Chan7b6b8342007-07-07 22:50:15 -07006874 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006875
6876 cmd->transceiver = XCVR_INTERNAL;
6877 cmd->phy_address = bp->phy_addr;
6878
6879 return 0;
6880}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006881
Michael Chanb6016b72005-05-26 13:03:09 -07006882static int
6883bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6884{
Michael Chan972ec0d2006-01-23 16:12:43 -08006885 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006886 u8 autoneg = bp->autoneg;
6887 u8 req_duplex = bp->req_duplex;
6888 u16 req_line_speed = bp->req_line_speed;
6889 u32 advertising = bp->advertising;
Michael Chan7b6b8342007-07-07 22:50:15 -07006890 int err = -EINVAL;
6891
6892 spin_lock_bh(&bp->phy_lock);
6893
6894 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6895 goto err_out_unlock;
6896
Michael Chan583c28e2008-01-21 19:51:35 -08006897 if (cmd->port != bp->phy_port &&
6898 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
Michael Chan7b6b8342007-07-07 22:50:15 -07006899 goto err_out_unlock;
Michael Chanb6016b72005-05-26 13:03:09 -07006900
Michael Chand6b14482008-07-14 22:37:21 -07006901 /* If device is down, we can store the settings only if the user
6902 * is setting the currently active port.
6903 */
6904 if (!netif_running(dev) && cmd->port != bp->phy_port)
6905 goto err_out_unlock;
6906
Michael Chanb6016b72005-05-26 13:03:09 -07006907 if (cmd->autoneg == AUTONEG_ENABLE) {
6908 autoneg |= AUTONEG_SPEED;
6909
Michael Chanbeb499a2010-02-15 19:42:10 +00006910 advertising = cmd->advertising;
6911 if (cmd->port == PORT_TP) {
6912 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6913 if (!advertising)
Michael Chanb6016b72005-05-26 13:03:09 -07006914 advertising = ETHTOOL_ALL_COPPER_SPEED;
Michael Chanbeb499a2010-02-15 19:42:10 +00006915 } else {
6916 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6917 if (!advertising)
6918 advertising = ETHTOOL_ALL_FIBRE_SPEED;
Michael Chanb6016b72005-05-26 13:03:09 -07006919 }
6920 advertising |= ADVERTISED_Autoneg;
6921 }
6922 else {
David Decotigny25db0332011-04-27 18:32:39 +00006923 u32 speed = ethtool_cmd_speed(cmd);
Michael Chan7b6b8342007-07-07 22:50:15 -07006924 if (cmd->port == PORT_FIBRE) {
David Decotigny25db0332011-04-27 18:32:39 +00006925 if ((speed != SPEED_1000 &&
6926 speed != SPEED_2500) ||
Michael Chan80be4432006-11-19 14:07:28 -08006927 (cmd->duplex != DUPLEX_FULL))
Michael Chan7b6b8342007-07-07 22:50:15 -07006928 goto err_out_unlock;
Michael Chan80be4432006-11-19 14:07:28 -08006929
David Decotigny25db0332011-04-27 18:32:39 +00006930 if (speed == SPEED_2500 &&
Michael Chan583c28e2008-01-21 19:51:35 -08006931 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan7b6b8342007-07-07 22:50:15 -07006932 goto err_out_unlock;
David Decotigny25db0332011-04-27 18:32:39 +00006933 } else if (speed == SPEED_1000 || speed == SPEED_2500)
Michael Chan7b6b8342007-07-07 22:50:15 -07006934 goto err_out_unlock;
6935
Michael Chanb6016b72005-05-26 13:03:09 -07006936 autoneg &= ~AUTONEG_SPEED;
David Decotigny25db0332011-04-27 18:32:39 +00006937 req_line_speed = speed;
Michael Chanb6016b72005-05-26 13:03:09 -07006938 req_duplex = cmd->duplex;
6939 advertising = 0;
6940 }
6941
6942 bp->autoneg = autoneg;
6943 bp->advertising = advertising;
6944 bp->req_line_speed = req_line_speed;
6945 bp->req_duplex = req_duplex;
6946
Michael Chand6b14482008-07-14 22:37:21 -07006947 err = 0;
6948 /* If device is down, the new settings will be picked up when it is
6949 * brought up.
6950 */
6951 if (netif_running(dev))
6952 err = bnx2_setup_phy(bp, cmd->port);
Michael Chanb6016b72005-05-26 13:03:09 -07006953
Michael Chan7b6b8342007-07-07 22:50:15 -07006954err_out_unlock:
Michael Chanc770a652005-08-25 15:38:39 -07006955 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006956
Michael Chan7b6b8342007-07-07 22:50:15 -07006957 return err;
Michael Chanb6016b72005-05-26 13:03:09 -07006958}
6959
6960static void
6961bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6962{
Michael Chan972ec0d2006-01-23 16:12:43 -08006963 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006964
Rick Jones68aad782011-11-07 13:29:27 +00006965 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
6966 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
6967 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
6968 strlcpy(info->fw_version, bp->fw_version, sizeof(info->fw_version));
Michael Chanb6016b72005-05-26 13:03:09 -07006969}
6970
Michael Chan244ac4f2006-03-20 17:48:46 -08006971#define BNX2_REGDUMP_LEN (32 * 1024)
6972
6973static int
6974bnx2_get_regs_len(struct net_device *dev)
6975{
6976 return BNX2_REGDUMP_LEN;
6977}
6978
6979static void
6980bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6981{
6982 u32 *p = _p, i, offset;
6983 u8 *orig_p = _p;
6984 struct bnx2 *bp = netdev_priv(dev);
Joe Perchesb6bc7652010-12-21 02:16:08 -08006985 static const u32 reg_boundaries[] = {
6986 0x0000, 0x0098, 0x0400, 0x045c,
6987 0x0800, 0x0880, 0x0c00, 0x0c10,
6988 0x0c30, 0x0d08, 0x1000, 0x101c,
6989 0x1040, 0x1048, 0x1080, 0x10a4,
6990 0x1400, 0x1490, 0x1498, 0x14f0,
6991 0x1500, 0x155c, 0x1580, 0x15dc,
6992 0x1600, 0x1658, 0x1680, 0x16d8,
6993 0x1800, 0x1820, 0x1840, 0x1854,
6994 0x1880, 0x1894, 0x1900, 0x1984,
6995 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6996 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6997 0x2000, 0x2030, 0x23c0, 0x2400,
6998 0x2800, 0x2820, 0x2830, 0x2850,
6999 0x2b40, 0x2c10, 0x2fc0, 0x3058,
7000 0x3c00, 0x3c94, 0x4000, 0x4010,
7001 0x4080, 0x4090, 0x43c0, 0x4458,
7002 0x4c00, 0x4c18, 0x4c40, 0x4c54,
7003 0x4fc0, 0x5010, 0x53c0, 0x5444,
7004 0x5c00, 0x5c18, 0x5c80, 0x5c90,
7005 0x5fc0, 0x6000, 0x6400, 0x6428,
7006 0x6800, 0x6848, 0x684c, 0x6860,
7007 0x6888, 0x6910, 0x8000
7008 };
Michael Chan244ac4f2006-03-20 17:48:46 -08007009
7010 regs->version = 0;
7011
7012 memset(p, 0, BNX2_REGDUMP_LEN);
7013
7014 if (!netif_running(bp->dev))
7015 return;
7016
7017 i = 0;
7018 offset = reg_boundaries[0];
7019 p += offset;
7020 while (offset < BNX2_REGDUMP_LEN) {
Michael Chane503e062012-12-06 10:33:08 +00007021 *p++ = BNX2_RD(bp, offset);
Michael Chan244ac4f2006-03-20 17:48:46 -08007022 offset += 4;
7023 if (offset == reg_boundaries[i + 1]) {
7024 offset = reg_boundaries[i + 2];
7025 p = (u32 *) (orig_p + offset);
7026 i += 2;
7027 }
7028 }
7029}
7030
Michael Chanb6016b72005-05-26 13:03:09 -07007031static void
7032bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7033{
Michael Chan972ec0d2006-01-23 16:12:43 -08007034 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007035
David S. Millerf86e82f2008-01-21 17:15:40 -08007036 if (bp->flags & BNX2_FLAG_NO_WOL) {
Michael Chanb6016b72005-05-26 13:03:09 -07007037 wol->supported = 0;
7038 wol->wolopts = 0;
7039 }
7040 else {
7041 wol->supported = WAKE_MAGIC;
7042 if (bp->wol)
7043 wol->wolopts = WAKE_MAGIC;
7044 else
7045 wol->wolopts = 0;
7046 }
7047 memset(&wol->sopass, 0, sizeof(wol->sopass));
7048}
7049
7050static int
7051bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7052{
Michael Chan972ec0d2006-01-23 16:12:43 -08007053 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007054
7055 if (wol->wolopts & ~WAKE_MAGIC)
7056 return -EINVAL;
7057
7058 if (wol->wolopts & WAKE_MAGIC) {
David S. Millerf86e82f2008-01-21 17:15:40 -08007059 if (bp->flags & BNX2_FLAG_NO_WOL)
Michael Chanb6016b72005-05-26 13:03:09 -07007060 return -EINVAL;
7061
7062 bp->wol = 1;
7063 }
7064 else {
7065 bp->wol = 0;
7066 }
Michael Chan6d5e85c2013-08-06 15:50:08 -07007067
7068 device_set_wakeup_enable(&bp->pdev->dev, bp->wol);
7069
Michael Chanb6016b72005-05-26 13:03:09 -07007070 return 0;
7071}
7072
7073static int
7074bnx2_nway_reset(struct net_device *dev)
7075{
Michael Chan972ec0d2006-01-23 16:12:43 -08007076 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007077 u32 bmcr;
7078
Michael Chan9f52b562008-10-09 12:21:46 -07007079 if (!netif_running(dev))
7080 return -EAGAIN;
7081
Michael Chanb6016b72005-05-26 13:03:09 -07007082 if (!(bp->autoneg & AUTONEG_SPEED)) {
7083 return -EINVAL;
7084 }
7085
Michael Chanc770a652005-08-25 15:38:39 -07007086 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007087
Michael Chan583c28e2008-01-21 19:51:35 -08007088 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
Michael Chan7b6b8342007-07-07 22:50:15 -07007089 int rc;
7090
7091 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
7092 spin_unlock_bh(&bp->phy_lock);
7093 return rc;
7094 }
7095
Michael Chanb6016b72005-05-26 13:03:09 -07007096 /* Force a link down visible on the other side */
Michael Chan583c28e2008-01-21 19:51:35 -08007097 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanca58c3a2007-05-03 13:22:52 -07007098 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
Michael Chanc770a652005-08-25 15:38:39 -07007099 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007100
7101 msleep(20);
7102
Michael Chanc770a652005-08-25 15:38:39 -07007103 spin_lock_bh(&bp->phy_lock);
Michael Chanf8dd0642006-11-19 14:08:29 -08007104
Michael Chan40105c02008-11-12 16:02:45 -08007105 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
Michael Chanf8dd0642006-11-19 14:08:29 -08007106 bp->serdes_an_pending = 1;
7107 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -07007108 }
7109
Michael Chanca58c3a2007-05-03 13:22:52 -07007110 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07007111 bmcr &= ~BMCR_LOOPBACK;
Michael Chanca58c3a2007-05-03 13:22:52 -07007112 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
Michael Chanb6016b72005-05-26 13:03:09 -07007113
Michael Chanc770a652005-08-25 15:38:39 -07007114 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007115
7116 return 0;
7117}
7118
Ooiwa Naohiro7959ea22009-06-24 00:19:06 -07007119static u32
7120bnx2_get_link(struct net_device *dev)
7121{
7122 struct bnx2 *bp = netdev_priv(dev);
7123
7124 return bp->link_up;
7125}
7126
Michael Chanb6016b72005-05-26 13:03:09 -07007127static int
7128bnx2_get_eeprom_len(struct net_device *dev)
7129{
Michael Chan972ec0d2006-01-23 16:12:43 -08007130 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007131
Michael Chan1122db72006-01-23 16:11:42 -08007132 if (bp->flash_info == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -07007133 return 0;
7134
Michael Chan1122db72006-01-23 16:11:42 -08007135 return (int) bp->flash_size;
Michael Chanb6016b72005-05-26 13:03:09 -07007136}
7137
7138static int
7139bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7140 u8 *eebuf)
7141{
Michael Chan972ec0d2006-01-23 16:12:43 -08007142 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007143 int rc;
7144
John W. Linville1064e942005-11-10 12:58:24 -08007145 /* parameters already validated in ethtool_get_eeprom */
Michael Chanb6016b72005-05-26 13:03:09 -07007146
7147 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
7148
7149 return rc;
7150}
7151
7152static int
7153bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7154 u8 *eebuf)
7155{
Michael Chan972ec0d2006-01-23 16:12:43 -08007156 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007157 int rc;
7158
John W. Linville1064e942005-11-10 12:58:24 -08007159 /* parameters already validated in ethtool_set_eeprom */
Michael Chanb6016b72005-05-26 13:03:09 -07007160
7161 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7162
7163 return rc;
7164}
7165
7166static int
7167bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7168{
Michael Chan972ec0d2006-01-23 16:12:43 -08007169 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007170
7171 memset(coal, 0, sizeof(struct ethtool_coalesce));
7172
7173 coal->rx_coalesce_usecs = bp->rx_ticks;
7174 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7175 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7176 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7177
7178 coal->tx_coalesce_usecs = bp->tx_ticks;
7179 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7180 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7181 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7182
7183 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7184
7185 return 0;
7186}
7187
7188static int
7189bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7190{
Michael Chan972ec0d2006-01-23 16:12:43 -08007191 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007192
7193 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7194 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7195
Jeff Garzik6aa20a22006-09-13 13:24:59 -04007196 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
Michael Chanb6016b72005-05-26 13:03:09 -07007197 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7198
7199 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7200 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7201
7202 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7203 if (bp->rx_quick_cons_trip_int > 0xff)
7204 bp->rx_quick_cons_trip_int = 0xff;
7205
7206 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7207 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7208
7209 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7210 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7211
7212 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7213 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7214
7215 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7216 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7217 0xff;
7218
7219 bp->stats_ticks = coal->stats_block_coalesce_usecs;
Michael Chan61d9e3f2009-08-21 16:20:46 +00007220 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
Michael Chan02537b062007-06-04 21:24:07 -07007221 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7222 bp->stats_ticks = USEC_PER_SEC;
7223 }
Michael Chan7ea69202007-07-16 18:27:10 -07007224 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7225 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7226 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
Michael Chanb6016b72005-05-26 13:03:09 -07007227
7228 if (netif_running(bp->dev)) {
Michael Chan212f9932010-04-27 11:28:10 +00007229 bnx2_netif_stop(bp, true);
Michael Chan9a120bc2008-05-16 22:17:45 -07007230 bnx2_init_nic(bp, 0);
Michael Chan212f9932010-04-27 11:28:10 +00007231 bnx2_netif_start(bp, true);
Michael Chanb6016b72005-05-26 13:03:09 -07007232 }
7233
7234 return 0;
7235}
7236
7237static void
7238bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7239{
Michael Chan972ec0d2006-01-23 16:12:43 -08007240 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007241
Michael Chan2bc40782012-12-06 10:33:09 +00007242 ering->rx_max_pending = BNX2_MAX_TOTAL_RX_DESC_CNT;
7243 ering->rx_jumbo_max_pending = BNX2_MAX_TOTAL_RX_PG_DESC_CNT;
Michael Chanb6016b72005-05-26 13:03:09 -07007244
7245 ering->rx_pending = bp->rx_ring_size;
Michael Chan47bf4242007-12-12 11:19:12 -08007246 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
Michael Chanb6016b72005-05-26 13:03:09 -07007247
Michael Chan2bc40782012-12-06 10:33:09 +00007248 ering->tx_max_pending = BNX2_MAX_TX_DESC_CNT;
Michael Chanb6016b72005-05-26 13:03:09 -07007249 ering->tx_pending = bp->tx_ring_size;
7250}
7251
7252static int
Michael Chanb0332812012-02-05 15:24:38 +00007253bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx, bool reset_irq)
Michael Chanb6016b72005-05-26 13:03:09 -07007254{
Michael Chan13daffa2006-03-20 17:49:20 -08007255 if (netif_running(bp->dev)) {
Michael Chan354fcd72010-01-17 07:30:44 +00007256 /* Reset will erase chipset stats; save them */
7257 bnx2_save_stats(bp);
7258
Michael Chan212f9932010-04-27 11:28:10 +00007259 bnx2_netif_stop(bp, true);
Michael Chan13daffa2006-03-20 17:49:20 -08007260 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
Michael Chanb0332812012-02-05 15:24:38 +00007261 if (reset_irq) {
7262 bnx2_free_irq(bp);
7263 bnx2_del_napi(bp);
7264 } else {
7265 __bnx2_free_irq(bp);
7266 }
Michael Chan13daffa2006-03-20 17:49:20 -08007267 bnx2_free_skbs(bp);
7268 bnx2_free_mem(bp);
7269 }
7270
Michael Chan5d5d0012007-12-12 11:17:43 -08007271 bnx2_set_rx_ring_size(bp, rx);
7272 bp->tx_ring_size = tx;
Michael Chanb6016b72005-05-26 13:03:09 -07007273
7274 if (netif_running(bp->dev)) {
Michael Chanb0332812012-02-05 15:24:38 +00007275 int rc = 0;
Michael Chan13daffa2006-03-20 17:49:20 -08007276
Michael Chanb0332812012-02-05 15:24:38 +00007277 if (reset_irq) {
7278 rc = bnx2_setup_int_mode(bp, disable_msi);
7279 bnx2_init_napi(bp);
7280 }
7281
7282 if (!rc)
7283 rc = bnx2_alloc_mem(bp);
7284
Michael Chan6fefb652009-08-21 16:20:45 +00007285 if (!rc)
Michael Chana29ba9d2010-12-31 11:03:14 -08007286 rc = bnx2_request_irq(bp);
7287
7288 if (!rc)
Michael Chan6fefb652009-08-21 16:20:45 +00007289 rc = bnx2_init_nic(bp, 0);
7290
7291 if (rc) {
7292 bnx2_napi_enable(bp);
7293 dev_close(bp->dev);
Michael Chan13daffa2006-03-20 17:49:20 -08007294 return rc;
Michael Chan6fefb652009-08-21 16:20:45 +00007295 }
Michael Chane9f26c42010-02-15 19:42:08 +00007296#ifdef BCM_CNIC
7297 mutex_lock(&bp->cnic_lock);
7298 /* Let cnic know about the new status block. */
7299 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7300 bnx2_setup_cnic_irq_info(bp);
7301 mutex_unlock(&bp->cnic_lock);
7302#endif
Michael Chan212f9932010-04-27 11:28:10 +00007303 bnx2_netif_start(bp, true);
Michael Chanb6016b72005-05-26 13:03:09 -07007304 }
Michael Chanb6016b72005-05-26 13:03:09 -07007305 return 0;
7306}
7307
Michael Chan5d5d0012007-12-12 11:17:43 -08007308static int
7309bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7310{
7311 struct bnx2 *bp = netdev_priv(dev);
7312 int rc;
7313
Michael Chan2bc40782012-12-06 10:33:09 +00007314 if ((ering->rx_pending > BNX2_MAX_TOTAL_RX_DESC_CNT) ||
7315 (ering->tx_pending > BNX2_MAX_TX_DESC_CNT) ||
Michael Chan5d5d0012007-12-12 11:17:43 -08007316 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7317
7318 return -EINVAL;
7319 }
Michael Chanb0332812012-02-05 15:24:38 +00007320 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending,
7321 false);
Michael Chan5d5d0012007-12-12 11:17:43 -08007322 return rc;
7323}
7324
Michael Chanb6016b72005-05-26 13:03:09 -07007325static void
7326bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7327{
Michael Chan972ec0d2006-01-23 16:12:43 -08007328 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007329
7330 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7331 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7332 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7333}
7334
7335static int
7336bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7337{
Michael Chan972ec0d2006-01-23 16:12:43 -08007338 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007339
7340 bp->req_flow_ctrl = 0;
7341 if (epause->rx_pause)
7342 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7343 if (epause->tx_pause)
7344 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7345
7346 if (epause->autoneg) {
7347 bp->autoneg |= AUTONEG_FLOW_CTRL;
7348 }
7349 else {
7350 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7351 }
7352
Michael Chan9f52b562008-10-09 12:21:46 -07007353 if (netif_running(dev)) {
7354 spin_lock_bh(&bp->phy_lock);
7355 bnx2_setup_phy(bp, bp->phy_port);
7356 spin_unlock_bh(&bp->phy_lock);
7357 }
Michael Chanb6016b72005-05-26 13:03:09 -07007358
7359 return 0;
7360}
7361
Peter Hagervall14ab9b82005-08-10 14:18:16 -07007362static struct {
Michael Chanb6016b72005-05-26 13:03:09 -07007363 char string[ETH_GSTRING_LEN];
Michael Chan790dab22009-08-21 16:20:47 +00007364} bnx2_stats_str_arr[] = {
Michael Chanb6016b72005-05-26 13:03:09 -07007365 { "rx_bytes" },
7366 { "rx_error_bytes" },
7367 { "tx_bytes" },
7368 { "tx_error_bytes" },
7369 { "rx_ucast_packets" },
7370 { "rx_mcast_packets" },
7371 { "rx_bcast_packets" },
7372 { "tx_ucast_packets" },
7373 { "tx_mcast_packets" },
7374 { "tx_bcast_packets" },
7375 { "tx_mac_errors" },
7376 { "tx_carrier_errors" },
7377 { "rx_crc_errors" },
7378 { "rx_align_errors" },
7379 { "tx_single_collisions" },
7380 { "tx_multi_collisions" },
7381 { "tx_deferred" },
7382 { "tx_excess_collisions" },
7383 { "tx_late_collisions" },
7384 { "tx_total_collisions" },
7385 { "rx_fragments" },
7386 { "rx_jabbers" },
7387 { "rx_undersize_packets" },
7388 { "rx_oversize_packets" },
7389 { "rx_64_byte_packets" },
7390 { "rx_65_to_127_byte_packets" },
7391 { "rx_128_to_255_byte_packets" },
7392 { "rx_256_to_511_byte_packets" },
7393 { "rx_512_to_1023_byte_packets" },
7394 { "rx_1024_to_1522_byte_packets" },
7395 { "rx_1523_to_9022_byte_packets" },
7396 { "tx_64_byte_packets" },
7397 { "tx_65_to_127_byte_packets" },
7398 { "tx_128_to_255_byte_packets" },
7399 { "tx_256_to_511_byte_packets" },
7400 { "tx_512_to_1023_byte_packets" },
7401 { "tx_1024_to_1522_byte_packets" },
7402 { "tx_1523_to_9022_byte_packets" },
7403 { "rx_xon_frames" },
7404 { "rx_xoff_frames" },
7405 { "tx_xon_frames" },
7406 { "tx_xoff_frames" },
7407 { "rx_mac_ctrl_frames" },
7408 { "rx_filtered_packets" },
Michael Chan790dab22009-08-21 16:20:47 +00007409 { "rx_ftq_discards" },
Michael Chanb6016b72005-05-26 13:03:09 -07007410 { "rx_discards" },
Michael Chancea94db2006-06-12 22:16:13 -07007411 { "rx_fw_discards" },
Michael Chanb6016b72005-05-26 13:03:09 -07007412};
7413
Jim Cromie0db83cd2012-04-10 14:56:03 +00007414#define BNX2_NUM_STATS ARRAY_SIZE(bnx2_stats_str_arr)
Michael Chan790dab22009-08-21 16:20:47 +00007415
Michael Chanb6016b72005-05-26 13:03:09 -07007416#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7417
Arjan van de Venf71e1302006-03-03 21:33:57 -05007418static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
Michael Chanb6016b72005-05-26 13:03:09 -07007419 STATS_OFFSET32(stat_IfHCInOctets_hi),
7420 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7421 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7422 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7423 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7424 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7425 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7426 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7427 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7428 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7429 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
Jeff Garzik6aa20a22006-09-13 13:24:59 -04007430 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7431 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7432 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7433 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7434 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7435 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7436 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7437 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7438 STATS_OFFSET32(stat_EtherStatsCollisions),
7439 STATS_OFFSET32(stat_EtherStatsFragments),
7440 STATS_OFFSET32(stat_EtherStatsJabbers),
7441 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7442 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7443 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7444 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7445 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7446 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7447 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7448 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7449 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7450 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7451 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7452 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7453 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7454 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7455 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7456 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7457 STATS_OFFSET32(stat_XonPauseFramesReceived),
7458 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7459 STATS_OFFSET32(stat_OutXonSent),
7460 STATS_OFFSET32(stat_OutXoffSent),
7461 STATS_OFFSET32(stat_MacControlFramesReceived),
7462 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
Michael Chan790dab22009-08-21 16:20:47 +00007463 STATS_OFFSET32(stat_IfInFTQDiscards),
Jeff Garzik6aa20a22006-09-13 13:24:59 -04007464 STATS_OFFSET32(stat_IfInMBUFDiscards),
Michael Chancea94db2006-06-12 22:16:13 -07007465 STATS_OFFSET32(stat_FwRxDrop),
Michael Chanb6016b72005-05-26 13:03:09 -07007466};
7467
7468/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7469 * skipped because of errata.
Jeff Garzik6aa20a22006-09-13 13:24:59 -04007470 */
Peter Hagervall14ab9b82005-08-10 14:18:16 -07007471static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
Michael Chanb6016b72005-05-26 13:03:09 -07007472 8,0,8,8,8,8,8,8,8,8,
7473 4,0,4,4,4,4,4,4,4,4,
7474 4,4,4,4,4,4,4,4,4,4,
7475 4,4,4,4,4,4,4,4,4,4,
Michael Chan790dab22009-08-21 16:20:47 +00007476 4,4,4,4,4,4,4,
Michael Chanb6016b72005-05-26 13:03:09 -07007477};
7478
Michael Chan5b0c76a2005-11-04 08:45:49 -08007479static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7480 8,0,8,8,8,8,8,8,8,8,
7481 4,4,4,4,4,4,4,4,4,4,
7482 4,4,4,4,4,4,4,4,4,4,
7483 4,4,4,4,4,4,4,4,4,4,
Michael Chan790dab22009-08-21 16:20:47 +00007484 4,4,4,4,4,4,4,
Michael Chan5b0c76a2005-11-04 08:45:49 -08007485};
7486
Michael Chanb6016b72005-05-26 13:03:09 -07007487#define BNX2_NUM_TESTS 6
7488
Peter Hagervall14ab9b82005-08-10 14:18:16 -07007489static struct {
Michael Chanb6016b72005-05-26 13:03:09 -07007490 char string[ETH_GSTRING_LEN];
7491} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7492 { "register_test (offline)" },
7493 { "memory_test (offline)" },
7494 { "loopback_test (offline)" },
7495 { "nvram_test (online)" },
7496 { "interrupt_test (online)" },
7497 { "link_test (online)" },
7498};
7499
7500static int
Jeff Garzikb9f2c042007-10-03 18:07:32 -07007501bnx2_get_sset_count(struct net_device *dev, int sset)
Michael Chanb6016b72005-05-26 13:03:09 -07007502{
Jeff Garzikb9f2c042007-10-03 18:07:32 -07007503 switch (sset) {
7504 case ETH_SS_TEST:
7505 return BNX2_NUM_TESTS;
7506 case ETH_SS_STATS:
7507 return BNX2_NUM_STATS;
7508 default:
7509 return -EOPNOTSUPP;
7510 }
Michael Chanb6016b72005-05-26 13:03:09 -07007511}
7512
7513static void
7514bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7515{
Michael Chan972ec0d2006-01-23 16:12:43 -08007516 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007517
7518 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7519 if (etest->flags & ETH_TEST_FL_OFFLINE) {
Michael Chan80be4432006-11-19 14:07:28 -08007520 int i;
7521
Michael Chan212f9932010-04-27 11:28:10 +00007522 bnx2_netif_stop(bp, true);
Michael Chanb6016b72005-05-26 13:03:09 -07007523 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7524 bnx2_free_skbs(bp);
7525
7526 if (bnx2_test_registers(bp) != 0) {
7527 buf[0] = 1;
7528 etest->flags |= ETH_TEST_FL_FAILED;
7529 }
7530 if (bnx2_test_memory(bp) != 0) {
7531 buf[1] = 1;
7532 etest->flags |= ETH_TEST_FL_FAILED;
7533 }
Michael Chanbc5a0692006-01-23 16:13:22 -08007534 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
Michael Chanb6016b72005-05-26 13:03:09 -07007535 etest->flags |= ETH_TEST_FL_FAILED;
Michael Chanb6016b72005-05-26 13:03:09 -07007536
Michael Chan9f52b562008-10-09 12:21:46 -07007537 if (!netif_running(bp->dev))
7538 bnx2_shutdown_chip(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07007539 else {
Michael Chan9a120bc2008-05-16 22:17:45 -07007540 bnx2_init_nic(bp, 1);
Michael Chan212f9932010-04-27 11:28:10 +00007541 bnx2_netif_start(bp, true);
Michael Chanb6016b72005-05-26 13:03:09 -07007542 }
7543
7544 /* wait for link up */
Michael Chan80be4432006-11-19 14:07:28 -08007545 for (i = 0; i < 7; i++) {
7546 if (bp->link_up)
7547 break;
7548 msleep_interruptible(1000);
7549 }
Michael Chanb6016b72005-05-26 13:03:09 -07007550 }
7551
7552 if (bnx2_test_nvram(bp) != 0) {
7553 buf[3] = 1;
7554 etest->flags |= ETH_TEST_FL_FAILED;
7555 }
7556 if (bnx2_test_intr(bp) != 0) {
7557 buf[4] = 1;
7558 etest->flags |= ETH_TEST_FL_FAILED;
7559 }
7560
7561 if (bnx2_test_link(bp) != 0) {
7562 buf[5] = 1;
7563 etest->flags |= ETH_TEST_FL_FAILED;
7564
7565 }
7566}
7567
7568static void
7569bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7570{
7571 switch (stringset) {
7572 case ETH_SS_STATS:
7573 memcpy(buf, bnx2_stats_str_arr,
7574 sizeof(bnx2_stats_str_arr));
7575 break;
7576 case ETH_SS_TEST:
7577 memcpy(buf, bnx2_tests_str_arr,
7578 sizeof(bnx2_tests_str_arr));
7579 break;
7580 }
7581}
7582
Michael Chanb6016b72005-05-26 13:03:09 -07007583static void
7584bnx2_get_ethtool_stats(struct net_device *dev,
7585 struct ethtool_stats *stats, u64 *buf)
7586{
Michael Chan972ec0d2006-01-23 16:12:43 -08007587 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007588 int i;
7589 u32 *hw_stats = (u32 *) bp->stats_blk;
Michael Chan354fcd72010-01-17 07:30:44 +00007590 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
Peter Hagervall14ab9b82005-08-10 14:18:16 -07007591 u8 *stats_len_arr = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07007592
7593 if (hw_stats == NULL) {
7594 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7595 return;
7596 }
7597
Michael Chan4ce45e02012-12-06 10:33:10 +00007598 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) ||
7599 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) ||
7600 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A2) ||
7601 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0))
Michael Chanb6016b72005-05-26 13:03:09 -07007602 stats_len_arr = bnx2_5706_stats_len_arr;
Michael Chan5b0c76a2005-11-04 08:45:49 -08007603 else
7604 stats_len_arr = bnx2_5708_stats_len_arr;
Michael Chanb6016b72005-05-26 13:03:09 -07007605
7606 for (i = 0; i < BNX2_NUM_STATS; i++) {
Michael Chan354fcd72010-01-17 07:30:44 +00007607 unsigned long offset;
7608
Michael Chanb6016b72005-05-26 13:03:09 -07007609 if (stats_len_arr[i] == 0) {
7610 /* skip this counter */
7611 buf[i] = 0;
7612 continue;
7613 }
Michael Chan354fcd72010-01-17 07:30:44 +00007614
7615 offset = bnx2_stats_offset_arr[i];
Michael Chanb6016b72005-05-26 13:03:09 -07007616 if (stats_len_arr[i] == 4) {
7617 /* 4-byte counter */
Michael Chan354fcd72010-01-17 07:30:44 +00007618 buf[i] = (u64) *(hw_stats + offset) +
7619 *(temp_stats + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07007620 continue;
7621 }
7622 /* 8-byte counter */
Michael Chan354fcd72010-01-17 07:30:44 +00007623 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7624 *(hw_stats + offset + 1) +
7625 (((u64) *(temp_stats + offset)) << 32) +
7626 *(temp_stats + offset + 1);
Michael Chanb6016b72005-05-26 13:03:09 -07007627 }
7628}
7629
7630static int
stephen hemminger2e17e1a2011-04-04 11:06:36 +00007631bnx2_set_phys_id(struct net_device *dev, enum ethtool_phys_id_state state)
Michael Chanb6016b72005-05-26 13:03:09 -07007632{
Michael Chan972ec0d2006-01-23 16:12:43 -08007633 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007634
stephen hemminger2e17e1a2011-04-04 11:06:36 +00007635 switch (state) {
7636 case ETHTOOL_ID_ACTIVE:
Michael Chane503e062012-12-06 10:33:08 +00007637 bp->leds_save = BNX2_RD(bp, BNX2_MISC_CFG);
7638 BNX2_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
Allan, Bruce Wfce55922011-04-13 13:09:10 +00007639 return 1; /* cycle on/off once per second */
Michael Chanb6016b72005-05-26 13:03:09 -07007640
stephen hemminger2e17e1a2011-04-04 11:06:36 +00007641 case ETHTOOL_ID_ON:
Michael Chane503e062012-12-06 10:33:08 +00007642 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7643 BNX2_EMAC_LED_1000MB_OVERRIDE |
7644 BNX2_EMAC_LED_100MB_OVERRIDE |
7645 BNX2_EMAC_LED_10MB_OVERRIDE |
7646 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7647 BNX2_EMAC_LED_TRAFFIC);
stephen hemminger2e17e1a2011-04-04 11:06:36 +00007648 break;
Michael Chanb6016b72005-05-26 13:03:09 -07007649
stephen hemminger2e17e1a2011-04-04 11:06:36 +00007650 case ETHTOOL_ID_OFF:
Michael Chane503e062012-12-06 10:33:08 +00007651 BNX2_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
stephen hemminger2e17e1a2011-04-04 11:06:36 +00007652 break;
7653
7654 case ETHTOOL_ID_INACTIVE:
Michael Chane503e062012-12-06 10:33:08 +00007655 BNX2_WR(bp, BNX2_EMAC_LED, 0);
7656 BNX2_WR(bp, BNX2_MISC_CFG, bp->leds_save);
stephen hemminger2e17e1a2011-04-04 11:06:36 +00007657 break;
Michael Chanb6016b72005-05-26 13:03:09 -07007658 }
Michael Chan9f52b562008-10-09 12:21:46 -07007659
Michael Chanb6016b72005-05-26 13:03:09 -07007660 return 0;
7661}
7662
Michał Mirosławc8f44af2011-11-15 15:29:55 +00007663static netdev_features_t
7664bnx2_fix_features(struct net_device *dev, netdev_features_t features)
Michael Chan4666f872007-05-03 13:22:28 -07007665{
7666 struct bnx2 *bp = netdev_priv(dev);
7667
Michał Mirosław8d7dfc22011-04-10 04:47:46 +00007668 if (!(bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
Patrick McHardyf6469682013-04-19 02:04:27 +00007669 features |= NETIF_F_HW_VLAN_CTAG_RX;
Michał Mirosław8d7dfc22011-04-10 04:47:46 +00007670
7671 return features;
Michael Chan4666f872007-05-03 13:22:28 -07007672}
7673
Michael Chanfdc85412010-07-03 20:42:16 +00007674static int
Michał Mirosławc8f44af2011-11-15 15:29:55 +00007675bnx2_set_features(struct net_device *dev, netdev_features_t features)
Michael Chanfdc85412010-07-03 20:42:16 +00007676{
Jesse Gross7d0fd212010-10-20 13:56:09 +00007677 struct bnx2 *bp = netdev_priv(dev);
Jesse Gross7d0fd212010-10-20 13:56:09 +00007678
Michael Chan7c810472011-01-24 12:59:02 +00007679 /* TSO with VLAN tag won't work with current firmware */
Patrick McHardyf6469682013-04-19 02:04:27 +00007680 if (features & NETIF_F_HW_VLAN_CTAG_TX)
Michał Mirosław8d7dfc22011-04-10 04:47:46 +00007681 dev->vlan_features |= (dev->hw_features & NETIF_F_ALL_TSO);
7682 else
7683 dev->vlan_features &= ~NETIF_F_ALL_TSO;
Michael Chan7c810472011-01-24 12:59:02 +00007684
Patrick McHardyf6469682013-04-19 02:04:27 +00007685 if ((!!(features & NETIF_F_HW_VLAN_CTAG_RX) !=
Jesse Gross7d0fd212010-10-20 13:56:09 +00007686 !!(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) &&
7687 netif_running(dev)) {
7688 bnx2_netif_stop(bp, false);
Michał Mirosław8d7dfc22011-04-10 04:47:46 +00007689 dev->features = features;
Jesse Gross7d0fd212010-10-20 13:56:09 +00007690 bnx2_set_rx_mode(dev);
7691 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
7692 bnx2_netif_start(bp, false);
Michał Mirosław8d7dfc22011-04-10 04:47:46 +00007693 return 1;
Jesse Gross7d0fd212010-10-20 13:56:09 +00007694 }
7695
7696 return 0;
Michael Chanfdc85412010-07-03 20:42:16 +00007697}
7698
Michael Chanb0332812012-02-05 15:24:38 +00007699static void bnx2_get_channels(struct net_device *dev,
7700 struct ethtool_channels *channels)
7701{
7702 struct bnx2 *bp = netdev_priv(dev);
7703 u32 max_rx_rings = 1;
7704 u32 max_tx_rings = 1;
7705
7706 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {
7707 max_rx_rings = RX_MAX_RINGS;
7708 max_tx_rings = TX_MAX_RINGS;
7709 }
7710
7711 channels->max_rx = max_rx_rings;
7712 channels->max_tx = max_tx_rings;
7713 channels->max_other = 0;
7714 channels->max_combined = 0;
7715 channels->rx_count = bp->num_rx_rings;
7716 channels->tx_count = bp->num_tx_rings;
7717 channels->other_count = 0;
7718 channels->combined_count = 0;
7719}
7720
7721static int bnx2_set_channels(struct net_device *dev,
7722 struct ethtool_channels *channels)
7723{
7724 struct bnx2 *bp = netdev_priv(dev);
7725 u32 max_rx_rings = 1;
7726 u32 max_tx_rings = 1;
7727 int rc = 0;
7728
7729 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !disable_msi) {
7730 max_rx_rings = RX_MAX_RINGS;
7731 max_tx_rings = TX_MAX_RINGS;
7732 }
7733 if (channels->rx_count > max_rx_rings ||
7734 channels->tx_count > max_tx_rings)
7735 return -EINVAL;
7736
7737 bp->num_req_rx_rings = channels->rx_count;
7738 bp->num_req_tx_rings = channels->tx_count;
7739
7740 if (netif_running(dev))
7741 rc = bnx2_change_ring_size(bp, bp->rx_ring_size,
7742 bp->tx_ring_size, true);
7743
7744 return rc;
7745}
7746
Jeff Garzik7282d492006-09-13 14:30:00 -04007747static const struct ethtool_ops bnx2_ethtool_ops = {
Michael Chanb6016b72005-05-26 13:03:09 -07007748 .get_settings = bnx2_get_settings,
7749 .set_settings = bnx2_set_settings,
7750 .get_drvinfo = bnx2_get_drvinfo,
Michael Chan244ac4f2006-03-20 17:48:46 -08007751 .get_regs_len = bnx2_get_regs_len,
7752 .get_regs = bnx2_get_regs,
Michael Chanb6016b72005-05-26 13:03:09 -07007753 .get_wol = bnx2_get_wol,
7754 .set_wol = bnx2_set_wol,
7755 .nway_reset = bnx2_nway_reset,
Ooiwa Naohiro7959ea22009-06-24 00:19:06 -07007756 .get_link = bnx2_get_link,
Michael Chanb6016b72005-05-26 13:03:09 -07007757 .get_eeprom_len = bnx2_get_eeprom_len,
7758 .get_eeprom = bnx2_get_eeprom,
7759 .set_eeprom = bnx2_set_eeprom,
7760 .get_coalesce = bnx2_get_coalesce,
7761 .set_coalesce = bnx2_set_coalesce,
7762 .get_ringparam = bnx2_get_ringparam,
7763 .set_ringparam = bnx2_set_ringparam,
7764 .get_pauseparam = bnx2_get_pauseparam,
7765 .set_pauseparam = bnx2_set_pauseparam,
Michael Chanb6016b72005-05-26 13:03:09 -07007766 .self_test = bnx2_self_test,
7767 .get_strings = bnx2_get_strings,
stephen hemminger2e17e1a2011-04-04 11:06:36 +00007768 .set_phys_id = bnx2_set_phys_id,
Michael Chanb6016b72005-05-26 13:03:09 -07007769 .get_ethtool_stats = bnx2_get_ethtool_stats,
Jeff Garzikb9f2c042007-10-03 18:07:32 -07007770 .get_sset_count = bnx2_get_sset_count,
Michael Chanb0332812012-02-05 15:24:38 +00007771 .get_channels = bnx2_get_channels,
7772 .set_channels = bnx2_set_channels,
Michael Chanb6016b72005-05-26 13:03:09 -07007773};
7774
7775/* Called with rtnl_lock */
7776static int
7777bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7778{
Peter Hagervall14ab9b82005-08-10 14:18:16 -07007779 struct mii_ioctl_data *data = if_mii(ifr);
Michael Chan972ec0d2006-01-23 16:12:43 -08007780 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007781 int err;
7782
7783 switch(cmd) {
7784 case SIOCGMIIPHY:
7785 data->phy_id = bp->phy_addr;
7786
7787 /* fallthru */
7788 case SIOCGMIIREG: {
7789 u32 mii_regval;
7790
Michael Chan583c28e2008-01-21 19:51:35 -08007791 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan7b6b8342007-07-07 22:50:15 -07007792 return -EOPNOTSUPP;
7793
Michael Chandad3e452007-05-03 13:18:03 -07007794 if (!netif_running(dev))
7795 return -EAGAIN;
7796
Michael Chanc770a652005-08-25 15:38:39 -07007797 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007798 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
Michael Chanc770a652005-08-25 15:38:39 -07007799 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007800
7801 data->val_out = mii_regval;
7802
7803 return err;
7804 }
7805
7806 case SIOCSMIIREG:
Michael Chan583c28e2008-01-21 19:51:35 -08007807 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan7b6b8342007-07-07 22:50:15 -07007808 return -EOPNOTSUPP;
7809
Michael Chandad3e452007-05-03 13:18:03 -07007810 if (!netif_running(dev))
7811 return -EAGAIN;
7812
Michael Chanc770a652005-08-25 15:38:39 -07007813 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007814 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
Michael Chanc770a652005-08-25 15:38:39 -07007815 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07007816
7817 return err;
7818
7819 default:
7820 /* do nothing */
7821 break;
7822 }
7823 return -EOPNOTSUPP;
7824}
7825
7826/* Called with rtnl_lock */
7827static int
7828bnx2_change_mac_addr(struct net_device *dev, void *p)
7829{
7830 struct sockaddr *addr = p;
Michael Chan972ec0d2006-01-23 16:12:43 -08007831 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007832
Michael Chan73eef4c2005-08-25 15:39:15 -07007833 if (!is_valid_ether_addr(addr->sa_data))
Danny Kukawka504f9b52012-02-21 02:07:49 +00007834 return -EADDRNOTAVAIL;
Michael Chan73eef4c2005-08-25 15:39:15 -07007835
Michael Chanb6016b72005-05-26 13:03:09 -07007836 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7837 if (netif_running(dev))
Benjamin Li5fcaed02008-07-14 22:39:52 -07007838 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07007839
7840 return 0;
7841}
7842
7843/* Called with rtnl_lock */
7844static int
7845bnx2_change_mtu(struct net_device *dev, int new_mtu)
7846{
Michael Chan972ec0d2006-01-23 16:12:43 -08007847 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007848
7849 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7850 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7851 return -EINVAL;
7852
7853 dev->mtu = new_mtu;
Michael Chanb0332812012-02-05 15:24:38 +00007854 return bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size,
7855 false);
Michael Chanb6016b72005-05-26 13:03:09 -07007856}
7857
Alexey Dobriyan257ddbd2010-01-27 10:17:41 +00007858#ifdef CONFIG_NET_POLL_CONTROLLER
Michael Chanb6016b72005-05-26 13:03:09 -07007859static void
7860poll_bnx2(struct net_device *dev)
7861{
Michael Chan972ec0d2006-01-23 16:12:43 -08007862 struct bnx2 *bp = netdev_priv(dev);
Neil Hormanb2af2c12008-11-12 16:23:44 -08007863 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07007864
Neil Hormanb2af2c12008-11-12 16:23:44 -08007865 for (i = 0; i < bp->irq_nvecs; i++) {
Michael Chan1bf1e342010-03-23 13:13:12 +00007866 struct bnx2_irq *irq = &bp->irq_tbl[i];
7867
7868 disable_irq(irq->vector);
7869 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7870 enable_irq(irq->vector);
Neil Hormanb2af2c12008-11-12 16:23:44 -08007871 }
Michael Chanb6016b72005-05-26 13:03:09 -07007872}
7873#endif
7874
Bill Pembertoncfd95a62012-12-03 09:22:58 -05007875static void
Michael Chan253c8b72007-01-08 19:56:01 -08007876bnx2_get_5709_media(struct bnx2 *bp)
7877{
Michael Chane503e062012-12-06 10:33:08 +00007878 u32 val = BNX2_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
Michael Chan253c8b72007-01-08 19:56:01 -08007879 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7880 u32 strap;
7881
7882 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7883 return;
7884 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
Michael Chan583c28e2008-01-21 19:51:35 -08007885 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chan253c8b72007-01-08 19:56:01 -08007886 return;
7887 }
7888
7889 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7890 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7891 else
7892 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7893
Michael Chanaefd90e2012-06-16 15:45:43 +00007894 if (bp->func == 0) {
Michael Chan253c8b72007-01-08 19:56:01 -08007895 switch (strap) {
7896 case 0x4:
7897 case 0x5:
7898 case 0x6:
Michael Chan583c28e2008-01-21 19:51:35 -08007899 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chan253c8b72007-01-08 19:56:01 -08007900 return;
7901 }
7902 } else {
7903 switch (strap) {
7904 case 0x1:
7905 case 0x2:
7906 case 0x4:
Michael Chan583c28e2008-01-21 19:51:35 -08007907 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chan253c8b72007-01-08 19:56:01 -08007908 return;
7909 }
7910 }
7911}
7912
Bill Pembertoncfd95a62012-12-03 09:22:58 -05007913static void
Michael Chan883e5152007-05-03 13:25:11 -07007914bnx2_get_pci_speed(struct bnx2 *bp)
7915{
7916 u32 reg;
7917
Michael Chane503e062012-12-06 10:33:08 +00007918 reg = BNX2_RD(bp, BNX2_PCICFG_MISC_STATUS);
Michael Chan883e5152007-05-03 13:25:11 -07007919 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7920 u32 clkreg;
7921
David S. Millerf86e82f2008-01-21 17:15:40 -08007922 bp->flags |= BNX2_FLAG_PCIX;
Michael Chan883e5152007-05-03 13:25:11 -07007923
Michael Chane503e062012-12-06 10:33:08 +00007924 clkreg = BNX2_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
Michael Chan883e5152007-05-03 13:25:11 -07007925
7926 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7927 switch (clkreg) {
7928 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7929 bp->bus_speed_mhz = 133;
7930 break;
7931
7932 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7933 bp->bus_speed_mhz = 100;
7934 break;
7935
7936 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7937 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7938 bp->bus_speed_mhz = 66;
7939 break;
7940
7941 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7942 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7943 bp->bus_speed_mhz = 50;
7944 break;
7945
7946 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7947 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7948 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7949 bp->bus_speed_mhz = 33;
7950 break;
7951 }
7952 }
7953 else {
7954 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7955 bp->bus_speed_mhz = 66;
7956 else
7957 bp->bus_speed_mhz = 33;
7958 }
7959
7960 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
David S. Millerf86e82f2008-01-21 17:15:40 -08007961 bp->flags |= BNX2_FLAG_PCI_32BIT;
Michael Chan883e5152007-05-03 13:25:11 -07007962
7963}
7964
Bill Pembertoncfd95a62012-12-03 09:22:58 -05007965static void
Michael Chan76d99062009-12-03 09:46:34 +00007966bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7967{
Matt Carlsondf25bc32010-02-26 14:04:44 +00007968 int rc, i, j;
Michael Chan76d99062009-12-03 09:46:34 +00007969 u8 *data;
Matt Carlsondf25bc32010-02-26 14:04:44 +00007970 unsigned int block_end, rosize, len;
Michael Chan76d99062009-12-03 09:46:34 +00007971
Michael Chan012093f2009-12-03 15:58:00 -08007972#define BNX2_VPD_NVRAM_OFFSET 0x300
7973#define BNX2_VPD_LEN 128
Michael Chan76d99062009-12-03 09:46:34 +00007974#define BNX2_MAX_VER_SLEN 30
7975
7976 data = kmalloc(256, GFP_KERNEL);
7977 if (!data)
7978 return;
7979
Michael Chan012093f2009-12-03 15:58:00 -08007980 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7981 BNX2_VPD_LEN);
Michael Chan76d99062009-12-03 09:46:34 +00007982 if (rc)
7983 goto vpd_done;
7984
Michael Chan012093f2009-12-03 15:58:00 -08007985 for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7986 data[i] = data[i + BNX2_VPD_LEN + 3];
7987 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
7988 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
7989 data[i + 3] = data[i + BNX2_VPD_LEN];
Michael Chan76d99062009-12-03 09:46:34 +00007990 }
7991
Matt Carlsondf25bc32010-02-26 14:04:44 +00007992 i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
7993 if (i < 0)
Michael Chan76d99062009-12-03 09:46:34 +00007994 goto vpd_done;
Matt Carlsondf25bc32010-02-26 14:04:44 +00007995
7996 rosize = pci_vpd_lrdt_size(&data[i]);
7997 i += PCI_VPD_LRDT_TAG_SIZE;
7998 block_end = i + rosize;
7999
8000 if (block_end > BNX2_VPD_LEN)
8001 goto vpd_done;
8002
8003 j = pci_vpd_find_info_keyword(data, i, rosize,
8004 PCI_VPD_RO_KEYWORD_MFR_ID);
8005 if (j < 0)
8006 goto vpd_done;
8007
8008 len = pci_vpd_info_field_size(&data[j]);
8009
8010 j += PCI_VPD_INFO_FLD_HDR_SIZE;
8011 if (j + len > block_end || len != 4 ||
8012 memcmp(&data[j], "1028", 4))
8013 goto vpd_done;
8014
8015 j = pci_vpd_find_info_keyword(data, i, rosize,
8016 PCI_VPD_RO_KEYWORD_VENDOR0);
8017 if (j < 0)
8018 goto vpd_done;
8019
8020 len = pci_vpd_info_field_size(&data[j]);
8021
8022 j += PCI_VPD_INFO_FLD_HDR_SIZE;
8023 if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
8024 goto vpd_done;
8025
8026 memcpy(bp->fw_version, &data[j], len);
8027 bp->fw_version[len] = ' ';
Michael Chan76d99062009-12-03 09:46:34 +00008028
8029vpd_done:
8030 kfree(data);
8031}
8032
Bill Pembertoncfd95a62012-12-03 09:22:58 -05008033static int
Michael Chanb6016b72005-05-26 13:03:09 -07008034bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
8035{
8036 struct bnx2 *bp;
Michael Chan58fc2ea2007-07-07 22:52:02 -07008037 int rc, i, j;
Michael Chanb6016b72005-05-26 13:03:09 -07008038 u32 reg;
Michael Chan40453c82007-05-03 13:19:18 -07008039 u64 dma_mask, persist_dma_mask;
John Feeneycd709aa2010-08-22 17:45:53 +00008040 int err;
Michael Chanb6016b72005-05-26 13:03:09 -07008041
Michael Chanb6016b72005-05-26 13:03:09 -07008042 SET_NETDEV_DEV(dev, &pdev->dev);
Michael Chan972ec0d2006-01-23 16:12:43 -08008043 bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07008044
8045 bp->flags = 0;
8046 bp->phy_flags = 0;
8047
Michael Chan354fcd72010-01-17 07:30:44 +00008048 bp->temp_stats_blk =
8049 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
8050
8051 if (bp->temp_stats_blk == NULL) {
8052 rc = -ENOMEM;
8053 goto err_out;
8054 }
8055
Michael Chanb6016b72005-05-26 13:03:09 -07008056 /* enable device (incl. PCI PM wakeup), and bus-mastering */
8057 rc = pci_enable_device(pdev);
8058 if (rc) {
Joe Perches3a9c6a42010-02-17 15:01:51 +00008059 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
Michael Chanb6016b72005-05-26 13:03:09 -07008060 goto err_out;
8061 }
8062
8063 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04008064 dev_err(&pdev->dev,
Joe Perches3a9c6a42010-02-17 15:01:51 +00008065 "Cannot find PCI device base address, aborting\n");
Michael Chanb6016b72005-05-26 13:03:09 -07008066 rc = -ENODEV;
8067 goto err_out_disable;
8068 }
8069
8070 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
8071 if (rc) {
Joe Perches3a9c6a42010-02-17 15:01:51 +00008072 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
Michael Chanb6016b72005-05-26 13:03:09 -07008073 goto err_out_disable;
8074 }
8075
8076 pci_set_master(pdev);
8077
Yijing Wang85768272013-06-18 16:12:37 +08008078 bp->pm_cap = pdev->pm_cap;
Michael Chanb6016b72005-05-26 13:03:09 -07008079 if (bp->pm_cap == 0) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04008080 dev_err(&pdev->dev,
Joe Perches3a9c6a42010-02-17 15:01:51 +00008081 "Cannot find power management capability, aborting\n");
Michael Chanb6016b72005-05-26 13:03:09 -07008082 rc = -EIO;
8083 goto err_out_release;
8084 }
8085
Michael Chanb6016b72005-05-26 13:03:09 -07008086 bp->dev = dev;
8087 bp->pdev = pdev;
8088
8089 spin_lock_init(&bp->phy_lock);
Michael Chan1b8227c2007-05-03 13:24:05 -07008090 spin_lock_init(&bp->indirect_lock);
Michael Chanc5a88952009-08-14 15:49:45 +00008091#ifdef BCM_CNIC
8092 mutex_init(&bp->cnic_lock);
8093#endif
David Howellsc4028952006-11-22 14:57:56 +00008094 INIT_WORK(&bp->reset_task, bnx2_reset_task);
Michael Chanb6016b72005-05-26 13:03:09 -07008095
Francois Romieuc0357e92012-03-09 14:51:47 +01008096 bp->regview = pci_iomap(pdev, 0, MB_GET_CID_ADDR(TX_TSS_CID +
8097 TX_MAX_TSS_RINGS + 1));
Michael Chanb6016b72005-05-26 13:03:09 -07008098 if (!bp->regview) {
Joe Perches3a9c6a42010-02-17 15:01:51 +00008099 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
Michael Chanb6016b72005-05-26 13:03:09 -07008100 rc = -ENOMEM;
8101 goto err_out_release;
8102 }
8103
8104 /* Configure byte swap and enable write to the reg_window registers.
8105 * Rely on CPU to do target byte swapping on big endian systems
8106 * The chip's target access swapping will not swap all accesses
8107 */
Michael Chane503e062012-12-06 10:33:08 +00008108 BNX2_WR(bp, BNX2_PCICFG_MISC_CONFIG,
8109 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
8110 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
Michael Chanb6016b72005-05-26 13:03:09 -07008111
Michael Chane503e062012-12-06 10:33:08 +00008112 bp->chip_id = BNX2_RD(bp, BNX2_MISC_ID);
Michael Chanb6016b72005-05-26 13:03:09 -07008113
Michael Chan4ce45e02012-12-06 10:33:10 +00008114 if (BNX2_CHIP(bp) == BNX2_CHIP_5709) {
Jon Masone82760e2011-06-27 07:44:43 +00008115 if (!pci_is_pcie(pdev)) {
8116 dev_err(&pdev->dev, "Not PCIE, aborting\n");
Michael Chan883e5152007-05-03 13:25:11 -07008117 rc = -EIO;
8118 goto err_out_unmap;
8119 }
David S. Millerf86e82f2008-01-21 17:15:40 -08008120 bp->flags |= BNX2_FLAG_PCIE;
Michael Chan4ce45e02012-12-06 10:33:10 +00008121 if (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax)
David S. Millerf86e82f2008-01-21 17:15:40 -08008122 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
Michael Chanc239f272010-10-11 16:12:28 -07008123
8124 /* AER (Advanced Error Reporting) hooks */
8125 err = pci_enable_pcie_error_reporting(pdev);
Michael Chan4bb9ebc2011-01-25 22:14:51 +00008126 if (!err)
8127 bp->flags |= BNX2_FLAG_AER_ENABLED;
Michael Chanc239f272010-10-11 16:12:28 -07008128
Michael Chan883e5152007-05-03 13:25:11 -07008129 } else {
Michael Chan59b47d82006-11-19 14:10:45 -08008130 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
8131 if (bp->pcix_cap == 0) {
8132 dev_err(&pdev->dev,
Joe Perches3a9c6a42010-02-17 15:01:51 +00008133 "Cannot find PCIX capability, aborting\n");
Michael Chan59b47d82006-11-19 14:10:45 -08008134 rc = -EIO;
8135 goto err_out_unmap;
8136 }
Michael Chan61d9e3f2009-08-21 16:20:46 +00008137 bp->flags |= BNX2_FLAG_BROKEN_STATS;
Michael Chan59b47d82006-11-19 14:10:45 -08008138 }
8139
Michael Chan4ce45e02012-12-06 10:33:10 +00008140 if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&
8141 BNX2_CHIP_REV(bp) != BNX2_CHIP_REV_Ax) {
Yijing Wang555a8422013-08-08 21:02:22 +08008142 if (pdev->msix_cap)
David S. Millerf86e82f2008-01-21 17:15:40 -08008143 bp->flags |= BNX2_FLAG_MSIX_CAP;
Michael Chanb4b36042007-12-20 19:59:30 -08008144 }
8145
Michael Chan4ce45e02012-12-06 10:33:10 +00008146 if (BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A0 &&
8147 BNX2_CHIP_ID(bp) != BNX2_CHIP_ID_5706_A1) {
Yijing Wang555a8422013-08-08 21:02:22 +08008148 if (pdev->msi_cap)
David S. Millerf86e82f2008-01-21 17:15:40 -08008149 bp->flags |= BNX2_FLAG_MSI_CAP;
Michael Chan8e6a72c2007-05-03 13:24:48 -07008150 }
8151
Michael Chan40453c82007-05-03 13:19:18 -07008152 /* 5708 cannot support DMA addresses > 40-bit. */
Michael Chan4ce45e02012-12-06 10:33:10 +00008153 if (BNX2_CHIP(bp) == BNX2_CHIP_5708)
Yang Hongyang50cf1562009-04-06 19:01:14 -07008154 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
Michael Chan40453c82007-05-03 13:19:18 -07008155 else
Yang Hongyang6a355282009-04-06 19:01:13 -07008156 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
Michael Chan40453c82007-05-03 13:19:18 -07008157
8158 /* Configure DMA attributes. */
8159 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
8160 dev->features |= NETIF_F_HIGHDMA;
8161 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
8162 if (rc) {
8163 dev_err(&pdev->dev,
Joe Perches3a9c6a42010-02-17 15:01:51 +00008164 "pci_set_consistent_dma_mask failed, aborting\n");
Michael Chan40453c82007-05-03 13:19:18 -07008165 goto err_out_unmap;
8166 }
Yang Hongyang284901a2009-04-06 19:01:15 -07008167 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
Joe Perches3a9c6a42010-02-17 15:01:51 +00008168 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
Michael Chan40453c82007-05-03 13:19:18 -07008169 goto err_out_unmap;
8170 }
8171
David S. Millerf86e82f2008-01-21 17:15:40 -08008172 if (!(bp->flags & BNX2_FLAG_PCIE))
Michael Chan883e5152007-05-03 13:25:11 -07008173 bnx2_get_pci_speed(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07008174
8175 /* 5706A0 may falsely detect SERR and PERR. */
Michael Chan4ce45e02012-12-06 10:33:10 +00008176 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
Michael Chane503e062012-12-06 10:33:08 +00008177 reg = BNX2_RD(bp, PCI_COMMAND);
Michael Chanb6016b72005-05-26 13:03:09 -07008178 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
Michael Chane503e062012-12-06 10:33:08 +00008179 BNX2_WR(bp, PCI_COMMAND, reg);
Michael Chan4ce45e02012-12-06 10:33:10 +00008180 } else if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A1) &&
David S. Millerf86e82f2008-01-21 17:15:40 -08008181 !(bp->flags & BNX2_FLAG_PCIX)) {
Michael Chanb6016b72005-05-26 13:03:09 -07008182
Jeff Garzik9b91cf92006-06-27 11:39:50 -04008183 dev_err(&pdev->dev,
Joe Perches3a9c6a42010-02-17 15:01:51 +00008184 "5706 A1 can only be used in a PCIX bus, aborting\n");
Michael Chanb6016b72005-05-26 13:03:09 -07008185 goto err_out_unmap;
8186 }
8187
8188 bnx2_init_nvram(bp);
8189
Michael Chan2726d6e2008-01-29 21:35:05 -08008190 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
Michael Chane3648b32005-11-04 08:51:21 -08008191
Michael Chanaefd90e2012-06-16 15:45:43 +00008192 if (bnx2_reg_rd_ind(bp, BNX2_MCP_TOE_ID) & BNX2_MCP_TOE_ID_FUNCTION_ID)
8193 bp->func = 1;
8194
Michael Chane3648b32005-11-04 08:51:21 -08008195 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
Michael Chan24cb2302007-01-25 15:49:56 -08008196 BNX2_SHM_HDR_SIGNATURE_SIG) {
Michael Chanaefd90e2012-06-16 15:45:43 +00008197 u32 off = bp->func << 2;
Michael Chan24cb2302007-01-25 15:49:56 -08008198
Michael Chan2726d6e2008-01-29 21:35:05 -08008199 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
Michael Chan24cb2302007-01-25 15:49:56 -08008200 } else
Michael Chane3648b32005-11-04 08:51:21 -08008201 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8202
Michael Chanb6016b72005-05-26 13:03:09 -07008203 /* Get the permanent MAC address. First we need to make sure the
8204 * firmware is actually running.
8205 */
Michael Chan2726d6e2008-01-29 21:35:05 -08008206 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
Michael Chanb6016b72005-05-26 13:03:09 -07008207
8208 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8209 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
Joe Perches3a9c6a42010-02-17 15:01:51 +00008210 dev_err(&pdev->dev, "Firmware not running, aborting\n");
Michael Chanb6016b72005-05-26 13:03:09 -07008211 rc = -ENODEV;
8212 goto err_out_unmap;
8213 }
8214
Michael Chan76d99062009-12-03 09:46:34 +00008215 bnx2_read_vpd_fw_ver(bp);
8216
8217 j = strlen(bp->fw_version);
Michael Chan2726d6e2008-01-29 21:35:05 -08008218 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
Michael Chan76d99062009-12-03 09:46:34 +00008219 for (i = 0; i < 3 && j < 24; i++) {
Michael Chan58fc2ea2007-07-07 22:52:02 -07008220 u8 num, k, skip0;
8221
Michael Chan76d99062009-12-03 09:46:34 +00008222 if (i == 0) {
8223 bp->fw_version[j++] = 'b';
8224 bp->fw_version[j++] = 'c';
8225 bp->fw_version[j++] = ' ';
8226 }
Michael Chan58fc2ea2007-07-07 22:52:02 -07008227 num = (u8) (reg >> (24 - (i * 8)));
8228 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8229 if (num >= k || !skip0 || k == 1) {
8230 bp->fw_version[j++] = (num / k) + '0';
8231 skip0 = 0;
8232 }
8233 }
8234 if (i != 2)
8235 bp->fw_version[j++] = '.';
8236 }
Michael Chan2726d6e2008-01-29 21:35:05 -08008237 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
Michael Chan846f5c62007-10-10 16:16:51 -07008238 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8239 bp->wol = 1;
8240
8241 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
David S. Millerf86e82f2008-01-21 17:15:40 -08008242 bp->flags |= BNX2_FLAG_ASF_ENABLE;
Michael Chanc2d3db82007-07-16 18:26:43 -07008243
8244 for (i = 0; i < 30; i++) {
Michael Chan2726d6e2008-01-29 21:35:05 -08008245 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
Michael Chanc2d3db82007-07-16 18:26:43 -07008246 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8247 break;
8248 msleep(10);
8249 }
8250 }
Michael Chan2726d6e2008-01-29 21:35:05 -08008251 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
Michael Chan58fc2ea2007-07-07 22:52:02 -07008252 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8253 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8254 reg != BNX2_CONDITION_MFW_RUN_NONE) {
Michael Chan2726d6e2008-01-29 21:35:05 -08008255 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
Michael Chan58fc2ea2007-07-07 22:52:02 -07008256
Michael Chan76d99062009-12-03 09:46:34 +00008257 if (j < 32)
8258 bp->fw_version[j++] = ' ';
8259 for (i = 0; i < 3 && j < 28; i++) {
Michael Chan2726d6e2008-01-29 21:35:05 -08008260 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
Michael Chan3aeb7d22011-07-20 14:55:25 +00008261 reg = be32_to_cpu(reg);
Michael Chan58fc2ea2007-07-07 22:52:02 -07008262 memcpy(&bp->fw_version[j], &reg, 4);
8263 j += 4;
8264 }
8265 }
Michael Chanb6016b72005-05-26 13:03:09 -07008266
Michael Chan2726d6e2008-01-29 21:35:05 -08008267 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
Michael Chanb6016b72005-05-26 13:03:09 -07008268 bp->mac_addr[0] = (u8) (reg >> 8);
8269 bp->mac_addr[1] = (u8) reg;
8270
Michael Chan2726d6e2008-01-29 21:35:05 -08008271 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
Michael Chanb6016b72005-05-26 13:03:09 -07008272 bp->mac_addr[2] = (u8) (reg >> 24);
8273 bp->mac_addr[3] = (u8) (reg >> 16);
8274 bp->mac_addr[4] = (u8) (reg >> 8);
8275 bp->mac_addr[5] = (u8) reg;
8276
Michael Chan2bc40782012-12-06 10:33:09 +00008277 bp->tx_ring_size = BNX2_MAX_TX_DESC_CNT;
Michael Chan932f3772006-08-15 01:39:36 -07008278 bnx2_set_rx_ring_size(bp, 255);
Michael Chanb6016b72005-05-26 13:03:09 -07008279
Michael Chancf7474a2009-08-21 16:20:48 +00008280 bp->tx_quick_cons_trip_int = 2;
Michael Chanb6016b72005-05-26 13:03:09 -07008281 bp->tx_quick_cons_trip = 20;
Michael Chancf7474a2009-08-21 16:20:48 +00008282 bp->tx_ticks_int = 18;
Michael Chanb6016b72005-05-26 13:03:09 -07008283 bp->tx_ticks = 80;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04008284
Michael Chancf7474a2009-08-21 16:20:48 +00008285 bp->rx_quick_cons_trip_int = 2;
8286 bp->rx_quick_cons_trip = 12;
Michael Chanb6016b72005-05-26 13:03:09 -07008287 bp->rx_ticks_int = 18;
8288 bp->rx_ticks = 18;
8289
Michael Chan7ea69202007-07-16 18:27:10 -07008290 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
Michael Chanb6016b72005-05-26 13:03:09 -07008291
Benjamin Liac392ab2008-09-18 16:40:49 -07008292 bp->current_interval = BNX2_TIMER_INTERVAL;
Michael Chanb6016b72005-05-26 13:03:09 -07008293
Michael Chan5b0c76a2005-11-04 08:45:49 -08008294 bp->phy_addr = 1;
8295
Michael Chanb6016b72005-05-26 13:03:09 -07008296 /* Disable WOL support if we are running on a SERDES chip. */
Michael Chan4ce45e02012-12-06 10:33:10 +00008297 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
Michael Chan253c8b72007-01-08 19:56:01 -08008298 bnx2_get_5709_media(bp);
Michael Chan4ce45e02012-12-06 10:33:10 +00008299 else if (BNX2_CHIP_BOND(bp) & BNX2_CHIP_BOND_SERDES_BIT)
Michael Chan583c28e2008-01-21 19:51:35 -08008300 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chanbac0dff2006-11-19 14:15:05 -08008301
Michael Chan0d8a6572007-07-07 22:49:43 -07008302 bp->phy_port = PORT_TP;
Michael Chan583c28e2008-01-21 19:51:35 -08008303 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan0d8a6572007-07-07 22:49:43 -07008304 bp->phy_port = PORT_FIBRE;
Michael Chan2726d6e2008-01-29 21:35:05 -08008305 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
Michael Chan846f5c62007-10-10 16:16:51 -07008306 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
David S. Millerf86e82f2008-01-21 17:15:40 -08008307 bp->flags |= BNX2_FLAG_NO_WOL;
Michael Chan846f5c62007-10-10 16:16:51 -07008308 bp->wol = 0;
8309 }
Michael Chan4ce45e02012-12-06 10:33:10 +00008310 if (BNX2_CHIP(bp) == BNX2_CHIP_5706) {
Michael Chan38ea3682008-02-23 19:48:57 -08008311 /* Don't do parallel detect on this board because of
8312 * some board problems. The link will not go down
8313 * if we do parallel detect.
8314 */
8315 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8316 pdev->subsystem_device == 0x310c)
8317 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8318 } else {
Michael Chan5b0c76a2005-11-04 08:45:49 -08008319 bp->phy_addr = 2;
Michael Chan5b0c76a2005-11-04 08:45:49 -08008320 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
Michael Chan583c28e2008-01-21 19:51:35 -08008321 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
Michael Chan5b0c76a2005-11-04 08:45:49 -08008322 }
Michael Chan4ce45e02012-12-06 10:33:10 +00008323 } else if (BNX2_CHIP(bp) == BNX2_CHIP_5706 ||
8324 BNX2_CHIP(bp) == BNX2_CHIP_5708)
Michael Chan583c28e2008-01-21 19:51:35 -08008325 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
Michael Chan4ce45e02012-12-06 10:33:10 +00008326 else if (BNX2_CHIP(bp) == BNX2_CHIP_5709 &&
8327 (BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Ax ||
8328 BNX2_CHIP_REV(bp) == BNX2_CHIP_REV_Bx))
Michael Chan583c28e2008-01-21 19:51:35 -08008329 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
Michael Chanb6016b72005-05-26 13:03:09 -07008330
Michael Chan7c62e832008-07-14 22:39:03 -07008331 bnx2_init_fw_cap(bp);
8332
Michael Chan4ce45e02012-12-06 10:33:10 +00008333 if ((BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_A0) ||
8334 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B0) ||
8335 (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5708_B1) ||
Michael Chane503e062012-12-06 10:33:08 +00008336 !(BNX2_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
David S. Millerf86e82f2008-01-21 17:15:40 -08008337 bp->flags |= BNX2_FLAG_NO_WOL;
Michael Chan846f5c62007-10-10 16:16:51 -07008338 bp->wol = 0;
8339 }
Michael Chandda1e392006-01-23 16:08:14 -08008340
Michael Chan6d5e85c2013-08-06 15:50:08 -07008341 if (bp->flags & BNX2_FLAG_NO_WOL)
8342 device_set_wakeup_capable(&bp->pdev->dev, false);
8343 else
8344 device_set_wakeup_enable(&bp->pdev->dev, bp->wol);
8345
Michael Chan4ce45e02012-12-06 10:33:10 +00008346 if (BNX2_CHIP_ID(bp) == BNX2_CHIP_ID_5706_A0) {
Michael Chanb6016b72005-05-26 13:03:09 -07008347 bp->tx_quick_cons_trip_int =
8348 bp->tx_quick_cons_trip;
8349 bp->tx_ticks_int = bp->tx_ticks;
8350 bp->rx_quick_cons_trip_int =
8351 bp->rx_quick_cons_trip;
8352 bp->rx_ticks_int = bp->rx_ticks;
8353 bp->comp_prod_trip_int = bp->comp_prod_trip;
8354 bp->com_ticks_int = bp->com_ticks;
8355 bp->cmd_ticks_int = bp->cmd_ticks;
8356 }
8357
Michael Chanf9317a42006-09-29 17:06:23 -07008358 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8359 *
8360 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8361 * with byte enables disabled on the unused 32-bit word. This is legal
8362 * but causes problems on the AMD 8132 which will eventually stop
8363 * responding after a while.
8364 *
8365 * AMD believes this incompatibility is unique to the 5706, and
Michael Ellerman88187df2007-01-25 19:34:07 +11008366 * prefers to locally disable MSI rather than globally disabling it.
Michael Chanf9317a42006-09-29 17:06:23 -07008367 */
Michael Chan4ce45e02012-12-06 10:33:10 +00008368 if (BNX2_CHIP(bp) == BNX2_CHIP_5706 && disable_msi == 0) {
Michael Chanf9317a42006-09-29 17:06:23 -07008369 struct pci_dev *amd_8132 = NULL;
8370
8371 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8372 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8373 amd_8132))) {
Michael Chanf9317a42006-09-29 17:06:23 -07008374
Auke Kok44c10132007-06-08 15:46:36 -07008375 if (amd_8132->revision >= 0x10 &&
8376 amd_8132->revision <= 0x13) {
Michael Chanf9317a42006-09-29 17:06:23 -07008377 disable_msi = 1;
8378 pci_dev_put(amd_8132);
8379 break;
8380 }
8381 }
8382 }
8383
Michael Chandeaf3912007-07-07 22:48:00 -07008384 bnx2_set_default_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07008385 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8386
Michael Chancd339a02005-08-25 15:35:24 -07008387 init_timer(&bp->timer);
Benjamin Liac392ab2008-09-18 16:40:49 -07008388 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
Michael Chancd339a02005-08-25 15:35:24 -07008389 bp->timer.data = (unsigned long) bp;
8390 bp->timer.function = bnx2_timer;
8391
Michael Chan7625eb22011-06-08 19:29:36 +00008392#ifdef BCM_CNIC
Michael Chan41c21782011-07-13 17:24:22 +00008393 if (bnx2_shmem_rd(bp, BNX2_ISCSI_INITIATOR) & BNX2_ISCSI_INITIATOR_EN)
8394 bp->cnic_eth_dev.max_iscsi_conn =
8395 (bnx2_shmem_rd(bp, BNX2_ISCSI_MAX_CONN) &
8396 BNX2_ISCSI_MAX_CONN_MASK) >> BNX2_ISCSI_MAX_CONN_SHIFT;
Michael Chan4bd9b0ff2012-12-06 10:33:12 +00008397 bp->cnic_probe = bnx2_cnic_probe;
Michael Chan7625eb22011-06-08 19:29:36 +00008398#endif
Michael Chanc239f272010-10-11 16:12:28 -07008399 pci_save_state(pdev);
8400
Michael Chanb6016b72005-05-26 13:03:09 -07008401 return 0;
8402
8403err_out_unmap:
Michael Chan4bb9ebc2011-01-25 22:14:51 +00008404 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
Michael Chanc239f272010-10-11 16:12:28 -07008405 pci_disable_pcie_error_reporting(pdev);
Michael Chan4bb9ebc2011-01-25 22:14:51 +00008406 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8407 }
Michael Chanc239f272010-10-11 16:12:28 -07008408
Francois Romieuc0357e92012-03-09 14:51:47 +01008409 pci_iounmap(pdev, bp->regview);
8410 bp->regview = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07008411
8412err_out_release:
8413 pci_release_regions(pdev);
8414
8415err_out_disable:
8416 pci_disable_device(pdev);
8417 pci_set_drvdata(pdev, NULL);
8418
8419err_out:
8420 return rc;
8421}
8422
Bill Pembertoncfd95a62012-12-03 09:22:58 -05008423static char *
Michael Chan883e5152007-05-03 13:25:11 -07008424bnx2_bus_string(struct bnx2 *bp, char *str)
8425{
8426 char *s = str;
8427
David S. Millerf86e82f2008-01-21 17:15:40 -08008428 if (bp->flags & BNX2_FLAG_PCIE) {
Michael Chan883e5152007-05-03 13:25:11 -07008429 s += sprintf(s, "PCI Express");
8430 } else {
8431 s += sprintf(s, "PCI");
David S. Millerf86e82f2008-01-21 17:15:40 -08008432 if (bp->flags & BNX2_FLAG_PCIX)
Michael Chan883e5152007-05-03 13:25:11 -07008433 s += sprintf(s, "-X");
David S. Millerf86e82f2008-01-21 17:15:40 -08008434 if (bp->flags & BNX2_FLAG_PCI_32BIT)
Michael Chan883e5152007-05-03 13:25:11 -07008435 s += sprintf(s, " 32-bit");
8436 else
8437 s += sprintf(s, " 64-bit");
8438 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8439 }
8440 return str;
8441}
8442
Michael Chanf048fa92010-06-01 15:05:36 +00008443static void
8444bnx2_del_napi(struct bnx2 *bp)
8445{
8446 int i;
8447
8448 for (i = 0; i < bp->irq_nvecs; i++)
8449 netif_napi_del(&bp->bnx2_napi[i].napi);
8450}
8451
8452static void
Michael Chan35efa7c2007-12-20 19:56:37 -08008453bnx2_init_napi(struct bnx2 *bp)
8454{
Michael Chanb4b36042007-12-20 19:59:30 -08008455 int i;
Michael Chan35efa7c2007-12-20 19:56:37 -08008456
Benjamin Li4327ba42010-03-23 13:13:11 +00008457 for (i = 0; i < bp->irq_nvecs; i++) {
Michael Chan35e90102008-06-19 16:37:42 -07008458 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8459 int (*poll)(struct napi_struct *, int);
8460
8461 if (i == 0)
8462 poll = bnx2_poll;
8463 else
Michael Chanf0ea2e62008-06-19 16:41:57 -07008464 poll = bnx2_poll_msix;
Michael Chan35e90102008-06-19 16:37:42 -07008465
8466 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
Michael Chanb4b36042007-12-20 19:59:30 -08008467 bnapi->bp = bp;
8468 }
Michael Chan35efa7c2007-12-20 19:56:37 -08008469}
8470
Stephen Hemminger0421eae2008-11-21 17:31:27 -08008471static const struct net_device_ops bnx2_netdev_ops = {
8472 .ndo_open = bnx2_open,
8473 .ndo_start_xmit = bnx2_start_xmit,
8474 .ndo_stop = bnx2_close,
Eric Dumazet5d07bf22010-07-08 04:08:43 +00008475 .ndo_get_stats64 = bnx2_get_stats64,
Stephen Hemminger0421eae2008-11-21 17:31:27 -08008476 .ndo_set_rx_mode = bnx2_set_rx_mode,
8477 .ndo_do_ioctl = bnx2_ioctl,
8478 .ndo_validate_addr = eth_validate_addr,
8479 .ndo_set_mac_address = bnx2_change_mac_addr,
8480 .ndo_change_mtu = bnx2_change_mtu,
Michał Mirosław8d7dfc22011-04-10 04:47:46 +00008481 .ndo_fix_features = bnx2_fix_features,
8482 .ndo_set_features = bnx2_set_features,
Stephen Hemminger0421eae2008-11-21 17:31:27 -08008483 .ndo_tx_timeout = bnx2_tx_timeout,
Alexey Dobriyan257ddbd2010-01-27 10:17:41 +00008484#ifdef CONFIG_NET_POLL_CONTROLLER
Stephen Hemminger0421eae2008-11-21 17:31:27 -08008485 .ndo_poll_controller = poll_bnx2,
8486#endif
8487};
8488
Bill Pembertoncfd95a62012-12-03 09:22:58 -05008489static int
Michael Chanb6016b72005-05-26 13:03:09 -07008490bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8491{
8492 static int version_printed = 0;
Francois Romieuc0357e92012-03-09 14:51:47 +01008493 struct net_device *dev;
Michael Chanb6016b72005-05-26 13:03:09 -07008494 struct bnx2 *bp;
Joe Perches0795af52007-10-03 17:59:30 -07008495 int rc;
Michael Chan883e5152007-05-03 13:25:11 -07008496 char str[40];
Michael Chanb6016b72005-05-26 13:03:09 -07008497
8498 if (version_printed++ == 0)
Joe Perches3a9c6a42010-02-17 15:01:51 +00008499 pr_info("%s", version);
Michael Chanb6016b72005-05-26 13:03:09 -07008500
8501 /* dev zeroed in init_etherdev */
Benjamin Li706bf242008-07-18 17:55:11 -07008502 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
Michael Chanb6016b72005-05-26 13:03:09 -07008503 if (!dev)
8504 return -ENOMEM;
8505
8506 rc = bnx2_init_board(pdev, dev);
Francois Romieuc0357e92012-03-09 14:51:47 +01008507 if (rc < 0)
8508 goto err_free;
Michael Chanb6016b72005-05-26 13:03:09 -07008509
Stephen Hemminger0421eae2008-11-21 17:31:27 -08008510 dev->netdev_ops = &bnx2_netdev_ops;
Michael Chanb6016b72005-05-26 13:03:09 -07008511 dev->watchdog_timeo = TX_TIMEOUT;
Michael Chanb6016b72005-05-26 13:03:09 -07008512 dev->ethtool_ops = &bnx2_ethtool_ops;
Michael Chanb6016b72005-05-26 13:03:09 -07008513
Michael Chan972ec0d2006-01-23 16:12:43 -08008514 bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07008515
Michael Chan1b2f9222007-05-03 13:20:19 -07008516 pci_set_drvdata(pdev, dev);
8517
8518 memcpy(dev->dev_addr, bp->mac_addr, 6);
Michael Chan1b2f9222007-05-03 13:20:19 -07008519
Michał Mirosław8d7dfc22011-04-10 04:47:46 +00008520 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
8521 NETIF_F_TSO | NETIF_F_TSO_ECN |
8522 NETIF_F_RXHASH | NETIF_F_RXCSUM;
8523
Michael Chan4ce45e02012-12-06 10:33:10 +00008524 if (BNX2_CHIP(bp) == BNX2_CHIP_5709)
Michał Mirosław8d7dfc22011-04-10 04:47:46 +00008525 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8526
8527 dev->vlan_features = dev->hw_features;
Patrick McHardyf6469682013-04-19 02:04:27 +00008528 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
Michał Mirosław8d7dfc22011-04-10 04:47:46 +00008529 dev->features |= dev->hw_features;
Jiri Pirko01789342011-08-16 06:29:00 +00008530 dev->priv_flags |= IFF_UNICAST_FLT;
Michał Mirosław8d7dfc22011-04-10 04:47:46 +00008531
Michael Chanb6016b72005-05-26 13:03:09 -07008532 if ((rc = register_netdev(dev))) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04008533 dev_err(&pdev->dev, "Cannot register net device\n");
Michael Chan57579f72009-04-04 16:51:14 -07008534 goto error;
Michael Chanb6016b72005-05-26 13:03:09 -07008535 }
8536
Francois Romieuc0357e92012-03-09 14:51:47 +01008537 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, "
8538 "node addr %pM\n", board_info[ent->driver_data].name,
Michael Chan4ce45e02012-12-06 10:33:10 +00008539 ((BNX2_CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8540 ((BNX2_CHIP_ID(bp) & 0x0ff0) >> 4),
Francois Romieuc0357e92012-03-09 14:51:47 +01008541 bnx2_bus_string(bp, str), (long)pci_resource_start(pdev, 0),
8542 pdev->irq, dev->dev_addr);
Michael Chanb6016b72005-05-26 13:03:09 -07008543
Michael Chanb6016b72005-05-26 13:03:09 -07008544 return 0;
Michael Chan57579f72009-04-04 16:51:14 -07008545
8546error:
Michael Chanfda4d852012-12-11 18:24:20 -08008547 pci_iounmap(pdev, bp->regview);
Michael Chan57579f72009-04-04 16:51:14 -07008548 pci_release_regions(pdev);
8549 pci_disable_device(pdev);
8550 pci_set_drvdata(pdev, NULL);
Francois Romieuc0357e92012-03-09 14:51:47 +01008551err_free:
Michael Chan57579f72009-04-04 16:51:14 -07008552 free_netdev(dev);
8553 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07008554}
8555
Bill Pembertoncfd95a62012-12-03 09:22:58 -05008556static void
Michael Chanb6016b72005-05-26 13:03:09 -07008557bnx2_remove_one(struct pci_dev *pdev)
8558{
8559 struct net_device *dev = pci_get_drvdata(pdev);
Michael Chan972ec0d2006-01-23 16:12:43 -08008560 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07008561
8562 unregister_netdev(dev);
8563
Neil Horman8333a462011-04-26 10:30:11 +00008564 del_timer_sync(&bp->timer);
Michael Chancd634012011-07-15 06:53:58 +00008565 cancel_work_sync(&bp->reset_task);
Neil Horman8333a462011-04-26 10:30:11 +00008566
Francois Romieuc0357e92012-03-09 14:51:47 +01008567 pci_iounmap(bp->pdev, bp->regview);
Michael Chanb6016b72005-05-26 13:03:09 -07008568
Michael Chan354fcd72010-01-17 07:30:44 +00008569 kfree(bp->temp_stats_blk);
8570
Michael Chan4bb9ebc2011-01-25 22:14:51 +00008571 if (bp->flags & BNX2_FLAG_AER_ENABLED) {
Michael Chanc239f272010-10-11 16:12:28 -07008572 pci_disable_pcie_error_reporting(pdev);
Michael Chan4bb9ebc2011-01-25 22:14:51 +00008573 bp->flags &= ~BNX2_FLAG_AER_ENABLED;
8574 }
John Feeneycd709aa2010-08-22 17:45:53 +00008575
françois romieu7880b722011-09-30 00:36:52 +00008576 bnx2_release_firmware(bp);
8577
Michael Chanc239f272010-10-11 16:12:28 -07008578 free_netdev(dev);
John Feeneycd709aa2010-08-22 17:45:53 +00008579
Michael Chanb6016b72005-05-26 13:03:09 -07008580 pci_release_regions(pdev);
8581 pci_disable_device(pdev);
8582 pci_set_drvdata(pdev, NULL);
8583}
8584
8585static int
Michael Chan28fb4eb2013-08-06 15:50:10 -07008586bnx2_suspend(struct device *device)
Michael Chanb6016b72005-05-26 13:03:09 -07008587{
Michael Chan28fb4eb2013-08-06 15:50:10 -07008588 struct pci_dev *pdev = to_pci_dev(device);
Michael Chanb6016b72005-05-26 13:03:09 -07008589 struct net_device *dev = pci_get_drvdata(pdev);
Michael Chan972ec0d2006-01-23 16:12:43 -08008590 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07008591
Michael Chan28fb4eb2013-08-06 15:50:10 -07008592 if (netif_running(dev)) {
8593 cancel_work_sync(&bp->reset_task);
8594 bnx2_netif_stop(bp, true);
8595 netif_device_detach(dev);
8596 del_timer_sync(&bp->timer);
8597 bnx2_shutdown_chip(bp);
8598 __bnx2_free_irq(bp);
8599 bnx2_free_skbs(bp);
8600 }
8601 bnx2_setup_wol(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07008602 return 0;
8603}
8604
8605static int
Michael Chan28fb4eb2013-08-06 15:50:10 -07008606bnx2_resume(struct device *device)
Michael Chanb6016b72005-05-26 13:03:09 -07008607{
Michael Chan28fb4eb2013-08-06 15:50:10 -07008608 struct pci_dev *pdev = to_pci_dev(device);
Michael Chanb6016b72005-05-26 13:03:09 -07008609 struct net_device *dev = pci_get_drvdata(pdev);
Michael Chan972ec0d2006-01-23 16:12:43 -08008610 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07008611
8612 if (!netif_running(dev))
8613 return 0;
8614
Pavel Machek829ca9a2005-09-03 15:56:56 -07008615 bnx2_set_power_state(bp, PCI_D0);
Michael Chanb6016b72005-05-26 13:03:09 -07008616 netif_device_attach(dev);
Michael Chan28fb4eb2013-08-06 15:50:10 -07008617 bnx2_request_irq(bp);
Michael Chan9a120bc2008-05-16 22:17:45 -07008618 bnx2_init_nic(bp, 1);
Michael Chan212f9932010-04-27 11:28:10 +00008619 bnx2_netif_start(bp, true);
Michael Chanb6016b72005-05-26 13:03:09 -07008620 return 0;
8621}
8622
Michael Chan28fb4eb2013-08-06 15:50:10 -07008623#ifdef CONFIG_PM_SLEEP
8624static SIMPLE_DEV_PM_OPS(bnx2_pm_ops, bnx2_suspend, bnx2_resume);
8625#define BNX2_PM_OPS (&bnx2_pm_ops)
8626
8627#else
8628
8629#define BNX2_PM_OPS NULL
8630
8631#endif /* CONFIG_PM_SLEEP */
Wendy Xiong6ff2da42008-05-16 22:18:21 -07008632/**
8633 * bnx2_io_error_detected - called when PCI error is detected
8634 * @pdev: Pointer to PCI device
8635 * @state: The current pci connection state
8636 *
8637 * This function is called after a PCI bus error affecting
8638 * this device has been detected.
8639 */
8640static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8641 pci_channel_state_t state)
8642{
8643 struct net_device *dev = pci_get_drvdata(pdev);
8644 struct bnx2 *bp = netdev_priv(dev);
8645
8646 rtnl_lock();
8647 netif_device_detach(dev);
8648
Dean Nelson2ec3de22009-07-31 09:13:18 +00008649 if (state == pci_channel_io_perm_failure) {
8650 rtnl_unlock();
8651 return PCI_ERS_RESULT_DISCONNECT;
8652 }
8653
Wendy Xiong6ff2da42008-05-16 22:18:21 -07008654 if (netif_running(dev)) {
Michael Chan212f9932010-04-27 11:28:10 +00008655 bnx2_netif_stop(bp, true);
Wendy Xiong6ff2da42008-05-16 22:18:21 -07008656 del_timer_sync(&bp->timer);
8657 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8658 }
8659
8660 pci_disable_device(pdev);
8661 rtnl_unlock();
8662
8663 /* Request a slot slot reset. */
8664 return PCI_ERS_RESULT_NEED_RESET;
8665}
8666
8667/**
8668 * bnx2_io_slot_reset - called after the pci bus has been reset.
8669 * @pdev: Pointer to PCI device
8670 *
8671 * Restart the card from scratch, as if from a cold-boot.
8672 */
8673static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8674{
8675 struct net_device *dev = pci_get_drvdata(pdev);
8676 struct bnx2 *bp = netdev_priv(dev);
Michael Chan02481bc2013-08-06 15:50:07 -07008677 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
8678 int err = 0;
Wendy Xiong6ff2da42008-05-16 22:18:21 -07008679
8680 rtnl_lock();
8681 if (pci_enable_device(pdev)) {
8682 dev_err(&pdev->dev,
Joe Perches3a9c6a42010-02-17 15:01:51 +00008683 "Cannot re-enable PCI device after reset\n");
John Feeneycd709aa2010-08-22 17:45:53 +00008684 } else {
8685 pci_set_master(pdev);
8686 pci_restore_state(pdev);
8687 pci_save_state(pdev);
Wendy Xiong6ff2da42008-05-16 22:18:21 -07008688
Michael Chan25bfb1dd2013-08-06 15:50:11 -07008689 if (netif_running(dev))
Michael Chan02481bc2013-08-06 15:50:07 -07008690 err = bnx2_init_nic(bp, 1);
Michael Chan25bfb1dd2013-08-06 15:50:11 -07008691
Michael Chan02481bc2013-08-06 15:50:07 -07008692 if (!err)
8693 result = PCI_ERS_RESULT_RECOVERED;
8694 }
8695
8696 if (result != PCI_ERS_RESULT_RECOVERED && netif_running(dev)) {
8697 bnx2_napi_enable(bp);
8698 dev_close(dev);
Wendy Xiong6ff2da42008-05-16 22:18:21 -07008699 }
Wendy Xiong6ff2da42008-05-16 22:18:21 -07008700 rtnl_unlock();
John Feeneycd709aa2010-08-22 17:45:53 +00008701
Michael Chan4bb9ebc2011-01-25 22:14:51 +00008702 if (!(bp->flags & BNX2_FLAG_AER_ENABLED))
Michael Chanc239f272010-10-11 16:12:28 -07008703 return result;
8704
John Feeneycd709aa2010-08-22 17:45:53 +00008705 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8706 if (err) {
8707 dev_err(&pdev->dev,
8708 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
8709 err); /* non-fatal, continue */
8710 }
8711
8712 return result;
Wendy Xiong6ff2da42008-05-16 22:18:21 -07008713}
8714
8715/**
8716 * bnx2_io_resume - called when traffic can start flowing again.
8717 * @pdev: Pointer to PCI device
8718 *
8719 * This callback is called when the error recovery driver tells us that
8720 * its OK to resume normal operation.
8721 */
8722static void bnx2_io_resume(struct pci_dev *pdev)
8723{
8724 struct net_device *dev = pci_get_drvdata(pdev);
8725 struct bnx2 *bp = netdev_priv(dev);
8726
8727 rtnl_lock();
8728 if (netif_running(dev))
Michael Chan212f9932010-04-27 11:28:10 +00008729 bnx2_netif_start(bp, true);
Wendy Xiong6ff2da42008-05-16 22:18:21 -07008730
8731 netif_device_attach(dev);
8732 rtnl_unlock();
8733}
8734
Michael Chan25bfb1dd2013-08-06 15:50:11 -07008735static void bnx2_shutdown(struct pci_dev *pdev)
8736{
8737 struct net_device *dev = pci_get_drvdata(pdev);
8738 struct bnx2 *bp;
8739
8740 if (!dev)
8741 return;
8742
8743 bp = netdev_priv(dev);
8744 if (!bp)
8745 return;
8746
8747 rtnl_lock();
8748 if (netif_running(dev))
8749 dev_close(bp->dev);
8750
8751 if (system_state == SYSTEM_POWER_OFF)
8752 bnx2_set_power_state(bp, PCI_D3hot);
8753
8754 rtnl_unlock();
8755}
8756
Michael Chanfda4d852012-12-11 18:24:20 -08008757static const struct pci_error_handlers bnx2_err_handler = {
Wendy Xiong6ff2da42008-05-16 22:18:21 -07008758 .error_detected = bnx2_io_error_detected,
8759 .slot_reset = bnx2_io_slot_reset,
8760 .resume = bnx2_io_resume,
8761};
8762
Michael Chanb6016b72005-05-26 13:03:09 -07008763static struct pci_driver bnx2_pci_driver = {
Peter Hagervall14ab9b82005-08-10 14:18:16 -07008764 .name = DRV_MODULE_NAME,
8765 .id_table = bnx2_pci_tbl,
8766 .probe = bnx2_init_one,
Bill Pembertoncfd95a62012-12-03 09:22:58 -05008767 .remove = bnx2_remove_one,
Michael Chan28fb4eb2013-08-06 15:50:10 -07008768 .driver.pm = BNX2_PM_OPS,
Wendy Xiong6ff2da42008-05-16 22:18:21 -07008769 .err_handler = &bnx2_err_handler,
Michael Chan25bfb1dd2013-08-06 15:50:11 -07008770 .shutdown = bnx2_shutdown,
Michael Chanb6016b72005-05-26 13:03:09 -07008771};
8772
Peter Hüwe5a4123f2013-05-21 12:58:05 +00008773module_pci_driver(bnx2_pci_driver);