Gitiles
Code Review Sign In
review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / 3f54fb1e09da301173bc44845f93a1be7fe33d8f / . / drivers / clk / samsung / clk-exynos7.c
blob: 8dfd820ccc8f73e7160d820f0973cec4fb05e641 [file] [log] [blame]
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]1/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9*/
10
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]11#include <linux/clk-provider.h>
12#include <linux/of.h>
13
14#include "clk.h"
15#include <dt-bindings/clock/exynos7-clk.h>
16
17/* Register Offset definitions for CMU_TOPC (0x10570000) */
18#define CC_PLL_LOCK 0x0000
19#define BUS0_PLL_LOCK 0x0004
20#define BUS1_DPLL_LOCK 0x0008
21#define MFC_PLL_LOCK 0x000C
22#define AUD_PLL_LOCK 0x0010
23#define CC_PLL_CON0 0x0100
24#define BUS0_PLL_CON0 0x0110
25#define BUS1_DPLL_CON0 0x0120
26#define MFC_PLL_CON0 0x0130
27#define AUD_PLL_CON0 0x0140
28#define MUX_SEL_TOPC0 0x0200
29#define MUX_SEL_TOPC1 0x0204
Naveen Krishna Chf5e127c2014-10-28 16:48:53 +0530[diff] [blame]30#define MUX_SEL_TOPC2 0x0208
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]31#define MUX_SEL_TOPC3 0x020C
Naveen Krishna Chf5e127c2014-10-28 16:48:53 +0530[diff] [blame]32#define DIV_TOPC0 0x0600
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]33#define DIV_TOPC1 0x0604
34#define DIV_TOPC3 0x060C
Alim Akhtar2cbb5152015-09-10 14:14:27 +0530[diff] [blame]35#define ENABLE_ACLK_TOPC0 0x0800
Tony K Nadackal49cab822014-12-17 13:03:37 +0530[diff] [blame]36#define ENABLE_ACLK_TOPC1 0x0804
Alim Akhtar2cbb5152015-09-10 14:14:27 +0530[diff] [blame]37#define ENABLE_SCLK_TOPC1 0x0A04
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]38
39static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]40 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_topc_bus0_pll", 1, 2, 0),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]41 FFACTOR(0, "ffac_topc_bus0_pll_div4",
42 "ffac_topc_bus0_pll_div2", 1, 2, 0),
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]43 FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_topc_bus1_pll", 1, 2, 0),
44 FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_topc_cc_pll", 1, 2, 0),
45 FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_topc_mfc_pll", 1, 2, 0),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]46};
47
48/* List of parent clocks for Muxes in CMU_TOPC */
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]49PNAME(mout_topc_aud_pll_ctrl_p) = { "fin_pll", "fout_aud_pll" };
50PNAME(mout_topc_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
51PNAME(mout_topc_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
52PNAME(mout_topc_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
53PNAME(mout_topc_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]54
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]55PNAME(mout_topc_group2) = { "mout_topc_bus0_pll_half",
56 "mout_topc_bus1_pll_half", "mout_topc_cc_pll_half",
57 "mout_topc_mfc_pll_half" };
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]58
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]59PNAME(mout_topc_bus0_pll_half_p) = { "mout_topc_bus0_pll",
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]60 "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]61PNAME(mout_topc_bus1_pll_half_p) = { "mout_topc_bus1_pll",
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]62 "ffac_topc_bus1_pll_div2"};
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]63PNAME(mout_topc_cc_pll_half_p) = { "mout_topc_cc_pll",
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]64 "ffac_topc_cc_pll_div2"};
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]65PNAME(mout_topc_mfc_pll_half_p) = { "mout_topc_mfc_pll",
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]66 "ffac_topc_mfc_pll_div2"};
67
68
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]69PNAME(mout_topc_bus0_pll_out_p) = {"mout_topc_bus0_pll",
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]70 "ffac_topc_bus0_pll_div2"};
71
72static unsigned long topc_clk_regs[] __initdata = {
73 CC_PLL_LOCK,
74 BUS0_PLL_LOCK,
75 BUS1_DPLL_LOCK,
76 MFC_PLL_LOCK,
77 AUD_PLL_LOCK,
78 CC_PLL_CON0,
79 BUS0_PLL_CON0,
80 BUS1_DPLL_CON0,
81 MFC_PLL_CON0,
82 AUD_PLL_CON0,
83 MUX_SEL_TOPC0,
84 MUX_SEL_TOPC1,
Naveen Krishna Chf5e127c2014-10-28 16:48:53 +0530[diff] [blame]85 MUX_SEL_TOPC2,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]86 MUX_SEL_TOPC3,
Naveen Krishna Chf5e127c2014-10-28 16:48:53 +0530[diff] [blame]87 DIV_TOPC0,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]88 DIV_TOPC1,
89 DIV_TOPC3,
90};
91
92static struct samsung_mux_clock topc_mux_clks[] __initdata = {
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]93 MUX(0, "mout_topc_bus0_pll", mout_topc_bus0_pll_ctrl_p,
94 MUX_SEL_TOPC0, 0, 1),
95 MUX(0, "mout_topc_bus1_pll", mout_topc_bus1_pll_ctrl_p,
96 MUX_SEL_TOPC0, 4, 1),
97 MUX(0, "mout_topc_cc_pll", mout_topc_cc_pll_ctrl_p,
98 MUX_SEL_TOPC0, 8, 1),
99 MUX(0, "mout_topc_mfc_pll", mout_topc_mfc_pll_ctrl_p,
100 MUX_SEL_TOPC0, 12, 1),
101 MUX(0, "mout_topc_bus0_pll_half", mout_topc_bus0_pll_half_p,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]102 MUX_SEL_TOPC0, 16, 2),
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]103 MUX(0, "mout_topc_bus1_pll_half", mout_topc_bus1_pll_half_p,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]104 MUX_SEL_TOPC0, 20, 1),
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]105 MUX(0, "mout_topc_cc_pll_half", mout_topc_cc_pll_half_p,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]106 MUX_SEL_TOPC0, 24, 1),
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]107 MUX(0, "mout_topc_mfc_pll_half", mout_topc_mfc_pll_half_p,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]108 MUX_SEL_TOPC0, 28, 1),
109
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]110 MUX(0, "mout_topc_aud_pll", mout_topc_aud_pll_ctrl_p,
111 MUX_SEL_TOPC1, 0, 1),
112 MUX(0, "mout_topc_bus0_pll_out", mout_topc_bus0_pll_out_p,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]113 MUX_SEL_TOPC1, 16, 1),
114
Naveen Krishna Chf5e127c2014-10-28 16:48:53 +0530[diff] [blame]115 MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
116
Tony K Nadackal49cab822014-12-17 13:03:37 +0530[diff] [blame]117 MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]118 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
119};
120
121static struct samsung_div_clock topc_div_clks[] __initdata = {
Naveen Krishna Chf5e127c2014-10-28 16:48:53 +0530[diff] [blame]122 DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
123 DIV_TOPC0, 4, 4),
124
Tony K Nadackal49cab822014-12-17 13:03:37 +0530[diff] [blame]125 DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532",
126 DIV_TOPC1, 20, 4),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]127 DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
128 DIV_TOPC1, 24, 4),
129
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]130 DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_topc_bus0_pll_out",
Alim Akhtarfa9f3a52015-08-26 09:00:41 +0530[diff] [blame]131 DIV_TOPC3, 0, 4),
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]132 DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_topc_bus1_pll",
Alim Akhtarfa9f3a52015-08-26 09:00:41 +0530[diff] [blame]133 DIV_TOPC3, 8, 4),
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]134 DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_topc_cc_pll",
Alim Akhtarfa9f3a52015-08-26 09:00:41 +0530[diff] [blame]135 DIV_TOPC3, 12, 4),
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]136 DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_topc_mfc_pll",
Alim Akhtarfa9f3a52015-08-26 09:00:41 +0530[diff] [blame]137 DIV_TOPC3, 16, 4),
Alim Akhtardc504b22015-09-10 14:14:26 +0530[diff] [blame]138 DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_topc_aud_pll",
Alim Akhtarfa9f3a52015-08-26 09:00:41 +0530[diff] [blame]139 DIV_TOPC3, 28, 4),
Padmavathi Venna9f930a32015-01-13 16:57:42 +0530[diff] [blame]140};
141
142static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
143 PLL_36XX_RATE(491520000, 20, 1, 0, 31457),
144 {},
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]145};
146
Tony K Nadackal49cab822014-12-17 13:03:37 +0530[diff] [blame]147static struct samsung_gate_clock topc_gate_clks[] __initdata = {
Alim Akhtar2cbb5152015-09-10 14:14:27 +0530[diff] [blame]148 GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133",
149 ENABLE_ACLK_TOPC0, 4, 0, 0),
150
Tony K Nadackal49cab822014-12-17 13:03:37 +0530[diff] [blame]151 GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
152 ENABLE_ACLK_TOPC1, 20, 0, 0),
Alim Akhtar2cbb5152015-09-10 14:14:27 +0530[diff] [blame]153
154 GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66",
155 ENABLE_ACLK_TOPC1, 24, 0, 0),
156
157 GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll",
158 ENABLE_SCLK_TOPC1, 20, 0, 0),
159 GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
160 ENABLE_SCLK_TOPC1, 17, 0, 0),
161 GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll",
162 ENABLE_SCLK_TOPC1, 16, 0, 0),
163 GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll",
164 ENABLE_SCLK_TOPC1, 13, 0, 0),
165 GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll",
166 ENABLE_SCLK_TOPC1, 12, 0, 0),
167 GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll",
168 ENABLE_SCLK_TOPC1, 5, 0, 0),
169 GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll",
170 ENABLE_SCLK_TOPC1, 4, 0, 0),
171 GATE(SCLK_CC_PLL_B, "sclk_cc_pll_b", "dout_sclk_cc_pll",
172 ENABLE_SCLK_TOPC1, 1, 0, 0),
173 GATE(SCLK_CC_PLL_A, "sclk_cc_pll_a", "dout_sclk_cc_pll",
174 ENABLE_SCLK_TOPC1, 0, 0, 0),
Tony K Nadackal49cab822014-12-17 13:03:37 +0530[diff] [blame]175};
176
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]177static struct samsung_pll_clock topc_pll_clks[] __initdata = {
178 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
179 BUS0_PLL_CON0, NULL),
180 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
181 CC_PLL_CON0, NULL),
182 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
183 BUS1_DPLL_CON0, NULL),
184 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
185 MFC_PLL_CON0, NULL),
Padmavathi Venna9f930a32015-01-13 16:57:42 +0530[diff] [blame]186 PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
187 AUD_PLL_CON0, pll1460x_24mhz_tbl),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]188};
189
190static struct samsung_cmu_info topc_cmu_info __initdata = {
191 .pll_clks = topc_pll_clks,
192 .nr_pll_clks = ARRAY_SIZE(topc_pll_clks),
193 .mux_clks = topc_mux_clks,
194 .nr_mux_clks = ARRAY_SIZE(topc_mux_clks),
195 .div_clks = topc_div_clks,
196 .nr_div_clks = ARRAY_SIZE(topc_div_clks),
Tony K Nadackal49cab822014-12-17 13:03:37 +0530[diff] [blame]197 .gate_clks = topc_gate_clks,
198 .nr_gate_clks = ARRAY_SIZE(topc_gate_clks),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]199 .fixed_factor_clks = topc_fixed_factor_clks,
200 .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks),
201 .nr_clk_ids = TOPC_NR_CLK,
202 .clk_regs = topc_clk_regs,
203 .nr_clk_regs = ARRAY_SIZE(topc_clk_regs),
204};
205
206static void __init exynos7_clk_topc_init(struct device_node *np)
207{
208 samsung_cmu_register_one(np, &topc_cmu_info);
209}
210
211CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
212 exynos7_clk_topc_init);
213
214/* Register Offset definitions for CMU_TOP0 (0x105D0000) */
215#define MUX_SEL_TOP00 0x0200
216#define MUX_SEL_TOP01 0x0204
217#define MUX_SEL_TOP03 0x020C
Padmavathi Venna9f930a32015-01-13 16:57:42 +0530[diff] [blame]218#define MUX_SEL_TOP0_PERIC0 0x0230
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]219#define MUX_SEL_TOP0_PERIC1 0x0234
220#define MUX_SEL_TOP0_PERIC2 0x0238
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]221#define MUX_SEL_TOP0_PERIC3 0x023C
222#define DIV_TOP03 0x060C
Padmavathi Venna9f930a32015-01-13 16:57:42 +0530[diff] [blame]223#define DIV_TOP0_PERIC0 0x0630
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]224#define DIV_TOP0_PERIC1 0x0634
225#define DIV_TOP0_PERIC2 0x0638
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]226#define DIV_TOP0_PERIC3 0x063C
Alim Akhtar3f54fb12015-09-10 14:14:31 +0530[diff] [blame^]227#define ENABLE_ACLK_TOP03 0x080C
Padmavathi Venna9f930a32015-01-13 16:57:42 +0530[diff] [blame]228#define ENABLE_SCLK_TOP0_PERIC0 0x0A30
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]229#define ENABLE_SCLK_TOP0_PERIC1 0x0A34
230#define ENABLE_SCLK_TOP0_PERIC2 0x0A38
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]231#define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
232
233/* List of parent clocks for Muxes in CMU_TOP0 */
Alim Akhtarcf5ee642015-09-10 14:14:28 +0530[diff] [blame]234PNAME(mout_top0_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_a" };
235PNAME(mout_top0_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_a" };
236PNAME(mout_top0_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_a" };
237PNAME(mout_top0_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_a" };
238PNAME(mout_top0_aud_pll_user_p) = { "fin_pll", "sclk_aud_pll" };
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]239
Alim Akhtarcf5ee642015-09-10 14:14:28 +0530[diff] [blame]240PNAME(mout_top0_bus0_pll_half_p) = {"mout_top0_bus0_pll_user",
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]241 "ffac_top0_bus0_pll_div2"};
Alim Akhtarcf5ee642015-09-10 14:14:28 +0530[diff] [blame]242PNAME(mout_top0_bus1_pll_half_p) = {"mout_top0_bus1_pll_user",
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]243 "ffac_top0_bus1_pll_div2"};
Alim Akhtarcf5ee642015-09-10 14:14:28 +0530[diff] [blame]244PNAME(mout_top0_cc_pll_half_p) = {"mout_top0_cc_pll_user",
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]245 "ffac_top0_cc_pll_div2"};
Alim Akhtarcf5ee642015-09-10 14:14:28 +0530[diff] [blame]246PNAME(mout_top0_mfc_pll_half_p) = {"mout_top0_mfc_pll_user",
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]247 "ffac_top0_mfc_pll_div2"};
248
Alim Akhtarcf5ee642015-09-10 14:14:28 +0530[diff] [blame]249PNAME(mout_top0_group1) = {"mout_top0_bus0_pll_half",
250 "mout_top0_bus1_pll_half", "mout_top0_cc_pll_half",
251 "mout_top0_mfc_pll_half"};
Padmavathi Venna9f930a32015-01-13 16:57:42 +0530[diff] [blame]252PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
253 "ioclk_audiocdclk1", "ioclk_spdif_extclk",
Alim Akhtarcf5ee642015-09-10 14:14:28 +0530[diff] [blame]254 "mout_top0_aud_pll_user", "mout_top0_bus0_pll_half",
255 "mout_top0_bus1_pll_half"};
256PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll_user",
257 "mout_top0_bus0_pll_half", "mout_top0_bus1_pll_half"};
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]258
259static unsigned long top0_clk_regs[] __initdata = {
260 MUX_SEL_TOP00,
261 MUX_SEL_TOP01,
262 MUX_SEL_TOP03,
Padmavathi Venna9f930a32015-01-13 16:57:42 +0530[diff] [blame]263 MUX_SEL_TOP0_PERIC0,
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]264 MUX_SEL_TOP0_PERIC1,
265 MUX_SEL_TOP0_PERIC2,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]266 MUX_SEL_TOP0_PERIC3,
267 DIV_TOP03,
Padmavathi Venna9f930a32015-01-13 16:57:42 +0530[diff] [blame]268 DIV_TOP0_PERIC0,
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]269 DIV_TOP0_PERIC1,
270 DIV_TOP0_PERIC2,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]271 DIV_TOP0_PERIC3,
Padmavathi Venna9f930a32015-01-13 16:57:42 +0530[diff] [blame]272 ENABLE_SCLK_TOP0_PERIC0,
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]273 ENABLE_SCLK_TOP0_PERIC1,
274 ENABLE_SCLK_TOP0_PERIC2,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]275 ENABLE_SCLK_TOP0_PERIC3,
276};
277
278static struct samsung_mux_clock top0_mux_clks[] __initdata = {
Alim Akhtarcf5ee642015-09-10 14:14:28 +0530[diff] [blame]279 MUX(0, "mout_top0_aud_pll_user", mout_top0_aud_pll_user_p,
280 MUX_SEL_TOP00, 0, 1),
281 MUX(0, "mout_top0_mfc_pll_user", mout_top0_mfc_pll_user_p,
282 MUX_SEL_TOP00, 4, 1),
283 MUX(0, "mout_top0_cc_pll_user", mout_top0_cc_pll_user_p,
284 MUX_SEL_TOP00, 8, 1),
285 MUX(0, "mout_top0_bus1_pll_user", mout_top0_bus1_pll_user_p,
286 MUX_SEL_TOP00, 12, 1),
287 MUX(0, "mout_top0_bus0_pll_user", mout_top0_bus0_pll_user_p,
288 MUX_SEL_TOP00, 16, 1),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]289
Alim Akhtarcf5ee642015-09-10 14:14:28 +0530[diff] [blame]290 MUX(0, "mout_top0_mfc_pll_half", mout_top0_mfc_pll_half_p,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]291 MUX_SEL_TOP01, 4, 1),
Alim Akhtarcf5ee642015-09-10 14:14:28 +0530[diff] [blame]292 MUX(0, "mout_top0_cc_pll_half", mout_top0_cc_pll_half_p,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]293 MUX_SEL_TOP01, 8, 1),
Alim Akhtarcf5ee642015-09-10 14:14:28 +0530[diff] [blame]294 MUX(0, "mout_top0_bus1_pll_half", mout_top0_bus1_pll_half_p,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]295 MUX_SEL_TOP01, 12, 1),
Alim Akhtarcf5ee642015-09-10 14:14:28 +0530[diff] [blame]296 MUX(0, "mout_top0_bus0_pll_half", mout_top0_bus0_pll_half_p,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]297 MUX_SEL_TOP01, 16, 1),
298
299 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
300 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
301
Padmavathi Venna9f930a32015-01-13 16:57:42 +0530[diff] [blame]302 MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3),
303 MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2),
304 MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2),
305
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]306 MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
307 MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
308
309 MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
310 MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]311 MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
312 MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
313 MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
314 MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]315 MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]316};
317
318static struct samsung_div_clock top0_div_clks[] __initdata = {
319 DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
320 DIV_TOP03, 12, 6),
321 DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
322 DIV_TOP03, 20, 6),
323
Padmavathi Venna9f930a32015-01-13 16:57:42 +0530[diff] [blame]324 DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4),
325 DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12),
326 DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10),
327
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]328 DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
329 DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
330
331 DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
332 DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
333
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]334 DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
335 DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
336 DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
337 DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]338 DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]339};
340
341static struct samsung_gate_clock top0_gate_clks[] __initdata = {
Alim Akhtar3f54fb12015-09-10 14:14:31 +0530[diff] [blame^]342 GATE(CLK_ACLK_PERIC0_66, "aclk_peric0_66", "dout_aclk_peric0_66",
343 ENABLE_ACLK_TOP03, 20, CLK_SET_RATE_PARENT, 0),
344
Padmavathi Venna9f930a32015-01-13 16:57:42 +0530[diff] [blame]345 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
346 ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
347 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1",
348 ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
349 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
350 ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0),
351
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]352 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
353 ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
354 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
355 ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
356
357 GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3",
358 ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
359 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2",
360 ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]361 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
362 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
363 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
364 ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
365 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
366 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
367 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
368 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]369 GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4",
370 ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]371};
372
373static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
Alim Akhtarcf5ee642015-09-10 14:14:28 +0530[diff] [blame]374 FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll_user",
375 1, 2, 0),
376 FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll_user",
377 1, 2, 0),
378 FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll_user", 1, 2, 0),
379 FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll_user", 1, 2, 0),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]380};
381
382static struct samsung_cmu_info top0_cmu_info __initdata = {
383 .mux_clks = top0_mux_clks,
384 .nr_mux_clks = ARRAY_SIZE(top0_mux_clks),
385 .div_clks = top0_div_clks,
386 .nr_div_clks = ARRAY_SIZE(top0_div_clks),
387 .gate_clks = top0_gate_clks,
388 .nr_gate_clks = ARRAY_SIZE(top0_gate_clks),
389 .fixed_factor_clks = top0_fixed_factor_clks,
390 .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks),
391 .nr_clk_ids = TOP0_NR_CLK,
392 .clk_regs = top0_clk_regs,
393 .nr_clk_regs = ARRAY_SIZE(top0_clk_regs),
394};
395
396static void __init exynos7_clk_top0_init(struct device_node *np)
397{
398 samsung_cmu_register_one(np, &top0_cmu_info);
399}
400
401CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
402 exynos7_clk_top0_init);
403
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]404/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
405#define MUX_SEL_TOP10 0x0200
406#define MUX_SEL_TOP11 0x0204
407#define MUX_SEL_TOP13 0x020C
408#define MUX_SEL_TOP1_FSYS0 0x0224
409#define MUX_SEL_TOP1_FSYS1 0x0228
Alim Akhtarcfc75882015-08-26 09:00:42 +0530[diff] [blame]410#define MUX_SEL_TOP1_FSYS11 0x022C
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]411#define DIV_TOP13 0x060C
412#define DIV_TOP1_FSYS0 0x0624
413#define DIV_TOP1_FSYS1 0x0628
Alim Akhtarcfc75882015-08-26 09:00:42 +0530[diff] [blame]414#define DIV_TOP1_FSYS11 0x062C
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]415#define ENABLE_ACLK_TOP13 0x080C
416#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
417#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
Alim Akhtarcfc75882015-08-26 09:00:42 +0530[diff] [blame]418#define ENABLE_SCLK_TOP1_FSYS11 0x0A2C
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]419
420/* List of parent clocks for Muxes in CMU_TOP1 */
Alim Akhtar9b3ad362015-09-10 14:14:29 +0530[diff] [blame]421PNAME(mout_top1_bus0_pll_user_p) = { "fin_pll", "sclk_bus0_pll_b" };
422PNAME(mout_top1_bus1_pll_user_p) = { "fin_pll", "sclk_bus1_pll_b" };
423PNAME(mout_top1_cc_pll_user_p) = { "fin_pll", "sclk_cc_pll_b" };
424PNAME(mout_top1_mfc_pll_user_p) = { "fin_pll", "sclk_mfc_pll_b" };
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]425
Alim Akhtar9b3ad362015-09-10 14:14:29 +0530[diff] [blame]426PNAME(mout_top1_bus0_pll_half_p) = {"mout_top1_bus0_pll_user",
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]427 "ffac_top1_bus0_pll_div2"};
Alim Akhtar9b3ad362015-09-10 14:14:29 +0530[diff] [blame]428PNAME(mout_top1_bus1_pll_half_p) = {"mout_top1_bus1_pll_user",
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]429 "ffac_top1_bus1_pll_div2"};
Alim Akhtar9b3ad362015-09-10 14:14:29 +0530[diff] [blame]430PNAME(mout_top1_cc_pll_half_p) = {"mout_top1_cc_pll_user",
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]431 "ffac_top1_cc_pll_div2"};
Alim Akhtar9b3ad362015-09-10 14:14:29 +0530[diff] [blame]432PNAME(mout_top1_mfc_pll_half_p) = {"mout_top1_mfc_pll_user",
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]433 "ffac_top1_mfc_pll_div2"};
434
Alim Akhtar9b3ad362015-09-10 14:14:29 +0530[diff] [blame]435PNAME(mout_top1_group1) = {"mout_top1_bus0_pll_half",
436 "mout_top1_bus1_pll_half", "mout_top1_cc_pll_half",
437 "mout_top1_mfc_pll_half"};
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]438
439static unsigned long top1_clk_regs[] __initdata = {
440 MUX_SEL_TOP10,
441 MUX_SEL_TOP11,
442 MUX_SEL_TOP13,
443 MUX_SEL_TOP1_FSYS0,
444 MUX_SEL_TOP1_FSYS1,
Alim Akhtarcfc75882015-08-26 09:00:42 +0530[diff] [blame]445 MUX_SEL_TOP1_FSYS11,
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]446 DIV_TOP13,
447 DIV_TOP1_FSYS0,
448 DIV_TOP1_FSYS1,
Alim Akhtarcfc75882015-08-26 09:00:42 +0530[diff] [blame]449 DIV_TOP1_FSYS11,
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]450 ENABLE_ACLK_TOP13,
451 ENABLE_SCLK_TOP1_FSYS0,
452 ENABLE_SCLK_TOP1_FSYS1,
Alim Akhtarcfc75882015-08-26 09:00:42 +0530[diff] [blame]453 ENABLE_SCLK_TOP1_FSYS11,
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]454};
455
456static struct samsung_mux_clock top1_mux_clks[] __initdata = {
Alim Akhtar9b3ad362015-09-10 14:14:29 +0530[diff] [blame]457 MUX(0, "mout_top1_mfc_pll_user", mout_top1_mfc_pll_user_p,
458 MUX_SEL_TOP10, 4, 1),
459 MUX(0, "mout_top1_cc_pll_user", mout_top1_cc_pll_user_p,
460 MUX_SEL_TOP10, 8, 1),
461 MUX(0, "mout_top1_bus1_pll_user", mout_top1_bus1_pll_user_p,
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]462 MUX_SEL_TOP10, 12, 1),
Alim Akhtar9b3ad362015-09-10 14:14:29 +0530[diff] [blame]463 MUX(0, "mout_top1_bus0_pll_user", mout_top1_bus0_pll_user_p,
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]464 MUX_SEL_TOP10, 16, 1),
465
Alim Akhtar9b3ad362015-09-10 14:14:29 +0530[diff] [blame]466 MUX(0, "mout_top1_mfc_pll_half", mout_top1_mfc_pll_half_p,
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]467 MUX_SEL_TOP11, 4, 1),
Alim Akhtar9b3ad362015-09-10 14:14:29 +0530[diff] [blame]468 MUX(0, "mout_top1_cc_pll_half", mout_top1_cc_pll_half_p,
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]469 MUX_SEL_TOP11, 8, 1),
Alim Akhtar9b3ad362015-09-10 14:14:29 +0530[diff] [blame]470 MUX(0, "mout_top1_bus1_pll_half", mout_top1_bus1_pll_half_p,
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]471 MUX_SEL_TOP11, 12, 1),
Alim Akhtar9b3ad362015-09-10 14:14:29 +0530[diff] [blame]472 MUX(0, "mout_top1_bus0_pll_half", mout_top1_bus0_pll_half_p,
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]473 MUX_SEL_TOP11, 16, 1),
474
475 MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
476 MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
477
Alim Akhtarcfc75882015-08-26 09:00:42 +0530[diff] [blame]478 MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 16, 2),
Vivek Gautam83f191a2014-11-21 19:05:51 +0530[diff] [blame]479 MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
480 MUX_SEL_TOP1_FSYS0, 28, 2),
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]481
Alim Akhtarcfc75882015-08-26 09:00:42 +0530[diff] [blame]482 MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 0, 2),
483 MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS11, 12, 2),
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]484};
485
486static struct samsung_div_clock top1_div_clks[] __initdata = {
487 DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
488 DIV_TOP13, 24, 4),
489 DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
490 DIV_TOP13, 28, 4),
491
492 DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
Alim Akhtarcfc75882015-08-26 09:00:42 +0530[diff] [blame]493 DIV_TOP1_FSYS0, 16, 10),
Vivek Gautam83f191a2014-11-21 19:05:51 +0530[diff] [blame]494 DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
495 DIV_TOP1_FSYS0, 28, 4),
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]496
497 DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
Alim Akhtarcfc75882015-08-26 09:00:42 +0530[diff] [blame]498 DIV_TOP1_FSYS11, 0, 10),
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]499 DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
Alim Akhtarcfc75882015-08-26 09:00:42 +0530[diff] [blame]500 DIV_TOP1_FSYS11, 12, 10),
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]501};
502
503static struct samsung_gate_clock top1_gate_clks[] __initdata = {
504 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
Alim Akhtarcfc75882015-08-26 09:00:42 +0530[diff] [blame]505 ENABLE_SCLK_TOP1_FSYS0, 16, CLK_SET_RATE_PARENT, 0),
Vivek Gautam83f191a2014-11-21 19:05:51 +0530[diff] [blame]506 GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
507 ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]508
509 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
Alim Akhtarcfc75882015-08-26 09:00:42 +0530[diff] [blame]510 ENABLE_SCLK_TOP1_FSYS11, 0, CLK_SET_RATE_PARENT, 0),
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]511 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
Alim Akhtarcfc75882015-08-26 09:00:42 +0530[diff] [blame]512 ENABLE_SCLK_TOP1_FSYS11, 12, CLK_SET_RATE_PARENT, 0),
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]513};
514
515static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
Alim Akhtar9b3ad362015-09-10 14:14:29 +0530[diff] [blame]516 FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll_user",
517 1, 2, 0),
518 FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll_user",
519 1, 2, 0),
520 FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll_user", 1, 2, 0),
521 FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll_user", 1, 2, 0),
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]522};
523
524static struct samsung_cmu_info top1_cmu_info __initdata = {
525 .mux_clks = top1_mux_clks,
526 .nr_mux_clks = ARRAY_SIZE(top1_mux_clks),
527 .div_clks = top1_div_clks,
528 .nr_div_clks = ARRAY_SIZE(top1_div_clks),
529 .gate_clks = top1_gate_clks,
530 .nr_gate_clks = ARRAY_SIZE(top1_gate_clks),
531 .fixed_factor_clks = top1_fixed_factor_clks,
532 .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks),
533 .nr_clk_ids = TOP1_NR_CLK,
534 .clk_regs = top1_clk_regs,
535 .nr_clk_regs = ARRAY_SIZE(top1_clk_regs),
536};
537
538static void __init exynos7_clk_top1_init(struct device_node *np)
539{
540 samsung_cmu_register_one(np, &top1_cmu_info);
541}
542
543CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
544 exynos7_clk_top1_init);
545
Naveen Krishna Chf5e127c2014-10-28 16:48:53 +0530[diff] [blame]546/* Register Offset definitions for CMU_CCORE (0x105B0000) */
547#define MUX_SEL_CCORE 0x0200
548#define DIV_CCORE 0x0600
549#define ENABLE_ACLK_CCORE0 0x0800
550#define ENABLE_ACLK_CCORE1 0x0804
551#define ENABLE_PCLK_CCORE 0x0900
552
553/*
554 * List of parent clocks for Muxes in CMU_CCORE
555 */
Alim Akhtar56365ee2015-09-10 14:14:30 +0530[diff] [blame]556PNAME(mout_aclk_ccore_133_user_p) = { "fin_pll", "aclk_ccore_133" };
Naveen Krishna Chf5e127c2014-10-28 16:48:53 +0530[diff] [blame]557
558static unsigned long ccore_clk_regs[] __initdata = {
559 MUX_SEL_CCORE,
560 ENABLE_PCLK_CCORE,
561};
562
563static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
Alim Akhtar56365ee2015-09-10 14:14:30 +0530[diff] [blame]564 MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_user_p,
Naveen Krishna Chf5e127c2014-10-28 16:48:53 +0530[diff] [blame]565 MUX_SEL_CCORE, 1, 1),
566};
567
568static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
569 GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
570 ENABLE_PCLK_CCORE, 8, 0, 0),
571};
572
573static struct samsung_cmu_info ccore_cmu_info __initdata = {
574 .mux_clks = ccore_mux_clks,
575 .nr_mux_clks = ARRAY_SIZE(ccore_mux_clks),
576 .gate_clks = ccore_gate_clks,
577 .nr_gate_clks = ARRAY_SIZE(ccore_gate_clks),
578 .nr_clk_ids = CCORE_NR_CLK,
579 .clk_regs = ccore_clk_regs,
580 .nr_clk_regs = ARRAY_SIZE(ccore_clk_regs),
581};
582
583static void __init exynos7_clk_ccore_init(struct device_node *np)
584{
585 samsung_cmu_register_one(np, &ccore_cmu_info);
586}
587
588CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
589 exynos7_clk_ccore_init);
590
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]591/* Register Offset definitions for CMU_PERIC0 (0x13610000) */
592#define MUX_SEL_PERIC0 0x0200
593#define ENABLE_PCLK_PERIC0 0x0900
594#define ENABLE_SCLK_PERIC0 0x0A00
595
596/* List of parent clocks for Muxes in CMU_PERIC0 */
Alim Akhtar3f54fb12015-09-10 14:14:31 +0530[diff] [blame^]597PNAME(mout_aclk_peric0_66_user_p) = { "fin_pll", "aclk_peric0_66" };
598PNAME(mout_sclk_uart0_user_p) = { "fin_pll", "sclk_uart0" };
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]599
600static unsigned long peric0_clk_regs[] __initdata = {
601 MUX_SEL_PERIC0,
602 ENABLE_PCLK_PERIC0,
603 ENABLE_SCLK_PERIC0,
604};
605
606static struct samsung_mux_clock peric0_mux_clks[] __initdata = {
Alim Akhtar3f54fb12015-09-10 14:14:31 +0530[diff] [blame^]607 MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_user_p,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]608 MUX_SEL_PERIC0, 0, 1),
Alim Akhtar3f54fb12015-09-10 14:14:31 +0530[diff] [blame^]609 MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_user_p,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]610 MUX_SEL_PERIC0, 16, 1),
611};
612
613static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
Naveen Krishna Ch57a2b482014-10-21 11:13:51 +0530[diff] [blame]614 GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
615 ENABLE_PCLK_PERIC0, 8, 0, 0),
616 GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
617 ENABLE_PCLK_PERIC0, 9, 0, 0),
618 GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
619 ENABLE_PCLK_PERIC0, 10, 0, 0),
620 GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
621 ENABLE_PCLK_PERIC0, 11, 0, 0),
622 GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
623 ENABLE_PCLK_PERIC0, 12, 0, 0),
624 GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
625 ENABLE_PCLK_PERIC0, 13, 0, 0),
626 GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
627 ENABLE_PCLK_PERIC0, 14, 0, 0),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]628 GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
629 ENABLE_PCLK_PERIC0, 16, 0, 0),
Abhilash Kesavan932e9822014-10-28 16:48:55 +0530[diff] [blame]630 GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
631 ENABLE_PCLK_PERIC0, 20, 0, 0),
Naveen Krishna Ch2ab2dfe2014-10-28 16:48:54 +0530[diff] [blame]632 GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
633 ENABLE_PCLK_PERIC0, 21, 0, 0),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]634
635 GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
636 ENABLE_SCLK_PERIC0, 16, 0, 0),
Naveen Krishna Ch2ab2dfe2014-10-28 16:48:54 +0530[diff] [blame]637 GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]638};
639
640static struct samsung_cmu_info peric0_cmu_info __initdata = {
641 .mux_clks = peric0_mux_clks,
642 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
643 .gate_clks = peric0_gate_clks,
644 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
645 .nr_clk_ids = PERIC0_NR_CLK,
646 .clk_regs = peric0_clk_regs,
647 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
648};
649
650static void __init exynos7_clk_peric0_init(struct device_node *np)
651{
652 samsung_cmu_register_one(np, &peric0_cmu_info);
653}
654
655/* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
656#define MUX_SEL_PERIC10 0x0200
657#define MUX_SEL_PERIC11 0x0204
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]658#define MUX_SEL_PERIC12 0x0208
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]659#define ENABLE_PCLK_PERIC1 0x0900
660#define ENABLE_SCLK_PERIC10 0x0A00
661
662CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
663 exynos7_clk_peric0_init);
664
665/* List of parent clocks for Muxes in CMU_PERIC1 */
666PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" };
667PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" };
668PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" };
669PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" };
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]670PNAME(mout_sclk_spi0_p) = { "fin_pll", "sclk_spi0" };
671PNAME(mout_sclk_spi1_p) = { "fin_pll", "sclk_spi1" };
672PNAME(mout_sclk_spi2_p) = { "fin_pll", "sclk_spi2" };
673PNAME(mout_sclk_spi3_p) = { "fin_pll", "sclk_spi3" };
674PNAME(mout_sclk_spi4_p) = { "fin_pll", "sclk_spi4" };
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]675
676static unsigned long peric1_clk_regs[] __initdata = {
677 MUX_SEL_PERIC10,
678 MUX_SEL_PERIC11,
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]679 MUX_SEL_PERIC12,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]680 ENABLE_PCLK_PERIC1,
681 ENABLE_SCLK_PERIC10,
682};
683
684static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
685 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
686 MUX_SEL_PERIC10, 0, 1),
687
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]688 MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p,
689 MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
690 MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p,
691 MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
692 MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p,
693 MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
694 MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p,
695 MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
696 MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p,
697 MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]698 MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
699 MUX_SEL_PERIC11, 20, 1),
700 MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
701 MUX_SEL_PERIC11, 24, 1),
702 MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p,
703 MUX_SEL_PERIC11, 28, 1),
704};
705
706static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
Naveen Krishna Ch57a2b482014-10-21 11:13:51 +0530[diff] [blame]707 GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
708 ENABLE_PCLK_PERIC1, 4, 0, 0),
709 GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
710 ENABLE_PCLK_PERIC1, 5, 0, 0),
711 GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
712 ENABLE_PCLK_PERIC1, 6, 0, 0),
713 GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
714 ENABLE_PCLK_PERIC1, 7, 0, 0),
715 GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
716 ENABLE_PCLK_PERIC1, 8, 0, 0),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]717 GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
718 ENABLE_PCLK_PERIC1, 9, 0, 0),
719 GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
720 ENABLE_PCLK_PERIC1, 10, 0, 0),
721 GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
722 ENABLE_PCLK_PERIC1, 11, 0, 0),
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]723 GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
724 ENABLE_PCLK_PERIC1, 12, 0, 0),
725 GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user",
726 ENABLE_PCLK_PERIC1, 13, 0, 0),
727 GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user",
728 ENABLE_PCLK_PERIC1, 14, 0, 0),
729 GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user",
730 ENABLE_PCLK_PERIC1, 15, 0, 0),
731 GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
732 ENABLE_PCLK_PERIC1, 16, 0, 0),
Padmavathi Venna9f930a32015-01-13 16:57:42 +0530[diff] [blame]733 GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user",
734 ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0),
735 GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user",
736 ENABLE_PCLK_PERIC1, 18, 0, 0),
737 GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user",
738 ENABLE_PCLK_PERIC1, 19, 0, 0),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]739
740 GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
741 ENABLE_SCLK_PERIC10, 9, 0, 0),
742 GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
743 ENABLE_SCLK_PERIC10, 10, 0, 0),
744 GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
745 ENABLE_SCLK_PERIC10, 11, 0, 0),
Padmavathi Vennaee74b562015-01-13 16:57:41 +0530[diff] [blame]746 GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
747 ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
748 GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user",
749 ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
750 GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
751 ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
752 GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user",
753 ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
754 GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
755 ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
Padmavathi Venna9f930a32015-01-13 16:57:42 +0530[diff] [blame]756 GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
757 ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0),
758 GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1",
759 ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0),
760 GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif",
761 ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]762};
763
764static struct samsung_cmu_info peric1_cmu_info __initdata = {
765 .mux_clks = peric1_mux_clks,
766 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
767 .gate_clks = peric1_gate_clks,
768 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
769 .nr_clk_ids = PERIC1_NR_CLK,
770 .clk_regs = peric1_clk_regs,
771 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
772};
773
774static void __init exynos7_clk_peric1_init(struct device_node *np)
775{
776 samsung_cmu_register_one(np, &peric1_cmu_info);
777}
778
779CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
780 exynos7_clk_peric1_init);
781
782/* Register Offset definitions for CMU_PERIS (0x10040000) */
783#define MUX_SEL_PERIS 0x0200
Naveen Krishna Ch2ab2dfe2014-10-28 16:48:54 +0530[diff] [blame]784#define ENABLE_PCLK_PERIS 0x0900
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]785#define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910
Naveen Krishna Ch2ab2dfe2014-10-28 16:48:54 +0530[diff] [blame]786#define ENABLE_SCLK_PERIS 0x0A00
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]787#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10
788
789/* List of parent clocks for Muxes in CMU_PERIS */
790PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" };
791
792static unsigned long peris_clk_regs[] __initdata = {
793 MUX_SEL_PERIS,
Naveen Krishna Ch2ab2dfe2014-10-28 16:48:54 +0530[diff] [blame]794 ENABLE_PCLK_PERIS,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]795 ENABLE_PCLK_PERIS_SECURE_CHIPID,
Naveen Krishna Ch2ab2dfe2014-10-28 16:48:54 +0530[diff] [blame]796 ENABLE_SCLK_PERIS,
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]797 ENABLE_SCLK_PERIS_SECURE_CHIPID,
798};
799
800static struct samsung_mux_clock peris_mux_clks[] __initdata = {
801 MUX(0, "mout_aclk_peris_66_user",
802 mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1),
803};
804
805static struct samsung_gate_clock peris_gate_clks[] __initdata = {
Naveen Krishna Ch2ab2dfe2014-10-28 16:48:54 +0530[diff] [blame]806 GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
807 ENABLE_PCLK_PERIS, 6, 0, 0),
808 GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
809 ENABLE_PCLK_PERIS, 10, 0, 0),
810
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]811 GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
812 ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
813 GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
814 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
Naveen Krishna Ch2ab2dfe2014-10-28 16:48:54 +0530[diff] [blame]815
816 GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530[diff] [blame]817};
818
819static struct samsung_cmu_info peris_cmu_info __initdata = {
820 .mux_clks = peris_mux_clks,
821 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
822 .gate_clks = peris_gate_clks,
823 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
824 .nr_clk_ids = PERIS_NR_CLK,
825 .clk_regs = peris_clk_regs,
826 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
827};
828
829static void __init exynos7_clk_peris_init(struct device_node *np)
830{
831 samsung_cmu_register_one(np, &peris_cmu_info);
832}
833
834CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
835 exynos7_clk_peris_init);
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]836
837/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
838#define MUX_SEL_FSYS00 0x0200
839#define MUX_SEL_FSYS01 0x0204
Vivek Gautam83f191a2014-11-21 19:05:51 +0530[diff] [blame]840#define MUX_SEL_FSYS02 0x0208
841#define ENABLE_ACLK_FSYS00 0x0800
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]842#define ENABLE_ACLK_FSYS01 0x0804
Vivek Gautam83f191a2014-11-21 19:05:51 +0530[diff] [blame]843#define ENABLE_SCLK_FSYS01 0x0A04
844#define ENABLE_SCLK_FSYS02 0x0A08
845#define ENABLE_SCLK_FSYS04 0x0A10
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]846
847/*
848 * List of parent clocks for Muxes in CMU_FSYS0
849 */
850PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" };
851PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" };
852
Vivek Gautam83f191a2014-11-21 19:05:51 +0530[diff] [blame]853PNAME(mout_sclk_usbdrd300_p) = { "fin_pll", "sclk_usbdrd300" };
854PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p) = { "fin_pll",
855 "phyclk_usbdrd300_udrd30_phyclock" };
856PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p) = { "fin_pll",
857 "phyclk_usbdrd300_udrd30_pipe_pclk" };
858
859/* fixed rate clocks used in the FSYS0 block */
860struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = {
861 FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL,
862 CLK_IS_ROOT, 60000000),
863 FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL,
864 CLK_IS_ROOT, 125000000),
865};
866
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]867static unsigned long fsys0_clk_regs[] __initdata = {
868 MUX_SEL_FSYS00,
869 MUX_SEL_FSYS01,
Vivek Gautam83f191a2014-11-21 19:05:51 +0530[diff] [blame]870 MUX_SEL_FSYS02,
871 ENABLE_ACLK_FSYS00,
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]872 ENABLE_ACLK_FSYS01,
Vivek Gautam83f191a2014-11-21 19:05:51 +0530[diff] [blame]873 ENABLE_SCLK_FSYS01,
874 ENABLE_SCLK_FSYS02,
875 ENABLE_SCLK_FSYS04,
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]876};
877
878static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
879 MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
880 MUX_SEL_FSYS00, 24, 1),
881
882 MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
Vivek Gautam83f191a2014-11-21 19:05:51 +0530[diff] [blame]883 MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p,
884 MUX_SEL_FSYS01, 28, 1),
885
886 MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
887 mout_phyclk_usbdrd300_udrd30_pipe_pclk_p,
888 MUX_SEL_FSYS02, 24, 1),
889 MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
890 mout_phyclk_usbdrd300_udrd30_phyclk_p,
891 MUX_SEL_FSYS02, 28, 1),
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]892};
893
894static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
Padmavathi Venna9cc2a0c92015-01-13 16:57:40 +0530[diff] [blame]895 GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
896 ENABLE_ACLK_FSYS00, 3, 0, 0),
897 GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
898 ENABLE_ACLK_FSYS00, 4, 0, 0),
Alim Akhtar7cca2e02015-08-26 09:00:43 +0530[diff] [blame]899 GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
900 "mout_aclk_fsys0_200_user",
901 ENABLE_ACLK_FSYS00, 19, 0, 0),
Vivek Gautam83f191a2014-11-21 19:05:51 +0530[diff] [blame]902
903 GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
904 ENABLE_ACLK_FSYS01, 29, 0, 0),
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]905 GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
906 ENABLE_ACLK_FSYS01, 31, 0, 0),
Vivek Gautam83f191a2014-11-21 19:05:51 +0530[diff] [blame]907
908 GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk",
909 "mout_sclk_usbdrd300_user",
910 ENABLE_SCLK_FSYS01, 4, 0, 0),
911 GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll",
912 ENABLE_SCLK_FSYS01, 8, 0, 0),
913
914 GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER,
915 "phyclk_usbdrd300_udrd30_pipe_pclk_user",
916 "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
917 ENABLE_SCLK_FSYS02, 24, 0, 0),
918 GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER,
919 "phyclk_usbdrd300_udrd30_phyclk_user",
920 "mout_phyclk_usbdrd300_udrd30_phyclk_user",
921 ENABLE_SCLK_FSYS02, 28, 0, 0),
922
923 GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy",
924 "fin_pll",
925 ENABLE_SCLK_FSYS04, 28, 0, 0),
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]926};
927
928static struct samsung_cmu_info fsys0_cmu_info __initdata = {
929 .mux_clks = fsys0_mux_clks,
930 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
931 .gate_clks = fsys0_gate_clks,
932 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
Alim Akhtar7cca2e02015-08-26 09:00:43 +0530[diff] [blame]933 .nr_clk_ids = FSYS0_NR_CLK,
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]934 .clk_regs = fsys0_clk_regs,
935 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
936};
937
938static void __init exynos7_clk_fsys0_init(struct device_node *np)
939{
940 samsung_cmu_register_one(np, &fsys0_cmu_info);
941}
942
943CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
944 exynos7_clk_fsys0_init);
945
946/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
947#define MUX_SEL_FSYS10 0x0200
948#define MUX_SEL_FSYS11 0x0204
949#define ENABLE_ACLK_FSYS1 0x0800
950
951/*
952 * List of parent clocks for Muxes in CMU_FSYS1
953 */
954PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" };
955PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" };
956PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" };
957
958static unsigned long fsys1_clk_regs[] __initdata = {
959 MUX_SEL_FSYS10,
960 MUX_SEL_FSYS11,
961 ENABLE_ACLK_FSYS1,
962};
963
964static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
965 MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
966 MUX_SEL_FSYS10, 28, 1),
967
968 MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
969 MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
970};
971
972static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
973 GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
974 ENABLE_ACLK_FSYS1, 29, 0, 0),
975 GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
976 ENABLE_ACLK_FSYS1, 30, 0, 0),
977};
978
979static struct samsung_cmu_info fsys1_cmu_info __initdata = {
980 .mux_clks = fsys1_mux_clks,
981 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
982 .gate_clks = fsys1_gate_clks,
983 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
Alim Akhtar167c9e42015-08-26 09:00:44 +0530[diff] [blame]984 .nr_clk_ids = FSYS1_NR_CLK,
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530[diff] [blame]985 .clk_regs = fsys1_clk_regs,
986 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
987};
988
989static void __init exynos7_clk_fsys1_init(struct device_node *np)
990{
991 samsung_cmu_register_one(np, &fsys1_cmu_info);
992}
993
994CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
995 exynos7_clk_fsys1_init);
Tony K Nadackal49cab822014-12-17 13:03:37 +0530[diff] [blame]996
997#define MUX_SEL_MSCL 0x0200
998#define DIV_MSCL 0x0600
999#define ENABLE_ACLK_MSCL 0x0800
1000#define ENABLE_PCLK_MSCL 0x0900
1001
1002/* List of parent clocks for Muxes in CMU_MSCL */
1003PNAME(mout_aclk_mscl_532_user_p) = { "fin_pll", "aclk_mscl_532" };
1004
1005static unsigned long mscl_clk_regs[] __initdata = {
1006 MUX_SEL_MSCL,
1007 DIV_MSCL,
1008 ENABLE_ACLK_MSCL,
1009 ENABLE_PCLK_MSCL,
1010};
1011
1012static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
1013 MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532",
1014 mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1),
1015};
1016static struct samsung_div_clock mscl_div_clks[] __initdata = {
1017 DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532",
1018 DIV_MSCL, 0, 3),
1019};
1020static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
1021
1022 GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532",
1023 ENABLE_ACLK_MSCL, 31, 0, 0),
1024 GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532",
1025 ENABLE_ACLK_MSCL, 30, 0, 0),
1026 GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532",
1027 ENABLE_ACLK_MSCL, 29, 0, 0),
1028 GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532",
1029 ENABLE_ACLK_MSCL, 28, 0, 0),
1030 GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0",
1031 "usermux_aclk_mscl_532",
1032 ENABLE_ACLK_MSCL, 27, 0, 0),
1033 GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1",
1034 "usermux_aclk_mscl_532",
1035 ENABLE_ACLK_MSCL, 26, 0, 0),
1036 GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532",
1037 ENABLE_ACLK_MSCL, 25, 0, 0),
1038 GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532",
1039 ENABLE_ACLK_MSCL, 24, 0, 0),
1040 GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge",
1041 "usermux_aclk_mscl_532",
1042 ENABLE_ACLK_MSCL, 23, 0, 0),
1043 GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532",
1044 ENABLE_ACLK_MSCL, 22, 0, 0),
1045 GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532",
1046 ENABLE_ACLK_MSCL, 21, 0, 0),
1047 GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532",
1048 ENABLE_ACLK_MSCL, 20, 0, 0),
1049 GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532",
1050 ENABLE_ACLK_MSCL, 19, 0, 0),
1051 GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532",
1052 ENABLE_ACLK_MSCL, 18, 0, 0),
1053 GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532",
1054 ENABLE_ACLK_MSCL, 17, 0, 0),
1055 GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532",
1056 ENABLE_ACLK_MSCL, 16, 0, 0),
1057 GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p",
1058 "usermux_aclk_mscl_532",
1059 ENABLE_ACLK_MSCL, 15, 0, 0),
1060 GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p",
1061 "usermux_aclk_mscl_532",
1062 ENABLE_ACLK_MSCL, 14, 0, 0),
1063
1064 GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl",
1065 ENABLE_PCLK_MSCL, 31, 0, 0),
1066 GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl",
1067 ENABLE_PCLK_MSCL, 30, 0, 0),
1068 GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl",
1069 ENABLE_PCLK_MSCL, 29, 0, 0),
1070 GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl",
1071 ENABLE_PCLK_MSCL, 28, 0, 0),
1072 GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl",
1073 ENABLE_PCLK_MSCL, 27, 0, 0),
1074 GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl",
1075 ENABLE_PCLK_MSCL, 26, 0, 0),
1076 GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl",
1077 ENABLE_PCLK_MSCL, 25, 0, 0),
1078 GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl",
1079 ENABLE_PCLK_MSCL, 24, 0, 0),
1080 GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl",
1081 ENABLE_PCLK_MSCL, 23, 0, 0),
1082 GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl",
1083 ENABLE_PCLK_MSCL, 22, 0, 0),
1084 GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl",
1085 ENABLE_PCLK_MSCL, 21, 0, 0),
1086 GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl",
1087 ENABLE_PCLK_MSCL, 20, 0, 0),
1088};
1089
1090static struct samsung_cmu_info mscl_cmu_info __initdata = {
1091 .mux_clks = mscl_mux_clks,
1092 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
1093 .div_clks = mscl_div_clks,
1094 .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
1095 .gate_clks = mscl_gate_clks,
1096 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
1097 .nr_clk_ids = MSCL_NR_CLK,
1098 .clk_regs = mscl_clk_regs,
1099 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
1100};
1101
1102static void __init exynos7_clk_mscl_init(struct device_node *np)
1103{
1104 samsung_cmu_register_one(np, &mscl_cmu_info);
1105}
1106
1107CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl",
1108 exynos7_clk_mscl_init);
Padmavathi Venna9f930a32015-01-13 16:57:42 +0530[diff] [blame]1109
1110/* Register Offset definitions for CMU_AUD (0x114C0000) */
1111#define MUX_SEL_AUD 0x0200
1112#define DIV_AUD0 0x0600
1113#define DIV_AUD1 0x0604
1114#define ENABLE_ACLK_AUD 0x0800
1115#define ENABLE_PCLK_AUD 0x0900
1116#define ENABLE_SCLK_AUD 0x0A00
1117
1118/*
1119 * List of parent clocks for Muxes in CMU_AUD
1120 */
1121PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" };
1122PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" };
1123
1124static unsigned long aud_clk_regs[] __initdata = {
1125 MUX_SEL_AUD,
1126 DIV_AUD0,
1127 DIV_AUD1,
1128 ENABLE_ACLK_AUD,
1129 ENABLE_PCLK_AUD,
1130 ENABLE_SCLK_AUD,
1131};
1132
1133static struct samsung_mux_clock aud_mux_clks[] __initdata = {
1134 MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
1135 MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
1136 MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),
1137};
1138
1139static struct samsung_div_clock aud_div_clks[] __initdata = {
1140 DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4),
1141 DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4),
1142 DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4),
1143
1144 DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4),
1145 DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8),
1146 DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4),
1147 DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5),
1148 DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4),
1149};
1150
1151static struct samsung_gate_clock aud_gate_clks[] __initdata = {
1152 GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm",
1153 ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
1154 GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s",
1155 ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0),
1156 GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0),
1157 GATE(0, "sclk_slimbus", "dout_sclk_slimbus",
1158 ENABLE_SCLK_AUD, 30, 0, 0),
1159
1160 GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0),
1161 GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0),
1162 GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0),
1163 GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0),
1164 GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0),
1165 GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0),
1166 GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud",
1167 ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0),
1168 GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud",
1169 ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
1170 GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0),
1171 GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0),
1172
1173 GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0),
1174 GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud",
1175 ENABLE_ACLK_AUD, 28, 0, 0),
1176 GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0),
1177};
1178
1179static struct samsung_cmu_info aud_cmu_info __initdata = {
1180 .mux_clks = aud_mux_clks,
1181 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
1182 .div_clks = aud_div_clks,
1183 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
1184 .gate_clks = aud_gate_clks,
1185 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
1186 .nr_clk_ids = AUD_NR_CLK,
1187 .clk_regs = aud_clk_regs,
1188 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
1189};
1190
1191static void __init exynos7_clk_aud_init(struct device_node *np)
1192{
1193 samsung_cmu_register_one(np, &aud_cmu_info);
1194}
1195
1196CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud",
1197 exynos7_clk_aud_init);