blob: f5e43fab1951aceadc14f07ebb4681320debf7f1 [file] [log] [blame]
Naveen Krishna Ch532abc32014-09-22 10:17:04 +05301/*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9*/
10
11#include <linux/clk.h>
12#include <linux/clkdev.h>
13#include <linux/clk-provider.h>
14#include <linux/of.h>
15
16#include "clk.h"
17#include <dt-bindings/clock/exynos7-clk.h>
18
19/* Register Offset definitions for CMU_TOPC (0x10570000) */
20#define CC_PLL_LOCK 0x0000
21#define BUS0_PLL_LOCK 0x0004
22#define BUS1_DPLL_LOCK 0x0008
23#define MFC_PLL_LOCK 0x000C
24#define AUD_PLL_LOCK 0x0010
25#define CC_PLL_CON0 0x0100
26#define BUS0_PLL_CON0 0x0110
27#define BUS1_DPLL_CON0 0x0120
28#define MFC_PLL_CON0 0x0130
29#define AUD_PLL_CON0 0x0140
30#define MUX_SEL_TOPC0 0x0200
31#define MUX_SEL_TOPC1 0x0204
32#define MUX_SEL_TOPC3 0x020C
33#define DIV_TOPC1 0x0604
34#define DIV_TOPC3 0x060C
35
36static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
37 FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
38 FFACTOR(0, "ffac_topc_bus0_pll_div4",
39 "ffac_topc_bus0_pll_div2", 1, 2, 0),
40 FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0),
41 FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0),
42 FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0),
43};
44
45/* List of parent clocks for Muxes in CMU_TOPC */
46PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
47PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
48PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
49PNAME(mout_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
50
51PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc",
52 "mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc",
53 "mout_sclk_mfc_pll_cmuc" };
54
55PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl",
56 "ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
57PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl",
58 "ffac_topc_bus1_pll_div2"};
59PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl",
60 "ffac_topc_cc_pll_div2"};
61PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl",
62 "ffac_topc_mfc_pll_div2"};
63
64
65PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl",
66 "ffac_topc_bus0_pll_div2"};
67
68static unsigned long topc_clk_regs[] __initdata = {
69 CC_PLL_LOCK,
70 BUS0_PLL_LOCK,
71 BUS1_DPLL_LOCK,
72 MFC_PLL_LOCK,
73 AUD_PLL_LOCK,
74 CC_PLL_CON0,
75 BUS0_PLL_CON0,
76 BUS1_DPLL_CON0,
77 MFC_PLL_CON0,
78 AUD_PLL_CON0,
79 MUX_SEL_TOPC0,
80 MUX_SEL_TOPC1,
81 MUX_SEL_TOPC3,
82 DIV_TOPC1,
83 DIV_TOPC3,
84};
85
86static struct samsung_mux_clock topc_mux_clks[] __initdata = {
87 MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1),
88 MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1),
89 MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1),
90 MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1),
91
92 MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p,
93 MUX_SEL_TOPC0, 16, 2),
94 MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p,
95 MUX_SEL_TOPC0, 20, 1),
96 MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p,
97 MUX_SEL_TOPC0, 24, 1),
98 MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p,
99 MUX_SEL_TOPC0, 28, 1),
100
101 MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
102 MUX_SEL_TOPC1, 16, 1),
103
104 MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
105};
106
107static struct samsung_div_clock topc_div_clks[] __initdata = {
108 DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
109 DIV_TOPC1, 24, 4),
110
111 DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out",
112 DIV_TOPC3, 0, 3),
113 DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl",
114 DIV_TOPC3, 8, 3),
115 DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl",
116 DIV_TOPC3, 12, 3),
117 DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
118 DIV_TOPC3, 16, 3),
119};
120
121static struct samsung_pll_clock topc_pll_clks[] __initdata = {
122 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
123 BUS0_PLL_CON0, NULL),
124 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
125 CC_PLL_CON0, NULL),
126 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
127 BUS1_DPLL_CON0, NULL),
128 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
129 MFC_PLL_CON0, NULL),
130 PLL(pll_1460x, 0, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
131 AUD_PLL_CON0, NULL),
132};
133
134static struct samsung_cmu_info topc_cmu_info __initdata = {
135 .pll_clks = topc_pll_clks,
136 .nr_pll_clks = ARRAY_SIZE(topc_pll_clks),
137 .mux_clks = topc_mux_clks,
138 .nr_mux_clks = ARRAY_SIZE(topc_mux_clks),
139 .div_clks = topc_div_clks,
140 .nr_div_clks = ARRAY_SIZE(topc_div_clks),
141 .fixed_factor_clks = topc_fixed_factor_clks,
142 .nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks),
143 .nr_clk_ids = TOPC_NR_CLK,
144 .clk_regs = topc_clk_regs,
145 .nr_clk_regs = ARRAY_SIZE(topc_clk_regs),
146};
147
148static void __init exynos7_clk_topc_init(struct device_node *np)
149{
150 samsung_cmu_register_one(np, &topc_cmu_info);
151}
152
153CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
154 exynos7_clk_topc_init);
155
156/* Register Offset definitions for CMU_TOP0 (0x105D0000) */
157#define MUX_SEL_TOP00 0x0200
158#define MUX_SEL_TOP01 0x0204
159#define MUX_SEL_TOP03 0x020C
160#define MUX_SEL_TOP0_PERIC3 0x023C
161#define DIV_TOP03 0x060C
162#define DIV_TOP0_PERIC3 0x063C
163#define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
164
165/* List of parent clocks for Muxes in CMU_TOP0 */
166PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" };
167PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" };
168PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" };
169PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" };
170
171PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll",
172 "ffac_top0_bus0_pll_div2"};
173PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll",
174 "ffac_top0_bus1_pll_div2"};
175PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll",
176 "ffac_top0_cc_pll_div2"};
177PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll",
178 "ffac_top0_mfc_pll_div2"};
179
180PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll",
181 "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll",
182 "mout_top0_half_mfc_pll"};
183
184static unsigned long top0_clk_regs[] __initdata = {
185 MUX_SEL_TOP00,
186 MUX_SEL_TOP01,
187 MUX_SEL_TOP03,
188 MUX_SEL_TOP0_PERIC3,
189 DIV_TOP03,
190 DIV_TOP0_PERIC3,
191 ENABLE_SCLK_TOP0_PERIC3,
192};
193
194static struct samsung_mux_clock top0_mux_clks[] __initdata = {
195 MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1),
196 MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1),
197 MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1),
198 MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1),
199
200 MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p,
201 MUX_SEL_TOP01, 4, 1),
202 MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p,
203 MUX_SEL_TOP01, 8, 1),
204 MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p,
205 MUX_SEL_TOP01, 12, 1),
206 MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p,
207 MUX_SEL_TOP01, 16, 1),
208
209 MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
210 MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
211
212 MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
213 MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
214 MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
215 MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
216};
217
218static struct samsung_div_clock top0_div_clks[] __initdata = {
219 DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
220 DIV_TOP03, 12, 6),
221 DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
222 DIV_TOP03, 20, 6),
223
224 DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
225 DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
226 DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
227 DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
228};
229
230static struct samsung_gate_clock top0_gate_clks[] __initdata = {
231 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
232 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
233 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
234 ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
235 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
236 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
237 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
238 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
239};
240
241static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
242 FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0),
243 FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0),
244 FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0),
245 FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0),
246};
247
248static struct samsung_cmu_info top0_cmu_info __initdata = {
249 .mux_clks = top0_mux_clks,
250 .nr_mux_clks = ARRAY_SIZE(top0_mux_clks),
251 .div_clks = top0_div_clks,
252 .nr_div_clks = ARRAY_SIZE(top0_div_clks),
253 .gate_clks = top0_gate_clks,
254 .nr_gate_clks = ARRAY_SIZE(top0_gate_clks),
255 .fixed_factor_clks = top0_fixed_factor_clks,
256 .nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks),
257 .nr_clk_ids = TOP0_NR_CLK,
258 .clk_regs = top0_clk_regs,
259 .nr_clk_regs = ARRAY_SIZE(top0_clk_regs),
260};
261
262static void __init exynos7_clk_top0_init(struct device_node *np)
263{
264 samsung_cmu_register_one(np, &top0_cmu_info);
265}
266
267CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
268 exynos7_clk_top0_init);
269
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530270/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
271#define MUX_SEL_TOP10 0x0200
272#define MUX_SEL_TOP11 0x0204
273#define MUX_SEL_TOP13 0x020C
274#define MUX_SEL_TOP1_FSYS0 0x0224
275#define MUX_SEL_TOP1_FSYS1 0x0228
276#define DIV_TOP13 0x060C
277#define DIV_TOP1_FSYS0 0x0624
278#define DIV_TOP1_FSYS1 0x0628
279#define ENABLE_ACLK_TOP13 0x080C
280#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
281#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
282
283/* List of parent clocks for Muxes in CMU_TOP1 */
284PNAME(mout_top1_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" };
285PNAME(mout_top1_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll_b" };
286PNAME(mout_top1_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll_b" };
287PNAME(mout_top1_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll_b" };
288
289PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
290 "ffac_top1_bus0_pll_div2"};
291PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
292 "ffac_top1_bus1_pll_div2"};
293PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
294 "ffac_top1_cc_pll_div2"};
295PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
296 "ffac_top1_mfc_pll_div2"};
297
298PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
299 "mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
300 "mout_top1_half_mfc_pll"};
301
302static unsigned long top1_clk_regs[] __initdata = {
303 MUX_SEL_TOP10,
304 MUX_SEL_TOP11,
305 MUX_SEL_TOP13,
306 MUX_SEL_TOP1_FSYS0,
307 MUX_SEL_TOP1_FSYS1,
308 DIV_TOP13,
309 DIV_TOP1_FSYS0,
310 DIV_TOP1_FSYS1,
311 ENABLE_ACLK_TOP13,
312 ENABLE_SCLK_TOP1_FSYS0,
313 ENABLE_SCLK_TOP1_FSYS1,
314};
315
316static struct samsung_mux_clock top1_mux_clks[] __initdata = {
317 MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
318 MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
319 MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
320 MUX_SEL_TOP10, 12, 1),
321 MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
322 MUX_SEL_TOP10, 16, 1),
323
324 MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
325 MUX_SEL_TOP11, 4, 1),
326 MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
327 MUX_SEL_TOP11, 8, 1),
328 MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
329 MUX_SEL_TOP11, 12, 1),
330 MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
331 MUX_SEL_TOP11, 16, 1),
332
333 MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
334 MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
335
336 MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
337
338 MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
339 MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
340};
341
342static struct samsung_div_clock top1_div_clks[] __initdata = {
343 DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
344 DIV_TOP13, 24, 4),
345 DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
346 DIV_TOP13, 28, 4),
347
348 DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
349 DIV_TOP1_FSYS0, 24, 4),
350
351 DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
352 DIV_TOP1_FSYS1, 24, 4),
353 DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
354 DIV_TOP1_FSYS1, 28, 4),
355};
356
357static struct samsung_gate_clock top1_gate_clks[] __initdata = {
358 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
359 ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
360
361 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
362 ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
363 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
364 ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
365};
366
367static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
368 FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
369 FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
370 FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
371 FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
372};
373
374static struct samsung_cmu_info top1_cmu_info __initdata = {
375 .mux_clks = top1_mux_clks,
376 .nr_mux_clks = ARRAY_SIZE(top1_mux_clks),
377 .div_clks = top1_div_clks,
378 .nr_div_clks = ARRAY_SIZE(top1_div_clks),
379 .gate_clks = top1_gate_clks,
380 .nr_gate_clks = ARRAY_SIZE(top1_gate_clks),
381 .fixed_factor_clks = top1_fixed_factor_clks,
382 .nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks),
383 .nr_clk_ids = TOP1_NR_CLK,
384 .clk_regs = top1_clk_regs,
385 .nr_clk_regs = ARRAY_SIZE(top1_clk_regs),
386};
387
388static void __init exynos7_clk_top1_init(struct device_node *np)
389{
390 samsung_cmu_register_one(np, &top1_cmu_info);
391}
392
393CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
394 exynos7_clk_top1_init);
395
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530396/* Register Offset definitions for CMU_PERIC0 (0x13610000) */
397#define MUX_SEL_PERIC0 0x0200
398#define ENABLE_PCLK_PERIC0 0x0900
399#define ENABLE_SCLK_PERIC0 0x0A00
400
401/* List of parent clocks for Muxes in CMU_PERIC0 */
402PNAME(mout_aclk_peric0_66_p) = { "fin_pll", "dout_aclk_peric0_66" };
403PNAME(mout_sclk_uart0_p) = { "fin_pll", "sclk_uart0" };
404
405static unsigned long peric0_clk_regs[] __initdata = {
406 MUX_SEL_PERIC0,
407 ENABLE_PCLK_PERIC0,
408 ENABLE_SCLK_PERIC0,
409};
410
411static struct samsung_mux_clock peric0_mux_clks[] __initdata = {
412 MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p,
413 MUX_SEL_PERIC0, 0, 1),
414 MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p,
415 MUX_SEL_PERIC0, 16, 1),
416};
417
418static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
Naveen Krishna Ch57a2b482014-10-21 11:13:51 +0530419 GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
420 ENABLE_PCLK_PERIC0, 8, 0, 0),
421 GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
422 ENABLE_PCLK_PERIC0, 9, 0, 0),
423 GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
424 ENABLE_PCLK_PERIC0, 10, 0, 0),
425 GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
426 ENABLE_PCLK_PERIC0, 11, 0, 0),
427 GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
428 ENABLE_PCLK_PERIC0, 12, 0, 0),
429 GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
430 ENABLE_PCLK_PERIC0, 13, 0, 0),
431 GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
432 ENABLE_PCLK_PERIC0, 14, 0, 0),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530433 GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
434 ENABLE_PCLK_PERIC0, 16, 0, 0),
435
436 GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
437 ENABLE_SCLK_PERIC0, 16, 0, 0),
438};
439
440static struct samsung_cmu_info peric0_cmu_info __initdata = {
441 .mux_clks = peric0_mux_clks,
442 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
443 .gate_clks = peric0_gate_clks,
444 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
445 .nr_clk_ids = PERIC0_NR_CLK,
446 .clk_regs = peric0_clk_regs,
447 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
448};
449
450static void __init exynos7_clk_peric0_init(struct device_node *np)
451{
452 samsung_cmu_register_one(np, &peric0_cmu_info);
453}
454
455/* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
456#define MUX_SEL_PERIC10 0x0200
457#define MUX_SEL_PERIC11 0x0204
458#define ENABLE_PCLK_PERIC1 0x0900
459#define ENABLE_SCLK_PERIC10 0x0A00
460
461CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
462 exynos7_clk_peric0_init);
463
464/* List of parent clocks for Muxes in CMU_PERIC1 */
465PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" };
466PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" };
467PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" };
468PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" };
469
470static unsigned long peric1_clk_regs[] __initdata = {
471 MUX_SEL_PERIC10,
472 MUX_SEL_PERIC11,
473 ENABLE_PCLK_PERIC1,
474 ENABLE_SCLK_PERIC10,
475};
476
477static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
478 MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
479 MUX_SEL_PERIC10, 0, 1),
480
481 MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
482 MUX_SEL_PERIC11, 20, 1),
483 MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
484 MUX_SEL_PERIC11, 24, 1),
485 MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p,
486 MUX_SEL_PERIC11, 28, 1),
487};
488
489static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
Naveen Krishna Ch57a2b482014-10-21 11:13:51 +0530490 GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
491 ENABLE_PCLK_PERIC1, 4, 0, 0),
492 GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
493 ENABLE_PCLK_PERIC1, 5, 0, 0),
494 GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
495 ENABLE_PCLK_PERIC1, 6, 0, 0),
496 GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
497 ENABLE_PCLK_PERIC1, 7, 0, 0),
498 GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
499 ENABLE_PCLK_PERIC1, 8, 0, 0),
Naveen Krishna Ch532abc32014-09-22 10:17:04 +0530500 GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
501 ENABLE_PCLK_PERIC1, 9, 0, 0),
502 GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
503 ENABLE_PCLK_PERIC1, 10, 0, 0),
504 GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
505 ENABLE_PCLK_PERIC1, 11, 0, 0),
506
507 GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
508 ENABLE_SCLK_PERIC10, 9, 0, 0),
509 GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
510 ENABLE_SCLK_PERIC10, 10, 0, 0),
511 GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
512 ENABLE_SCLK_PERIC10, 11, 0, 0),
513};
514
515static struct samsung_cmu_info peric1_cmu_info __initdata = {
516 .mux_clks = peric1_mux_clks,
517 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
518 .gate_clks = peric1_gate_clks,
519 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
520 .nr_clk_ids = PERIC1_NR_CLK,
521 .clk_regs = peric1_clk_regs,
522 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
523};
524
525static void __init exynos7_clk_peric1_init(struct device_node *np)
526{
527 samsung_cmu_register_one(np, &peric1_cmu_info);
528}
529
530CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
531 exynos7_clk_peric1_init);
532
533/* Register Offset definitions for CMU_PERIS (0x10040000) */
534#define MUX_SEL_PERIS 0x0200
535#define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910
536#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10
537
538/* List of parent clocks for Muxes in CMU_PERIS */
539PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" };
540
541static unsigned long peris_clk_regs[] __initdata = {
542 MUX_SEL_PERIS,
543 ENABLE_PCLK_PERIS_SECURE_CHIPID,
544 ENABLE_SCLK_PERIS_SECURE_CHIPID,
545};
546
547static struct samsung_mux_clock peris_mux_clks[] __initdata = {
548 MUX(0, "mout_aclk_peris_66_user",
549 mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1),
550};
551
552static struct samsung_gate_clock peris_gate_clks[] __initdata = {
553 GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
554 ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
555 GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
556 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
557};
558
559static struct samsung_cmu_info peris_cmu_info __initdata = {
560 .mux_clks = peris_mux_clks,
561 .nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
562 .gate_clks = peris_gate_clks,
563 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
564 .nr_clk_ids = PERIS_NR_CLK,
565 .clk_regs = peris_clk_regs,
566 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
567};
568
569static void __init exynos7_clk_peris_init(struct device_node *np)
570{
571 samsung_cmu_register_one(np, &peris_cmu_info);
572}
573
574CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
575 exynos7_clk_peris_init);
Naveen Krishna Ch6d0c8c72014-10-21 11:13:52 +0530576
577/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
578#define MUX_SEL_FSYS00 0x0200
579#define MUX_SEL_FSYS01 0x0204
580#define ENABLE_ACLK_FSYS01 0x0804
581
582/*
583 * List of parent clocks for Muxes in CMU_FSYS0
584 */
585PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" };
586PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" };
587
588static unsigned long fsys0_clk_regs[] __initdata = {
589 MUX_SEL_FSYS00,
590 MUX_SEL_FSYS01,
591 ENABLE_ACLK_FSYS01,
592};
593
594static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
595 MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
596 MUX_SEL_FSYS00, 24, 1),
597
598 MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
599};
600
601static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
602 GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
603 ENABLE_ACLK_FSYS01, 31, 0, 0),
604};
605
606static struct samsung_cmu_info fsys0_cmu_info __initdata = {
607 .mux_clks = fsys0_mux_clks,
608 .nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
609 .gate_clks = fsys0_gate_clks,
610 .nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
611 .nr_clk_ids = TOP1_NR_CLK,
612 .clk_regs = fsys0_clk_regs,
613 .nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
614};
615
616static void __init exynos7_clk_fsys0_init(struct device_node *np)
617{
618 samsung_cmu_register_one(np, &fsys0_cmu_info);
619}
620
621CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
622 exynos7_clk_fsys0_init);
623
624/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
625#define MUX_SEL_FSYS10 0x0200
626#define MUX_SEL_FSYS11 0x0204
627#define ENABLE_ACLK_FSYS1 0x0800
628
629/*
630 * List of parent clocks for Muxes in CMU_FSYS1
631 */
632PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" };
633PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" };
634PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" };
635
636static unsigned long fsys1_clk_regs[] __initdata = {
637 MUX_SEL_FSYS10,
638 MUX_SEL_FSYS11,
639 ENABLE_ACLK_FSYS1,
640};
641
642static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
643 MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
644 MUX_SEL_FSYS10, 28, 1),
645
646 MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
647 MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
648};
649
650static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
651 GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
652 ENABLE_ACLK_FSYS1, 29, 0, 0),
653 GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
654 ENABLE_ACLK_FSYS1, 30, 0, 0),
655};
656
657static struct samsung_cmu_info fsys1_cmu_info __initdata = {
658 .mux_clks = fsys1_mux_clks,
659 .nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
660 .gate_clks = fsys1_gate_clks,
661 .nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
662 .nr_clk_ids = TOP1_NR_CLK,
663 .clk_regs = fsys1_clk_regs,
664 .nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
665};
666
667static void __init exynos7_clk_fsys1_init(struct device_node *np)
668{
669 samsung_cmu_register_one(np, &fsys1_cmu_info);
670}
671
672CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
673 exynos7_clk_fsys1_init);