Blame - drivers/scsi/qla2xxx/qla_dbg.c - SHIFTPHONES/kernel/shift/mainline

blob: 907a7acb163960d204df86273fb51321618d62a7 [file] [log] [blame]

Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1	/*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	2	* QLogic Fibre Channel HBA Driver
Armen Baloyan	bd21eaf	2014-04-11 16:54:24 -0400	[diff] [blame]	3	* Copyright (c) 2003-2014 QLogic Corporation
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	4	*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	5	* See LICENSE.qla2xxx for copyright and licensing details.
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	6	*/
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	7
				8	/*
				9	* Table for showing the current message id in use for particular level
				10	* Change this table for addition of log/debug messages.
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	11	* ----------------------------------------------------------------------
				12	* \| Level \| Last Value Used \| Holes \|
				13	* ----------------------------------------------------------------------
Sawan Chandak	4243c11	2016-01-27 12:03:31 -0500	[diff] [blame]	14	* \| Module Init and Probe \| 0x018f \| 0x0146 \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	15	* \| \| \| 0x015b-0x0160 \|
Himanshu Madhani	d14e72f	2015-04-09 15:00:03 -0400	[diff] [blame]	16	* \| \| \| 0x016e-0x0170 \|
Himanshu Madhani	2f56a7f	2015-12-17 14:56:57 -0500	[diff] [blame]	17	* \| Mailbox commands \| 0x1192 \| \|
				18	* \| \| \| \|
Giridhar Malavali	088d09d	2016-07-06 11:14:20 -0400	[diff] [blame^]	19	* \| Device Discovery \| 0x2003 \| 0x2016 \|
Bart Van Assche	6593d5b	2013-06-25 11:27:24 -0400	[diff] [blame]	20	* \| \| \| 0x2011-0x2012, \|
Himanshu Madhani	df57cab	2014-09-25 05:16:46 -0400	[diff] [blame]	21	* \| \| \| 0x2099-0x20a4 \|
Himanshu Madhani	6eb5471	2015-12-17 14:57:00 -0500	[diff] [blame]	22	* \| Queue Command and IO tracing \| 0x3074 \| 0x300b \|
Arun Easi	9e522cd	2012-08-22 14:21:31 -0400	[diff] [blame]	23	* \| \| \| 0x3027-0x3028 \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	24	* \| \| \| 0x303d-0x3041 \|
				25	* \| \| \| 0x302d,0x3033 \|
				26	* \| \| \| 0x3036,0x3038 \|
				27	* \| \| \| 0x303a \|
Armen Baloyan	e8f5e95	2013-10-30 03:38:17 -0400	[diff] [blame]	28	* \| DPC Thread \| 0x4023 \| 0x4002,0x4013 \|
Alexei Potashnik	b7bd104	2015-12-17 14:57:02 -0500	[diff] [blame]	29	* \| Async Events \| 0x5089 \| 0x502b-0x502f \|
Joe Carnuccio	a29b3dd	2016-07-06 11:14:19 -0400	[diff] [blame]	30	* \| \| \| 0x5047 \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	31	* \| \| \| 0x5084,0x5075 \|
Chad Dupuis	a78951b	2013-08-27 01:37:34 -0400	[diff] [blame]	32	* \| \| \| 0x503d,0x5044 \|
Chad Dupuis	8e5a948	2014-08-08 07:38:09 -0400	[diff] [blame]	33	* \| \| \| 0x507b,0x505f \|
Armen Baloyan	71e5600	2013-08-27 01:37:38 -0400	[diff] [blame]	34	* \| Timer Routines \| 0x6012 \| \|
Harish Zunjarrao	243de67	2016-01-27 12:03:33 -0500	[diff] [blame]	35	* \| User Space Interactions \| 0x70e3 \| 0x7018,0x702e \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	36	* \| \| \| 0x7020,0x7024 \|
				37	* \| \| \| 0x7039,0x7045 \|
				38	* \| \| \| 0x7073-0x7075 \|
				39	* \| \| \| 0x70a5-0x70a6 \|
				40	* \| \| \| 0x70a8,0x70ab \|
				41	* \| \| \| 0x70ad-0x70ae \|
Joe Carnuccio	f1d7ce6	2016-07-06 11:14:17 -0400	[diff] [blame]	42	* \| \| \| 0x70d0-0x70d6 \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	43	* \| \| \| 0x70d7-0x70db \|
				44	* \| \| \| 0x70de-0x70df \|
Chad Dupuis	7108b76	2014-04-11 16:54:45 -0400	[diff] [blame]	45	* \| Task Management \| 0x803d \| 0x8000,0x800b \|
Chad Dupuis	63ee707	2014-04-11 16:54:46 -0400	[diff] [blame]	46	* \| \| \| 0x8019 \|
Chad Dupuis	7108b76	2014-04-11 16:54:45 -0400	[diff] [blame]	47	* \| \| \| 0x8025,0x8026 \|
				48	* \| \| \| 0x8031,0x8032 \|
				49	* \| \| \| 0x8039,0x803c \|
Saurav Kashyap	5f28d2d	2012-05-15 14:34:15 -0400	[diff] [blame]	50	* \| AER/EEH \| 0x9011 \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	51	* \| Virtual Port \| 0xa007 \| \|
Atul Deshmukh	27f4b72	2014-04-11 16:54:26 -0400	[diff] [blame]	52	* \| ISP82XX Specific \| 0xb157 \| 0xb002,0xb024 \|
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	53	* \| \| \| 0xb09e,0xb0ae \|
Hiral Patel	a018d8f	2014-04-11 16:54:34 -0400	[diff] [blame]	54	* \| \| \| 0xb0c3,0xb0c6 \|
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	55	* \| \| \| 0xb0e0-0xb0ef \|
				56	* \| \| \| 0xb085,0xb0dc \|
				57	* \| \| \| 0xb107,0xb108 \|
				58	* \| \| \| 0xb111,0xb11e \|
				59	* \| \| \| 0xb12c,0xb12d \|
				60	* \| \| \| 0xb13a,0xb142 \|
				61	* \| \| \| 0xb13c-0xb140 \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	62	* \| \| \| 0xb149 \|
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	63	* \| MultiQ \| 0xc00c \| \|
Himanshu Madhani	ce1025c	2015-12-17 14:56:58 -0500	[diff] [blame]	64	* \| Misc \| 0xd301 \| 0xd031-0xd0ff \|
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	65	* \| \| \| 0xd101-0xd1fe \|
Joe Carnuccio	2ac224b	2014-09-25 05:16:36 -0400	[diff] [blame]	66	* \| \| \| 0xd214-0xd2fe \|
Alexei Potashnik	a6ca887	2015-07-14 16:00:44 -0400	[diff] [blame]	67	* \| Target Mode \| 0xe080 \| \|
Alexei Potashnik	b7bd104	2015-12-17 14:57:02 -0500	[diff] [blame]	68	* \| Target Mode Management \| 0xf09b \| 0xf002 \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	69	* \| \| \| 0xf046-0xf049 \|
Alexei Potashnik	a6ca887	2015-07-14 16:00:44 -0400	[diff] [blame]	70	* \| Target Mode Task Management \| 0x1000d \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	71	* ----------------------------------------------------------------------
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	72	*/
				73
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	74	#include "qla_def.h"
				75
				76	#include <linux/delay.h>
				77
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	78	static uint32_t ql_dbg_offset = 0x800;
				79
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	80	static inline void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	81	qla2xxx_prep_dump(struct qla_hw_data ha, struct qla2xxx_fw_dump fw_dump)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	82	{
				83	fw_dump->fw_major_version = htonl(ha->fw_major_version);
				84	fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
				85	fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
				86	fw_dump->fw_attributes = htonl(ha->fw_attributes);
				87
				88	fw_dump->vendor = htonl(ha->pdev->vendor);
				89	fw_dump->device = htonl(ha->pdev->device);
				90	fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
				91	fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
				92	}
				93
				94	static inline void *
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	95	qla2xxx_copy_queues(struct qla_hw_data ha, void ptr)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	96	{
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	97	struct req_que *req = ha->req_q_map[0];
				98	struct rsp_que *rsp = ha->rsp_q_map[0];
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	99	/* Request queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	100	memcpy(ptr, req->ring, req->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	101	sizeof(request_t));
				102
				103	/* Response queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	104	ptr += req->length * sizeof(request_t);
				105	memcpy(ptr, rsp->ring, rsp->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	106	sizeof(response_t));
				107
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	108	return ptr + (rsp->length * sizeof(response_t));
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	109	}
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	110
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	111	int
				112	qla27xx_dump_mpi_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
				113	uint32_t ram_dwords, void **nxt)
				114	{
				115	int rval;
				116	uint32_t cnt, stat, timer, dwords, idx;
Bart Van Assche	52c8282	2015-07-09 07:23:26 -0700	[diff] [blame]	117	uint16_t mb0;
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	118	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				119	dma_addr_t dump_dma = ha->gid_list_dma;
				120	uint32_t dump = (uint32_t )ha->gid_list;
				121
				122	rval = QLA_SUCCESS;
				123	mb0 = 0;
				124
				125	WRT_REG_WORD(&reg->mailbox0, MBC_LOAD_DUMP_MPI_RAM);
				126	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				127
				128	dwords = qla2x00_gid_list_size(ha) / 4;
				129	for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
				130	cnt += dwords, addr += dwords) {
				131	if (cnt + dwords > ram_dwords)
				132	dwords = ram_dwords - cnt;
				133
				134	WRT_REG_WORD(&reg->mailbox1, LSW(addr));
				135	WRT_REG_WORD(&reg->mailbox8, MSW(addr));
				136
				137	WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
				138	WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
				139	WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
				140	WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
				141
				142	WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
				143	WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
				144
				145	WRT_REG_WORD(&reg->mailbox9, 0);
				146	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
				147
				148	ha->flags.mbox_int = 0;
				149	for (timer = 6000000; timer; timer--) {
				150	/* Check for pending interrupts. */
				151	stat = RD_REG_DWORD(&reg->host_status);
				152	if (stat & HSRX_RISC_INT) {
				153	stat &= 0xff;
				154
				155	if (stat == 0x1 \|\| stat == 0x2 \|\|
				156	stat == 0x10 \|\| stat == 0x11) {
				157	set_bit(MBX_INTERRUPT,
				158	&ha->mbx_cmd_flags);
				159
				160	mb0 = RD_REG_WORD(&reg->mailbox0);
Bart Van Assche	52c8282	2015-07-09 07:23:26 -0700	[diff] [blame]	161	RD_REG_WORD(&reg->mailbox1);
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	162
				163	WRT_REG_DWORD(&reg->hccr,
				164	HCCRX_CLR_RISC_INT);
				165	RD_REG_DWORD(&reg->hccr);
				166	break;
				167	}
				168
				169	/* Clear this intr; it wasn't a mailbox intr */
				170	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
				171	RD_REG_DWORD(&reg->hccr);
				172	}
				173	udelay(5);
				174	}
				175	ha->flags.mbox_int = 1;
				176
				177	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				178	rval = mb0 & MBS_MASK;
				179	for (idx = 0; idx < dwords; idx++)
				180	ram[cnt + idx] = IS_QLA27XX(ha) ?
				181	le32_to_cpu(dump[idx]) : swab32(dump[idx]);
				182	} else {
				183	rval = QLA_FUNCTION_FAILED;
				184	}
				185	}
				186
				187	*nxt = rval == QLA_SUCCESS ? &ram[cnt] : NULL;
				188	return rval;
				189	}
				190
				191	int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	192	qla24xx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	193	uint32_t ram_dwords, void **nxt)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	194	{
				195	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	196	uint32_t cnt, stat, timer, dwords, idx;
				197	uint16_t mb0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	198	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	199	dma_addr_t dump_dma = ha->gid_list_dma;
				200	uint32_t dump = (uint32_t )ha->gid_list;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	201
				202	rval = QLA_SUCCESS;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	203	mb0 = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	204
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	205	WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	206	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				207
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	208	dwords = qla2x00_gid_list_size(ha) / 4;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	209	for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
				210	cnt += dwords, addr += dwords) {
				211	if (cnt + dwords > ram_dwords)
				212	dwords = ram_dwords - cnt;
				213
				214	WRT_REG_WORD(&reg->mailbox1, LSW(addr));
				215	WRT_REG_WORD(&reg->mailbox8, MSW(addr));
				216
				217	WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
				218	WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
				219	WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
				220	WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
				221
				222	WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
				223	WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	224	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
				225
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	226	ha->flags.mbox_int = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	227	for (timer = 6000000; timer; timer--) {
				228	/* Check for pending interrupts. */
				229	stat = RD_REG_DWORD(&reg->host_status);
				230	if (stat & HSRX_RISC_INT) {
				231	stat &= 0xff;
				232
				233	if (stat == 0x1 \|\| stat == 0x2 \|\|
				234	stat == 0x10 \|\| stat == 0x11) {
				235	set_bit(MBX_INTERRUPT,
				236	&ha->mbx_cmd_flags);
				237
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	238	mb0 = RD_REG_WORD(&reg->mailbox0);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	239
				240	WRT_REG_DWORD(&reg->hccr,
				241	HCCRX_CLR_RISC_INT);
				242	RD_REG_DWORD(&reg->hccr);
				243	break;
				244	}
				245
				246	/* Clear this intr; it wasn't a mailbox intr */
				247	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
				248	RD_REG_DWORD(&reg->hccr);
				249	}
				250	udelay(5);
				251	}
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	252	ha->flags.mbox_int = 1;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	253
				254	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	255	rval = mb0 & MBS_MASK;
				256	for (idx = 0; idx < dwords; idx++)
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	257	ram[cnt + idx] = IS_QLA27XX(ha) ?
				258	le32_to_cpu(dump[idx]) : swab32(dump[idx]);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	259	} else {
				260	rval = QLA_FUNCTION_FAILED;
				261	}
				262	}
				263
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	264	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	265	return rval;
				266	}
				267
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	268	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	269	qla24xx_dump_memory(struct qla_hw_data ha, uint32_t code_ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	270	uint32_t cram_size, void **nxt)
				271	{
				272	int rval;
				273
				274	/* Code RAM. */
				275	rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
				276	if (rval != QLA_SUCCESS)
				277	return rval;
				278
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	279	set_bit(RISC_SRAM_DUMP_CMPL, &ha->fw_dump_cap_flags);
				280
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	281	/* External Memory. */
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	282	rval = qla24xx_dump_ram(ha, 0x100000, *nxt,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	283	ha->fw_memory_size - 0x100000 + 1, nxt);
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	284	if (rval == QLA_SUCCESS)
				285	set_bit(RISC_EXT_MEM_DUMP_CMPL, &ha->fw_dump_cap_flags);
				286
				287	return rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	288	}
				289
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	290	static uint32_t *
				291	qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
				292	uint32_t count, uint32_t *buf)
				293	{
				294	uint32_t __iomem *dmp_reg;
				295
				296	WRT_REG_DWORD(&reg->iobase_addr, iobase);
				297	dmp_reg = &reg->iobase_window;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	298	for ( ; count--; dmp_reg++)
				299	*buf++ = htonl(RD_REG_DWORD(dmp_reg));
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	300
				301	return buf;
				302	}
				303
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	304	void
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	305	qla24xx_pause_risc(struct device_reg_24xx __iomem reg, struct qla_hw_data ha)
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	306	{
Andrew Vasquez	c3b058a	2007-09-20 14:07:38 -0700	[diff] [blame]	307	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	308
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	309	/* 100 usec delay is sufficient enough for hardware to pause RISC */
				310	udelay(100);
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	311	if (RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED)
				312	set_bit(RISC_PAUSE_CMPL, &ha->fw_dump_cap_flags);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	313	}
				314
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	315	int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	316	qla24xx_soft_reset(struct qla_hw_data *ha)
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	317	{
				318	int rval = QLA_SUCCESS;
				319	uint32_t cnt;
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	320	uint16_t wd;
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	321	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				322
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	323	/*
				324	* Reset RISC. The delay is dependent on system architecture.
				325	* Driver can proceed with the reset sequence after waiting
				326	* for a timeout period.
				327	*/
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	328	WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				329	for (cnt = 0; cnt < 30000; cnt++) {
				330	if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
				331	break;
				332
				333	udelay(10);
				334	}
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	335	if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
				336	set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	337
				338	WRT_REG_DWORD(&reg->ctrl_status,
				339	CSRX_ISP_SOFT_RESET\|CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				340	pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
				341
				342	udelay(100);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	343
				344	/* Wait for soft-reset to complete. */
				345	for (cnt = 0; cnt < 30000; cnt++) {
				346	if ((RD_REG_DWORD(&reg->ctrl_status) &
				347	CSRX_ISP_SOFT_RESET) == 0)
				348	break;
				349
				350	udelay(10);
				351	}
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	352	if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
				353	set_bit(ISP_RESET_CMPL, &ha->fw_dump_cap_flags);
				354
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	355	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				356	RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
				357
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	358	for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	359	rval == QLA_SUCCESS; cnt--) {
				360	if (cnt)
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	361	udelay(10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	362	else
				363	rval = QLA_FUNCTION_TIMEOUT;
				364	}
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	365	if (rval == QLA_SUCCESS)
				366	set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	367
				368	return rval;
				369	}
				370
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	371	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	372	qla2xxx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint16_t ram,
Andrew Vasquez	e18e963	2009-06-17 10:30:31 -0700	[diff] [blame]	373	uint32_t ram_words, void **nxt)
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	374	{
				375	int rval;
				376	uint32_t cnt, stat, timer, words, idx;
				377	uint16_t mb0;
				378	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				379	dma_addr_t dump_dma = ha->gid_list_dma;
				380	uint16_t dump = (uint16_t )ha->gid_list;
				381
				382	rval = QLA_SUCCESS;
				383	mb0 = 0;
				384
				385	WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
				386	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				387
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	388	words = qla2x00_gid_list_size(ha) / 2;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	389	for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
				390	cnt += words, addr += words) {
				391	if (cnt + words > ram_words)
				392	words = ram_words - cnt;
				393
				394	WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
				395	WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
				396
				397	WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
				398	WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
				399	WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
				400	WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
				401
				402	WRT_MAILBOX_REG(ha, reg, 4, words);
				403	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				404
				405	for (timer = 6000000; timer; timer--) {
				406	/* Check for pending interrupts. */
				407	stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
				408	if (stat & HSR_RISC_INT) {
				409	stat &= 0xff;
				410
				411	if (stat == 0x1 \|\| stat == 0x2) {
				412	set_bit(MBX_INTERRUPT,
				413	&ha->mbx_cmd_flags);
				414
				415	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				416
				417	/* Release mailbox registers. */
				418	WRT_REG_WORD(&reg->semaphore, 0);
				419	WRT_REG_WORD(&reg->hccr,
				420	HCCR_CLR_RISC_INT);
				421	RD_REG_WORD(&reg->hccr);
				422	break;
				423	} else if (stat == 0x10 \|\| stat == 0x11) {
				424	set_bit(MBX_INTERRUPT,
				425	&ha->mbx_cmd_flags);
				426
				427	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				428
				429	WRT_REG_WORD(&reg->hccr,
				430	HCCR_CLR_RISC_INT);
				431	RD_REG_WORD(&reg->hccr);
				432	break;
				433	}
				434
				435	/* clear this intr; it wasn't a mailbox intr */
				436	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				437	RD_REG_WORD(&reg->hccr);
				438	}
				439	udelay(5);
				440	}
				441
				442	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				443	rval = mb0 & MBS_MASK;
				444	for (idx = 0; idx < words; idx++)
				445	ram[cnt + idx] = swab16(dump[idx]);
				446	} else {
				447	rval = QLA_FUNCTION_FAILED;
				448	}
				449	}
				450
				451	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
				452	return rval;
				453	}
				454
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	455	static inline void
				456	qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
				457	uint16_t *buf)
				458	{
				459	uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
				460
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	461	for ( ; count--; dmp_reg++)
				462	*buf++ = htons(RD_REG_WORD(dmp_reg));
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	463	}
				464
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	465	static inline void *
				466	qla24xx_copy_eft(struct qla_hw_data ha, void ptr)
				467	{
				468	if (!ha->eft)
				469	return ptr;
				470
				471	memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
				472	return ptr + ntohl(ha->fw_dump->eft_size);
				473	}
				474
				475	static inline void *
				476	qla25xx_copy_fce(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				477	{
				478	uint32_t cnt;
				479	uint32_t *iter_reg;
				480	struct qla2xxx_fce_chain *fcec = ptr;
				481
				482	if (!ha->fce)
				483	return ptr;
				484
				485	*last_chain = &fcec->type;
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	486	fcec->type = htonl(DUMP_CHAIN_FCE);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	487	fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
				488	fce_calc_size(ha->fce_bufs));
				489	fcec->size = htonl(fce_calc_size(ha->fce_bufs));
				490	fcec->addr_l = htonl(LSD(ha->fce_dma));
				491	fcec->addr_h = htonl(MSD(ha->fce_dma));
				492
				493	iter_reg = fcec->eregs;
				494	for (cnt = 0; cnt < 8; cnt++)
				495	*iter_reg++ = htonl(ha->fce_mb[cnt]);
				496
				497	memcpy(iter_reg, ha->fce, ntohl(fcec->size));
				498
Giridhar Malavali	3cb0a67	2011-11-18 09:03:11 -0800	[diff] [blame]	499	return (char *)iter_reg + ntohl(fcec->size);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	500	}
				501
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	502	static inline void *
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	503	qla2xxx_copy_atioqueues(struct qla_hw_data ha, void ptr,
				504	uint32_t **last_chain)
				505	{
				506	struct qla2xxx_mqueue_chain *q;
				507	struct qla2xxx_mqueue_header *qh;
				508	uint32_t num_queues;
				509	int que;
				510	struct {
				511	int length;
				512	void *ring;
				513	} aq, *aqp;
				514
Arun Easi	00876ae	2013-03-25 02:21:37 -0400	[diff] [blame]	515	if (!ha->tgt.atio_ring)
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	516	return ptr;
				517
				518	num_queues = 1;
				519	aqp = &aq;
				520	aqp->length = ha->tgt.atio_q_length;
				521	aqp->ring = ha->tgt.atio_ring;
				522
				523	for (que = 0; que < num_queues; que++) {
				524	/* aqp = ha->atio_q_map[que]; */
				525	q = ptr;
				526	*last_chain = &q->type;
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	527	q->type = htonl(DUMP_CHAIN_QUEUE);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	528	q->chain_size = htonl(
				529	sizeof(struct qla2xxx_mqueue_chain) +
				530	sizeof(struct qla2xxx_mqueue_header) +
				531	(aqp->length * sizeof(request_t)));
				532	ptr += sizeof(struct qla2xxx_mqueue_chain);
				533
				534	/* Add header. */
				535	qh = ptr;
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	536	qh->queue = htonl(TYPE_ATIO_QUEUE);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	537	qh->number = htonl(que);
				538	qh->size = htonl(aqp->length * sizeof(request_t));
				539	ptr += sizeof(struct qla2xxx_mqueue_header);
				540
				541	/* Add data. */
				542	memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
				543
				544	ptr += aqp->length * sizeof(request_t);
				545	}
				546
				547	return ptr;
				548	}
				549
				550	static inline void *
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	551	qla25xx_copy_mqueues(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				552	{
				553	struct qla2xxx_mqueue_chain *q;
				554	struct qla2xxx_mqueue_header *qh;
				555	struct req_que *req;
				556	struct rsp_que *rsp;
				557	int que;
				558
				559	if (!ha->mqenable)
				560	return ptr;
				561
				562	/* Request queues */
				563	for (que = 1; que < ha->max_req_queues; que++) {
				564	req = ha->req_q_map[que];
				565	if (!req)
				566	break;
				567
				568	/* Add chain. */
				569	q = ptr;
				570	*last_chain = &q->type;
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	571	q->type = htonl(DUMP_CHAIN_QUEUE);
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	572	q->chain_size = htonl(
				573	sizeof(struct qla2xxx_mqueue_chain) +
				574	sizeof(struct qla2xxx_mqueue_header) +
				575	(req->length * sizeof(request_t)));
				576	ptr += sizeof(struct qla2xxx_mqueue_chain);
				577
				578	/* Add header. */
				579	qh = ptr;
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	580	qh->queue = htonl(TYPE_REQUEST_QUEUE);
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	581	qh->number = htonl(que);
				582	qh->size = htonl(req->length * sizeof(request_t));
				583	ptr += sizeof(struct qla2xxx_mqueue_header);
				584
				585	/* Add data. */
				586	memcpy(ptr, req->ring, req->length * sizeof(request_t));
				587	ptr += req->length * sizeof(request_t);
				588	}
				589
				590	/* Response queues */
				591	for (que = 1; que < ha->max_rsp_queues; que++) {
				592	rsp = ha->rsp_q_map[que];
				593	if (!rsp)
				594	break;
				595
				596	/* Add chain. */
				597	q = ptr;
				598	*last_chain = &q->type;
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	599	q->type = htonl(DUMP_CHAIN_QUEUE);
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	600	q->chain_size = htonl(
				601	sizeof(struct qla2xxx_mqueue_chain) +
				602	sizeof(struct qla2xxx_mqueue_header) +
				603	(rsp->length * sizeof(response_t)));
				604	ptr += sizeof(struct qla2xxx_mqueue_chain);
				605
				606	/* Add header. */
				607	qh = ptr;
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	608	qh->queue = htonl(TYPE_RESPONSE_QUEUE);
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	609	qh->number = htonl(que);
				610	qh->size = htonl(rsp->length * sizeof(response_t));
				611	ptr += sizeof(struct qla2xxx_mqueue_header);
				612
				613	/* Add data. */
				614	memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
				615	ptr += rsp->length * sizeof(response_t);
				616	}
				617
				618	return ptr;
				619	}
				620
				621	static inline void *
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	622	qla25xx_copy_mq(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				623	{
				624	uint32_t cnt, que_idx;
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	625	uint8_t que_cnt;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	626	struct qla2xxx_mq_chain *mq = ptr;
Bart Van Assche	118e2ef	2015-07-09 07:24:27 -0700	[diff] [blame]	627	device_reg_t *reg;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	628
Chad Dupuis	f73cb69	2014-02-26 04:15:06 -0500	[diff] [blame]	629	if (!ha->mqenable \|\| IS_QLA83XX(ha) \|\| IS_QLA27XX(ha))
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	630	return ptr;
				631
				632	mq = ptr;
				633	*last_chain = &mq->type;
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	634	mq->type = htonl(DUMP_CHAIN_MQ);
				635	mq->chain_size = htonl(sizeof(struct qla2xxx_mq_chain));
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	636
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	637	que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
				638	ha->max_req_queues : ha->max_rsp_queues;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	639	mq->count = htonl(que_cnt);
				640	for (cnt = 0; cnt < que_cnt; cnt++) {
Andrew Vasquez	da9b1d5	2013-08-27 01:37:30 -0400	[diff] [blame]	641	reg = ISP_QUE_REG(ha, cnt);
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	642	que_idx = cnt * 4;
Andrew Vasquez	da9b1d5	2013-08-27 01:37:30 -0400	[diff] [blame]	643	mq->qregs[que_idx] =
				644	htonl(RD_REG_DWORD(&reg->isp25mq.req_q_in));
				645	mq->qregs[que_idx+1] =
				646	htonl(RD_REG_DWORD(&reg->isp25mq.req_q_out));
				647	mq->qregs[que_idx+2] =
				648	htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_in));
				649	mq->qregs[que_idx+3] =
				650	htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_out));
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	651	}
				652
				653	return ptr + sizeof(struct qla2xxx_mq_chain);
				654	}
				655
Giridhar Malavali	08de284	2011-08-16 11:31:44 -0700	[diff] [blame]	656	void
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	657	qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
				658	{
				659	struct qla_hw_data *ha = vha->hw;
				660
				661	if (rval != QLA_SUCCESS) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	662	ql_log(ql_log_warn, vha, 0xd000,
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	663	"Failed to dump firmware (%x), dump status flags (0x%lx).\n",
				664	rval, ha->fw_dump_cap_flags);
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	665	ha->fw_dumped = 0;
				666	} else {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	667	ql_log(ql_log_info, vha, 0xd001,
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	668	"Firmware dump saved to temp buffer (%ld/%p), dump status flags (0x%lx).\n",
				669	vha->host_no, ha->fw_dump, ha->fw_dump_cap_flags);
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	670	ha->fw_dumped = 1;
				671	qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
				672	}
				673	}
				674
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	675	/**
				676	* qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
				677	* @ha: HA context
				678	* @hardware_locked: Called with the hardware_lock
				679	*/
				680	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	681	qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	682	{
				683	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	684	uint32_t cnt;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	685	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	686	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	687	uint16_t __iomem *dmp_reg;
				688	unsigned long flags;
				689	struct qla2300_fw_dump *fw;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	690	void *nxt;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	691	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	692
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	693	flags = 0;
				694
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	695	#ifndef __CHECKER__
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	696	if (!hardware_locked)
				697	spin_lock_irqsave(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	698	#endif
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	699
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	700	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	701	ql_log(ql_log_warn, vha, 0xd002,
				702	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	703	goto qla2300_fw_dump_failed;
				704	}
				705
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	706	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	707	ql_log(ql_log_warn, vha, 0xd003,
				708	"Firmware has been previously dumped (%p) "
				709	"-- ignoring request.\n",
				710	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	711	goto qla2300_fw_dump_failed;
				712	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	713	fw = &ha->fw_dump->isp.isp23;
				714	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	715
				716	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	717	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	718
				719	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	720	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	721	if (IS_QLA2300(ha)) {
				722	for (cnt = 30000;
				723	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				724	rval == QLA_SUCCESS; cnt--) {
				725	if (cnt)
				726	udelay(100);
				727	else
				728	rval = QLA_FUNCTION_TIMEOUT;
				729	}
				730	} else {
				731	RD_REG_WORD(&reg->hccr); /* PCI Posting. */
				732	udelay(10);
				733	}
				734
				735	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	736	dmp_reg = &reg->flash_address;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	737	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++, dmp_reg++)
				738	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	739
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	740	dmp_reg = &reg->u.isp2300.req_q_in;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	741	for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2;
				742	cnt++, dmp_reg++)
				743	fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	744
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	745	dmp_reg = &reg->u.isp2300.mailbox0;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	746	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2;
				747	cnt++, dmp_reg++)
				748	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	749
				750	WRT_REG_WORD(&reg->ctrl_status, 0x40);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	751	qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	752
				753	WRT_REG_WORD(&reg->ctrl_status, 0x50);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	754	qla2xxx_read_window(reg, 48, fw->dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	755
				756	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	757	dmp_reg = &reg->risc_hw;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	758	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2;
				759	cnt++, dmp_reg++)
				760	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	761
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	762	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	763	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	764
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	765	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	766	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	767
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	768	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	769	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	770
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	771	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	772	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	773
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	774	WRT_REG_WORD(&reg->pcr, 0x2800);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	775	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	776
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	777	WRT_REG_WORD(&reg->pcr, 0x2A00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	778	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	779
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	780	WRT_REG_WORD(&reg->pcr, 0x2C00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	781	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	782
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	783	WRT_REG_WORD(&reg->pcr, 0x2E00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	784	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	785
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	786	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	787	qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	788
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	789	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	790	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	791
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	792	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	793	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	794
				795	/* Reset RISC. */
				796	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				797	for (cnt = 0; cnt < 30000; cnt++) {
				798	if ((RD_REG_WORD(&reg->ctrl_status) &
				799	CSR_ISP_SOFT_RESET) == 0)
				800	break;
				801
				802	udelay(10);
				803	}
				804	}
				805
				806	if (!IS_QLA2300(ha)) {
				807	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				808	rval == QLA_SUCCESS; cnt--) {
				809	if (cnt)
				810	udelay(100);
				811	else
				812	rval = QLA_FUNCTION_TIMEOUT;
				813	}
				814	}
				815
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	816	/* Get RISC SRAM. */
				817	if (rval == QLA_SUCCESS)
				818	rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
				819	sizeof(fw->risc_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	820
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	821	/* Get stack SRAM. */
				822	if (rval == QLA_SUCCESS)
				823	rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
				824	sizeof(fw->stack_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	825
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	826	/* Get data SRAM. */
				827	if (rval == QLA_SUCCESS)
				828	rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
				829	ha->fw_memory_size - 0x11000 + 1, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	830
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	831	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	832	qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	833
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	834	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	835
				836	qla2300_fw_dump_failed:
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	837	#ifndef __CHECKER__
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	838	if (!hardware_locked)
				839	spin_unlock_irqrestore(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	840	#else
				841	;
				842	#endif
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	843	}
				844
				845	/**
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	846	* qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
				847	* @ha: HA context
				848	* @hardware_locked: Called with the hardware_lock
				849	*/
				850	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	851	qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	852	{
				853	int rval;
				854	uint32_t cnt, timer;
				855	uint16_t risc_address;
				856	uint16_t mb0, mb2;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	857	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	858	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	859	uint16_t __iomem *dmp_reg;
				860	unsigned long flags;
				861	struct qla2100_fw_dump *fw;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	862	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	863
				864	risc_address = 0;
				865	mb0 = mb2 = 0;
				866	flags = 0;
				867
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	868	#ifndef __CHECKER__
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	869	if (!hardware_locked)
				870	spin_lock_irqsave(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	871	#endif
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	872
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	873	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	874	ql_log(ql_log_warn, vha, 0xd004,
				875	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	876	goto qla2100_fw_dump_failed;
				877	}
				878
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	879	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	880	ql_log(ql_log_warn, vha, 0xd005,
				881	"Firmware has been previously dumped (%p) "
				882	"-- ignoring request.\n",
				883	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	884	goto qla2100_fw_dump_failed;
				885	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	886	fw = &ha->fw_dump->isp.isp21;
				887	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	888
				889	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	890	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	891
				892	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	893	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	894	for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				895	rval == QLA_SUCCESS; cnt--) {
				896	if (cnt)
				897	udelay(100);
				898	else
				899	rval = QLA_FUNCTION_TIMEOUT;
				900	}
				901	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	902	dmp_reg = &reg->flash_address;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	903	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++, dmp_reg++)
				904	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	905
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	906	dmp_reg = &reg->u.isp2100.mailbox0;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	907	for (cnt = 0; cnt < ha->mbx_count; cnt++, dmp_reg++) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	908	if (cnt == 8)
				909	dmp_reg = &reg->u_end.isp2200.mailbox8;
				910
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	911	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	912	}
				913
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	914	dmp_reg = &reg->u.isp2100.unused_2[0];
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	915	for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++, dmp_reg++)
				916	fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	917
				918	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	919	dmp_reg = &reg->risc_hw;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	920	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++, dmp_reg++)
				921	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	922
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	923	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	924	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	925
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	926	WRT_REG_WORD(&reg->pcr, 0x2100);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	927	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	928
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	929	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	930	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	931
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	932	WRT_REG_WORD(&reg->pcr, 0x2300);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	933	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	934
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	935	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	936	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	937
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	938	WRT_REG_WORD(&reg->pcr, 0x2500);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	939	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	940
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	941	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	942	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	943
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	944	WRT_REG_WORD(&reg->pcr, 0x2700);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	945	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	946
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	947	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	948	qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	949
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	950	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	951	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	952
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	953	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	954	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	955
				956	/* Reset the ISP. */
				957	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				958	}
				959
				960	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				961	rval == QLA_SUCCESS; cnt--) {
				962	if (cnt)
				963	udelay(100);
				964	else
				965	rval = QLA_FUNCTION_TIMEOUT;
				966	}
				967
				968	/* Pause RISC. */
				969	if (rval == QLA_SUCCESS && (IS_QLA2200(ha) \|\| (IS_QLA2100(ha) &&
				970	(RD_REG_WORD(&reg->mctr) & (BIT_1 \| BIT_0)) != 0))) {
				971
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	972	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	973	for (cnt = 30000;
				974	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				975	rval == QLA_SUCCESS; cnt--) {
				976	if (cnt)
				977	udelay(100);
				978	else
				979	rval = QLA_FUNCTION_TIMEOUT;
				980	}
				981	if (rval == QLA_SUCCESS) {
				982	/* Set memory configuration and timing. */
				983	if (IS_QLA2100(ha))
				984	WRT_REG_WORD(&reg->mctr, 0xf1);
				985	else
				986	WRT_REG_WORD(&reg->mctr, 0xf2);
				987	RD_REG_WORD(&reg->mctr); /* PCI Posting. */
				988
				989	/* Release RISC. */
				990	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
				991	}
				992	}
				993
				994	if (rval == QLA_SUCCESS) {
				995	/* Get RISC SRAM. */
				996	risc_address = 0x1000;
				997	WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
				998	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				999	}
				1000	for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
				1001	cnt++, risc_address++) {
				1002	WRT_MAILBOX_REG(ha, reg, 1, risc_address);
				1003	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				1004
				1005	for (timer = 6000000; timer != 0; timer--) {
				1006	/* Check for pending interrupts. */
				1007	if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
				1008	if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
				1009	set_bit(MBX_INTERRUPT,
				1010	&ha->mbx_cmd_flags);
				1011
				1012	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				1013	mb2 = RD_MAILBOX_REG(ha, reg, 2);
				1014
				1015	WRT_REG_WORD(&reg->semaphore, 0);
				1016	WRT_REG_WORD(&reg->hccr,
				1017	HCCR_CLR_RISC_INT);
				1018	RD_REG_WORD(&reg->hccr);
				1019	break;
				1020	}
				1021	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				1022	RD_REG_WORD(&reg->hccr);
				1023	}
				1024	udelay(5);
				1025	}
				1026
				1027	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				1028	rval = mb0 & MBS_MASK;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1029	fw->risc_ram[cnt] = htons(mb2);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1030	} else {
				1031	rval = QLA_FUNCTION_FAILED;
				1032	}
				1033	}
				1034
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1035	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1036	qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1037
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1038	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1039
				1040	qla2100_fw_dump_failed:
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1041	#ifndef __CHECKER__
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1042	if (!hardware_locked)
				1043	spin_unlock_irqrestore(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1044	#else
				1045	;
				1046	#endif
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1047	}
				1048
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1049	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1050	qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1051	{
				1052	int rval;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1053	uint32_t cnt;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1054	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1055	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1056	uint32_t __iomem *dmp_reg;
				1057	uint32_t *iter_reg;
				1058	uint16_t __iomem *mbx_reg;
				1059	unsigned long flags;
				1060	struct qla24xx_fw_dump *fw;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1061	void *nxt;
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1062	void *nxt_chain;
				1063	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1064	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1065
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	1066	if (IS_P3P_TYPE(ha))
Giridhar Malavali	a908301	2010-04-12 17:59:55 -0700	[diff] [blame]	1067	return;
				1068
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1069	flags = 0;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1070	ha->fw_dump_cap_flags = 0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1071
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1072	#ifndef __CHECKER__
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1073	if (!hardware_locked)
				1074	spin_lock_irqsave(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1075	#endif
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1076
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	1077	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1078	ql_log(ql_log_warn, vha, 0xd006,
				1079	"No buffer available for dump.\n");
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1080	goto qla24xx_fw_dump_failed;
				1081	}
				1082
				1083	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1084	ql_log(ql_log_warn, vha, 0xd007,
				1085	"Firmware has been previously dumped (%p) "
				1086	"-- ignoring request.\n",
				1087	ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1088	goto qla24xx_fw_dump_failed;
				1089	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1090	fw = &ha->fw_dump->isp.isp24;
				1091	qla2xxx_prep_dump(ha, ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1092
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	1093	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1094
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	1095	/*
				1096	* Pause RISC. No need to track timeout, as resetting the chip
				1097	* is the right approach incase of pause timeout
				1098	*/
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1099	qla24xx_pause_risc(reg, ha);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1100
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1101	/* Host interface registers. */
				1102	dmp_reg = &reg->flash_addr;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	1103	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++)
				1104	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1105
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1106	/* Disable interrupts. */
				1107	WRT_REG_DWORD(&reg->ictrl, 0);
				1108	RD_REG_DWORD(&reg->ictrl);
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1109
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1110	/* Shadow registers. */
				1111	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1112	RD_REG_DWORD(&reg->iobase_addr);
				1113	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1114	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1115
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1116	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1117	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1118
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1119	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1120	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1121
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1122	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1123	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1124
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1125	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1126	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1127
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1128	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1129	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1130
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1131	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1132	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1133
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1134	/* Mailbox registers. */
				1135	mbx_reg = &reg->mailbox0;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	1136	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, dmp_reg++)
				1137	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1138
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1139	/* Transfer sequence registers. */
				1140	iter_reg = fw->xseq_gp_reg;
				1141	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1142	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1143	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1144	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1145	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1146	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1147	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1148	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1149
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1150	qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
				1151	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1152
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1153	/* Receive sequence registers. */
				1154	iter_reg = fw->rseq_gp_reg;
				1155	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1156	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1157	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1158	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1159	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1160	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1161	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1162	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1163
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1164	qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
				1165	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1166	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1167
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1168	/* Command DMA registers. */
				1169	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1170
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1171	/* Queues. */
				1172	iter_reg = fw->req0_dma_reg;
				1173	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1174	dmp_reg = &reg->iobase_q;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	1175	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
				1176	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1177
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1178	iter_reg = fw->resp0_dma_reg;
				1179	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1180	dmp_reg = &reg->iobase_q;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	1181	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
				1182	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1183
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1184	iter_reg = fw->req1_dma_reg;
				1185	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1186	dmp_reg = &reg->iobase_q;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	1187	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
				1188	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1189
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1190	/* Transmit DMA registers. */
				1191	iter_reg = fw->xmt0_dma_reg;
				1192	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1193	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1194
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1195	iter_reg = fw->xmt1_dma_reg;
				1196	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1197	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1198
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1199	iter_reg = fw->xmt2_dma_reg;
				1200	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1201	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1202
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1203	iter_reg = fw->xmt3_dma_reg;
				1204	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1205	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1206
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1207	iter_reg = fw->xmt4_dma_reg;
				1208	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1209	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1210
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1211	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1212
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1213	/* Receive DMA registers. */
				1214	iter_reg = fw->rcvt0_data_dma_reg;
				1215	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1216	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1217
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1218	iter_reg = fw->rcvt1_data_dma_reg;
				1219	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1220	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1221
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1222	/* RISC registers. */
				1223	iter_reg = fw->risc_gp_reg;
				1224	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1225	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1226	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1227	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1228	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1229	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1230	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1231	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1232
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1233	/* Local memory controller registers. */
				1234	iter_reg = fw->lmc_reg;
				1235	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1236	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1237	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1238	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1239	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1240	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1241	qla24xx_read_window(reg, 0x3060, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1242
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1243	/* Fibre Protocol Module registers. */
				1244	iter_reg = fw->fpm_hdw_reg;
				1245	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1246	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1247	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1248	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1249	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1250	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1251	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1252	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1253	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1254	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1255	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1256	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1257
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1258	/* Frame Buffer registers. */
				1259	iter_reg = fw->fb_hdw_reg;
				1260	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1261	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1262	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1263	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1264	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1265	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1266	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1267	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1268	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1269	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1270	qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1271
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1272	rval = qla24xx_soft_reset(ha);
				1273	if (rval != QLA_SUCCESS)
				1274	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1275
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1276	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1277	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1278	if (rval != QLA_SUCCESS)
				1279	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1280
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1281	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1282
				1283	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1284
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1285	nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
				1286	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
				1287	if (last_chain) {
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	1288	ha->fw_dump->version \|= htonl(DUMP_CHAIN_VARIANT);
				1289	*last_chain \|= htonl(DUMP_CHAIN_LAST);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1290	}
				1291
				1292	/* Adjust valid length. */
				1293	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1294
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1295	qla24xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1296	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1297
				1298	qla24xx_fw_dump_failed:
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1299	#ifndef __CHECKER__
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1300	if (!hardware_locked)
				1301	spin_unlock_irqrestore(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1302	#else
				1303	;
				1304	#endif
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1305	}
				1306
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1307	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1308	qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1309	{
				1310	int rval;
				1311	uint32_t cnt;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1312	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1313	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1314	uint32_t __iomem *dmp_reg;
				1315	uint32_t *iter_reg;
				1316	uint16_t __iomem *mbx_reg;
				1317	unsigned long flags;
				1318	struct qla25xx_fw_dump *fw;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1319	void nxt, nxt_chain;
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1320	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1321	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1322
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1323	flags = 0;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1324	ha->fw_dump_cap_flags = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1325
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1326	#ifndef __CHECKER__
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1327	if (!hardware_locked)
				1328	spin_lock_irqsave(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1329	#endif
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1330
				1331	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1332	ql_log(ql_log_warn, vha, 0xd008,
				1333	"No buffer available for dump.\n");
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1334	goto qla25xx_fw_dump_failed;
				1335	}
				1336
				1337	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1338	ql_log(ql_log_warn, vha, 0xd009,
				1339	"Firmware has been previously dumped (%p) "
				1340	"-- ignoring request.\n",
				1341	ha->fw_dump);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1342	goto qla25xx_fw_dump_failed;
				1343	}
				1344	fw = &ha->fw_dump->isp.isp25;
				1345	qla2xxx_prep_dump(ha, ha->fw_dump);
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	1346	ha->fw_dump->version = htonl(2);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1347
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1348	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1349
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	1350	/*
				1351	* Pause RISC. No need to track timeout, as resetting the chip
				1352	* is the right approach incase of pause timeout
				1353	*/
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1354	qla24xx_pause_risc(reg, ha);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1355
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1356	/* Host/Risc registers. */
				1357	iter_reg = fw->host_risc_reg;
				1358	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1359	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1360
				1361	/* PCIe registers. */
				1362	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1363	RD_REG_DWORD(&reg->iobase_addr);
				1364	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1365	dmp_reg = &reg->iobase_c4;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	1366	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg));
				1367	dmp_reg++;
				1368	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg));
				1369	dmp_reg++;
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1370	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1371	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1372
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1373	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1374	RD_REG_DWORD(&reg->iobase_window);
				1375
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1376	/* Host interface registers. */
				1377	dmp_reg = &reg->flash_addr;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	1378	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++)
				1379	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1380
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1381	/* Disable interrupts. */
				1382	WRT_REG_DWORD(&reg->ictrl, 0);
				1383	RD_REG_DWORD(&reg->ictrl);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1384
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1385	/* Shadow registers. */
				1386	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1387	RD_REG_DWORD(&reg->iobase_addr);
				1388	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1389	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1390
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1391	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1392	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1393
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1394	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1395	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1396
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1397	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1398	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1399
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1400	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1401	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1402
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1403	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1404	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1405
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1406	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1407	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1408
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1409	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1410	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1411
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1412	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1413	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1414
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1415	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1416	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1417
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1418	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1419	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1420
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1421	/* RISC I/O register. */
				1422	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1423	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1424
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1425	/* Mailbox registers. */
				1426	mbx_reg = &reg->mailbox0;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	1427	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, mbx_reg++)
				1428	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1429
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1430	/* Transfer sequence registers. */
				1431	iter_reg = fw->xseq_gp_reg;
				1432	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1433	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1434	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1435	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1436	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1437	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1438	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1439	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1440
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1441	iter_reg = fw->xseq_0_reg;
				1442	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1443	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1444	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1445
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1446	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1447
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1448	/* Receive sequence registers. */
				1449	iter_reg = fw->rseq_gp_reg;
				1450	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1451	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1452	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1453	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1454	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1455	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1456	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1457	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1458
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1459	iter_reg = fw->rseq_0_reg;
				1460	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1461	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1462
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1463	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1464	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1465
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1466	/* Auxiliary sequence registers. */
				1467	iter_reg = fw->aseq_gp_reg;
				1468	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1469	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1470	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1471	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1472	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1473	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1474	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1475	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1476
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1477	iter_reg = fw->aseq_0_reg;
				1478	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1479	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1480
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1481	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1482	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1483
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1484	/* Command DMA registers. */
				1485	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1486
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1487	/* Queues. */
				1488	iter_reg = fw->req0_dma_reg;
				1489	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1490	dmp_reg = &reg->iobase_q;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	1491	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
				1492	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1493
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1494	iter_reg = fw->resp0_dma_reg;
				1495	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1496	dmp_reg = &reg->iobase_q;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	1497	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
				1498	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1499
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1500	iter_reg = fw->req1_dma_reg;
				1501	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1502	dmp_reg = &reg->iobase_q;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	1503	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
				1504	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1505
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1506	/* Transmit DMA registers. */
				1507	iter_reg = fw->xmt0_dma_reg;
				1508	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1509	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1510
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1511	iter_reg = fw->xmt1_dma_reg;
				1512	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1513	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1514
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1515	iter_reg = fw->xmt2_dma_reg;
				1516	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1517	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1518
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1519	iter_reg = fw->xmt3_dma_reg;
				1520	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1521	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1522
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1523	iter_reg = fw->xmt4_dma_reg;
				1524	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1525	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1526
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1527	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1528
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1529	/* Receive DMA registers. */
				1530	iter_reg = fw->rcvt0_data_dma_reg;
				1531	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1532	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1533
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1534	iter_reg = fw->rcvt1_data_dma_reg;
				1535	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1536	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1537
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1538	/* RISC registers. */
				1539	iter_reg = fw->risc_gp_reg;
				1540	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1541	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1542	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1543	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1544	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1545	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1546	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1547	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1548
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1549	/* Local memory controller registers. */
				1550	iter_reg = fw->lmc_reg;
				1551	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1552	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1553	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1554	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1555	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1556	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1557	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1558	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1559
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1560	/* Fibre Protocol Module registers. */
				1561	iter_reg = fw->fpm_hdw_reg;
				1562	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1563	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1564	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1565	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1566	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1567	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1568	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1569	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1570	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1571	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1572	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1573	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1574
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1575	/* Frame Buffer registers. */
				1576	iter_reg = fw->fb_hdw_reg;
				1577	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1578	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1579	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1580	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1581	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1582	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1583	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1584	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1585	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1586	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1587	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1588	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1589
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1590	/* Multi queue registers */
				1591	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1592	&last_chain);
				1593
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1594	rval = qla24xx_soft_reset(ha);
				1595	if (rval != QLA_SUCCESS)
				1596	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1597
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1598	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1599	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1600	if (rval != QLA_SUCCESS)
				1601	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1602
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1603	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1604
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	1605	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1606
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1607	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1608	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1609	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1610	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1611	if (last_chain) {
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	1612	ha->fw_dump->version \|= htonl(DUMP_CHAIN_VARIANT);
				1613	*last_chain \|= htonl(DUMP_CHAIN_LAST);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1614	}
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1615
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1616	/* Adjust valid length. */
				1617	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1618
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1619	qla25xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1620	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1621
				1622	qla25xx_fw_dump_failed:
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1623	#ifndef __CHECKER__
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1624	if (!hardware_locked)
				1625	spin_unlock_irqrestore(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1626	#else
				1627	;
				1628	#endif
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1629	}
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1630
				1631	void
				1632	qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1633	{
				1634	int rval;
				1635	uint32_t cnt;
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1636	struct qla_hw_data *ha = vha->hw;
				1637	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1638	uint32_t __iomem *dmp_reg;
				1639	uint32_t *iter_reg;
				1640	uint16_t __iomem *mbx_reg;
				1641	unsigned long flags;
				1642	struct qla81xx_fw_dump *fw;
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1643	void nxt, nxt_chain;
				1644	uint32_t *last_chain = NULL;
				1645	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1646
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1647	flags = 0;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1648	ha->fw_dump_cap_flags = 0;
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1649
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1650	#ifndef __CHECKER__
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1651	if (!hardware_locked)
				1652	spin_lock_irqsave(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1653	#endif
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1654
				1655	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1656	ql_log(ql_log_warn, vha, 0xd00a,
				1657	"No buffer available for dump.\n");
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1658	goto qla81xx_fw_dump_failed;
				1659	}
				1660
				1661	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1662	ql_log(ql_log_warn, vha, 0xd00b,
				1663	"Firmware has been previously dumped (%p) "
				1664	"-- ignoring request.\n",
				1665	ha->fw_dump);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1666	goto qla81xx_fw_dump_failed;
				1667	}
				1668	fw = &ha->fw_dump->isp.isp81;
				1669	qla2xxx_prep_dump(ha, ha->fw_dump);
				1670
				1671	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1672
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	1673	/*
				1674	* Pause RISC. No need to track timeout, as resetting the chip
				1675	* is the right approach incase of pause timeout
				1676	*/
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1677	qla24xx_pause_risc(reg, ha);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1678
				1679	/* Host/Risc registers. */
				1680	iter_reg = fw->host_risc_reg;
				1681	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1682	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1683
				1684	/* PCIe registers. */
				1685	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1686	RD_REG_DWORD(&reg->iobase_addr);
				1687	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1688	dmp_reg = &reg->iobase_c4;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	1689	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg));
				1690	dmp_reg++;
				1691	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg));
				1692	dmp_reg++;
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1693	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1694	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				1695
				1696	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1697	RD_REG_DWORD(&reg->iobase_window);
				1698
				1699	/* Host interface registers. */
				1700	dmp_reg = &reg->flash_addr;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	1701	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++)
				1702	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg));
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1703
				1704	/* Disable interrupts. */
				1705	WRT_REG_DWORD(&reg->ictrl, 0);
				1706	RD_REG_DWORD(&reg->ictrl);
				1707
				1708	/* Shadow registers. */
				1709	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1710	RD_REG_DWORD(&reg->iobase_addr);
				1711	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1712	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1713
				1714	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1715	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1716
				1717	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1718	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1719
				1720	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1721	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1722
				1723	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1724	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1725
				1726	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1727	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1728
				1729	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1730	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1731
				1732	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1733	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1734
				1735	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1736	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1737
				1738	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1739	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1740
				1741	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1742	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1743
				1744	/* RISC I/O register. */
				1745	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1746	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				1747
				1748	/* Mailbox registers. */
				1749	mbx_reg = &reg->mailbox0;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	1750	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, mbx_reg++)
				1751	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg));
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1752
				1753	/* Transfer sequence registers. */
				1754	iter_reg = fw->xseq_gp_reg;
				1755	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1756	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1757	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1758	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1759	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1760	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1761	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1762	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				1763
				1764	iter_reg = fw->xseq_0_reg;
				1765	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1766	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1767	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				1768
				1769	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				1770
				1771	/* Receive sequence registers. */
				1772	iter_reg = fw->rseq_gp_reg;
				1773	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1774	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1775	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1776	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1777	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1778	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1779	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1780	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				1781
				1782	iter_reg = fw->rseq_0_reg;
				1783	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1784	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				1785
				1786	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1787	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				1788
				1789	/* Auxiliary sequence registers. */
				1790	iter_reg = fw->aseq_gp_reg;
				1791	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1792	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1793	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1794	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1795	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1796	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1797	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1798	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				1799
				1800	iter_reg = fw->aseq_0_reg;
				1801	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1802	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				1803
				1804	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1805	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				1806
				1807	/* Command DMA registers. */
				1808	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
				1809
				1810	/* Queues. */
				1811	iter_reg = fw->req0_dma_reg;
				1812	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1813	dmp_reg = &reg->iobase_q;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	1814	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
				1815	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1816
				1817	iter_reg = fw->resp0_dma_reg;
				1818	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1819	dmp_reg = &reg->iobase_q;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	1820	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
				1821	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1822
				1823	iter_reg = fw->req1_dma_reg;
				1824	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1825	dmp_reg = &reg->iobase_q;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	1826	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
				1827	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1828
				1829	/* Transmit DMA registers. */
				1830	iter_reg = fw->xmt0_dma_reg;
				1831	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1832	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				1833
				1834	iter_reg = fw->xmt1_dma_reg;
				1835	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1836	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				1837
				1838	iter_reg = fw->xmt2_dma_reg;
				1839	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1840	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				1841
				1842	iter_reg = fw->xmt3_dma_reg;
				1843	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1844	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				1845
				1846	iter_reg = fw->xmt4_dma_reg;
				1847	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1848	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				1849
				1850	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				1851
				1852	/* Receive DMA registers. */
				1853	iter_reg = fw->rcvt0_data_dma_reg;
				1854	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1855	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				1856
				1857	iter_reg = fw->rcvt1_data_dma_reg;
				1858	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1859	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				1860
				1861	/* RISC registers. */
				1862	iter_reg = fw->risc_gp_reg;
				1863	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1864	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1865	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1866	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1867	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1868	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1869	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1870	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				1871
				1872	/* Local memory controller registers. */
				1873	iter_reg = fw->lmc_reg;
				1874	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1875	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1876	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1877	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1878	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1879	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1880	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1881	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				1882
				1883	/* Fibre Protocol Module registers. */
				1884	iter_reg = fw->fpm_hdw_reg;
				1885	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1886	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1887	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1888	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1889	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1890	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1891	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1892	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1893	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1894	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1895	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1896	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				1897	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				1898	qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				1899
				1900	/* Frame Buffer registers. */
				1901	iter_reg = fw->fb_hdw_reg;
				1902	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1903	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1904	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1905	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1906	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1907	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1908	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1909	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1910	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1911	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1912	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1913	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				1914	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				1915
				1916	/* Multi queue registers */
				1917	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1918	&last_chain);
				1919
				1920	rval = qla24xx_soft_reset(ha);
				1921	if (rval != QLA_SUCCESS)
				1922	goto qla81xx_fw_dump_failed_0;
				1923
				1924	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				1925	&nxt);
				1926	if (rval != QLA_SUCCESS)
				1927	goto qla81xx_fw_dump_failed_0;
				1928
				1929	nxt = qla2xxx_copy_queues(ha, nxt);
				1930
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	1931	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1932
				1933	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1934	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1935	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1936	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1937	if (last_chain) {
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	1938	ha->fw_dump->version \|= htonl(DUMP_CHAIN_VARIANT);
				1939	*last_chain \|= htonl(DUMP_CHAIN_LAST);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1940	}
				1941
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1942	/* Adjust valid length. */
				1943	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1944
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1945	qla81xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1946	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1947
				1948	qla81xx_fw_dump_failed:
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1949	#ifndef __CHECKER__
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1950	if (!hardware_locked)
				1951	spin_unlock_irqrestore(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1952	#else
				1953	;
				1954	#endif
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1955	}
				1956
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1957	void
				1958	qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1959	{
				1960	int rval;
Bart Van Assche	52c8282	2015-07-09 07:23:26 -0700	[diff] [blame]	1961	uint32_t cnt;
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1962	struct qla_hw_data *ha = vha->hw;
				1963	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1964	uint32_t __iomem *dmp_reg;
				1965	uint32_t *iter_reg;
				1966	uint16_t __iomem *mbx_reg;
				1967	unsigned long flags;
				1968	struct qla83xx_fw_dump *fw;
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1969	void nxt, nxt_chain;
				1970	uint32_t *last_chain = NULL;
				1971	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1972
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1973	flags = 0;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	1974	ha->fw_dump_cap_flags = 0;
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1975
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1976	#ifndef __CHECKER__
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1977	if (!hardware_locked)
				1978	spin_lock_irqsave(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	1979	#endif
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1980
				1981	if (!ha->fw_dump) {
				1982	ql_log(ql_log_warn, vha, 0xd00c,
				1983	"No buffer available for dump!!!\n");
				1984	goto qla83xx_fw_dump_failed;
				1985	}
				1986
				1987	if (ha->fw_dumped) {
				1988	ql_log(ql_log_warn, vha, 0xd00d,
				1989	"Firmware has been previously dumped (%p) -- ignoring "
				1990	"request...\n", ha->fw_dump);
				1991	goto qla83xx_fw_dump_failed;
				1992	}
				1993	fw = &ha->fw_dump->isp.isp83;
				1994	qla2xxx_prep_dump(ha, ha->fw_dump);
				1995
				1996	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1997
Hiral Patel	2f389fc	2014-04-11 16:54:20 -0400	[diff] [blame]	1998	/*
				1999	* Pause RISC. No need to track timeout, as resetting the chip
				2000	* is the right approach incase of pause timeout
				2001	*/
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	2002	qla24xx_pause_risc(reg, ha);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2003
				2004	WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
				2005	dmp_reg = &reg->iobase_window;
Bart Van Assche	52c8282	2015-07-09 07:23:26 -0700	[diff] [blame]	2006	RD_REG_DWORD(dmp_reg);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2007	WRT_REG_DWORD(dmp_reg, 0);
				2008
				2009	dmp_reg = &reg->unused_4_1[0];
Bart Van Assche	52c8282	2015-07-09 07:23:26 -0700	[diff] [blame]	2010	RD_REG_DWORD(dmp_reg);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2011	WRT_REG_DWORD(dmp_reg, 0);
				2012
				2013	WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
				2014	dmp_reg = &reg->unused_4_1[2];
Bart Van Assche	52c8282	2015-07-09 07:23:26 -0700	[diff] [blame]	2015	RD_REG_DWORD(dmp_reg);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2016	WRT_REG_DWORD(dmp_reg, 0);
				2017
				2018	/* select PCR and disable ecc checking and correction */
				2019	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				2020	RD_REG_DWORD(&reg->iobase_addr);
				2021	WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
				2022
				2023	/* Host/Risc registers. */
				2024	iter_reg = fw->host_risc_reg;
				2025	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				2026	iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				2027	qla24xx_read_window(reg, 0x7040, 16, iter_reg);
				2028
				2029	/* PCIe registers. */
				2030	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				2031	RD_REG_DWORD(&reg->iobase_addr);
				2032	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				2033	dmp_reg = &reg->iobase_c4;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	2034	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg));
				2035	dmp_reg++;
				2036	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg));
				2037	dmp_reg++;
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2038	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				2039	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				2040
				2041	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				2042	RD_REG_DWORD(&reg->iobase_window);
				2043
				2044	/* Host interface registers. */
				2045	dmp_reg = &reg->flash_addr;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	2046	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++)
				2047	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg));
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2048
				2049	/* Disable interrupts. */
				2050	WRT_REG_DWORD(&reg->ictrl, 0);
				2051	RD_REG_DWORD(&reg->ictrl);
				2052
				2053	/* Shadow registers. */
				2054	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				2055	RD_REG_DWORD(&reg->iobase_addr);
				2056	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				2057	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2058
				2059	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				2060	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2061
				2062	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				2063	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2064
				2065	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				2066	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2067
				2068	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				2069	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2070
				2071	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				2072	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2073
				2074	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				2075	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2076
				2077	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				2078	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2079
				2080	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				2081	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2082
				2083	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				2084	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2085
				2086	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				2087	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				2088
				2089	/* RISC I/O register. */
				2090	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				2091	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				2092
				2093	/* Mailbox registers. */
				2094	mbx_reg = &reg->mailbox0;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	2095	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, dmp_reg++)
				2096	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg));
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2097
				2098	/* Transfer sequence registers. */
				2099	iter_reg = fw->xseq_gp_reg;
				2100	iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
				2101	iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
				2102	iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
				2103	iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
				2104	iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
				2105	iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
				2106	iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
				2107	iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
				2108	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				2109	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				2110	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				2111	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				2112	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				2113	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				2114	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				2115	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				2116
				2117	iter_reg = fw->xseq_0_reg;
				2118	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				2119	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				2120	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				2121
				2122	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				2123
				2124	qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
				2125
				2126	/* Receive sequence registers. */
				2127	iter_reg = fw->rseq_gp_reg;
				2128	iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
				2129	iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
				2130	iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
				2131	iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
				2132	iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
				2133	iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
				2134	iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
				2135	iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
				2136	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				2137	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				2138	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				2139	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				2140	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				2141	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				2142	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				2143	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				2144
				2145	iter_reg = fw->rseq_0_reg;
				2146	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				2147	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				2148
				2149	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				2150	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				2151	qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
				2152
				2153	/* Auxiliary sequence registers. */
				2154	iter_reg = fw->aseq_gp_reg;
				2155	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				2156	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				2157	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				2158	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				2159	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				2160	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				2161	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				2162	iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				2163	iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
				2164	iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
				2165	iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
				2166	iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
				2167	iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
				2168	iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
				2169	iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
				2170	qla24xx_read_window(reg, 0xB170, 16, iter_reg);
				2171
				2172	iter_reg = fw->aseq_0_reg;
				2173	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				2174	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				2175
				2176	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				2177	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				2178	qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
				2179
				2180	/* Command DMA registers. */
				2181	iter_reg = fw->cmd_dma_reg;
				2182	iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
				2183	iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
				2184	iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
				2185	qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
				2186
				2187	/* Queues. */
				2188	iter_reg = fw->req0_dma_reg;
				2189	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				2190	dmp_reg = &reg->iobase_q;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	2191	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
				2192	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2193
				2194	iter_reg = fw->resp0_dma_reg;
				2195	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				2196	dmp_reg = &reg->iobase_q;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	2197	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
				2198	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2199
				2200	iter_reg = fw->req1_dma_reg;
				2201	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				2202	dmp_reg = &reg->iobase_q;
Joe Carnuccio	da08ef5	2016-01-27 12:03:34 -0500	[diff] [blame]	2203	for (cnt = 0; cnt < 7; cnt++, dmp_reg++)
				2204	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg));
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2205
				2206	/* Transmit DMA registers. */
				2207	iter_reg = fw->xmt0_dma_reg;
				2208	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				2209	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				2210
				2211	iter_reg = fw->xmt1_dma_reg;
				2212	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				2213	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				2214
				2215	iter_reg = fw->xmt2_dma_reg;
				2216	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				2217	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				2218
				2219	iter_reg = fw->xmt3_dma_reg;
				2220	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				2221	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				2222
				2223	iter_reg = fw->xmt4_dma_reg;
				2224	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				2225	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				2226
				2227	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				2228
				2229	/* Receive DMA registers. */
				2230	iter_reg = fw->rcvt0_data_dma_reg;
				2231	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				2232	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				2233
				2234	iter_reg = fw->rcvt1_data_dma_reg;
				2235	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				2236	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				2237
				2238	/* RISC registers. */
				2239	iter_reg = fw->risc_gp_reg;
				2240	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				2241	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				2242	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				2243	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				2244	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				2245	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				2246	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				2247	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				2248
				2249	/* Local memory controller registers. */
				2250	iter_reg = fw->lmc_reg;
				2251	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				2252	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				2253	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				2254	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				2255	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				2256	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				2257	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				2258	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				2259
				2260	/* Fibre Protocol Module registers. */
				2261	iter_reg = fw->fpm_hdw_reg;
				2262	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				2263	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				2264	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				2265	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				2266	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				2267	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				2268	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				2269	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				2270	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				2271	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				2272	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				2273	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				2274	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				2275	iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				2276	iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
				2277	qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
				2278
				2279	/* RQ0 Array registers. */
				2280	iter_reg = fw->rq0_array_reg;
				2281	iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
				2282	iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
				2283	iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
				2284	iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
				2285	iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
				2286	iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
				2287	iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
				2288	iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
				2289	iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
				2290	iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
				2291	iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
				2292	iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
				2293	iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
				2294	iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
				2295	iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
				2296	qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
				2297
				2298	/* RQ1 Array registers. */
				2299	iter_reg = fw->rq1_array_reg;
				2300	iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
				2301	iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
				2302	iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
				2303	iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
				2304	iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
				2305	iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
				2306	iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
				2307	iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
				2308	iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
				2309	iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
				2310	iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
				2311	iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
				2312	iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
				2313	iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
				2314	iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
				2315	qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
				2316
				2317	/* RP0 Array registers. */
				2318	iter_reg = fw->rp0_array_reg;
				2319	iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
				2320	iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
				2321	iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
				2322	iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
				2323	iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
				2324	iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
				2325	iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
				2326	iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
				2327	iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
				2328	iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
				2329	iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
				2330	iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
				2331	iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
				2332	iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
				2333	iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
				2334	qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
				2335
				2336	/* RP1 Array registers. */
				2337	iter_reg = fw->rp1_array_reg;
				2338	iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
				2339	iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
				2340	iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
				2341	iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
				2342	iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
				2343	iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
				2344	iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
				2345	iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
				2346	iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
				2347	iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
				2348	iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
				2349	iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
				2350	iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
				2351	iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
				2352	iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
				2353	qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
				2354
				2355	iter_reg = fw->at0_array_reg;
				2356	iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
				2357	iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
				2358	iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
				2359	iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
				2360	iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
				2361	iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
				2362	iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
				2363	qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
				2364
				2365	/* I/O Queue Control registers. */
				2366	qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
				2367
				2368	/* Frame Buffer registers. */
				2369	iter_reg = fw->fb_hdw_reg;
				2370	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				2371	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				2372	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				2373	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				2374	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				2375	iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
				2376	iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
				2377	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				2378	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				2379	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				2380	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				2381	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				2382	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				2383	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				2384	iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
				2385	iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
				2386	iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
				2387	iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
				2388	iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
				2389	iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
				2390	iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
				2391	iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
				2392	iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
				2393	iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
				2394	iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
				2395	iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
				2396	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				2397
				2398	/* Multi queue registers */
				2399	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				2400	&last_chain);
				2401
				2402	rval = qla24xx_soft_reset(ha);
				2403	if (rval != QLA_SUCCESS) {
				2404	ql_log(ql_log_warn, vha, 0xd00e,
				2405	"SOFT RESET FAILED, forcing continuation of dump!!!\n");
				2406	rval = QLA_SUCCESS;
				2407
				2408	ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
				2409
				2410	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
				2411	RD_REG_DWORD(&reg->hccr);
				2412
				2413	WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
				2414	RD_REG_DWORD(&reg->hccr);
				2415
				2416	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				2417	RD_REG_DWORD(&reg->hccr);
				2418
				2419	for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
				2420	udelay(5);
				2421
				2422	if (!cnt) {
				2423	nxt = fw->code_ram;
Saurav Kashyap	8c0bc70	2012-11-21 02:40:35 -0500	[diff] [blame]	2424	nxt += sizeof(fw->code_ram);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2425	nxt += (ha->fw_memory_size - 0x100000 + 1);
				2426	goto copy_queue;
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	2427	} else {
				2428	set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2429	ql_log(ql_log_warn, vha, 0xd010,
				2430	"bigger hammer success?\n");
Hiral Patel	61f098d	2014-04-11 16:54:21 -0400	[diff] [blame]	2431	}
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2432	}
				2433
				2434	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				2435	&nxt);
				2436	if (rval != QLA_SUCCESS)
				2437	goto qla83xx_fw_dump_failed_0;
				2438
				2439	copy_queue:
				2440	nxt = qla2xxx_copy_queues(ha, nxt);
				2441
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	2442	qla24xx_copy_eft(ha, nxt);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2443
				2444	/* Chain entries -- started with MQ. */
				2445	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				2446	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	2447	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2448	if (last_chain) {
Bart Van Assche	ad95036	2015-07-09 07:24:08 -0700	[diff] [blame]	2449	ha->fw_dump->version \|= htonl(DUMP_CHAIN_VARIANT);
				2450	*last_chain \|= htonl(DUMP_CHAIN_LAST);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2451	}
				2452
				2453	/* Adjust valid length. */
				2454	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				2455
				2456	qla83xx_fw_dump_failed_0:
				2457	qla2xxx_dump_post_process(base_vha, rval);
				2458
				2459	qla83xx_fw_dump_failed:
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	2460	#ifndef __CHECKER__
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2461	if (!hardware_locked)
				2462	spin_unlock_irqrestore(&ha->hardware_lock, flags);
Bart Van Assche	8d16366	2015-07-09 07:25:46 -0700	[diff] [blame]	2463	#else
				2464	;
				2465	#endif
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2466	}
				2467
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	2468	/****************************************************************************/
				2469	/* Driver Debug Functions. */
				2470	/****************************************************************************/
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2471
				2472	static inline int
				2473	ql_mask_match(uint32_t level)
				2474	{
				2475	if (ql2xextended_error_logging == 1)
				2476	ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
				2477	return (level & ql2xextended_error_logging) == level;
				2478	}
				2479
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2480	/*
				2481	* This function is for formatting and logging debug information.
				2482	* It is to be used when vha is available. It formats the message
				2483	* and logs it to the messages file.
				2484	* parameters:
				2485	* level: The level of the debug messages to be printed.
				2486	* If ql2xextended_error_logging value is correctly set,
				2487	* this message will appear in the messages file.
				2488	* vha: Pointer to the scsi_qla_host_t.
				2489	* id: This is a unique identifier for the level. It identifies the
				2490	* part of the code from where the message originated.
				2491	* msg: The message to be displayed.
				2492	*/
				2493	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2494	ql_dbg(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2495	{
				2496	va_list va;
				2497	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2498
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2499	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2500	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2501
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2502	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2503
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2504	vaf.fmt = fmt;
				2505	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2506
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2507	if (vha != NULL) {
				2508	const struct pci_dev *pdev = vha->hw->pdev;
				2509	/* <module-name> <pci-name> <msg-id>:<host> Message */
				2510	pr_warn("%s [%s]-%04x:%ld: %pV",
				2511	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
				2512	vha->host_no, &vaf);
				2513	} else {
				2514	pr_warn("%s [%s]-%04x: : %pV",
				2515	QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2516	}
				2517
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2518	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2519
				2520	}
				2521
				2522	/*
				2523	* This function is for formatting and logging debug information.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2524	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2525	* i.e., before host allocation. It formats the message and logs it
				2526	* to the messages file.
				2527	* parameters:
				2528	* level: The level of the debug messages to be printed.
				2529	* If ql2xextended_error_logging value is correctly set,
				2530	* this message will appear in the messages file.
				2531	* pdev: Pointer to the struct pci_dev.
				2532	* id: This is a unique id for the level. It identifies the part
				2533	* of the code from where the message originated.
				2534	* msg: The message to be displayed.
				2535	*/
				2536	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2537	ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2538	const char *fmt, ...)
				2539	{
				2540	va_list va;
				2541	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2542
				2543	if (pdev == NULL)
				2544	return;
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2545	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2546	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2547
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2548	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2549
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2550	vaf.fmt = fmt;
				2551	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2552
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2553	/* <module-name> <dev-name>:<msg-id> Message */
				2554	pr_warn("%s [%s]-%04x: : %pV",
				2555	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2556
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2557	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2558	}
				2559
				2560	/*
				2561	* This function is for formatting and logging log messages.
				2562	* It is to be used when vha is available. It formats the message
				2563	* and logs it to the messages file. All the messages will be logged
				2564	* irrespective of value of ql2xextended_error_logging.
				2565	* parameters:
				2566	* level: The level of the log messages to be printed in the
				2567	* messages file.
				2568	* vha: Pointer to the scsi_qla_host_t
				2569	* id: This is a unique id for the level. It identifies the
				2570	* part of the code from where the message originated.
				2571	* msg: The message to be displayed.
				2572	*/
				2573	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2574	ql_log(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2575	{
				2576	va_list va;
				2577	struct va_format vaf;
				2578	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2579
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2580	if (level > ql_errlev)
				2581	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2582
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2583	if (vha != NULL) {
				2584	const struct pci_dev *pdev = vha->hw->pdev;
				2585	/* <module-name> <msg-id>:<host> Message */
				2586	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
				2587	QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
				2588	} else {
				2589	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2590	QL_MSGHDR, "0000:00:00.0", id);
				2591	}
				2592	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2593
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2594	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2595
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2596	vaf.fmt = fmt;
				2597	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2598
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2599	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2600	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2601	pr_crit("%s%pV", pbuf, &vaf);
				2602	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2603	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2604	pr_err("%s%pV", pbuf, &vaf);
				2605	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2606	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2607	pr_warn("%s%pV", pbuf, &vaf);
				2608	break;
				2609	default:
				2610	pr_info("%s%pV", pbuf, &vaf);
				2611	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2612	}
				2613
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2614	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2615	}
				2616
				2617	/*
				2618	* This function is for formatting and logging log messages.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2619	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2620	* i.e., before host allocation. It formats the message and logs
				2621	* it to the messages file. All the messages are logged irrespective
				2622	* of the value of ql2xextended_error_logging.
				2623	* parameters:
				2624	* level: The level of the log messages to be printed in the
				2625	* messages file.
				2626	* pdev: Pointer to the struct pci_dev.
				2627	* id: This is a unique id for the level. It identifies the
				2628	* part of the code from where the message originated.
				2629	* msg: The message to be displayed.
				2630	*/
				2631	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2632	ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2633	const char *fmt, ...)
				2634	{
				2635	va_list va;
				2636	struct va_format vaf;
				2637	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2638
				2639	if (pdev == NULL)
				2640	return;
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2641	if (level > ql_errlev)
				2642	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2643
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2644	/* <module-name> <dev-name>:<msg-id> Message */
				2645	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2646	QL_MSGHDR, dev_name(&(pdev->dev)), id);
				2647	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2648
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2649	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2650
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2651	vaf.fmt = fmt;
				2652	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2653
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2654	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2655	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2656	pr_crit("%s%pV", pbuf, &vaf);
				2657	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2658	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2659	pr_err("%s%pV", pbuf, &vaf);
				2660	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2661	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2662	pr_warn("%s%pV", pbuf, &vaf);
				2663	break;
				2664	default:
				2665	pr_info("%s%pV", pbuf, &vaf);
				2666	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2667	}
				2668
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2669	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2670	}
				2671
				2672	void
				2673	ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
				2674	{
				2675	int i;
				2676	struct qla_hw_data *ha = vha->hw;
				2677	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				2678	struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
				2679	struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
				2680	uint16_t __iomem *mbx_reg;
				2681
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2682	if (!ql_mask_match(level))
				2683	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2684
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	2685	if (IS_P3P_TYPE(ha))
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2686	mbx_reg = &reg82->mailbox_in[0];
				2687	else if (IS_FWI2_CAPABLE(ha))
				2688	mbx_reg = &reg24->mailbox0;
				2689	else
				2690	mbx_reg = MAILBOX_REG(ha, reg, 0);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2691
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2692	ql_dbg(level, vha, id, "Mailbox registers:\n");
				2693	for (i = 0; i < 6; i++)
				2694	ql_dbg(level, vha, id,
				2695	"mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2696	}
				2697
				2698
				2699	void
				2700	ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
				2701	uint8_t *b, uint32_t size)
				2702	{
				2703	uint32_t cnt;
				2704	uint8_t c;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2705
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2706	if (!ql_mask_match(level))
				2707	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2708
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2709	ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
				2710	"9 Ah Bh Ch Dh Eh Fh\n");
				2711	ql_dbg(level, vha, id, "----------------------------------"
				2712	"----------------------------\n");
				2713
				2714	ql_dbg(level, vha, id, " ");
				2715	for (cnt = 0; cnt < size;) {
				2716	c = *b++;
				2717	printk("%02x", (uint32_t) c);
				2718	cnt++;
				2719	if (!(cnt % 16))
				2720	printk("\n");
				2721	else
				2722	printk(" ");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2723	}
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2724	if (cnt % 16)
				2725	ql_dbg(level, vha, id, "\n");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2726	}