Blame - drivers/scsi/qla2xxx/qla_dbg.c - SHIFTPHONES/kernel/shift/mainline

blob: 66f6597d857b03244b4989847bdd88c1bac6640d [file] [log] [blame]

Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	1	/*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	2	* QLogic Fibre Channel HBA Driver
Saurav Kashyap	1e63395	2013-02-08 01:57:54 -0500	[diff] [blame]	3	* Copyright (c) 2003-2013 QLogic Corporation
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	4	*
Andrew Vasquez	fa90c54	2005-10-27 11:10:08 -0700	[diff] [blame]	5	* See LICENSE.qla2xxx for copyright and licensing details.
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	6	*/
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	7
				8	/*
				9	* Table for showing the current message id in use for particular level
				10	* Change this table for addition of log/debug messages.
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	11	* ----------------------------------------------------------------------
				12	* \| Level \| Last Value Used \| Holes \|
				13	* ----------------------------------------------------------------------
Chad Dupuis	f3ddac1	2013-10-30 03:38:16 -0400	[diff] [blame]	14	* \| Module Init and Probe \| 0x015b \| 0x4b,0xba,0xfa \|
Joe Carnuccio	c46e65c	2013-08-27 01:37:35 -0400	[diff] [blame]	15	* \| Mailbox commands \| 0x1181 \| 0x111a-0x111b \|
Joe Carnuccio	e9f4f41	2013-03-25 02:21:36 -0400	[diff] [blame]	16	* \| \| \| 0x1155-0x1158 \|
Joe Carnuccio	1ae47cf	2013-08-27 01:37:36 -0400	[diff] [blame]	17	* \| \| \| 0x1018-0x1019 \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	18	* \| \| \| 0x1115-0x1116 \|
Joe Carnuccio	1ae47cf	2013-08-27 01:37:36 -0400	[diff] [blame]	19	* \| \| \| 0x10ca \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	20	* \| Device Discovery \| 0x2095 \| 0x2020-0x2022, \|
Bart Van Assche	6593d5b	2013-06-25 11:27:24 -0400	[diff] [blame]	21	* \| \| \| 0x2011-0x2012, \|
Saurav Kashyap	2a8593f	2012-08-22 14:21:27 -0400	[diff] [blame]	22	* \| \| \| 0x2016 \|
Chad Dupuis	36008cf	2013-10-03 03:21:13 -0400	[diff] [blame]	23	* \| Queue Command and IO tracing \| 0x3059 \| 0x3006-0x300b \|
Arun Easi	9e522cd	2012-08-22 14:21:31 -0400	[diff] [blame]	24	* \| \| \| 0x3027-0x3028 \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	25	* \| \| \| 0x303d-0x3041 \|
				26	* \| \| \| 0x302d,0x3033 \|
				27	* \| \| \| 0x3036,0x3038 \|
				28	* \| \| \| 0x303a \|
Armen Baloyan	e8f5e95	2013-10-30 03:38:17 -0400	[diff] [blame^]	29	* \| DPC Thread \| 0x4023 \| 0x4002,0x4013 \|
Santosh Vernekar	454073c	2013-08-27 01:37:48 -0400	[diff] [blame]	30	* \| Async Events \| 0x5087 \| 0x502b-0x502f \|
Giridhar Malavali	9ba56b9	2012-02-09 11:15:36 -0800	[diff] [blame]	31	* \| \| \| 0x5047,0x5052 \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	32	* \| \| \| 0x5084,0x5075 \|
Chad Dupuis	a78951b	2013-08-27 01:37:34 -0400	[diff] [blame]	33	* \| \| \| 0x503d,0x5044 \|
Armen Baloyan	71e5600	2013-08-27 01:37:38 -0400	[diff] [blame]	34	* \| Timer Routines \| 0x6012 \| \|
Sawan Chandak	8c2cf7d	2013-08-27 01:37:51 -0400	[diff] [blame]	35	* \| User Space Interactions \| 0x70e1 \| 0x7018,0x702e, \|
Saurav Kashyap	78d56df	2013-01-30 03:34:42 -0500	[diff] [blame]	36	* \| \| \| 0x7020,0x7024, \|
Joe Carnuccio	733a95b	2012-02-09 11:15:55 -0800	[diff] [blame]	37	* \| \| \| 0x7039,0x7045, \|
				38	* \| \| \| 0x7073-0x7075, \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	39	* \| \| \| 0x707b,0x708c, \|
Saurav Kashyap	a9b6f72	2012-08-22 14:21:01 -0400	[diff] [blame]	40	* \| \| \| 0x70a5,0x70a6, \|
				41	* \| \| \| 0x70a8,0x70ab, \|
Giridhar Malavali	8ae6d9c	2013-03-28 08:21:23 -0400	[diff] [blame]	42	* \| \| \| 0x70ad-0x70ae, \|
Joe Carnuccio	1ae47cf	2013-08-27 01:37:36 -0400	[diff] [blame]	43	* \| \| \| 0x70d1-0x70db, \|
Bart Van Assche	a44c72f	2013-06-25 11:27:23 -0400	[diff] [blame]	44	* \| \| \| 0x7047,0x703b \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	45	* \| \| \| 0x70de-0x70df, \|
Armen Baloyan	5854771	2013-08-27 01:37:33 -0400	[diff] [blame]	46	* \| Task Management \| 0x803d \| 0x8025-0x8026 \|
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	47	* \| \| \| 0x800b,0x8039 \|
Saurav Kashyap	5f28d2d	2012-05-15 14:34:15 -0400	[diff] [blame]	48	* \| AER/EEH \| 0x9011 \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	49	* \| Virtual Port \| 0xa007 \| \|
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	50	* \| ISP82XX Specific \| 0xb14c \| 0xb002,0xb024 \|
				51	* \| \| \| 0xb09e,0xb0ae \|
				52	* \| \| \| 0xb0e0-0xb0ef \|
				53	* \| \| \| 0xb085,0xb0dc \|
				54	* \| \| \| 0xb107,0xb108 \|
				55	* \| \| \| 0xb111,0xb11e \|
				56	* \| \| \| 0xb12c,0xb12d \|
				57	* \| \| \| 0xb13a,0xb142 \|
				58	* \| \| \| 0xb13c-0xb140 \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	59	* \| \| \| 0xb149 \|
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	60	* \| MultiQ \| 0xc00c \| \|
				61	* \| Misc \| 0xd010 \| \|
Saurav Kashyap	6ddcfef	2013-08-27 01:37:53 -0400	[diff] [blame]	62	* \| Target Mode \| 0xe070 \| 0xe021 \|
				63	* \| Target Mode Management \| 0xf072 \| 0xf002-0xf003 \|
				64	* \| \| \| 0xf046-0xf049 \|
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	65	* \| Target Mode Task Management \| 0x1000b \| \|
Arun Easi	e02587d	2011-08-16 11:29:23 -0700	[diff] [blame]	66	* ----------------------------------------------------------------------
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	67	*/
				68
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	69	#include "qla_def.h"
				70
				71	#include <linux/delay.h>
				72
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	73	static uint32_t ql_dbg_offset = 0x800;
				74
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	75	static inline void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	76	qla2xxx_prep_dump(struct qla_hw_data ha, struct qla2xxx_fw_dump fw_dump)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	77	{
				78	fw_dump->fw_major_version = htonl(ha->fw_major_version);
				79	fw_dump->fw_minor_version = htonl(ha->fw_minor_version);
				80	fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version);
				81	fw_dump->fw_attributes = htonl(ha->fw_attributes);
				82
				83	fw_dump->vendor = htonl(ha->pdev->vendor);
				84	fw_dump->device = htonl(ha->pdev->device);
				85	fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor);
				86	fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device);
				87	}
				88
				89	static inline void *
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	90	qla2xxx_copy_queues(struct qla_hw_data ha, void ptr)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	91	{
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	92	struct req_que *req = ha->req_q_map[0];
				93	struct rsp_que *rsp = ha->rsp_q_map[0];
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	94	/* Request queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	95	memcpy(ptr, req->ring, req->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	96	sizeof(request_t));
				97
				98	/* Response queue. */
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	99	ptr += req->length * sizeof(request_t);
				100	memcpy(ptr, rsp->ring, rsp->length *
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	101	sizeof(response_t));
				102
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	103	return ptr + (rsp->length * sizeof(response_t));
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	104	}
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	105
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	106	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	107	qla24xx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint32_t ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	108	uint32_t ram_dwords, void **nxt)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	109	{
				110	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	111	uint32_t cnt, stat, timer, dwords, idx;
				112	uint16_t mb0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	113	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	114	dma_addr_t dump_dma = ha->gid_list_dma;
				115	uint32_t dump = (uint32_t )ha->gid_list;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	116
				117	rval = QLA_SUCCESS;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	118	mb0 = 0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	119
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	120	WRT_REG_WORD(&reg->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	121	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				122
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	123	dwords = qla2x00_gid_list_size(ha) / 4;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	124	for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS;
				125	cnt += dwords, addr += dwords) {
				126	if (cnt + dwords > ram_dwords)
				127	dwords = ram_dwords - cnt;
				128
				129	WRT_REG_WORD(&reg->mailbox1, LSW(addr));
				130	WRT_REG_WORD(&reg->mailbox8, MSW(addr));
				131
				132	WRT_REG_WORD(&reg->mailbox2, MSW(dump_dma));
				133	WRT_REG_WORD(&reg->mailbox3, LSW(dump_dma));
				134	WRT_REG_WORD(&reg->mailbox6, MSW(MSD(dump_dma)));
				135	WRT_REG_WORD(&reg->mailbox7, LSW(MSD(dump_dma)));
				136
				137	WRT_REG_WORD(&reg->mailbox4, MSW(dwords));
				138	WRT_REG_WORD(&reg->mailbox5, LSW(dwords));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	139	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
				140
				141	for (timer = 6000000; timer; timer--) {
				142	/* Check for pending interrupts. */
				143	stat = RD_REG_DWORD(&reg->host_status);
				144	if (stat & HSRX_RISC_INT) {
				145	stat &= 0xff;
				146
				147	if (stat == 0x1 \|\| stat == 0x2 \|\|
				148	stat == 0x10 \|\| stat == 0x11) {
				149	set_bit(MBX_INTERRUPT,
				150	&ha->mbx_cmd_flags);
				151
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	152	mb0 = RD_REG_WORD(&reg->mailbox0);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	153
				154	WRT_REG_DWORD(&reg->hccr,
				155	HCCRX_CLR_RISC_INT);
				156	RD_REG_DWORD(&reg->hccr);
				157	break;
				158	}
				159
				160	/* Clear this intr; it wasn't a mailbox intr */
				161	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
				162	RD_REG_DWORD(&reg->hccr);
				163	}
				164	udelay(5);
				165	}
				166
				167	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	168	rval = mb0 & MBS_MASK;
				169	for (idx = 0; idx < dwords; idx++)
				170	ram[cnt + idx] = swab32(dump[idx]);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	171	} else {
				172	rval = QLA_FUNCTION_FAILED;
				173	}
				174	}
				175
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	176	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	177	return rval;
				178	}
				179
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	180	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	181	qla24xx_dump_memory(struct qla_hw_data ha, uint32_t code_ram,
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	182	uint32_t cram_size, void **nxt)
				183	{
				184	int rval;
				185
				186	/* Code RAM. */
				187	rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt);
				188	if (rval != QLA_SUCCESS)
				189	return rval;
				190
				191	/* External Memory. */
				192	return qla24xx_dump_ram(ha, 0x100000, *nxt,
				193	ha->fw_memory_size - 0x100000 + 1, nxt);
				194	}
				195
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	196	static uint32_t *
				197	qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase,
				198	uint32_t count, uint32_t *buf)
				199	{
				200	uint32_t __iomem *dmp_reg;
				201
				202	WRT_REG_DWORD(&reg->iobase_addr, iobase);
				203	dmp_reg = &reg->iobase_window;
				204	while (count--)
				205	*buf++ = htonl(RD_REG_DWORD(dmp_reg++));
				206
				207	return buf;
				208	}
				209
				210	static inline int
				211	qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
				212	{
				213	int rval = QLA_SUCCESS;
				214	uint32_t cnt;
				215
Andrew Vasquez	c3b058a	2007-09-20 14:07:38 -0700	[diff] [blame]	216	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
Andrew Vasquez	aed1088	2009-06-03 09:55:26 -0700	[diff] [blame]	217	for (cnt = 30000;
				218	((RD_REG_DWORD(&reg->host_status) & HSRX_RISC_PAUSED) == 0) &&
Andrew Vasquez	c3b058a	2007-09-20 14:07:38 -0700	[diff] [blame]	219	rval == QLA_SUCCESS; cnt--) {
				220	if (cnt)
				221	udelay(100);
				222	else
				223	rval = QLA_FUNCTION_TIMEOUT;
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	224	}
				225
				226	return rval;
				227	}
				228
				229	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	230	qla24xx_soft_reset(struct qla_hw_data *ha)
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	231	{
				232	int rval = QLA_SUCCESS;
				233	uint32_t cnt;
				234	uint16_t mb0, wd;
				235	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				236
				237	/* Reset RISC. */
				238	WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				239	for (cnt = 0; cnt < 30000; cnt++) {
				240	if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
				241	break;
				242
				243	udelay(10);
				244	}
				245
				246	WRT_REG_DWORD(&reg->ctrl_status,
				247	CSRX_ISP_SOFT_RESET\|CSRX_DMA_SHUTDOWN\|MWB_4096_BYTES);
				248	pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
				249
				250	udelay(100);
				251	/* Wait for firmware to complete NVRAM accesses. */
				252	mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
				253	for (cnt = 10000 ; cnt && mb0; cnt--) {
				254	udelay(5);
				255	mb0 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
				256	barrier();
				257	}
				258
				259	/* Wait for soft-reset to complete. */
				260	for (cnt = 0; cnt < 30000; cnt++) {
				261	if ((RD_REG_DWORD(&reg->ctrl_status) &
				262	CSRX_ISP_SOFT_RESET) == 0)
				263	break;
				264
				265	udelay(10);
				266	}
				267	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				268	RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
				269
				270	for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
				271	rval == QLA_SUCCESS; cnt--) {
				272	if (cnt)
				273	udelay(100);
				274	else
				275	rval = QLA_FUNCTION_TIMEOUT;
				276	}
				277
				278	return rval;
				279	}
				280
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	281	static int
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	282	qla2xxx_dump_ram(struct qla_hw_data ha, uint32_t addr, uint16_t ram,
Andrew Vasquez	e18e963	2009-06-17 10:30:31 -0700	[diff] [blame]	283	uint32_t ram_words, void **nxt)
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	284	{
				285	int rval;
				286	uint32_t cnt, stat, timer, words, idx;
				287	uint16_t mb0;
				288	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				289	dma_addr_t dump_dma = ha->gid_list_dma;
				290	uint16_t dump = (uint16_t )ha->gid_list;
				291
				292	rval = QLA_SUCCESS;
				293	mb0 = 0;
				294
				295	WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED);
				296	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				297
Chad Dupuis	642ef98	2012-02-09 11:15:57 -0800	[diff] [blame]	298	words = qla2x00_gid_list_size(ha) / 2;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	299	for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS;
				300	cnt += words, addr += words) {
				301	if (cnt + words > ram_words)
				302	words = ram_words - cnt;
				303
				304	WRT_MAILBOX_REG(ha, reg, 1, LSW(addr));
				305	WRT_MAILBOX_REG(ha, reg, 8, MSW(addr));
				306
				307	WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma));
				308	WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma));
				309	WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma)));
				310	WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma)));
				311
				312	WRT_MAILBOX_REG(ha, reg, 4, words);
				313	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				314
				315	for (timer = 6000000; timer; timer--) {
				316	/* Check for pending interrupts. */
				317	stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
				318	if (stat & HSR_RISC_INT) {
				319	stat &= 0xff;
				320
				321	if (stat == 0x1 \|\| stat == 0x2) {
				322	set_bit(MBX_INTERRUPT,
				323	&ha->mbx_cmd_flags);
				324
				325	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				326
				327	/* Release mailbox registers. */
				328	WRT_REG_WORD(&reg->semaphore, 0);
				329	WRT_REG_WORD(&reg->hccr,
				330	HCCR_CLR_RISC_INT);
				331	RD_REG_WORD(&reg->hccr);
				332	break;
				333	} else if (stat == 0x10 \|\| stat == 0x11) {
				334	set_bit(MBX_INTERRUPT,
				335	&ha->mbx_cmd_flags);
				336
				337	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				338
				339	WRT_REG_WORD(&reg->hccr,
				340	HCCR_CLR_RISC_INT);
				341	RD_REG_WORD(&reg->hccr);
				342	break;
				343	}
				344
				345	/* clear this intr; it wasn't a mailbox intr */
				346	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				347	RD_REG_WORD(&reg->hccr);
				348	}
				349	udelay(5);
				350	}
				351
				352	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				353	rval = mb0 & MBS_MASK;
				354	for (idx = 0; idx < words; idx++)
				355	ram[cnt + idx] = swab16(dump[idx]);
				356	} else {
				357	rval = QLA_FUNCTION_FAILED;
				358	}
				359	}
				360
				361	*nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL;
				362	return rval;
				363	}
				364
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	365	static inline void
				366	qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count,
				367	uint16_t *buf)
				368	{
				369	uint16_t __iomem *dmp_reg = &reg->u.isp2300.fb_cmd;
				370
				371	while (count--)
				372	*buf++ = htons(RD_REG_WORD(dmp_reg++));
				373	}
				374
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	375	static inline void *
				376	qla24xx_copy_eft(struct qla_hw_data ha, void ptr)
				377	{
				378	if (!ha->eft)
				379	return ptr;
				380
				381	memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size));
				382	return ptr + ntohl(ha->fw_dump->eft_size);
				383	}
				384
				385	static inline void *
				386	qla25xx_copy_fce(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				387	{
				388	uint32_t cnt;
				389	uint32_t *iter_reg;
				390	struct qla2xxx_fce_chain *fcec = ptr;
				391
				392	if (!ha->fce)
				393	return ptr;
				394
				395	*last_chain = &fcec->type;
				396	fcec->type = __constant_htonl(DUMP_CHAIN_FCE);
				397	fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) +
				398	fce_calc_size(ha->fce_bufs));
				399	fcec->size = htonl(fce_calc_size(ha->fce_bufs));
				400	fcec->addr_l = htonl(LSD(ha->fce_dma));
				401	fcec->addr_h = htonl(MSD(ha->fce_dma));
				402
				403	iter_reg = fcec->eregs;
				404	for (cnt = 0; cnt < 8; cnt++)
				405	*iter_reg++ = htonl(ha->fce_mb[cnt]);
				406
				407	memcpy(iter_reg, ha->fce, ntohl(fcec->size));
				408
Giridhar Malavali	3cb0a67	2011-11-18 09:03:11 -0800	[diff] [blame]	409	return (char *)iter_reg + ntohl(fcec->size);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	410	}
				411
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	412	static inline void *
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	413	qla2xxx_copy_atioqueues(struct qla_hw_data ha, void ptr,
				414	uint32_t **last_chain)
				415	{
				416	struct qla2xxx_mqueue_chain *q;
				417	struct qla2xxx_mqueue_header *qh;
				418	uint32_t num_queues;
				419	int que;
				420	struct {
				421	int length;
				422	void *ring;
				423	} aq, *aqp;
				424
Arun Easi	00876ae	2013-03-25 02:21:37 -0400	[diff] [blame]	425	if (!ha->tgt.atio_ring)
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	426	return ptr;
				427
				428	num_queues = 1;
				429	aqp = &aq;
				430	aqp->length = ha->tgt.atio_q_length;
				431	aqp->ring = ha->tgt.atio_ring;
				432
				433	for (que = 0; que < num_queues; que++) {
				434	/* aqp = ha->atio_q_map[que]; */
				435	q = ptr;
				436	*last_chain = &q->type;
				437	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				438	q->chain_size = htonl(
				439	sizeof(struct qla2xxx_mqueue_chain) +
				440	sizeof(struct qla2xxx_mqueue_header) +
				441	(aqp->length * sizeof(request_t)));
				442	ptr += sizeof(struct qla2xxx_mqueue_chain);
				443
				444	/* Add header. */
				445	qh = ptr;
				446	qh->queue = __constant_htonl(TYPE_ATIO_QUEUE);
				447	qh->number = htonl(que);
				448	qh->size = htonl(aqp->length * sizeof(request_t));
				449	ptr += sizeof(struct qla2xxx_mqueue_header);
				450
				451	/* Add data. */
				452	memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t));
				453
				454	ptr += aqp->length * sizeof(request_t);
				455	}
				456
				457	return ptr;
				458	}
				459
				460	static inline void *
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	461	qla25xx_copy_mqueues(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				462	{
				463	struct qla2xxx_mqueue_chain *q;
				464	struct qla2xxx_mqueue_header *qh;
				465	struct req_que *req;
				466	struct rsp_que *rsp;
				467	int que;
				468
				469	if (!ha->mqenable)
				470	return ptr;
				471
				472	/* Request queues */
				473	for (que = 1; que < ha->max_req_queues; que++) {
				474	req = ha->req_q_map[que];
				475	if (!req)
				476	break;
				477
				478	/* Add chain. */
				479	q = ptr;
				480	*last_chain = &q->type;
				481	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				482	q->chain_size = htonl(
				483	sizeof(struct qla2xxx_mqueue_chain) +
				484	sizeof(struct qla2xxx_mqueue_header) +
				485	(req->length * sizeof(request_t)));
				486	ptr += sizeof(struct qla2xxx_mqueue_chain);
				487
				488	/* Add header. */
				489	qh = ptr;
				490	qh->queue = __constant_htonl(TYPE_REQUEST_QUEUE);
				491	qh->number = htonl(que);
				492	qh->size = htonl(req->length * sizeof(request_t));
				493	ptr += sizeof(struct qla2xxx_mqueue_header);
				494
				495	/* Add data. */
				496	memcpy(ptr, req->ring, req->length * sizeof(request_t));
				497	ptr += req->length * sizeof(request_t);
				498	}
				499
				500	/* Response queues */
				501	for (que = 1; que < ha->max_rsp_queues; que++) {
				502	rsp = ha->rsp_q_map[que];
				503	if (!rsp)
				504	break;
				505
				506	/* Add chain. */
				507	q = ptr;
				508	*last_chain = &q->type;
				509	q->type = __constant_htonl(DUMP_CHAIN_QUEUE);
				510	q->chain_size = htonl(
				511	sizeof(struct qla2xxx_mqueue_chain) +
				512	sizeof(struct qla2xxx_mqueue_header) +
				513	(rsp->length * sizeof(response_t)));
				514	ptr += sizeof(struct qla2xxx_mqueue_chain);
				515
				516	/* Add header. */
				517	qh = ptr;
				518	qh->queue = __constant_htonl(TYPE_RESPONSE_QUEUE);
				519	qh->number = htonl(que);
				520	qh->size = htonl(rsp->length * sizeof(response_t));
				521	ptr += sizeof(struct qla2xxx_mqueue_header);
				522
				523	/* Add data. */
				524	memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t));
				525	ptr += rsp->length * sizeof(response_t);
				526	}
				527
				528	return ptr;
				529	}
				530
				531	static inline void *
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	532	qla25xx_copy_mq(struct qla_hw_data ha, void ptr, uint32_t **last_chain)
				533	{
				534	uint32_t cnt, que_idx;
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	535	uint8_t que_cnt;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	536	struct qla2xxx_mq_chain *mq = ptr;
Andrew Vasquez	da9b1d5	2013-08-27 01:37:30 -0400	[diff] [blame]	537	device_reg_t __iomem *reg;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	538
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	539	if (!ha->mqenable \|\| IS_QLA83XX(ha))
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	540	return ptr;
				541
				542	mq = ptr;
				543	*last_chain = &mq->type;
				544	mq->type = __constant_htonl(DUMP_CHAIN_MQ);
				545	mq->chain_size = __constant_htonl(sizeof(struct qla2xxx_mq_chain));
				546
Anirban Chakraborty	2afa19a	2009-04-06 22:33:40 -0700	[diff] [blame]	547	que_cnt = ha->max_req_queues > ha->max_rsp_queues ?
				548	ha->max_req_queues : ha->max_rsp_queues;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	549	mq->count = htonl(que_cnt);
				550	for (cnt = 0; cnt < que_cnt; cnt++) {
Andrew Vasquez	da9b1d5	2013-08-27 01:37:30 -0400	[diff] [blame]	551	reg = ISP_QUE_REG(ha, cnt);
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	552	que_idx = cnt * 4;
Andrew Vasquez	da9b1d5	2013-08-27 01:37:30 -0400	[diff] [blame]	553	mq->qregs[que_idx] =
				554	htonl(RD_REG_DWORD(&reg->isp25mq.req_q_in));
				555	mq->qregs[que_idx+1] =
				556	htonl(RD_REG_DWORD(&reg->isp25mq.req_q_out));
				557	mq->qregs[que_idx+2] =
				558	htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_in));
				559	mq->qregs[que_idx+3] =
				560	htonl(RD_REG_DWORD(&reg->isp25mq.rsp_q_out));
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	561	}
				562
				563	return ptr + sizeof(struct qla2xxx_mq_chain);
				564	}
				565
Giridhar Malavali	08de284	2011-08-16 11:31:44 -0700	[diff] [blame]	566	void
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	567	qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval)
				568	{
				569	struct qla_hw_data *ha = vha->hw;
				570
				571	if (rval != QLA_SUCCESS) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	572	ql_log(ql_log_warn, vha, 0xd000,
				573	"Failed to dump firmware (%x).\n", rval);
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	574	ha->fw_dumped = 0;
				575	} else {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	576	ql_log(ql_log_info, vha, 0xd001,
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	577	"Firmware dump saved to temp buffer (%ld/%p).\n",
				578	vha->host_no, ha->fw_dump);
				579	ha->fw_dumped = 1;
				580	qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
				581	}
				582	}
				583
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	584	/**
				585	* qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
				586	* @ha: HA context
				587	* @hardware_locked: Called with the hardware_lock
				588	*/
				589	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	590	qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	591	{
				592	int rval;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	593	uint32_t cnt;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	594	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	595	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	596	uint16_t __iomem *dmp_reg;
				597	unsigned long flags;
				598	struct qla2300_fw_dump *fw;
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	599	void *nxt;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	600	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	601
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	602	flags = 0;
				603
				604	if (!hardware_locked)
				605	spin_lock_irqsave(&ha->hardware_lock, flags);
				606
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	607	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	608	ql_log(ql_log_warn, vha, 0xd002,
				609	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	610	goto qla2300_fw_dump_failed;
				611	}
				612
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	613	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	614	ql_log(ql_log_warn, vha, 0xd003,
				615	"Firmware has been previously dumped (%p) "
				616	"-- ignoring request.\n",
				617	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	618	goto qla2300_fw_dump_failed;
				619	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	620	fw = &ha->fw_dump->isp.isp23;
				621	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	622
				623	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	624	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	625
				626	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	627	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	628	if (IS_QLA2300(ha)) {
				629	for (cnt = 30000;
				630	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				631	rval == QLA_SUCCESS; cnt--) {
				632	if (cnt)
				633	udelay(100);
				634	else
				635	rval = QLA_FUNCTION_TIMEOUT;
				636	}
				637	} else {
				638	RD_REG_WORD(&reg->hccr); /* PCI Posting. */
				639	udelay(10);
				640	}
				641
				642	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	643	dmp_reg = &reg->flash_address;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	644	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	645	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	646
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	647	dmp_reg = &reg->u.isp2300.req_q_in;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	648	for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	649	fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	650
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	651	dmp_reg = &reg->u.isp2300.mailbox0;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	652	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	653	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	654
				655	WRT_REG_WORD(&reg->ctrl_status, 0x40);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	656	qla2xxx_read_window(reg, 32, fw->resp_dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	657
				658	WRT_REG_WORD(&reg->ctrl_status, 0x50);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	659	qla2xxx_read_window(reg, 48, fw->dma_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	660
				661	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	662	dmp_reg = &reg->risc_hw;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	663	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	664	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	665
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	666	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	667	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	668
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	669	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	670	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	671
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	672	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	673	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	674
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	675	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	676	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	677
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	678	WRT_REG_WORD(&reg->pcr, 0x2800);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	679	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	680
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	681	WRT_REG_WORD(&reg->pcr, 0x2A00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	682	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	683
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	684	WRT_REG_WORD(&reg->pcr, 0x2C00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	685	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	686
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	687	WRT_REG_WORD(&reg->pcr, 0x2E00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	688	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	689
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	690	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	691	qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	692
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	693	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	694	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	695
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	696	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	697	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	698
				699	/* Reset RISC. */
				700	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				701	for (cnt = 0; cnt < 30000; cnt++) {
				702	if ((RD_REG_WORD(&reg->ctrl_status) &
				703	CSR_ISP_SOFT_RESET) == 0)
				704	break;
				705
				706	udelay(10);
				707	}
				708	}
				709
				710	if (!IS_QLA2300(ha)) {
				711	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				712	rval == QLA_SUCCESS; cnt--) {
				713	if (cnt)
				714	udelay(100);
				715	else
				716	rval = QLA_FUNCTION_TIMEOUT;
				717	}
				718	}
				719
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	720	/* Get RISC SRAM. */
				721	if (rval == QLA_SUCCESS)
				722	rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram,
				723	sizeof(fw->risc_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	724
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	725	/* Get stack SRAM. */
				726	if (rval == QLA_SUCCESS)
				727	rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram,
				728	sizeof(fw->stack_ram) / 2, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	729
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	730	/* Get data SRAM. */
				731	if (rval == QLA_SUCCESS)
				732	rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram,
				733	ha->fw_memory_size - 0x11000 + 1, &nxt);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	734
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	735	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	736	qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	737
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	738	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	739
				740	qla2300_fw_dump_failed:
				741	if (!hardware_locked)
				742	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				743	}
				744
				745	/**
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	746	* qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
				747	* @ha: HA context
				748	* @hardware_locked: Called with the hardware_lock
				749	*/
				750	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	751	qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	752	{
				753	int rval;
				754	uint32_t cnt, timer;
				755	uint16_t risc_address;
				756	uint16_t mb0, mb2;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	757	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	3d71644	2005-07-06 10:30:26 -0700	[diff] [blame]	758	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	759	uint16_t __iomem *dmp_reg;
				760	unsigned long flags;
				761	struct qla2100_fw_dump *fw;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	762	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	763
				764	risc_address = 0;
				765	mb0 = mb2 = 0;
				766	flags = 0;
				767
				768	if (!hardware_locked)
				769	spin_lock_irqsave(&ha->hardware_lock, flags);
				770
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	771	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	772	ql_log(ql_log_warn, vha, 0xd004,
				773	"No buffer available for dump.\n");
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	774	goto qla2100_fw_dump_failed;
				775	}
				776
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	777	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	778	ql_log(ql_log_warn, vha, 0xd005,
				779	"Firmware has been previously dumped (%p) "
				780	"-- ignoring request.\n",
				781	ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	782	goto qla2100_fw_dump_failed;
				783	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	784	fw = &ha->fw_dump->isp.isp21;
				785	qla2xxx_prep_dump(ha, ha->fw_dump);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	786
				787	rval = QLA_SUCCESS;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	788	fw->hccr = htons(RD_REG_WORD(&reg->hccr));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	789
				790	/* Pause RISC. */
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	791	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	792	for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				793	rval == QLA_SUCCESS; cnt--) {
				794	if (cnt)
				795	udelay(100);
				796	else
				797	rval = QLA_FUNCTION_TIMEOUT;
				798	}
				799	if (rval == QLA_SUCCESS) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	800	dmp_reg = &reg->flash_address;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	801	for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	802	fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	803
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	804	dmp_reg = &reg->u.isp2100.mailbox0;
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	805	for (cnt = 0; cnt < ha->mbx_count; cnt++) {
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	806	if (cnt == 8)
				807	dmp_reg = &reg->u_end.isp2200.mailbox8;
				808
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	809	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	810	}
				811
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	812	dmp_reg = &reg->u.isp2100.unused_2[0];
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	813	for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	814	fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	815
				816	WRT_REG_WORD(&reg->ctrl_status, 0x00);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	817	dmp_reg = &reg->risc_hw;
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	818	for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	819	fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg++));
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	820
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	821	WRT_REG_WORD(&reg->pcr, 0x2000);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	822	qla2xxx_read_window(reg, 16, fw->risc_gp0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	823
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	824	WRT_REG_WORD(&reg->pcr, 0x2100);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	825	qla2xxx_read_window(reg, 16, fw->risc_gp1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	826
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	827	WRT_REG_WORD(&reg->pcr, 0x2200);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	828	qla2xxx_read_window(reg, 16, fw->risc_gp2_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	829
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	830	WRT_REG_WORD(&reg->pcr, 0x2300);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	831	qla2xxx_read_window(reg, 16, fw->risc_gp3_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	832
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	833	WRT_REG_WORD(&reg->pcr, 0x2400);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	834	qla2xxx_read_window(reg, 16, fw->risc_gp4_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	835
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	836	WRT_REG_WORD(&reg->pcr, 0x2500);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	837	qla2xxx_read_window(reg, 16, fw->risc_gp5_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	838
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	839	WRT_REG_WORD(&reg->pcr, 0x2600);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	840	qla2xxx_read_window(reg, 16, fw->risc_gp6_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	841
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	842	WRT_REG_WORD(&reg->pcr, 0x2700);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	843	qla2xxx_read_window(reg, 16, fw->risc_gp7_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	844
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	845	WRT_REG_WORD(&reg->ctrl_status, 0x10);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	846	qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	847
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	848	WRT_REG_WORD(&reg->ctrl_status, 0x20);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	849	qla2xxx_read_window(reg, 64, fw->fpm_b0_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	850
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	851	WRT_REG_WORD(&reg->ctrl_status, 0x30);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	852	qla2xxx_read_window(reg, 64, fw->fpm_b1_reg);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	853
				854	/* Reset the ISP. */
				855	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
				856	}
				857
				858	for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
				859	rval == QLA_SUCCESS; cnt--) {
				860	if (cnt)
				861	udelay(100);
				862	else
				863	rval = QLA_FUNCTION_TIMEOUT;
				864	}
				865
				866	/* Pause RISC. */
				867	if (rval == QLA_SUCCESS && (IS_QLA2200(ha) \|\| (IS_QLA2100(ha) &&
				868	(RD_REG_WORD(&reg->mctr) & (BIT_1 \| BIT_0)) != 0))) {
				869
Andrew Vasquez	fa2a1ce	2005-07-06 10:32:07 -0700	[diff] [blame]	870	WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	871	for (cnt = 30000;
				872	(RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
				873	rval == QLA_SUCCESS; cnt--) {
				874	if (cnt)
				875	udelay(100);
				876	else
				877	rval = QLA_FUNCTION_TIMEOUT;
				878	}
				879	if (rval == QLA_SUCCESS) {
				880	/* Set memory configuration and timing. */
				881	if (IS_QLA2100(ha))
				882	WRT_REG_WORD(&reg->mctr, 0xf1);
				883	else
				884	WRT_REG_WORD(&reg->mctr, 0xf2);
				885	RD_REG_WORD(&reg->mctr); /* PCI Posting. */
				886
				887	/* Release RISC. */
				888	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
				889	}
				890	}
				891
				892	if (rval == QLA_SUCCESS) {
				893	/* Get RISC SRAM. */
				894	risc_address = 0x1000;
				895	WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
				896	clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
				897	}
				898	for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
				899	cnt++, risc_address++) {
				900	WRT_MAILBOX_REG(ha, reg, 1, risc_address);
				901	WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
				902
				903	for (timer = 6000000; timer != 0; timer--) {
				904	/* Check for pending interrupts. */
				905	if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
				906	if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
				907	set_bit(MBX_INTERRUPT,
				908	&ha->mbx_cmd_flags);
				909
				910	mb0 = RD_MAILBOX_REG(ha, reg, 0);
				911	mb2 = RD_MAILBOX_REG(ha, reg, 2);
				912
				913	WRT_REG_WORD(&reg->semaphore, 0);
				914	WRT_REG_WORD(&reg->hccr,
				915	HCCR_CLR_RISC_INT);
				916	RD_REG_WORD(&reg->hccr);
				917	break;
				918	}
				919	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
				920	RD_REG_WORD(&reg->hccr);
				921	}
				922	udelay(5);
				923	}
				924
				925	if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
				926	rval = mb0 & MBS_MASK;
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	927	fw->risc_ram[cnt] = htons(mb2);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	928	} else {
				929	rval = QLA_FUNCTION_FAILED;
				930	}
				931	}
				932
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	933	if (rval == QLA_SUCCESS)
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	934	qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]);
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	935
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	936	qla2xxx_dump_post_process(base_vha, rval);
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	937
				938	qla2100_fw_dump_failed:
				939	if (!hardware_locked)
				940	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				941	}
				942
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	943	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	944	qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	945	{
				946	int rval;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	947	uint32_t cnt;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	948	uint32_t risc_address;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	949	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	950	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				951	uint32_t __iomem *dmp_reg;
				952	uint32_t *iter_reg;
				953	uint16_t __iomem *mbx_reg;
				954	unsigned long flags;
				955	struct qla24xx_fw_dump *fw;
				956	uint32_t ext_mem_cnt;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	957	void *nxt;
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	958	void *nxt_chain;
				959	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	960	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	961
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	962	if (IS_P3P_TYPE(ha))
Giridhar Malavali	a908301	2010-04-12 17:59:55 -0700	[diff] [blame]	963	return;
				964
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	965	risc_address = ext_mem_cnt = 0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	966	flags = 0;
				967
				968	if (!hardware_locked)
				969	spin_lock_irqsave(&ha->hardware_lock, flags);
				970
Andrew Vasquez	d4e3e04	2006-05-17 15:09:50 -0700	[diff] [blame]	971	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	972	ql_log(ql_log_warn, vha, 0xd006,
				973	"No buffer available for dump.\n");
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	974	goto qla24xx_fw_dump_failed;
				975	}
				976
				977	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	978	ql_log(ql_log_warn, vha, 0xd007,
				979	"Firmware has been previously dumped (%p) "
				980	"-- ignoring request.\n",
				981	ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	982	goto qla24xx_fw_dump_failed;
				983	}
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	984	fw = &ha->fw_dump->isp.isp24;
				985	qla2xxx_prep_dump(ha, ha->fw_dump);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	986
Andrew Vasquez	a7a167b	2006-06-23 16:10:29 -0700	[diff] [blame]	987	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	988
				989	/* Pause RISC. */
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	990	rval = qla24xx_pause_risc(reg);
				991	if (rval != QLA_SUCCESS)
				992	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	993
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	994	/* Host interface registers. */
				995	dmp_reg = &reg->flash_addr;
				996	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				997	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	998
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	999	/* Disable interrupts. */
				1000	WRT_REG_DWORD(&reg->ictrl, 0);
				1001	RD_REG_DWORD(&reg->ictrl);
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1002
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1003	/* Shadow registers. */
				1004	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1005	RD_REG_DWORD(&reg->iobase_addr);
				1006	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1007	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1008
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1009	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1010	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1011
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1012	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1013	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1014
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1015	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1016	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1017
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1018	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1019	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1020
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1021	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1022	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1023
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1024	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1025	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
andrew.vasquez@qlogic.com	210d535	2006-01-13 17:05:21 -0800	[diff] [blame]	1026
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1027	/* Mailbox registers. */
				1028	mbx_reg = &reg->mailbox0;
				1029	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1030	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1031
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1032	/* Transfer sequence registers. */
				1033	iter_reg = fw->xseq_gp_reg;
				1034	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1035	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1036	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1037	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1038	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1039	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1040	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1041	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1042
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1043	qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg);
				1044	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1045
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1046	/* Receive sequence registers. */
				1047	iter_reg = fw->rseq_gp_reg;
				1048	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1049	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1050	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1051	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1052	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1053	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1054	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1055	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1056
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1057	qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg);
				1058	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1059	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1060
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1061	/* Command DMA registers. */
				1062	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1063
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1064	/* Queues. */
				1065	iter_reg = fw->req0_dma_reg;
				1066	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1067	dmp_reg = &reg->iobase_q;
				1068	for (cnt = 0; cnt < 7; cnt++)
				1069	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1070
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1071	iter_reg = fw->resp0_dma_reg;
				1072	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1073	dmp_reg = &reg->iobase_q;
				1074	for (cnt = 0; cnt < 7; cnt++)
				1075	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1076
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1077	iter_reg = fw->req1_dma_reg;
				1078	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1079	dmp_reg = &reg->iobase_q;
				1080	for (cnt = 0; cnt < 7; cnt++)
				1081	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1082
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1083	/* Transmit DMA registers. */
				1084	iter_reg = fw->xmt0_dma_reg;
				1085	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1086	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1087
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1088	iter_reg = fw->xmt1_dma_reg;
				1089	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1090	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1091
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1092	iter_reg = fw->xmt2_dma_reg;
				1093	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1094	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1095
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1096	iter_reg = fw->xmt3_dma_reg;
				1097	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1098	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1099
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1100	iter_reg = fw->xmt4_dma_reg;
				1101	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1102	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1103
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1104	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1105
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1106	/* Receive DMA registers. */
				1107	iter_reg = fw->rcvt0_data_dma_reg;
				1108	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1109	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1110
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1111	iter_reg = fw->rcvt1_data_dma_reg;
				1112	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1113	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1114
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1115	/* RISC registers. */
				1116	iter_reg = fw->risc_gp_reg;
				1117	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1118	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1119	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1120	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1121	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1122	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1123	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1124	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1125
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1126	/* Local memory controller registers. */
				1127	iter_reg = fw->lmc_reg;
				1128	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1129	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1130	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1131	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1132	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1133	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1134	qla24xx_read_window(reg, 0x3060, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1135
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1136	/* Fibre Protocol Module registers. */
				1137	iter_reg = fw->fpm_hdw_reg;
				1138	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1139	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1140	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1141	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1142	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1143	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1144	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1145	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1146	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1147	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1148	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1149	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1150
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1151	/* Frame Buffer registers. */
				1152	iter_reg = fw->fb_hdw_reg;
				1153	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1154	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1155	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1156	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1157	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1158	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1159	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1160	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1161	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1162	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1163	qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1164
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1165	rval = qla24xx_soft_reset(ha);
				1166	if (rval != QLA_SUCCESS)
				1167	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1168
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1169	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1170	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1171	if (rval != QLA_SUCCESS)
				1172	goto qla24xx_fw_dump_failed_0;
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1173
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1174	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1175
				1176	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1177
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1178	nxt_chain = (void *)ha->fw_dump + ha->chain_offset;
				1179	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
				1180	if (last_chain) {
				1181	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1182	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1183	}
				1184
				1185	/* Adjust valid length. */
				1186	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1187
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1188	qla24xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1189	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	6d9b61e	2005-07-06 10:30:36 -0700	[diff] [blame]	1190
				1191	qla24xx_fw_dump_failed:
				1192	if (!hardware_locked)
				1193	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1194	}
				1195
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1196	void
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1197	qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1198	{
				1199	int rval;
				1200	uint32_t cnt;
				1201	uint32_t risc_address;
Anirban Chakraborty	7b867cf	2008-11-06 10:40:19 -0800	[diff] [blame]	1202	struct qla_hw_data *ha = vha->hw;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1203	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1204	uint32_t __iomem *dmp_reg;
				1205	uint32_t *iter_reg;
				1206	uint16_t __iomem *mbx_reg;
				1207	unsigned long flags;
				1208	struct qla25xx_fw_dump *fw;
				1209	uint32_t ext_mem_cnt;
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1210	void nxt, nxt_chain;
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1211	uint32_t *last_chain = NULL;
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1212	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1213
				1214	risc_address = ext_mem_cnt = 0;
				1215	flags = 0;
				1216
				1217	if (!hardware_locked)
				1218	spin_lock_irqsave(&ha->hardware_lock, flags);
				1219
				1220	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1221	ql_log(ql_log_warn, vha, 0xd008,
				1222	"No buffer available for dump.\n");
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1223	goto qla25xx_fw_dump_failed;
				1224	}
				1225
				1226	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1227	ql_log(ql_log_warn, vha, 0xd009,
				1228	"Firmware has been previously dumped (%p) "
				1229	"-- ignoring request.\n",
				1230	ha->fw_dump);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1231	goto qla25xx_fw_dump_failed;
				1232	}
				1233	fw = &ha->fw_dump->isp.isp25;
				1234	qla2xxx_prep_dump(ha, ha->fw_dump);
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1235	ha->fw_dump->version = __constant_htonl(2);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1236
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1237	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1238
				1239	/* Pause RISC. */
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1240	rval = qla24xx_pause_risc(reg);
				1241	if (rval != QLA_SUCCESS)
				1242	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1243
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1244	/* Host/Risc registers. */
				1245	iter_reg = fw->host_risc_reg;
				1246	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1247	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1248
				1249	/* PCIe registers. */
				1250	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1251	RD_REG_DWORD(&reg->iobase_addr);
				1252	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1253	dmp_reg = &reg->iobase_c4;
				1254	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1255	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1256	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1257	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1258
Andrew Vasquez	b583692	2007-09-20 14:07:39 -0700	[diff] [blame]	1259	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1260	RD_REG_DWORD(&reg->iobase_window);
				1261
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1262	/* Host interface registers. */
				1263	dmp_reg = &reg->flash_addr;
				1264	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1265	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1266
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1267	/* Disable interrupts. */
				1268	WRT_REG_DWORD(&reg->ictrl, 0);
				1269	RD_REG_DWORD(&reg->ictrl);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1270
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1271	/* Shadow registers. */
				1272	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1273	RD_REG_DWORD(&reg->iobase_addr);
				1274	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1275	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1276
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1277	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1278	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1279
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1280	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1281	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1282
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1283	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1284	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1285
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1286	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1287	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1288
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1289	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1290	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1291
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1292	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1293	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1294
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1295	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1296	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1297
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1298	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1299	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1300
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1301	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1302	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1303
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1304	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1305	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1306
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1307	/* RISC I/O register. */
				1308	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1309	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1310
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1311	/* Mailbox registers. */
				1312	mbx_reg = &reg->mailbox0;
				1313	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1314	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1315
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1316	/* Transfer sequence registers. */
				1317	iter_reg = fw->xseq_gp_reg;
				1318	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1319	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1320	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1321	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1322	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1323	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1324	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1325	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1326
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1327	iter_reg = fw->xseq_0_reg;
				1328	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1329	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1330	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1331
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1332	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1333
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1334	/* Receive sequence registers. */
				1335	iter_reg = fw->rseq_gp_reg;
				1336	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1337	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1338	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1339	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1340	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1341	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1342	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1343	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1344
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1345	iter_reg = fw->rseq_0_reg;
				1346	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1347	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1348
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1349	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1350	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1351
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1352	/* Auxiliary sequence registers. */
				1353	iter_reg = fw->aseq_gp_reg;
				1354	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1355	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1356	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1357	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1358	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1359	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1360	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1361	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1362
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1363	iter_reg = fw->aseq_0_reg;
				1364	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1365	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1366
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1367	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1368	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1369
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1370	/* Command DMA registers. */
				1371	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1372
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1373	/* Queues. */
				1374	iter_reg = fw->req0_dma_reg;
				1375	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1376	dmp_reg = &reg->iobase_q;
				1377	for (cnt = 0; cnt < 7; cnt++)
				1378	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1379
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1380	iter_reg = fw->resp0_dma_reg;
				1381	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1382	dmp_reg = &reg->iobase_q;
				1383	for (cnt = 0; cnt < 7; cnt++)
				1384	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1385
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1386	iter_reg = fw->req1_dma_reg;
				1387	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1388	dmp_reg = &reg->iobase_q;
				1389	for (cnt = 0; cnt < 7; cnt++)
				1390	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1391
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1392	/* Transmit DMA registers. */
				1393	iter_reg = fw->xmt0_dma_reg;
				1394	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1395	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1396
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1397	iter_reg = fw->xmt1_dma_reg;
				1398	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1399	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1400
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1401	iter_reg = fw->xmt2_dma_reg;
				1402	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1403	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1404
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1405	iter_reg = fw->xmt3_dma_reg;
				1406	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1407	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1408
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1409	iter_reg = fw->xmt4_dma_reg;
				1410	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1411	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1412
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1413	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1414
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1415	/* Receive DMA registers. */
				1416	iter_reg = fw->rcvt0_data_dma_reg;
				1417	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1418	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1419
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1420	iter_reg = fw->rcvt1_data_dma_reg;
				1421	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1422	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1423
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1424	/* RISC registers. */
				1425	iter_reg = fw->risc_gp_reg;
				1426	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1427	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1428	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1429	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1430	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1431	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1432	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1433	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1434
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1435	/* Local memory controller registers. */
				1436	iter_reg = fw->lmc_reg;
				1437	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1438	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1439	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1440	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1441	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1442	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1443	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1444	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1445
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1446	/* Fibre Protocol Module registers. */
				1447	iter_reg = fw->fpm_hdw_reg;
				1448	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1449	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1450	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1451	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1452	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1453	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1454	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1455	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1456	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1457	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1458	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1459	qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1460
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1461	/* Frame Buffer registers. */
				1462	iter_reg = fw->fb_hdw_reg;
				1463	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1464	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1465	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1466	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1467	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1468	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1469	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1470	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1471	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1472	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1473	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1474	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1475
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1476	/* Multi queue registers */
				1477	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1478	&last_chain);
				1479
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1480	rval = qla24xx_soft_reset(ha);
				1481	if (rval != QLA_SUCCESS)
				1482	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1483
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1484	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
Andrew Vasquez	c572270	2008-04-24 15:21:22 -0700	[diff] [blame]	1485	&nxt);
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1486	if (rval != QLA_SUCCESS)
				1487	goto qla25xx_fw_dump_failed_0;
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1488
Anirban Chakraborty	73208df	2008-12-09 16:45:39 -0800	[diff] [blame]	1489	nxt = qla2xxx_copy_queues(ha, nxt);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1490
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	1491	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1492
Andrew Vasquez	d63ab53	2009-01-05 11:18:09 -0800	[diff] [blame]	1493	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1494	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1495	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1496	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	bb99de6	2009-01-05 11:18:08 -0800	[diff] [blame]	1497	if (last_chain) {
				1498	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1499	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1500	}
Andrew Vasquez	df613b9	2008-01-17 09:02:17 -0800	[diff] [blame]	1501
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1502	/* Adjust valid length. */
				1503	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1504
Andrew Vasquez	c81d04c	2007-07-26 11:41:13 -0700	[diff] [blame]	1505	qla25xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1506	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	c3a2f0d	2007-07-19 20:37:34 -0700	[diff] [blame]	1507
				1508	qla25xx_fw_dump_failed:
				1509	if (!hardware_locked)
				1510	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1511	}
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1512
				1513	void
				1514	qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1515	{
				1516	int rval;
				1517	uint32_t cnt;
				1518	uint32_t risc_address;
				1519	struct qla_hw_data *ha = vha->hw;
				1520	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1521	uint32_t __iomem *dmp_reg;
				1522	uint32_t *iter_reg;
				1523	uint16_t __iomem *mbx_reg;
				1524	unsigned long flags;
				1525	struct qla81xx_fw_dump *fw;
				1526	uint32_t ext_mem_cnt;
				1527	void nxt, nxt_chain;
				1528	uint32_t *last_chain = NULL;
				1529	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1530
				1531	risc_address = ext_mem_cnt = 0;
				1532	flags = 0;
				1533
				1534	if (!hardware_locked)
				1535	spin_lock_irqsave(&ha->hardware_lock, flags);
				1536
				1537	if (!ha->fw_dump) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1538	ql_log(ql_log_warn, vha, 0xd00a,
				1539	"No buffer available for dump.\n");
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1540	goto qla81xx_fw_dump_failed;
				1541	}
				1542
				1543	if (ha->fw_dumped) {
Saurav Kashyap	7c3df13	2011-07-14 12:00:13 -0700	[diff] [blame]	1544	ql_log(ql_log_warn, vha, 0xd00b,
				1545	"Firmware has been previously dumped (%p) "
				1546	"-- ignoring request.\n",
				1547	ha->fw_dump);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1548	goto qla81xx_fw_dump_failed;
				1549	}
				1550	fw = &ha->fw_dump->isp.isp81;
				1551	qla2xxx_prep_dump(ha, ha->fw_dump);
				1552
				1553	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1554
				1555	/* Pause RISC. */
				1556	rval = qla24xx_pause_risc(reg);
				1557	if (rval != QLA_SUCCESS)
				1558	goto qla81xx_fw_dump_failed_0;
				1559
				1560	/* Host/Risc registers. */
				1561	iter_reg = fw->host_risc_reg;
				1562	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1563	qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1564
				1565	/* PCIe registers. */
				1566	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1567	RD_REG_DWORD(&reg->iobase_addr);
				1568	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1569	dmp_reg = &reg->iobase_c4;
				1570	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1571	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1572	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1573	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				1574
				1575	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1576	RD_REG_DWORD(&reg->iobase_window);
				1577
				1578	/* Host interface registers. */
				1579	dmp_reg = &reg->flash_addr;
				1580	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1581	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
				1582
				1583	/* Disable interrupts. */
				1584	WRT_REG_DWORD(&reg->ictrl, 0);
				1585	RD_REG_DWORD(&reg->ictrl);
				1586
				1587	/* Shadow registers. */
				1588	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1589	RD_REG_DWORD(&reg->iobase_addr);
				1590	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1591	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1592
				1593	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1594	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1595
				1596	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1597	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1598
				1599	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1600	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1601
				1602	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1603	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1604
				1605	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1606	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1607
				1608	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1609	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1610
				1611	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1612	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1613
				1614	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1615	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1616
				1617	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1618	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1619
				1620	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1621	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1622
				1623	/* RISC I/O register. */
				1624	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1625	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				1626
				1627	/* Mailbox registers. */
				1628	mbx_reg = &reg->mailbox0;
				1629	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1630	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
				1631
				1632	/* Transfer sequence registers. */
				1633	iter_reg = fw->xseq_gp_reg;
				1634	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1635	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1636	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1637	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1638	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1639	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1640	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1641	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				1642
				1643	iter_reg = fw->xseq_0_reg;
				1644	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1645	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1646	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				1647
				1648	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				1649
				1650	/* Receive sequence registers. */
				1651	iter_reg = fw->rseq_gp_reg;
				1652	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				1653	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				1654	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				1655	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				1656	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				1657	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				1658	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				1659	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				1660
				1661	iter_reg = fw->rseq_0_reg;
				1662	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				1663	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				1664
				1665	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				1666	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				1667
				1668	/* Auxiliary sequence registers. */
				1669	iter_reg = fw->aseq_gp_reg;
				1670	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				1671	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				1672	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				1673	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				1674	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				1675	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				1676	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				1677	qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				1678
				1679	iter_reg = fw->aseq_0_reg;
				1680	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				1681	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				1682
				1683	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				1684	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				1685
				1686	/* Command DMA registers. */
				1687	qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg);
				1688
				1689	/* Queues. */
				1690	iter_reg = fw->req0_dma_reg;
				1691	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				1692	dmp_reg = &reg->iobase_q;
				1693	for (cnt = 0; cnt < 7; cnt++)
				1694	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1695
				1696	iter_reg = fw->resp0_dma_reg;
				1697	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				1698	dmp_reg = &reg->iobase_q;
				1699	for (cnt = 0; cnt < 7; cnt++)
				1700	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1701
				1702	iter_reg = fw->req1_dma_reg;
				1703	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				1704	dmp_reg = &reg->iobase_q;
				1705	for (cnt = 0; cnt < 7; cnt++)
				1706	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				1707
				1708	/* Transmit DMA registers. */
				1709	iter_reg = fw->xmt0_dma_reg;
				1710	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				1711	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				1712
				1713	iter_reg = fw->xmt1_dma_reg;
				1714	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				1715	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				1716
				1717	iter_reg = fw->xmt2_dma_reg;
				1718	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				1719	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				1720
				1721	iter_reg = fw->xmt3_dma_reg;
				1722	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				1723	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				1724
				1725	iter_reg = fw->xmt4_dma_reg;
				1726	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				1727	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				1728
				1729	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				1730
				1731	/* Receive DMA registers. */
				1732	iter_reg = fw->rcvt0_data_dma_reg;
				1733	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				1734	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				1735
				1736	iter_reg = fw->rcvt1_data_dma_reg;
				1737	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				1738	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				1739
				1740	/* RISC registers. */
				1741	iter_reg = fw->risc_gp_reg;
				1742	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				1743	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				1744	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				1745	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				1746	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				1747	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				1748	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				1749	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				1750
				1751	/* Local memory controller registers. */
				1752	iter_reg = fw->lmc_reg;
				1753	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				1754	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				1755	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				1756	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				1757	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				1758	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				1759	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				1760	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				1761
				1762	/* Fibre Protocol Module registers. */
				1763	iter_reg = fw->fpm_hdw_reg;
				1764	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				1765	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				1766	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				1767	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				1768	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				1769	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				1770	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				1771	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				1772	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				1773	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				1774	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				1775	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				1776	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				1777	qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				1778
				1779	/* Frame Buffer registers. */
				1780	iter_reg = fw->fb_hdw_reg;
				1781	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				1782	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				1783	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				1784	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				1785	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				1786	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				1787	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				1788	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				1789	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				1790	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				1791	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				1792	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				1793	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				1794
				1795	/* Multi queue registers */
				1796	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				1797	&last_chain);
				1798
				1799	rval = qla24xx_soft_reset(ha);
				1800	if (rval != QLA_SUCCESS)
				1801	goto qla81xx_fw_dump_failed_0;
				1802
				1803	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				1804	&nxt);
				1805	if (rval != QLA_SUCCESS)
				1806	goto qla81xx_fw_dump_failed_0;
				1807
				1808	nxt = qla2xxx_copy_queues(ha, nxt);
				1809
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	1810	qla24xx_copy_eft(ha, nxt);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1811
				1812	/* Chain entries -- started with MQ. */
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1813	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				1814	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	1815	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1816	if (last_chain) {
				1817	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				1818	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				1819	}
				1820
Giridhar Malavali	050c9bb	2012-02-09 11:15:33 -0800	[diff] [blame]	1821	/* Adjust valid length. */
				1822	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				1823
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1824	qla81xx_fw_dump_failed_0:
Andrew Vasquez	3420d36	2009-10-13 15:16:45 -0700	[diff] [blame]	1825	qla2xxx_dump_post_process(base_vha, rval);
Andrew Vasquez	3a03eb7	2009-01-05 11:18:11 -0800	[diff] [blame]	1826
				1827	qla81xx_fw_dump_failed:
				1828	if (!hardware_locked)
				1829	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				1830	}
				1831
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	1832	void
				1833	qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
				1834	{
				1835	int rval;
				1836	uint32_t cnt, reg_data;
				1837	uint32_t risc_address;
				1838	struct qla_hw_data *ha = vha->hw;
				1839	struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
				1840	uint32_t __iomem *dmp_reg;
				1841	uint32_t *iter_reg;
				1842	uint16_t __iomem *mbx_reg;
				1843	unsigned long flags;
				1844	struct qla83xx_fw_dump *fw;
				1845	uint32_t ext_mem_cnt;
				1846	void nxt, nxt_chain;
				1847	uint32_t *last_chain = NULL;
				1848	struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
				1849
				1850	risc_address = ext_mem_cnt = 0;
				1851	flags = 0;
				1852
				1853	if (!hardware_locked)
				1854	spin_lock_irqsave(&ha->hardware_lock, flags);
				1855
				1856	if (!ha->fw_dump) {
				1857	ql_log(ql_log_warn, vha, 0xd00c,
				1858	"No buffer available for dump!!!\n");
				1859	goto qla83xx_fw_dump_failed;
				1860	}
				1861
				1862	if (ha->fw_dumped) {
				1863	ql_log(ql_log_warn, vha, 0xd00d,
				1864	"Firmware has been previously dumped (%p) -- ignoring "
				1865	"request...\n", ha->fw_dump);
				1866	goto qla83xx_fw_dump_failed;
				1867	}
				1868	fw = &ha->fw_dump->isp.isp83;
				1869	qla2xxx_prep_dump(ha, ha->fw_dump);
				1870
				1871	fw->host_status = htonl(RD_REG_DWORD(&reg->host_status));
				1872
				1873	/* Pause RISC. */
				1874	rval = qla24xx_pause_risc(reg);
				1875	if (rval != QLA_SUCCESS)
				1876	goto qla83xx_fw_dump_failed_0;
				1877
				1878	WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
				1879	dmp_reg = &reg->iobase_window;
				1880	reg_data = RD_REG_DWORD(dmp_reg);
				1881	WRT_REG_DWORD(dmp_reg, 0);
				1882
				1883	dmp_reg = &reg->unused_4_1[0];
				1884	reg_data = RD_REG_DWORD(dmp_reg);
				1885	WRT_REG_DWORD(dmp_reg, 0);
				1886
				1887	WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
				1888	dmp_reg = &reg->unused_4_1[2];
				1889	reg_data = RD_REG_DWORD(dmp_reg);
				1890	WRT_REG_DWORD(dmp_reg, 0);
				1891
				1892	/* select PCR and disable ecc checking and correction */
				1893	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1894	RD_REG_DWORD(&reg->iobase_addr);
				1895	WRT_REG_DWORD(&reg->iobase_select, 0x60000000); /* write to F0h = PCR */
				1896
				1897	/* Host/Risc registers. */
				1898	iter_reg = fw->host_risc_reg;
				1899	iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg);
				1900	iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg);
				1901	qla24xx_read_window(reg, 0x7040, 16, iter_reg);
				1902
				1903	/* PCIe registers. */
				1904	WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
				1905	RD_REG_DWORD(&reg->iobase_addr);
				1906	WRT_REG_DWORD(&reg->iobase_window, 0x01);
				1907	dmp_reg = &reg->iobase_c4;
				1908	fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg++));
				1909	fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg++));
				1910	fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg));
				1911	fw->pcie_regs[3] = htonl(RD_REG_DWORD(&reg->iobase_window));
				1912
				1913	WRT_REG_DWORD(&reg->iobase_window, 0x00);
				1914	RD_REG_DWORD(&reg->iobase_window);
				1915
				1916	/* Host interface registers. */
				1917	dmp_reg = &reg->flash_addr;
				1918	for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
				1919	fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg++));
				1920
				1921	/* Disable interrupts. */
				1922	WRT_REG_DWORD(&reg->ictrl, 0);
				1923	RD_REG_DWORD(&reg->ictrl);
				1924
				1925	/* Shadow registers. */
				1926	WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
				1927	RD_REG_DWORD(&reg->iobase_addr);
				1928	WRT_REG_DWORD(&reg->iobase_select, 0xB0000000);
				1929	fw->shadow_reg[0] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1930
				1931	WRT_REG_DWORD(&reg->iobase_select, 0xB0100000);
				1932	fw->shadow_reg[1] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1933
				1934	WRT_REG_DWORD(&reg->iobase_select, 0xB0200000);
				1935	fw->shadow_reg[2] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1936
				1937	WRT_REG_DWORD(&reg->iobase_select, 0xB0300000);
				1938	fw->shadow_reg[3] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1939
				1940	WRT_REG_DWORD(&reg->iobase_select, 0xB0400000);
				1941	fw->shadow_reg[4] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1942
				1943	WRT_REG_DWORD(&reg->iobase_select, 0xB0500000);
				1944	fw->shadow_reg[5] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1945
				1946	WRT_REG_DWORD(&reg->iobase_select, 0xB0600000);
				1947	fw->shadow_reg[6] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1948
				1949	WRT_REG_DWORD(&reg->iobase_select, 0xB0700000);
				1950	fw->shadow_reg[7] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1951
				1952	WRT_REG_DWORD(&reg->iobase_select, 0xB0800000);
				1953	fw->shadow_reg[8] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1954
				1955	WRT_REG_DWORD(&reg->iobase_select, 0xB0900000);
				1956	fw->shadow_reg[9] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1957
				1958	WRT_REG_DWORD(&reg->iobase_select, 0xB0A00000);
				1959	fw->shadow_reg[10] = htonl(RD_REG_DWORD(&reg->iobase_sdata));
				1960
				1961	/* RISC I/O register. */
				1962	WRT_REG_DWORD(&reg->iobase_addr, 0x0010);
				1963	fw->risc_io_reg = htonl(RD_REG_DWORD(&reg->iobase_window));
				1964
				1965	/* Mailbox registers. */
				1966	mbx_reg = &reg->mailbox0;
				1967	for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
				1968	fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg++));
				1969
				1970	/* Transfer sequence registers. */
				1971	iter_reg = fw->xseq_gp_reg;
				1972	iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg);
				1973	iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg);
				1974	iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg);
				1975	iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg);
				1976	iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg);
				1977	iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg);
				1978	iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg);
				1979	iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg);
				1980	iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg);
				1981	iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg);
				1982	iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg);
				1983	iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg);
				1984	iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg);
				1985	iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg);
				1986	iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg);
				1987	qla24xx_read_window(reg, 0xBF70, 16, iter_reg);
				1988
				1989	iter_reg = fw->xseq_0_reg;
				1990	iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg);
				1991	iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg);
				1992	qla24xx_read_window(reg, 0xBFE0, 16, iter_reg);
				1993
				1994	qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg);
				1995
				1996	qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg);
				1997
				1998	/* Receive sequence registers. */
				1999	iter_reg = fw->rseq_gp_reg;
				2000	iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg);
				2001	iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg);
				2002	iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg);
				2003	iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg);
				2004	iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg);
				2005	iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg);
				2006	iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg);
				2007	iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg);
				2008	iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg);
				2009	iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg);
				2010	iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg);
				2011	iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg);
				2012	iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg);
				2013	iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg);
				2014	iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg);
				2015	qla24xx_read_window(reg, 0xFF70, 16, iter_reg);
				2016
				2017	iter_reg = fw->rseq_0_reg;
				2018	iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg);
				2019	qla24xx_read_window(reg, 0xFFD0, 16, iter_reg);
				2020
				2021	qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg);
				2022	qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg);
				2023	qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg);
				2024
				2025	/* Auxiliary sequence registers. */
				2026	iter_reg = fw->aseq_gp_reg;
				2027	iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg);
				2028	iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg);
				2029	iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg);
				2030	iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg);
				2031	iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg);
				2032	iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg);
				2033	iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg);
				2034	iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg);
				2035	iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg);
				2036	iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg);
				2037	iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg);
				2038	iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg);
				2039	iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg);
				2040	iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg);
				2041	iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg);
				2042	qla24xx_read_window(reg, 0xB170, 16, iter_reg);
				2043
				2044	iter_reg = fw->aseq_0_reg;
				2045	iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg);
				2046	qla24xx_read_window(reg, 0xB0D0, 16, iter_reg);
				2047
				2048	qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg);
				2049	qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg);
				2050	qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg);
				2051
				2052	/* Command DMA registers. */
				2053	iter_reg = fw->cmd_dma_reg;
				2054	iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg);
				2055	iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg);
				2056	iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg);
				2057	qla24xx_read_window(reg, 0x71F0, 16, iter_reg);
				2058
				2059	/* Queues. */
				2060	iter_reg = fw->req0_dma_reg;
				2061	iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg);
				2062	dmp_reg = &reg->iobase_q;
				2063	for (cnt = 0; cnt < 7; cnt++)
				2064	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2065
				2066	iter_reg = fw->resp0_dma_reg;
				2067	iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg);
				2068	dmp_reg = &reg->iobase_q;
				2069	for (cnt = 0; cnt < 7; cnt++)
				2070	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2071
				2072	iter_reg = fw->req1_dma_reg;
				2073	iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg);
				2074	dmp_reg = &reg->iobase_q;
				2075	for (cnt = 0; cnt < 7; cnt++)
				2076	*iter_reg++ = htonl(RD_REG_DWORD(dmp_reg++));
				2077
				2078	/* Transmit DMA registers. */
				2079	iter_reg = fw->xmt0_dma_reg;
				2080	iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg);
				2081	qla24xx_read_window(reg, 0x7610, 16, iter_reg);
				2082
				2083	iter_reg = fw->xmt1_dma_reg;
				2084	iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg);
				2085	qla24xx_read_window(reg, 0x7630, 16, iter_reg);
				2086
				2087	iter_reg = fw->xmt2_dma_reg;
				2088	iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg);
				2089	qla24xx_read_window(reg, 0x7650, 16, iter_reg);
				2090
				2091	iter_reg = fw->xmt3_dma_reg;
				2092	iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg);
				2093	qla24xx_read_window(reg, 0x7670, 16, iter_reg);
				2094
				2095	iter_reg = fw->xmt4_dma_reg;
				2096	iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg);
				2097	qla24xx_read_window(reg, 0x7690, 16, iter_reg);
				2098
				2099	qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg);
				2100
				2101	/* Receive DMA registers. */
				2102	iter_reg = fw->rcvt0_data_dma_reg;
				2103	iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg);
				2104	qla24xx_read_window(reg, 0x7710, 16, iter_reg);
				2105
				2106	iter_reg = fw->rcvt1_data_dma_reg;
				2107	iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg);
				2108	qla24xx_read_window(reg, 0x7730, 16, iter_reg);
				2109
				2110	/* RISC registers. */
				2111	iter_reg = fw->risc_gp_reg;
				2112	iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg);
				2113	iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg);
				2114	iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg);
				2115	iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg);
				2116	iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg);
				2117	iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg);
				2118	iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg);
				2119	qla24xx_read_window(reg, 0x0F70, 16, iter_reg);
				2120
				2121	/* Local memory controller registers. */
				2122	iter_reg = fw->lmc_reg;
				2123	iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg);
				2124	iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg);
				2125	iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg);
				2126	iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg);
				2127	iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg);
				2128	iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg);
				2129	iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg);
				2130	qla24xx_read_window(reg, 0x3070, 16, iter_reg);
				2131
				2132	/* Fibre Protocol Module registers. */
				2133	iter_reg = fw->fpm_hdw_reg;
				2134	iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg);
				2135	iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg);
				2136	iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg);
				2137	iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg);
				2138	iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg);
				2139	iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg);
				2140	iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg);
				2141	iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg);
				2142	iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg);
				2143	iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg);
				2144	iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg);
				2145	iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg);
				2146	iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg);
				2147	iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg);
				2148	iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg);
				2149	qla24xx_read_window(reg, 0x40F0, 16, iter_reg);
				2150
				2151	/* RQ0 Array registers. */
				2152	iter_reg = fw->rq0_array_reg;
				2153	iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg);
				2154	iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg);
				2155	iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg);
				2156	iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg);
				2157	iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg);
				2158	iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg);
				2159	iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg);
				2160	iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg);
				2161	iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg);
				2162	iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg);
				2163	iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg);
				2164	iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg);
				2165	iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg);
				2166	iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg);
				2167	iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg);
				2168	qla24xx_read_window(reg, 0x5CF0, 16, iter_reg);
				2169
				2170	/* RQ1 Array registers. */
				2171	iter_reg = fw->rq1_array_reg;
				2172	iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg);
				2173	iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg);
				2174	iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg);
				2175	iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg);
				2176	iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg);
				2177	iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg);
				2178	iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg);
				2179	iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg);
				2180	iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg);
				2181	iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg);
				2182	iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg);
				2183	iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg);
				2184	iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg);
				2185	iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg);
				2186	iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg);
				2187	qla24xx_read_window(reg, 0x5DF0, 16, iter_reg);
				2188
				2189	/* RP0 Array registers. */
				2190	iter_reg = fw->rp0_array_reg;
				2191	iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg);
				2192	iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg);
				2193	iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg);
				2194	iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg);
				2195	iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg);
				2196	iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg);
				2197	iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg);
				2198	iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg);
				2199	iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg);
				2200	iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg);
				2201	iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg);
				2202	iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg);
				2203	iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg);
				2204	iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg);
				2205	iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg);
				2206	qla24xx_read_window(reg, 0x5EF0, 16, iter_reg);
				2207
				2208	/* RP1 Array registers. */
				2209	iter_reg = fw->rp1_array_reg;
				2210	iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg);
				2211	iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg);
				2212	iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg);
				2213	iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg);
				2214	iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg);
				2215	iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg);
				2216	iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg);
				2217	iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg);
				2218	iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg);
				2219	iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg);
				2220	iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg);
				2221	iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg);
				2222	iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg);
				2223	iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg);
				2224	iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg);
				2225	qla24xx_read_window(reg, 0x5FF0, 16, iter_reg);
				2226
				2227	iter_reg = fw->at0_array_reg;
				2228	iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg);
				2229	iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg);
				2230	iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg);
				2231	iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg);
				2232	iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg);
				2233	iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg);
				2234	iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg);
				2235	qla24xx_read_window(reg, 0x70F0, 16, iter_reg);
				2236
				2237	/* I/O Queue Control registers. */
				2238	qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg);
				2239
				2240	/* Frame Buffer registers. */
				2241	iter_reg = fw->fb_hdw_reg;
				2242	iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg);
				2243	iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg);
				2244	iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg);
				2245	iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg);
				2246	iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg);
				2247	iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg);
				2248	iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg);
				2249	iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg);
				2250	iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg);
				2251	iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg);
				2252	iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg);
				2253	iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg);
				2254	iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg);
				2255	iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg);
				2256	iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg);
				2257	iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg);
				2258	iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg);
				2259	iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg);
				2260	iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg);
				2261	iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg);
				2262	iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg);
				2263	iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg);
				2264	iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg);
				2265	iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg);
				2266	iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg);
				2267	iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg);
				2268	qla24xx_read_window(reg, 0x6F00, 16, iter_reg);
				2269
				2270	/* Multi queue registers */
				2271	nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset,
				2272	&last_chain);
				2273
				2274	rval = qla24xx_soft_reset(ha);
				2275	if (rval != QLA_SUCCESS) {
				2276	ql_log(ql_log_warn, vha, 0xd00e,
				2277	"SOFT RESET FAILED, forcing continuation of dump!!!\n");
				2278	rval = QLA_SUCCESS;
				2279
				2280	ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n");
				2281
				2282	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
				2283	RD_REG_DWORD(&reg->hccr);
				2284
				2285	WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
				2286	RD_REG_DWORD(&reg->hccr);
				2287
				2288	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
				2289	RD_REG_DWORD(&reg->hccr);
				2290
				2291	for (cnt = 30000; cnt && (RD_REG_WORD(&reg->mailbox0)); cnt--)
				2292	udelay(5);
				2293
				2294	if (!cnt) {
				2295	nxt = fw->code_ram;
Saurav Kashyap	8c0bc70	2012-11-21 02:40:35 -0500	[diff] [blame]	2296	nxt += sizeof(fw->code_ram);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2297	nxt += (ha->fw_memory_size - 0x100000 + 1);
				2298	goto copy_queue;
				2299	} else
				2300	ql_log(ql_log_warn, vha, 0xd010,
				2301	"bigger hammer success?\n");
				2302	}
				2303
				2304	rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram),
				2305	&nxt);
				2306	if (rval != QLA_SUCCESS)
				2307	goto qla83xx_fw_dump_failed_0;
				2308
				2309	copy_queue:
				2310	nxt = qla2xxx_copy_queues(ha, nxt);
				2311
Bart Van Assche	7f544d0	2013-06-25 11:27:27 -0400	[diff] [blame]	2312	qla24xx_copy_eft(ha, nxt);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2313
				2314	/* Chain entries -- started with MQ. */
				2315	nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain);
				2316	nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain);
Nicholas Bellinger	2d70c10	2012-05-15 14:34:28 -0400	[diff] [blame]	2317	nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain);
Giridhar Malavali	6246b8a	2012-02-09 11:15:34 -0800	[diff] [blame]	2318	if (last_chain) {
				2319	ha->fw_dump->version \|= __constant_htonl(DUMP_CHAIN_VARIANT);
				2320	*last_chain \|= __constant_htonl(DUMP_CHAIN_LAST);
				2321	}
				2322
				2323	/* Adjust valid length. */
				2324	ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump);
				2325
				2326	qla83xx_fw_dump_failed_0:
				2327	qla2xxx_dump_post_process(base_vha, rval);
				2328
				2329	qla83xx_fw_dump_failed:
				2330	if (!hardware_locked)
				2331	spin_unlock_irqrestore(&ha->hardware_lock, flags);
				2332	}
				2333
Linus Torvalds	1da177e	2005-04-16 15:20:36 -0700	[diff] [blame]	2334	/****************************************************************************/
				2335	/* Driver Debug Functions. */
				2336	/****************************************************************************/
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2337
				2338	static inline int
				2339	ql_mask_match(uint32_t level)
				2340	{
				2341	if (ql2xextended_error_logging == 1)
				2342	ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
				2343	return (level & ql2xextended_error_logging) == level;
				2344	}
				2345
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2346	/*
				2347	* This function is for formatting and logging debug information.
				2348	* It is to be used when vha is available. It formats the message
				2349	* and logs it to the messages file.
				2350	* parameters:
				2351	* level: The level of the debug messages to be printed.
				2352	* If ql2xextended_error_logging value is correctly set,
				2353	* this message will appear in the messages file.
				2354	* vha: Pointer to the scsi_qla_host_t.
				2355	* id: This is a unique identifier for the level. It identifies the
				2356	* part of the code from where the message originated.
				2357	* msg: The message to be displayed.
				2358	*/
				2359	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2360	ql_dbg(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2361	{
				2362	va_list va;
				2363	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2364
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2365	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2366	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2367
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2368	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2369
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2370	vaf.fmt = fmt;
				2371	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2372
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2373	if (vha != NULL) {
				2374	const struct pci_dev *pdev = vha->hw->pdev;
				2375	/* <module-name> <pci-name> <msg-id>:<host> Message */
				2376	pr_warn("%s [%s]-%04x:%ld: %pV",
				2377	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset,
				2378	vha->host_no, &vaf);
				2379	} else {
				2380	pr_warn("%s [%s]-%04x: : %pV",
				2381	QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2382	}
				2383
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2384	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2385
				2386	}
				2387
				2388	/*
				2389	* This function is for formatting and logging debug information.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2390	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2391	* i.e., before host allocation. It formats the message and logs it
				2392	* to the messages file.
				2393	* parameters:
				2394	* level: The level of the debug messages to be printed.
				2395	* If ql2xextended_error_logging value is correctly set,
				2396	* this message will appear in the messages file.
				2397	* pdev: Pointer to the struct pci_dev.
				2398	* id: This is a unique id for the level. It identifies the part
				2399	* of the code from where the message originated.
				2400	* msg: The message to be displayed.
				2401	*/
				2402	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2403	ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2404	const char *fmt, ...)
				2405	{
				2406	va_list va;
				2407	struct va_format vaf;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2408
				2409	if (pdev == NULL)
				2410	return;
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2411	if (!ql_mask_match(level))
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2412	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2413
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2414	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2415
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2416	vaf.fmt = fmt;
				2417	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2418
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2419	/* <module-name> <dev-name>:<msg-id> Message */
				2420	pr_warn("%s [%s]-%04x: : %pV",
				2421	QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2422
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2423	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2424	}
				2425
				2426	/*
				2427	* This function is for formatting and logging log messages.
				2428	* It is to be used when vha is available. It formats the message
				2429	* and logs it to the messages file. All the messages will be logged
				2430	* irrespective of value of ql2xextended_error_logging.
				2431	* parameters:
				2432	* level: The level of the log messages to be printed in the
				2433	* messages file.
				2434	* vha: Pointer to the scsi_qla_host_t
				2435	* id: This is a unique id for the level. It identifies the
				2436	* part of the code from where the message originated.
				2437	* msg: The message to be displayed.
				2438	*/
				2439	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2440	ql_log(uint32_t level, scsi_qla_host_t vha, int32_t id, const char fmt, ...)
				2441	{
				2442	va_list va;
				2443	struct va_format vaf;
				2444	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2445
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2446	if (level > ql_errlev)
				2447	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2448
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2449	if (vha != NULL) {
				2450	const struct pci_dev *pdev = vha->hw->pdev;
				2451	/* <module-name> <msg-id>:<host> Message */
				2452	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ",
				2453	QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no);
				2454	} else {
				2455	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2456	QL_MSGHDR, "0000:00:00.0", id);
				2457	}
				2458	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2459
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2460	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2461
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2462	vaf.fmt = fmt;
				2463	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2464
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2465	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2466	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2467	pr_crit("%s%pV", pbuf, &vaf);
				2468	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2469	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2470	pr_err("%s%pV", pbuf, &vaf);
				2471	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2472	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2473	pr_warn("%s%pV", pbuf, &vaf);
				2474	break;
				2475	default:
				2476	pr_info("%s%pV", pbuf, &vaf);
				2477	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2478	}
				2479
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2480	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2481	}
				2482
				2483	/*
				2484	* This function is for formatting and logging log messages.
Masanari Iida	d6a0358	2012-08-22 14:20:58 -0400	[diff] [blame]	2485	* It is to be used when vha is not available and pci is available,
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2486	* i.e., before host allocation. It formats the message and logs
				2487	* it to the messages file. All the messages are logged irrespective
				2488	* of the value of ql2xextended_error_logging.
				2489	* parameters:
				2490	* level: The level of the log messages to be printed in the
				2491	* messages file.
				2492	* pdev: Pointer to the struct pci_dev.
				2493	* id: This is a unique id for the level. It identifies the
				2494	* part of the code from where the message originated.
				2495	* msg: The message to be displayed.
				2496	*/
				2497	void
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2498	ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id,
				2499	const char *fmt, ...)
				2500	{
				2501	va_list va;
				2502	struct va_format vaf;
				2503	char pbuf[128];
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2504
				2505	if (pdev == NULL)
				2506	return;
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2507	if (level > ql_errlev)
				2508	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2509
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2510	/* <module-name> <dev-name>:<msg-id> Message */
				2511	snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ",
				2512	QL_MSGHDR, dev_name(&(pdev->dev)), id);
				2513	pbuf[sizeof(pbuf) - 1] = 0;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2514
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2515	va_start(va, fmt);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2516
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2517	vaf.fmt = fmt;
				2518	vaf.va = &va;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2519
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2520	switch (level) {
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2521	case ql_log_fatal: /* FATAL LOG */
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2522	pr_crit("%s%pV", pbuf, &vaf);
				2523	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2524	case ql_log_warn:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2525	pr_err("%s%pV", pbuf, &vaf);
				2526	break;
Chad Dupuis	70a3fc7	2012-02-09 11:15:48 -0800	[diff] [blame]	2527	case ql_log_info:
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2528	pr_warn("%s%pV", pbuf, &vaf);
				2529	break;
				2530	default:
				2531	pr_info("%s%pV", pbuf, &vaf);
				2532	break;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2533	}
				2534
Joe Perches	086b3e8	2011-11-18 09:03:05 -0800	[diff] [blame]	2535	va_end(va);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2536	}
				2537
				2538	void
				2539	ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id)
				2540	{
				2541	int i;
				2542	struct qla_hw_data *ha = vha->hw;
				2543	struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
				2544	struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
				2545	struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
				2546	uint16_t __iomem *mbx_reg;
				2547
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2548	if (!ql_mask_match(level))
				2549	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2550
Atul Deshmukh	7ec0eff	2013-08-27 01:37:28 -0400	[diff] [blame]	2551	if (IS_P3P_TYPE(ha))
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2552	mbx_reg = &reg82->mailbox_in[0];
				2553	else if (IS_FWI2_CAPABLE(ha))
				2554	mbx_reg = &reg24->mailbox0;
				2555	else
				2556	mbx_reg = MAILBOX_REG(ha, reg, 0);
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2557
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2558	ql_dbg(level, vha, id, "Mailbox registers:\n");
				2559	for (i = 0; i < 6; i++)
				2560	ql_dbg(level, vha, id,
				2561	"mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2562	}
				2563
				2564
				2565	void
				2566	ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id,
				2567	uint8_t *b, uint32_t size)
				2568	{
				2569	uint32_t cnt;
				2570	uint8_t c;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2571
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2572	if (!ql_mask_match(level))
				2573	return;
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2574
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2575	ql_dbg(level, vha, id, " 0 1 2 3 4 5 6 7 8 "
				2576	"9 Ah Bh Ch Dh Eh Fh\n");
				2577	ql_dbg(level, vha, id, "----------------------------------"
				2578	"----------------------------\n");
				2579
				2580	ql_dbg(level, vha, id, " ");
				2581	for (cnt = 0; cnt < size;) {
				2582	c = *b++;
				2583	printk("%02x", (uint32_t) c);
				2584	cnt++;
				2585	if (!(cnt % 16))
				2586	printk("\n");
				2587	else
				2588	printk(" ");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2589	}
Chad Dupuis	cfb0919	2011-11-18 09:03:07 -0800	[diff] [blame]	2590	if (cnt % 16)
				2591	ql_dbg(level, vha, id, "\n");
Saurav Kashyap	3ce8866	2011-07-14 12:00:12 -0700	[diff] [blame]	2592	}