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review.shift-gmbh.com / SHIFTPHONES / kernel / common / fd141d1a99a300944dc42a7820afb8c1bafd4035 / . / arch / powerpc / platforms / powernv / pci.h
blob: d088d4f061160335bb5d93de9cb23d7355497e57 [file] [log] [blame]
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]1#ifndef __POWERNV_PCI_H
2#define __POWERNV_PCI_H
3
Ian Munsief4568342016-07-14 07:17:00 +1000[diff] [blame]4#include <linux/iommu.h>
5#include <asm/iommu.h>
6#include <asm/msi_bitmap.h>
7
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]8struct pci_dn;
9
10enum pnv_phb_type {
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]11 PNV_PHB_IODA1 = 0,
12 PNV_PHB_IODA2 = 1,
13 PNV_PHB_NPU = 2,
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]14};
15
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]16/* Precise PHB model for error management */
17enum pnv_phb_model {
18 PNV_PHB_MODEL_UNKNOWN,
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]19 PNV_PHB_MODEL_P7IOC,
Gavin Shanaa0c0332013-04-25 19:20:57 +0000[diff] [blame]20 PNV_PHB_MODEL_PHB3,
Alistair Popple5d2aa712015-12-17 13:43:13 +1100[diff] [blame]21 PNV_PHB_MODEL_NPU,
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]22};
23
Gavin Shan5c9d6d72013-09-06 09:00:03 +0800[diff] [blame]24#define PNV_PCI_DIAG_BUF_SIZE 8192
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]25#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
26#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
27#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]28#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
29#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
Wei Yang781a8682015-03-25 16:23:57 +0800[diff] [blame]30#define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]31
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]32/* Data associated with a PE, including IOMMU tracking etc.. */
Gavin Shan4cce9552013-04-25 19:21:00 +0000[diff] [blame]33struct pnv_phb;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]34struct pnv_ioda_pe {
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]35 unsigned long flags;
Gavin Shan4cce9552013-04-25 19:21:00 +0000[diff] [blame]36 struct pnv_phb *phb;
Gavin Shanc5f77002016-05-20 16:41:35 +1000[diff] [blame]37 int device_count;
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]38
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]39 /* A PE can be associated with a single device or an
40 * entire bus (& children). In the former case, pdev
41 * is populated, in the later case, pbus is.
42 */
Wei Yang781a8682015-03-25 16:23:57 +0800[diff] [blame]43#ifdef CONFIG_PCI_IOV
44 struct pci_dev *parent_dev;
45#endif
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]46 struct pci_dev *pdev;
47 struct pci_bus *pbus;
48
49 /* Effective RID (device RID for a device PE and base bus
50 * RID with devfn 0 for a bus PE)
51 */
52 unsigned int rid;
53
54 /* PE number */
55 unsigned int pe_number;
56
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]57 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
Alexey Kardashevskiyb348aa62015-06-05 16:35:08 +1000[diff] [blame]58 struct iommu_table_group table_group;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]59
Benjamin Herrenschmidtcd15b042014-02-11 11:32:38 +1100[diff] [blame]60 /* 64-bit TCE bypass region */
61 bool tce_bypass_enabled;
62 uint64_t tce_bypass_base;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]63
64 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
65 * and -1 if not supported. (It's actually identical to the
66 * PE number)
67 */
68 int mve_number;
69
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]70 /* PEs in compound case */
71 struct pnv_ioda_pe *master;
72 struct list_head slaves;
73
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]74 /* Link in list of PE#s */
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]75 struct list_head list;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]76};
77
Gavin Shanf5bc6b72014-04-24 18:00:09 +1000[diff] [blame]78#define PNV_PHB_FLAG_EEH (1 << 0)
Ian Munsie4361b032016-07-14 07:17:06 +1000[diff] [blame]79#define PNV_PHB_FLAG_CXL (1 << 1) /* Real PHB supporting the cxl kernel API */
Gavin Shanf5bc6b72014-04-24 18:00:09 +1000[diff] [blame]80
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]81struct pnv_phb {
82 struct pci_controller *hose;
83 enum pnv_phb_type type;
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]84 enum pnv_phb_model model;
Gavin Shan8747f362013-06-20 13:21:06 +0800[diff] [blame]85 u64 hub_id;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]86 u64 opal_id;
Gavin Shanf5bc6b72014-04-24 18:00:09 +1000[diff] [blame]87 int flags;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]88 void __iomem *regs;
Benjamin Herrenschmidtfd141d1a2016-07-08 16:37:14 +1000[diff] [blame^]89 u64 regs_phys;
Gavin Shandb1266c2012-08-20 03:49:18 +0000[diff] [blame]90 int initialized;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]91 spinlock_t lock;
92
Gavin Shan37c367f2013-06-20 18:13:25 +0800[diff] [blame]93#ifdef CONFIG_DEBUG_FS
Gavin Shan7f52a5262014-04-24 18:00:18 +1000[diff] [blame]94 int has_dbgfs;
Gavin Shan37c367f2013-06-20 18:13:25 +0800[diff] [blame]95 struct dentry *dbgfs;
96#endif
97
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000[diff] [blame]98#ifdef CONFIG_PCI_MSI
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000[diff] [blame]99 unsigned int msi_base;
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000[diff] [blame]100 unsigned int msi32_support;
Gavin Shanfb1b55d2013-03-05 21:12:37 +0000[diff] [blame]101 struct msi_bitmap msi_bmp;
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000[diff] [blame]102#endif
103 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
Gavin Shan137436c2013-04-25 19:20:59 +0000[diff] [blame]104 unsigned int hwirq, unsigned int virq,
105 unsigned int is_64, struct msi_msg *msg);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]106 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
107 void (*fixup_phb)(struct pci_controller *hose);
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]108 int (*init_m64)(struct pnv_phb *phb);
Gavin Shan96a2f922015-06-19 12:26:17 +1000[diff] [blame]109 void (*reserve_m64_pe)(struct pci_bus *bus,
110 unsigned long *pe_bitmap, bool all);
Gavin Shan1e916772016-05-03 15:41:36 +1000[diff] [blame]111 struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all);
Gavin Shan49dec922014-07-21 14:42:33 +1000[diff] [blame]112 int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
113 void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
114 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]115
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]116 struct {
117 /* Global bridge info */
Gavin Shan92b8f132016-05-03 15:41:24 +1000[diff] [blame]118 unsigned int total_pe_num;
119 unsigned int reserved_pe_idx;
Gavin Shan63803c32016-05-20 16:41:32 +1000[diff] [blame]120 unsigned int root_pe_idx;
121 bool root_pe_populated;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]122
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]123 /* 32-bit MMIO window */
124 unsigned int m32_size;
125 unsigned int m32_segsize;
126 unsigned int m32_pci_base;
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]127
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]128 /* 64-bit MMIO window */
129 unsigned int m64_bar_idx;
130 unsigned long m64_size;
131 unsigned long m64_segsize;
132 unsigned long m64_base;
133 unsigned long m64_bar_alloc;
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]134
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]135 /* IO ports */
136 unsigned int io_size;
137 unsigned int io_segsize;
138 unsigned int io_pci_base;
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]139
Gavin Shan13ce7592016-05-03 15:41:23 +1000[diff] [blame]140 /* PE allocation */
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]141 struct mutex pe_alloc_mutex;
Gavin Shan13ce7592016-05-03 15:41:23 +1000[diff] [blame]142 unsigned long *pe_alloc;
143 struct pnv_ioda_pe *pe_array;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]144
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]145 /* M32 & IO segment maps */
Gavin Shan93289d82016-05-03 15:41:29 +1000[diff] [blame]146 unsigned int *m64_segmap;
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]147 unsigned int *m32_segmap;
148 unsigned int *io_segmap;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]149
Gavin Shan2b923ed2016-05-05 12:04:16 +1000[diff] [blame]150 /* DMA32 segment maps - IODA1 only */
151 unsigned int dma32_count;
152 unsigned int *dma32_segmap;
153
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]154 /* IRQ chip */
155 int irq_chip_init;
156 struct irq_chip irq_chip;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]157
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]158 /* Sorted list of used PE's based
159 * on the sequence of creation
160 */
161 struct list_head pe_list;
162 struct mutex pe_list_mutex;
Gavin Shan137436c2013-04-25 19:20:59 +0000[diff] [blame]163
Gavin Shanc1275622016-05-20 16:41:29 +1000[diff] [blame]164 /* Reverse map of PEs, indexed by {bus, devfn} */
165 unsigned int pe_rmap[0x10000];
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]166 } ioda;
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]167
Brian W Hartca1de5d2013-12-20 13:06:01 -0600[diff] [blame]168 /* PHB and hub status structure */
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]169 union {
170 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
171 struct OpalIoP7IOCPhbErrorData p7ioc;
Gavin Shan93aef2a2013-11-22 16:28:45 +0800[diff] [blame]172 struct OpalIoPhb3ErrorData phb3;
Brian W Hartca1de5d2013-12-20 13:06:01 -0600[diff] [blame]173 struct OpalIoP7IOCErrorData hub_diag;
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]174 } diag;
Brian W Hartca1de5d2013-12-20 13:06:01 -0600[diff] [blame]175
Ian Munsie4361b032016-07-14 07:17:06 +1000[diff] [blame]176#ifdef CONFIG_CXL_BASE
177 struct cxl_afu *cxl_afu;
178#endif
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]179};
180
181extern struct pci_ops pnv_pci_ops;
Alexey Kardashevskiyda004c32015-06-05 16:35:06 +1000[diff] [blame]182extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
183 unsigned long uaddr, enum dma_data_direction direction,
184 struct dma_attrs *attrs);
185extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
Alexey Kardashevskiy05c6cfb2015-06-05 16:35:15 +1000[diff] [blame]186extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
187 unsigned long *hpa, enum dma_data_direction *direction);
Alexey Kardashevskiyda004c32015-06-05 16:35:06 +1000[diff] [blame]188extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]189
Gavin Shan93aef2a2013-11-22 16:28:45 +0800[diff] [blame]190void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
191 unsigned char *log_buff);
Gavin Shan3532a7412015-03-17 16:15:03 +1100[diff] [blame]192int pnv_pci_cfg_read(struct pci_dn *pdn,
Gavin Shan9bf41be2013-06-27 13:46:48 +0800[diff] [blame]193 int where, int size, u32 *val);
Gavin Shan3532a7412015-03-17 16:15:03 +1100[diff] [blame]194int pnv_pci_cfg_write(struct pci_dn *pdn,
Gavin Shan9bf41be2013-06-27 13:46:48 +0800[diff] [blame]195 int where, int size, u32 val);
Alexey Kardashevskiy0eaf4de2015-06-05 16:35:09 +1000[diff] [blame]196extern struct iommu_table *pnv_pci_table_alloc(int nid);
197
198extern long pnv_pci_link_table_and_group(int node, int num,
199 struct iommu_table *tbl,
200 struct iommu_table_group *table_group);
201extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
202 struct iommu_table_group *table_group);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]203extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
204 void *tce_mem, u64 tce_size,
Alexey Kardashevskiy8fa5d452014-06-06 18:44:03 +1000[diff] [blame]205 u64 dma_offset, unsigned page_shift);
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]206extern void pnv_pci_init_ioda_hub(struct device_node *np);
Gavin Shanaa0c0332013-04-25 19:20:57 +0000[diff] [blame]207extern void pnv_pci_init_ioda2_phb(struct device_node *np);
Alistair Popple5d2aa712015-12-17 13:43:13 +1100[diff] [blame]208extern void pnv_pci_init_npu_phb(struct device_node *np);
Gavin Shand92a2082014-04-24 18:00:24 +1000[diff] [blame]209extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
Gavin Shancadf3642015-02-16 14:45:47 +1100[diff] [blame]210extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
Benjamin Herrenschmidt73ed1482013-05-10 16:59:18 +1000[diff] [blame]211
Daniel Axtens92ae0352015-04-28 15:12:05 +1000[diff] [blame]212extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
Gavin Shan1bc74f12016-02-09 15:50:22 +1100[diff] [blame]213extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
Daniel Axtens92ae0352015-04-28 15:12:05 +1000[diff] [blame]214extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
215extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
Ian Munsief4568342016-07-14 07:17:00 +1000[diff] [blame]216extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
217extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
Ian Munsie4361b032016-07-14 07:17:06 +1000[diff] [blame]218extern bool pnv_pci_enable_device_hook(struct pci_dev *dev);
Daniel Axtens92ae0352015-04-28 15:12:05 +1000[diff] [blame]219
Alexey Kardashevskiy7d623e42016-04-29 18:55:21 +1000[diff] [blame]220extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
221 const char *fmt, ...);
222#define pe_err(pe, fmt, ...) \
223 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
224#define pe_warn(pe, fmt, ...) \
225 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
226#define pe_info(pe, fmt, ...) \
227 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
228
Alistair Popple5d2aa712015-12-17 13:43:13 +1100[diff] [blame]229/* Nvlink functions */
Alexey Kardashevskiyf9f83452016-04-29 18:55:20 +1000[diff] [blame]230extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
Benjamin Herrenschmidta34ab7c2016-07-08 16:37:12 +1000[diff] [blame]231extern void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
Alexey Kardashevskiyb5cb9ab2016-04-29 18:55:24 +1000[diff] [blame]232extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
233extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
234 struct iommu_table *tbl);
235extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
236extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
237extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
Alistair Popple5d2aa712015-12-17 13:43:13 +1100[diff] [blame]238
Ian Munsie4361b032016-07-14 07:17:06 +1000[diff] [blame]239
240/* cxl functions */
241extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev);
242extern void pnv_cxl_disable_device(struct pci_dev *dev);
Ian Munsiea2f67d52016-07-14 07:17:10 +1000[diff] [blame]243extern int pnv_cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
244extern void pnv_cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
Ian Munsie4361b032016-07-14 07:17:06 +1000[diff] [blame]245
246
247/* phb ops (cxl switches these when enabling the kernel api on the phb) */
248extern const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops;
249
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]250#endif /* __POWERNV_PCI_H */