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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 2b923ed1bd96cc471bb0f0eddfed6ae4753d717b / . / arch / powerpc / platforms / powernv / pci.h
blob: 14d93911391d87d7fea14cd008248463dc3af492 [file] [log] [blame]
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]1#ifndef __POWERNV_PCI_H
2#define __POWERNV_PCI_H
3
4struct pci_dn;
5
6enum pnv_phb_type {
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]7 PNV_PHB_IODA1 = 0,
8 PNV_PHB_IODA2 = 1,
9 PNV_PHB_NPU = 2,
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]10};
11
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]12/* Precise PHB model for error management */
13enum pnv_phb_model {
14 PNV_PHB_MODEL_UNKNOWN,
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]15 PNV_PHB_MODEL_P7IOC,
Gavin Shanaa0c0332013-04-25 19:20:57 +0000[diff] [blame]16 PNV_PHB_MODEL_PHB3,
Alistair Popple5d2aa712015-12-17 13:43:13 +1100[diff] [blame]17 PNV_PHB_MODEL_NPU,
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]18};
19
Gavin Shan5c9d6d72013-09-06 09:00:03 +0800[diff] [blame]20#define PNV_PCI_DIAG_BUF_SIZE 8192
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]21#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
22#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
23#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]24#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
25#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
Wei Yang781a8682015-03-25 16:23:57 +0800[diff] [blame]26#define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
Alistair Popple5d2aa712015-12-17 13:43:13 +1100[diff] [blame]27#define PNV_IODA_PE_PEER (1 << 6) /* PE has peers */
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]28
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]29/* Data associated with a PE, including IOMMU tracking etc.. */
Gavin Shan4cce9552013-04-25 19:21:00 +0000[diff] [blame]30struct pnv_phb;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]31struct pnv_ioda_pe {
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]32 unsigned long flags;
Gavin Shan4cce9552013-04-25 19:21:00 +0000[diff] [blame]33 struct pnv_phb *phb;
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]34
Alistair Popple5d2aa712015-12-17 13:43:13 +1100[diff] [blame]35#define PNV_IODA_MAX_PEER_PES 8
36 struct pnv_ioda_pe *peers[PNV_IODA_MAX_PEER_PES];
37
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]38 /* A PE can be associated with a single device or an
39 * entire bus (& children). In the former case, pdev
40 * is populated, in the later case, pbus is.
41 */
Wei Yang781a8682015-03-25 16:23:57 +0800[diff] [blame]42#ifdef CONFIG_PCI_IOV
43 struct pci_dev *parent_dev;
44#endif
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]45 struct pci_dev *pdev;
46 struct pci_bus *pbus;
47
48 /* Effective RID (device RID for a device PE and base bus
49 * RID with devfn 0 for a bus PE)
50 */
51 unsigned int rid;
52
53 /* PE number */
54 unsigned int pe_number;
55
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]56 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
Alexey Kardashevskiyb348aa62015-06-05 16:35:08 +1000[diff] [blame]57 struct iommu_table_group table_group;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]58
Benjamin Herrenschmidtcd15b042014-02-11 11:32:38 +1100[diff] [blame]59 /* 64-bit TCE bypass region */
60 bool tce_bypass_enabled;
61 uint64_t tce_bypass_base;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]62
63 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
64 * and -1 if not supported. (It's actually identical to the
65 * PE number)
66 */
67 int mve_number;
68
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]69 /* PEs in compound case */
70 struct pnv_ioda_pe *master;
71 struct list_head slaves;
72
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]73 /* Link in list of PE#s */
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]74 struct list_head list;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]75};
76
Gavin Shanf5bc6b72014-04-24 18:00:09 +1000[diff] [blame]77#define PNV_PHB_FLAG_EEH (1 << 0)
78
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]79struct pnv_phb {
80 struct pci_controller *hose;
81 enum pnv_phb_type type;
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]82 enum pnv_phb_model model;
Gavin Shan8747f362013-06-20 13:21:06 +0800[diff] [blame]83 u64 hub_id;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]84 u64 opal_id;
Gavin Shanf5bc6b72014-04-24 18:00:09 +1000[diff] [blame]85 int flags;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]86 void __iomem *regs;
Gavin Shandb1266c2012-08-20 03:49:18 +0000[diff] [blame]87 int initialized;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]88 spinlock_t lock;
89
Gavin Shan37c367f2013-06-20 18:13:25 +0800[diff] [blame]90#ifdef CONFIG_DEBUG_FS
Gavin Shan7f52a5262014-04-24 18:00:18 +1000[diff] [blame]91 int has_dbgfs;
Gavin Shan37c367f2013-06-20 18:13:25 +0800[diff] [blame]92 struct dentry *dbgfs;
93#endif
94
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000[diff] [blame]95#ifdef CONFIG_PCI_MSI
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000[diff] [blame]96 unsigned int msi_base;
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000[diff] [blame]97 unsigned int msi32_support;
Gavin Shanfb1b55d2013-03-05 21:12:37 +0000[diff] [blame]98 struct msi_bitmap msi_bmp;
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000[diff] [blame]99#endif
100 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
Gavin Shan137436c2013-04-25 19:20:59 +0000[diff] [blame]101 unsigned int hwirq, unsigned int virq,
102 unsigned int is_64, struct msi_msg *msg);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]103 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
104 void (*fixup_phb)(struct pci_controller *hose);
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]105 int (*init_m64)(struct pnv_phb *phb);
Gavin Shan96a2f922015-06-19 12:26:17 +1000[diff] [blame]106 void (*reserve_m64_pe)(struct pci_bus *bus,
107 unsigned long *pe_bitmap, bool all);
Gavin Shan689ee8c2016-05-03 15:41:25 +1000[diff] [blame]108 unsigned int (*pick_m64_pe)(struct pci_bus *bus, bool all);
Gavin Shan49dec922014-07-21 14:42:33 +1000[diff] [blame]109 int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
110 void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
111 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]112
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]113 struct {
114 /* Global bridge info */
Gavin Shan92b8f132016-05-03 15:41:24 +1000[diff] [blame]115 unsigned int total_pe_num;
116 unsigned int reserved_pe_idx;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]117
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]118 /* 32-bit MMIO window */
119 unsigned int m32_size;
120 unsigned int m32_segsize;
121 unsigned int m32_pci_base;
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]122
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]123 /* 64-bit MMIO window */
124 unsigned int m64_bar_idx;
125 unsigned long m64_size;
126 unsigned long m64_segsize;
127 unsigned long m64_base;
128 unsigned long m64_bar_alloc;
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]129
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]130 /* IO ports */
131 unsigned int io_size;
132 unsigned int io_segsize;
133 unsigned int io_pci_base;
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]134
Gavin Shan13ce7592016-05-03 15:41:23 +1000[diff] [blame]135 /* PE allocation */
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]136 struct mutex pe_alloc_mutex;
Gavin Shan13ce7592016-05-03 15:41:23 +1000[diff] [blame]137 unsigned long *pe_alloc;
138 struct pnv_ioda_pe *pe_array;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]139
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]140 /* M32 & IO segment maps */
Gavin Shan93289d82016-05-03 15:41:29 +1000[diff] [blame]141 unsigned int *m64_segmap;
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]142 unsigned int *m32_segmap;
143 unsigned int *io_segmap;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]144
Gavin Shan2b923ed2016-05-05 12:04:16 +1000[diff] [blame^]145 /* DMA32 segment maps - IODA1 only */
146 unsigned int dma32_count;
147 unsigned int *dma32_segmap;
148
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]149 /* IRQ chip */
150 int irq_chip_init;
151 struct irq_chip irq_chip;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]152
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]153 /* Sorted list of used PE's based
154 * on the sequence of creation
155 */
156 struct list_head pe_list;
157 struct mutex pe_list_mutex;
Gavin Shan137436c2013-04-25 19:20:59 +0000[diff] [blame]158
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]159 /* Reverse map of PEs, will have to extend if
160 * we are to support more than 256 PEs, indexed
161 * bus { bus, devfn }
162 */
163 unsigned char pe_rmap[0x10000];
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]164
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]165 /* TCE cache invalidate registers (physical and
166 * remapped)
167 */
168 phys_addr_t tce_inval_reg_phys;
169 __be64 __iomem *tce_inval_reg;
170 } ioda;
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]171
Brian W Hartca1de5d2013-12-20 13:06:01 -0600[diff] [blame]172 /* PHB and hub status structure */
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]173 union {
174 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
175 struct OpalIoP7IOCPhbErrorData p7ioc;
Gavin Shan93aef2a2013-11-22 16:28:45 +0800[diff] [blame]176 struct OpalIoPhb3ErrorData phb3;
Brian W Hartca1de5d2013-12-20 13:06:01 -0600[diff] [blame]177 struct OpalIoP7IOCErrorData hub_diag;
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]178 } diag;
Brian W Hartca1de5d2013-12-20 13:06:01 -0600[diff] [blame]179
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]180};
181
182extern struct pci_ops pnv_pci_ops;
Alexey Kardashevskiyda004c32015-06-05 16:35:06 +1000[diff] [blame]183extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
184 unsigned long uaddr, enum dma_data_direction direction,
185 struct dma_attrs *attrs);
186extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
Alexey Kardashevskiy05c6cfb2015-06-05 16:35:15 +1000[diff] [blame]187extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
188 unsigned long *hpa, enum dma_data_direction *direction);
Alexey Kardashevskiyda004c32015-06-05 16:35:06 +1000[diff] [blame]189extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]190
Gavin Shan93aef2a2013-11-22 16:28:45 +0800[diff] [blame]191void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
192 unsigned char *log_buff);
Gavin Shan3532a7412015-03-17 16:15:03 +1100[diff] [blame]193int pnv_pci_cfg_read(struct pci_dn *pdn,
Gavin Shan9bf41be2013-06-27 13:46:48 +0800[diff] [blame]194 int where, int size, u32 *val);
Gavin Shan3532a7412015-03-17 16:15:03 +1100[diff] [blame]195int pnv_pci_cfg_write(struct pci_dn *pdn,
Gavin Shan9bf41be2013-06-27 13:46:48 +0800[diff] [blame]196 int where, int size, u32 val);
Alexey Kardashevskiy0eaf4de2015-06-05 16:35:09 +1000[diff] [blame]197extern struct iommu_table *pnv_pci_table_alloc(int nid);
198
199extern long pnv_pci_link_table_and_group(int node, int num,
200 struct iommu_table *tbl,
201 struct iommu_table_group *table_group);
202extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
203 struct iommu_table_group *table_group);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]204extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
205 void *tce_mem, u64 tce_size,
Alexey Kardashevskiy8fa5d452014-06-06 18:44:03 +1000[diff] [blame]206 u64 dma_offset, unsigned page_shift);
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]207extern void pnv_pci_init_ioda_hub(struct device_node *np);
Gavin Shanaa0c0332013-04-25 19:20:57 +0000[diff] [blame]208extern void pnv_pci_init_ioda2_phb(struct device_node *np);
Alistair Popple5d2aa712015-12-17 13:43:13 +1100[diff] [blame]209extern void pnv_pci_init_npu_phb(struct device_node *np);
Gavin Shan4cce9552013-04-25 19:21:00 +0000[diff] [blame]210extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
Benjamin Herrenschmidt3ad26e52013-10-11 18:23:53 +1100[diff] [blame]211 __be64 *startp, __be64 *endp, bool rm);
Gavin Shand92a2082014-04-24 18:00:24 +1000[diff] [blame]212extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
Gavin Shancadf3642015-02-16 14:45:47 +1100[diff] [blame]213extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
Benjamin Herrenschmidt73ed1482013-05-10 16:59:18 +1000[diff] [blame]214
Daniel Axtens92ae0352015-04-28 15:12:05 +1000[diff] [blame]215extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
Gavin Shan1bc74f12016-02-09 15:50:22 +1100[diff] [blame]216extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
Daniel Axtens92ae0352015-04-28 15:12:05 +1000[diff] [blame]217extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
218extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
219
Alistair Popple5d2aa712015-12-17 13:43:13 +1100[diff] [blame]220/* Nvlink functions */
221extern void pnv_npu_tce_invalidate_entire(struct pnv_ioda_pe *npe);
222extern void pnv_npu_tce_invalidate(struct pnv_ioda_pe *npe,
223 struct iommu_table *tbl,
224 unsigned long index,
225 unsigned long npages,
226 bool rm);
227extern void pnv_npu_init_dma_pe(struct pnv_ioda_pe *npe);
228extern void pnv_npu_setup_dma_pe(struct pnv_ioda_pe *npe);
229extern int pnv_npu_dma_set_bypass(struct pnv_ioda_pe *npe, bool enabled);
230extern int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask);
231
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]232#endif /* __POWERNV_PCI_H */