blob: acb19517f678b05020fdb3e5af0d5c04d4bb8eae [file] [log] [blame]
Thomas Gleixner2025cf92019-05-29 07:18:02 -07001/* SPDX-License-Identifier: GPL-2.0-only */
Dan Williamse1455742015-07-30 17:57:47 -04002/*
3 * Copyright (c) 2014-2015, Intel Corporation.
Dan Williamse1455742015-07-30 17:57:47 -04004 */
5
6#ifndef __NVDIMM_PFN_H
7#define __NVDIMM_PFN_H
8
9#include <linux/types.h>
Dan Williamsd9cbe092016-03-03 09:14:36 -080010#include <linux/mmzone.h>
Dan Williamse1455742015-07-30 17:57:47 -040011
12#define PFN_SIG_LEN 16
13#define PFN_SIG "NVDIMM_PFN_INFO\0"
Dan Williamsc5ed9262016-05-18 14:50:12 -070014#define DAX_SIG "NVDIMM_DAX_INFO\0"
Dan Williamse1455742015-07-30 17:57:47 -040015
16struct nd_pfn_sb {
17 u8 signature[PFN_SIG_LEN];
18 u8 uuid[16];
19 u8 parent_uuid[16];
20 __le32 flags;
21 __le16 version_major;
22 __le16 version_minor;
Dan Williamscfe30b82016-03-03 09:38:00 -080023 __le64 dataoff; /* relative to namespace_base + start_pad */
Dan Williamse1455742015-07-30 17:57:47 -040024 __le64 npfns;
25 __le32 mode;
Dan Williamscfe30b82016-03-03 09:38:00 -080026 /* minor-version-1 additions for section alignment */
27 __le32 start_pad;
28 __le32 end_trunc;
Dan Williams45a0dac2016-03-31 15:41:18 -070029 /* minor-version-2 record the base alignment of the mapping */
30 __le32 align;
Dan Williams7e3e8882019-07-18 15:58:36 -070031 /* minor-version-3 guarantee the padding and flags are zero */
Aneesh Kumar K.Vedbb52c2019-09-05 21:16:00 +053032 /* minor-version-4 record the page size and struct page size */
33 __le32 page_size;
34 __le16 page_struct_size;
35 u8 padding[3994];
Dan Williamse1455742015-07-30 17:57:47 -040036 __le64 checksum;
37};
Dan Williamsd9cbe092016-03-03 09:14:36 -080038
Dan Williamse1455742015-07-30 17:57:47 -040039#endif /* __NVDIMM_PFN_H */