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Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
Jesse Barnesd1d70672014-05-28 14:39:03 -070028#include <linux/async.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080029#include <linux/i2c.h>
Damien Lespiau178f7362013-08-06 20:32:18 +010030#include <linux/hdmi.h>
David Howells760285e2012-10-02 18:01:07 +010031#include <drm/i915_drm.h>
Jesse Barnes80824002009-09-10 15:28:06 -070032#include "i915_drv.h"
David Howells760285e2012-10-02 18:01:07 +010033#include <drm/drm_crtc.h>
34#include <drm/drm_crtc_helper.h>
35#include <drm/drm_fb_helper.h>
Dave Airlie0e32b392014-05-02 14:02:48 +100036#include <drm/drm_dp_mst_helper.h>
Gustavo Padovaneeca7782014-09-05 17:04:46 -030037#include <drm/drm_rect.h>
Ander Conselvan de Oliveira10f81c12015-03-20 16:18:01 +020038#include <drm/drm_atomic.h>
Chris Wilson913d8d12010-08-07 11:01:35 +010039
Daniel Vetter1d5bfac2013-03-28 00:03:25 +010040/**
41 * _wait_for - magic (register) wait macro
42 *
43 * Does the right thing for modeset paths when run under kdgb or similar atomic
44 * contexts. Note that it's important that we check the condition again after
45 * having timed out, since the timeout could be due to preemption or similar and
46 * we've never had a chance to check the condition before the timeout.
47 */
Chris Wilson481b6af2010-08-23 17:43:35 +010048#define _wait_for(COND, MS, W) ({ \
Daniel Vetter1d5bfac2013-03-28 00:03:25 +010049 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
Chris Wilson913d8d12010-08-07 11:01:35 +010050 int ret__ = 0; \
Akshay Joshi0206e352011-08-16 15:34:10 -040051 while (!(COND)) { \
Chris Wilson913d8d12010-08-07 11:01:35 +010052 if (time_after(jiffies, timeout__)) { \
Daniel Vetter1d5bfac2013-03-28 00:03:25 +010053 if (!(COND)) \
54 ret__ = -ETIMEDOUT; \
Chris Wilson913d8d12010-08-07 11:01:35 +010055 break; \
56 } \
Ville Syrjälä9848de02015-03-20 21:28:08 +020057 if ((W) && drm_can_sleep()) { \
58 usleep_range((W)*1000, (W)*2000); \
Ben Widawsky0cc27642012-09-01 22:59:48 -070059 } else { \
60 cpu_relax(); \
61 } \
Chris Wilson913d8d12010-08-07 11:01:35 +010062 } \
63 ret__; \
64})
65
Chris Wilson481b6af2010-08-23 17:43:35 +010066#define wait_for(COND, MS) _wait_for(COND, MS, 1)
67#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
Daniel Vetter6effa332013-03-28 11:31:04 +010068#define wait_for_atomic_us(COND, US) _wait_for((COND), \
69 DIV_ROUND_UP((US), 1000), 0)
Chris Wilson481b6af2010-08-23 17:43:35 +010070
Jani Nikula49938ac2014-01-10 17:10:20 +020071#define KHz(x) (1000 * (x))
72#define MHz(x) KHz(1000 * (x))
Chris Wilson021357a2010-09-07 20:54:59 +010073
Jesse Barnes79e53942008-11-07 14:24:08 -080074/*
75 * Display related stuff
76 */
77
78/* store information about an Ixxx DVO */
79/* The i830->i865 use multiple DVOs with multiple i2cs */
80/* the i915, i945 have a single sDVO i2c bus - which is different */
81#define MAX_OUTPUTS 6
82/* maximum connectors per crtcs in the mode set */
Jesse Barnes79e53942008-11-07 14:24:08 -080083
Sagar Kamble4726e0b2014-03-10 17:06:23 +053084/* Maximum cursor sizes */
85#define GEN2_CURSOR_WIDTH 64
86#define GEN2_CURSOR_HEIGHT 64
Damien Lespiau068be562014-03-28 14:17:49 +000087#define MAX_CURSOR_WIDTH 256
88#define MAX_CURSOR_HEIGHT 256
Sagar Kamble4726e0b2014-03-10 17:06:23 +053089
Jesse Barnes79e53942008-11-07 14:24:08 -080090#define INTEL_I2C_BUS_DVO 1
91#define INTEL_I2C_BUS_SDVO 2
92
93/* these are outputs from the chip - integrated only
94 external chips are via DVO or SDVO output */
Paulo Zanoni6847d71b2014-10-27 17:47:52 -020095enum intel_output_type {
96 INTEL_OUTPUT_UNUSED = 0,
97 INTEL_OUTPUT_ANALOG = 1,
98 INTEL_OUTPUT_DVO = 2,
99 INTEL_OUTPUT_SDVO = 3,
100 INTEL_OUTPUT_LVDS = 4,
101 INTEL_OUTPUT_TVOUT = 5,
102 INTEL_OUTPUT_HDMI = 6,
103 INTEL_OUTPUT_DISPLAYPORT = 7,
104 INTEL_OUTPUT_EDP = 8,
105 INTEL_OUTPUT_DSI = 9,
106 INTEL_OUTPUT_UNKNOWN = 10,
107 INTEL_OUTPUT_DP_MST = 11,
108};
Jesse Barnes79e53942008-11-07 14:24:08 -0800109
110#define INTEL_DVO_CHIP_NONE 0
111#define INTEL_DVO_CHIP_LVDS 1
112#define INTEL_DVO_CHIP_TMDS 2
113#define INTEL_DVO_CHIP_TVOUT 4
114
Shobhit Kumardfba2e22014-04-14 11:18:24 +0530115#define INTEL_DSI_VIDEO_MODE 0
116#define INTEL_DSI_COMMAND_MODE 1
Jani Nikula72ffa332013-08-27 15:12:17 +0300117
Jesse Barnes79e53942008-11-07 14:24:08 -0800118struct intel_framebuffer {
119 struct drm_framebuffer base;
Chris Wilson05394f32010-11-08 19:18:58 +0000120 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -0800121};
122
Chris Wilson37811fc2010-08-25 22:45:57 +0100123struct intel_fbdev {
124 struct drm_fb_helper helper;
Jesse Barnes8bcd4552014-02-07 12:10:38 -0800125 struct intel_framebuffer *fb;
Chris Wilson37811fc2010-08-25 22:45:57 +0100126 struct list_head fbdev_list;
127 struct drm_display_mode *our_mode;
Jesse Barnesd978ef12014-03-07 08:57:51 -0800128 int preferred_bpp;
Chris Wilson37811fc2010-08-25 22:45:57 +0100129};
Jesse Barnes79e53942008-11-07 14:24:08 -0800130
Eric Anholt21d40d32010-03-25 11:11:14 -0700131struct intel_encoder {
Chris Wilson4ef69c72010-09-09 15:14:28 +0100132 struct drm_encoder base;
Daniel Vetter9a935852012-07-05 22:34:27 +0200133 /*
134 * The new crtc this encoder will be driven from. Only differs from
135 * base->crtc while a modeset is in progress.
136 */
137 struct intel_crtc *new_crtc;
138
Paulo Zanoni6847d71b2014-10-27 17:47:52 -0200139 enum intel_output_type type;
Ville Syrjäläbc079e82014-03-03 16:15:28 +0200140 unsigned int cloneable;
Daniel Vetter5ab432e2012-06-30 08:59:56 +0200141 bool connectors_active;
Eric Anholt21d40d32010-03-25 11:11:14 -0700142 void (*hot_plug)(struct intel_encoder *);
Daniel Vetter7ae89232013-03-27 00:44:52 +0100143 bool (*compute_config)(struct intel_encoder *,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200144 struct intel_crtc_state *);
Daniel Vetterdafd2262012-11-26 17:22:07 +0100145 void (*pre_pll_enable)(struct intel_encoder *);
Daniel Vetterbf49ec82012-09-06 22:15:40 +0200146 void (*pre_enable)(struct intel_encoder *);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +0200147 void (*enable)(struct intel_encoder *);
Daniel Vetter6cc5f342013-03-27 00:44:53 +0100148 void (*mode_set)(struct intel_encoder *intel_encoder);
Daniel Vetteref9c3ae2012-06-29 22:40:09 +0200149 void (*disable)(struct intel_encoder *);
Daniel Vetterbf49ec82012-09-06 22:15:40 +0200150 void (*post_disable)(struct intel_encoder *);
Daniel Vetterf0947c32012-07-02 13:10:34 +0200151 /* Read out the current hw state of this connector, returning true if
152 * the encoder is active. If the encoder is enabled it also set the pipe
153 * it is connected to in the pipe parameter. */
154 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
Jesse Barnes045ac3b2013-05-14 17:08:26 -0700155 /* Reconstructs the equivalent mode flags for the current hardware
Daniel Vetterfdafa9e2013-06-12 11:47:24 +0200156 * state. This must be called _after_ display->get_pipe_config has
Xiong Zhang63000ef2013-06-28 12:59:06 +0800157 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
158 * be set correctly before calling this function. */
Jesse Barnes045ac3b2013-05-14 17:08:26 -0700159 void (*get_config)(struct intel_encoder *,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200160 struct intel_crtc_state *pipe_config);
Imre Deak07f9cd02014-08-18 14:42:45 +0300161 /*
162 * Called during system suspend after all pending requests for the
163 * encoder are flushed (for example for DP AUX transactions) and
164 * device interrupts are disabled.
165 */
166 void (*suspend)(struct intel_encoder *);
Ma Lingf8aed702009-08-24 13:50:24 +0800167 int crtc_mask;
Egbert Eich1d843f92013-02-25 12:06:49 -0500168 enum hpd_pin hpd_pin;
Jesse Barnes79e53942008-11-07 14:24:08 -0800169};
170
Jani Nikula1d508702012-10-19 14:51:49 +0300171struct intel_panel {
Jani Nikuladd06f902012-10-19 14:51:50 +0300172 struct drm_display_mode *fixed_mode;
Vandana Kannanec9ed192013-12-10 13:37:36 +0530173 struct drm_display_mode *downclock_mode;
Jani Nikula4d891522012-10-26 12:03:59 +0300174 int fitting_mode;
Jani Nikula58c68772013-11-08 16:48:54 +0200175
176 /* backlight */
177 struct {
Jani Nikulac91c9f32013-11-08 16:48:55 +0200178 bool present;
Jani Nikula58c68772013-11-08 16:48:54 +0200179 u32 level;
Jani Nikula6dda7302014-06-24 18:27:40 +0300180 u32 min;
Jani Nikula7bd688c2013-11-08 16:48:56 +0200181 u32 max;
Jani Nikula58c68772013-11-08 16:48:54 +0200182 bool enabled;
Jani Nikula636baeb2013-11-08 16:49:02 +0200183 bool combination_mode; /* gen 2/4 only */
184 bool active_low_pwm;
Jani Nikula58c68772013-11-08 16:48:54 +0200185 struct backlight_device *device;
186 } backlight;
Jani Nikulaab656bb2014-08-13 12:10:12 +0300187
188 void (*backlight_power)(struct intel_connector *, bool enable);
Jani Nikula1d508702012-10-19 14:51:49 +0300189};
190
Zhenyu Wang5daa55e2010-03-30 14:39:28 +0800191struct intel_connector {
192 struct drm_connector base;
Daniel Vetter9a935852012-07-05 22:34:27 +0200193 /*
194 * The fixed encoder this connector is connected to.
195 */
Chris Wilsondf0e9242010-09-09 16:20:55 +0100196 struct intel_encoder *encoder;
Daniel Vetter9a935852012-07-05 22:34:27 +0200197
198 /*
199 * The new encoder this connector will be driven. Only differs from
200 * encoder while a modeset is in progress.
201 */
202 struct intel_encoder *new_encoder;
203
Daniel Vetterf0947c32012-07-02 13:10:34 +0200204 /* Reads out the current hw, returning true if the connector is enabled
205 * and active (i.e. dpms ON state). */
206 bool (*get_hw_state)(struct intel_connector *);
Jani Nikula1d508702012-10-19 14:51:49 +0300207
Imre Deak4932e2c2014-02-11 17:12:48 +0200208 /*
209 * Removes all interfaces through which the connector is accessible
210 * - like sysfs, debugfs entries -, so that no new operations can be
211 * started on the connector. Also makes sure all currently pending
212 * operations finish before returing.
213 */
214 void (*unregister)(struct intel_connector *);
215
Jani Nikula1d508702012-10-19 14:51:49 +0300216 /* Panel info for eDP and LVDS */
217 struct intel_panel panel;
Jani Nikula9cd300e2012-10-19 14:51:52 +0300218
219 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
220 struct edid *edid;
Chris Wilsonbeb60602014-09-02 20:04:00 +0100221 struct edid *detect_edid;
Egbert Eich821450c2013-04-16 13:36:55 +0200222
223 /* since POLL and HPD connectors may use the same HPD line keep the native
224 state of connector->polled in case hotplug storm detection changes it */
225 u8 polled;
Dave Airlie0e32b392014-05-02 14:02:48 +1000226
227 void *port; /* store this opaque as its illegal to dereference it */
228
229 struct intel_dp *mst_port;
Zhenyu Wang5daa55e2010-03-30 14:39:28 +0800230};
231
Ville Syrjälä80ad9202013-04-19 14:36:51 +0300232typedef struct dpll {
233 /* given values */
234 int n;
235 int m1, m2;
236 int p1, p2;
237 /* derived values */
238 int dot;
239 int vco;
240 int m;
241 int p;
242} intel_clock_t;
243
Gustavo Padovaneeca7782014-09-05 17:04:46 -0300244struct intel_plane_state {
Matt Roper2b875c22014-12-01 15:40:13 -0800245 struct drm_plane_state base;
Gustavo Padovaneeca7782014-09-05 17:04:46 -0300246 struct drm_rect src;
247 struct drm_rect dst;
248 struct drm_rect clip;
Gustavo Padovaneeca7782014-09-05 17:04:46 -0300249 bool visible;
Matt Roper32b7eee2014-12-24 07:59:06 -0800250
251 /*
Chandra Kondurube41e332015-04-07 15:28:36 -0700252 * scaler_id
253 * = -1 : not using a scaler
254 * >= 0 : using a scalers
255 *
256 * plane requiring a scaler:
257 * - During check_plane, its bit is set in
258 * crtc_state->scaler_state.scaler_users by calling helper function
259 * update_scaler_users.
260 * - scaler_id indicates the scaler it got assigned.
261 *
262 * plane doesn't require a scaler:
263 * - this can happen when scaling is no more required or plane simply
264 * got disabled.
265 * - During check_plane, corresponding bit is reset in
266 * crtc_state->scaler_state.scaler_users by calling helper function
267 * update_scaler_users.
268 */
269 int scaler_id;
Gustavo Padovaneeca7782014-09-05 17:04:46 -0300270};
271
Damien Lespiau5724dbd2015-01-20 12:51:52 +0000272struct intel_initial_plane_config {
Damien Lespiau2d140302015-02-05 17:22:18 +0000273 struct intel_framebuffer *fb;
Damien Lespiau49af4492015-01-20 12:51:44 +0000274 unsigned int tiling;
Jesse Barnes46f297f2014-03-07 08:57:48 -0800275 int size;
276 u32 base;
277};
278
Chandra Kondurube41e332015-04-07 15:28:36 -0700279#define SKL_MIN_SRC_W 8
280#define SKL_MAX_SRC_W 4096
281#define SKL_MIN_SRC_H 8
Chandra Konduru6156a452015-04-27 13:48:39 -0700282#define SKL_MAX_SRC_H 4096
Chandra Kondurube41e332015-04-07 15:28:36 -0700283#define SKL_MIN_DST_W 8
284#define SKL_MAX_DST_W 4096
285#define SKL_MIN_DST_H 8
Chandra Konduru6156a452015-04-27 13:48:39 -0700286#define SKL_MAX_DST_H 4096
Chandra Kondurube41e332015-04-07 15:28:36 -0700287
288struct intel_scaler {
289 int id;
290 int in_use;
291 uint32_t mode;
292};
293
294struct intel_crtc_scaler_state {
295#define SKL_NUM_SCALERS 2
296 struct intel_scaler scalers[SKL_NUM_SCALERS];
297
298 /*
299 * scaler_users: keeps track of users requesting scalers on this crtc.
300 *
301 * If a bit is set, a user is using a scaler.
302 * Here user can be a plane or crtc as defined below:
303 * bits 0-30 - plane (bit position is index from drm_plane_index)
304 * bit 31 - crtc
305 *
306 * Instead of creating a new index to cover planes and crtc, using
307 * existing drm_plane_index for planes which is well less than 31
308 * planes and bit 31 for crtc. This should be fine to cover all
309 * our platforms.
310 *
311 * intel_atomic_setup_scalers will setup available scalers to users
312 * requesting scalers. It will gracefully fail if request exceeds
313 * avilability.
314 */
315#define SKL_CRTC_INDEX 31
316 unsigned scaler_users;
317
318 /* scaler used by crtc for panel fitting purpose */
319 int scaler_id;
320};
321
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200322struct intel_crtc_state {
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +0200323 struct drm_crtc_state base;
324
Daniel Vetterbb760062013-06-06 14:55:52 +0200325 /**
326 * quirks - bitfield with hw state readout quirks
327 *
328 * For various reasons the hw state readout code might not be able to
329 * completely faithfully read out the current state. These cases are
330 * tracked with quirk flags so that fastboot and state checker can act
331 * accordingly.
332 */
Daniel Vetter99535992014-04-13 12:00:33 +0200333#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
334#define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */
Daniel Vetterbb760062013-06-06 14:55:52 +0200335 unsigned long quirks;
336
Ville Syrjälä37327ab2013-09-04 18:25:28 +0300337 /* Pipe source size (ie. panel fitter input size)
338 * All planes will be positioned inside this space,
339 * and get clipped at the edges. */
340 int pipe_src_w, pipe_src_h;
341
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100342 /* Whether to set up the PCH/FDI. Note that we never allow sharing
343 * between pch encoders and cpu encoders. */
344 bool has_pch_encoder;
Daniel Vetter50f3b012013-03-27 00:44:56 +0100345
Jesse Barnese43823e2014-11-05 14:26:08 -0800346 /* Are we sending infoframes on the attached port */
347 bool has_infoframe;
348
Daniel Vetter3b117c82013-04-17 20:15:07 +0200349 /* CPU Transcoder for the pipe. Currently this can only differ from the
350 * pipe on Haswell (where we have a special eDP transcoder). */
351 enum transcoder cpu_transcoder;
352
Daniel Vetter50f3b012013-03-27 00:44:56 +0100353 /*
354 * Use reduced/limited/broadcast rbg range, compressing from the full
355 * range fed into the crtcs.
356 */
357 bool limited_color_range;
358
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200359 /* DP has a bunch of special case unfortunately, so mark the pipe
360 * accordingly. */
361 bool has_dp_encoder;
Daniel Vetterd8b32242013-04-25 17:54:44 +0200362
Daniel Vetter6897b4b52014-04-24 23:54:47 +0200363 /* Whether we should send NULL infoframes. Required for audio. */
364 bool has_hdmi_sink;
365
Daniel Vetter9ed109a2014-04-24 23:54:52 +0200366 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
367 * has_dp_encoder is set. */
368 bool has_audio;
369
Daniel Vetterd8b32242013-04-25 17:54:44 +0200370 /*
371 * Enable dithering, used when the selected pipe bpp doesn't match the
372 * plane bpp.
373 */
Daniel Vetter965e0c42013-03-27 00:44:57 +0100374 bool dither;
Daniel Vetterf47709a2013-03-28 10:42:02 +0100375
376 /* Controls for the clock computation, to override various stages. */
377 bool clock_set;
378
Daniel Vetter09ede542013-04-30 14:01:45 +0200379 /* SDVO TV has a bunch of special case. To make multifunction encoders
380 * work correctly, we need to track this at runtime.*/
381 bool sdvo_tv_clock;
382
Daniel Vettere29c22c2013-02-21 00:00:16 +0100383 /*
384 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
385 * required. This is set in the 2nd loop of calling encoder's
386 * ->compute_config if the first pick doesn't work out.
387 */
388 bool bw_constrained;
389
Daniel Vetterf47709a2013-03-28 10:42:02 +0100390 /* Settings for the intel dpll used on pretty much everything but
391 * haswell. */
Ville Syrjälä80ad9202013-04-19 14:36:51 +0300392 struct dpll dpll;
Daniel Vetterf47709a2013-03-28 10:42:02 +0100393
Daniel Vettera43f6e02013-06-07 23:10:32 +0200394 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
395 enum intel_dpll_id shared_dpll;
396
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +0000397 /*
398 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
399 * - enum skl_dpll on SKL
400 */
Daniel Vetterde7cfc62014-06-25 22:01:54 +0300401 uint32_t ddi_pll_sel;
402
Daniel Vetter66e985c2013-06-05 13:34:20 +0200403 /* Actual register state of the dpll, for shared dpll cross-checking. */
404 struct intel_dpll_hw_state dpll_hw_state;
405
Daniel Vetter965e0c42013-03-27 00:44:57 +0100406 int pipe_bpp;
Daniel Vetter6cf86a52013-04-02 23:38:10 +0200407 struct intel_link_m_n dp_m_n;
Daniel Vetterff9a6752013-06-01 17:16:21 +0200408
Pradeep Bhat439d7ac2014-04-05 12:13:28 +0530409 /* m2_n2 for eDP downclock */
410 struct intel_link_m_n dp_m2_n2;
Vandana Kannanf769cd22014-08-05 07:51:22 -0700411 bool has_drrs;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +0530412
Daniel Vetterff9a6752013-06-01 17:16:21 +0200413 /*
414 * Frequence the dpll for the port should run at. Differs from the
Ville Syrjälä3c52f4e2013-09-06 23:28:59 +0300415 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
416 * already multiplied by pixel_multiplier.
Daniel Vetterdf92b1e2013-03-28 10:41:58 +0100417 */
Daniel Vetterff9a6752013-06-01 17:16:21 +0200418 int port_clock;
419
Daniel Vetter6cc5f342013-03-27 00:44:53 +0100420 /* Used by SDVO (and if we ever fix it, HDMI). */
421 unsigned pixel_multiplier;
Jesse Barnes2dd24552013-04-25 12:55:01 -0700422
423 /* Panel fitter controls for gen2-gen4 + VLV */
Jesse Barnesb074cec2013-04-25 12:55:02 -0700424 struct {
425 u32 control;
426 u32 pgm_ratios;
Daniel Vetter68fc8742013-04-25 22:52:16 +0200427 u32 lvds_border_bits;
Jesse Barnesb074cec2013-04-25 12:55:02 -0700428 } gmch_pfit;
429
430 /* Panel fitter placement and size for Ironlake+ */
431 struct {
432 u32 pos;
433 u32 size;
Chris Wilsonfd4daa92013-08-27 17:04:17 +0100434 bool enabled;
Daniel Vetterfabf6e52014-05-29 14:10:22 +0200435 bool force_thru;
Jesse Barnesb074cec2013-04-25 12:55:02 -0700436 } pch_pfit;
Daniel Vetter33d29b12013-02-13 18:04:45 +0100437
Daniel Vetterca3a0ff2013-02-14 16:54:22 +0100438 /* FDI configuration, only valid if has_pch_encoder is set. */
Daniel Vetter33d29b12013-02-13 18:04:45 +0100439 int fdi_lanes;
Daniel Vetterca3a0ff2013-02-14 16:54:22 +0100440 struct intel_link_m_n fdi_m_n;
Paulo Zanoni42db64e2013-05-31 16:33:22 -0300441
442 bool ips_enabled;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +0300443
444 bool double_wide;
Dave Airlie0e32b392014-05-02 14:02:48 +1000445
446 bool dp_encoder_is_mst;
447 int pbn;
Chandra Kondurube41e332015-04-07 15:28:36 -0700448
449 struct intel_crtc_scaler_state scaler_state;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100450};
451
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +0300452struct intel_pipe_wm {
453 struct intel_wm_level wm[5];
454 uint32_t linetime;
455 bool fbc_wm_enabled;
Ville Syrjälä2a44b762014-03-07 18:32:09 +0200456 bool pipe_enabled;
457 bool sprites_enabled;
458 bool sprites_scaled;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +0300459};
460
Sourab Gupta84c33a62014-06-02 16:47:17 +0530461struct intel_mmio_flip {
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +0200462 struct work_struct work;
Daniel Vettereed29a52015-05-21 14:21:25 +0200463 struct drm_i915_gem_request *req;
Chris Wilsonb2cfe0a2015-04-27 13:41:16 +0100464 struct intel_crtc *crtc;
Sourab Gupta84c33a62014-06-02 16:47:17 +0530465};
466
Pradeep Bhat2ac96d22014-11-04 17:06:40 +0000467struct skl_pipe_wm {
468 struct skl_wm_level wm[8];
469 struct skl_wm_level trans_wm;
470 uint32_t linetime;
471};
472
Matt Roper32b7eee2014-12-24 07:59:06 -0800473/*
474 * Tracking of operations that need to be performed at the beginning/end of an
475 * atomic commit, outside the atomic section where interrupts are disabled.
476 * These are generally operations that grab mutexes or might otherwise sleep
477 * and thus can't be run with interrupts disabled.
478 */
479struct intel_crtc_atomic_commit {
Matt Roperc34c9ee2014-12-23 10:41:50 -0800480 /* vblank evasion */
481 bool evade;
482 unsigned start_vbl_count;
483
Matt Roper32b7eee2014-12-24 07:59:06 -0800484 /* Sleepable operations to perform before commit */
485 bool wait_for_flips;
486 bool disable_fbc;
487 bool pre_disable_primary;
488 bool update_wm;
Matt Roperea2c67b2014-12-23 10:41:52 -0800489 unsigned disabled_planes;
Matt Roper32b7eee2014-12-24 07:59:06 -0800490
491 /* Sleepable operations to perform after commit */
492 unsigned fb_bits;
493 bool wait_vblank;
494 bool update_fbc;
495 bool post_enable_primary;
496 unsigned update_sprite_watermarks;
497};
498
Jesse Barnes79e53942008-11-07 14:24:08 -0800499struct intel_crtc {
500 struct drm_crtc base;
Jesse Barnes80824002009-09-10 15:28:06 -0700501 enum pipe pipe;
502 enum plane plane;
Jesse Barnes79e53942008-11-07 14:24:08 -0800503 u8 lut_r[256], lut_g[256], lut_b[256];
Daniel Vetter08a48462012-07-02 11:43:47 +0200504 /*
505 * Whether the crtc and the connected output pipeline is active. Implies
506 * that crtc->enabled is set, i.e. the current mode configuration has
507 * some outputs connected to this crtc.
Daniel Vetter08a48462012-07-02 11:43:47 +0200508 */
509 bool active;
Imre Deak6efdf352013-10-16 17:25:52 +0300510 unsigned long enabled_power_domains;
Jesse Barnes652c3932009-08-17 13:31:43 -0700511 bool lowfreq_avail;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200512 struct intel_overlay *overlay;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -0500513 struct intel_unpin_work *unpin_work;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +0100514
Chris Wilsonb4a98e52012-11-01 09:26:26 +0000515 atomic_t unpin_work_count;
516
Daniel Vettere506a0c2012-07-05 12:17:29 +0200517 /* Display surface base address adjustement for pageflips. Note that on
518 * gen4+ this only adjusts up to a tile, offsets within a tile are
519 * handled in the hw itself (with the TILEOFF register). */
520 unsigned long dspaddr_offset;
521
Chris Wilson05394f32010-11-08 19:18:58 +0000522 struct drm_i915_gem_object *cursor_bo;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +0100523 uint32_t cursor_addr;
Chris Wilson4b0e3332014-05-30 16:35:26 +0300524 uint32_t cursor_cntl;
Ville Syrjälädc41c152014-08-13 11:57:05 +0300525 uint32_t cursor_size;
Chris Wilson4b0e3332014-05-30 16:35:26 +0300526 uint32_t cursor_base;
Jesse Barnes4b645f12011-10-12 09:51:31 -0700527
Damien Lespiau5724dbd2015-01-20 12:51:52 +0000528 struct intel_initial_plane_config plane_config;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200529 struct intel_crtc_state *config;
Ville Syrjälä76688512014-01-10 11:28:06 +0200530 bool new_enabled;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100531
Ville Syrjälä10d83732013-01-29 18:13:34 +0200532 /* reset counter value when the last flip was submitted */
533 unsigned int reset_counter;
Paulo Zanoni86642812013-04-12 17:57:57 -0300534
535 /* Access to these should be protected by dev_priv->irq_lock. */
536 bool cpu_fifo_underrun_disabled;
537 bool pch_fifo_underrun_disabled;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +0300538
539 /* per-pipe watermark state */
540 struct {
541 /* watermarks currently being used */
542 struct intel_pipe_wm active;
Pradeep Bhat2ac96d22014-11-04 17:06:40 +0000543 /* SKL wm values currently in use */
544 struct skl_pipe_wm skl_active;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +0300545 } wm;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300546
Ville Syrjälä80715b22014-05-15 20:23:23 +0300547 int scanline_offset;
Matt Roper32b7eee2014-12-24 07:59:06 -0800548
549 struct intel_crtc_atomic_commit atomic;
Chandra Kondurube41e332015-04-07 15:28:36 -0700550
551 /* scalers available on this crtc */
552 int num_scalers;
Jesse Barnes79e53942008-11-07 14:24:08 -0800553};
554
Ville Syrjäläc35426d2013-08-07 13:29:50 +0300555struct intel_plane_wm_parameters {
556 uint32_t horiz_pixels;
Damien Lespiaued57cb82014-07-15 09:21:24 +0200557 uint32_t vert_pixels;
Chandra Konduru2cd601c2015-04-27 15:47:37 -0700558 /*
559 * For packed pixel formats:
560 * bytes_per_pixel - holds bytes per pixel
561 * For planar pixel formats:
562 * bytes_per_pixel - holds bytes per pixel for uv-plane
563 * y_bytes_per_pixel - holds bytes per pixel for y-plane
564 */
Ville Syrjäläc35426d2013-08-07 13:29:50 +0300565 uint8_t bytes_per_pixel;
Chandra Konduru2cd601c2015-04-27 15:47:37 -0700566 uint8_t y_bytes_per_pixel;
Ville Syrjäläc35426d2013-08-07 13:29:50 +0300567 bool enabled;
568 bool scaled;
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +0000569 u64 tiling;
Tvrtko Ursulin1fc0a8f2015-03-23 11:10:38 +0000570 unsigned int rotation;
Ville Syrjäläc35426d2013-08-07 13:29:50 +0300571};
572
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800573struct intel_plane {
574 struct drm_plane base;
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700575 int plane;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800576 enum pipe pipe;
Damien Lespiau2d354c32012-10-22 18:19:27 +0100577 bool can_scale;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800578 int max_downscale;
Paulo Zanoni526682e2013-05-24 11:59:18 -0300579
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200580 /* FIXME convert to properties */
581 struct drm_intel_sprite_colorkey ckey;
582
Paulo Zanoni526682e2013-05-24 11:59:18 -0300583 /* Since we need to change the watermarks before/after
584 * enabling/disabling the planes, we need to store the parameters here
585 * as the other pieces of the struct may not reflect the values we want
586 * for the watermark calculations. Currently only Haswell uses this.
587 */
Ville Syrjäläc35426d2013-08-07 13:29:50 +0300588 struct intel_plane_wm_parameters wm;
Paulo Zanoni526682e2013-05-24 11:59:18 -0300589
Matt Roper8e7d6882015-01-21 16:35:41 -0800590 /*
591 * NOTE: Do not place new plane state fields here (e.g., when adding
592 * new plane properties). New runtime state should now be placed in
593 * the intel_plane_state structure and accessed via drm_plane->state.
594 */
595
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800596 void (*update_plane)(struct drm_plane *plane,
Ville Syrjäläb39d53f2013-08-06 22:24:09 +0300597 struct drm_crtc *crtc,
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800598 struct drm_framebuffer *fb,
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800599 int crtc_x, int crtc_y,
600 unsigned int crtc_w, unsigned int crtc_h,
601 uint32_t x, uint32_t y,
602 uint32_t src_w, uint32_t src_h);
Ville Syrjäläb39d53f2013-08-06 22:24:09 +0300603 void (*disable_plane)(struct drm_plane *plane,
Maarten Lankhorsta8ad0d82015-04-21 17:12:51 +0300604 struct drm_crtc *crtc, bool force);
Matt Roperc59cb172014-12-01 15:40:16 -0800605 int (*check_plane)(struct drm_plane *plane,
606 struct intel_plane_state *state);
607 void (*commit_plane)(struct drm_plane *plane,
608 struct intel_plane_state *state);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800609};
610
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300611struct intel_watermark_params {
612 unsigned long fifo_size;
613 unsigned long max_wm;
614 unsigned long default_wm;
615 unsigned long guard_size;
616 unsigned long cacheline_size;
617};
618
619struct cxsr_latency {
620 int is_desktop;
621 int is_ddr3;
622 unsigned long fsb_freq;
623 unsigned long mem_freq;
624 unsigned long display_sr;
625 unsigned long display_hpll_disable;
626 unsigned long cursor_sr;
627 unsigned long cursor_hpll_disable;
628};
629
Jesse Barnes79e53942008-11-07 14:24:08 -0800630#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
Ander Conselvan de Oliveira10f81c12015-03-20 16:18:01 +0200631#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
Zhenyu Wang5daa55e2010-03-30 14:39:28 +0800632#define to_intel_connector(x) container_of(x, struct intel_connector, base)
Chris Wilson4ef69c72010-09-09 15:14:28 +0100633#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
Jesse Barnes79e53942008-11-07 14:24:08 -0800634#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800635#define to_intel_plane(x) container_of(x, struct intel_plane, base)
Matt Roperea2c67b2014-12-23 10:41:52 -0800636#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
Matt Roper155e6362014-07-07 18:21:47 -0700637#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -0800638
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -0300639struct intel_hdmi {
Paulo Zanonib242b7f2013-02-18 19:00:26 -0300640 u32 hdmi_reg;
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -0300641 int ddc_bus;
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -0300642 uint32_t color_range;
Ville Syrjälä55bc60d2013-01-17 16:31:29 +0200643 bool color_range_auto;
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -0300644 bool has_hdmi_sink;
645 bool has_audio;
646 enum hdmi_force_audio force_audio;
Ville Syrjäläabedc072013-01-17 16:31:31 +0200647 bool rgb_quant_range_selectable;
Vandana Kannan94a11dd2014-06-11 11:06:01 +0530648 enum hdmi_picture_aspect aspect_ratio;
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -0300649 void (*write_infoframe)(struct drm_encoder *encoder,
Damien Lespiau178f7362013-08-06 20:32:18 +0100650 enum hdmi_infoframe_type type,
Ville Syrjäläfff63862013-12-10 15:19:08 +0200651 const void *frame, ssize_t len);
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300652 void (*set_infoframes)(struct drm_encoder *encoder,
Daniel Vetter6897b4b52014-04-24 23:54:47 +0200653 bool enable,
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300654 struct drm_display_mode *adjusted_mode);
Jesse Barnese43823e2014-11-05 14:26:08 -0800655 bool (*infoframe_enabled)(struct drm_encoder *encoder);
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -0300656};
657
Dave Airlie0e32b392014-05-02 14:02:48 +1000658struct intel_dp_mst_encoder;
Adam Jacksonb091cd92012-09-18 10:58:49 -0400659#define DP_MAX_DOWNSTREAM_PORTS 0x10
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300660
Ramalingam Cfe3cd482015-02-13 15:32:59 +0530661/*
662 * enum link_m_n_set:
663 * When platform provides two set of M_N registers for dp, we can
664 * program them and switch between them incase of DRRS.
665 * But When only one such register is provided, we have to program the
666 * required divider value on that registers itself based on the DRRS state.
667 *
668 * M1_N1 : Program dp_m_n on M1_N1 registers
669 * dp_m2_n2 on M2_N2 registers (If supported)
670 *
671 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
672 * M2_N2 registers are not supported
673 */
674
675enum link_m_n_set {
676 /* Sets the m1_n1 and m2_n2 */
677 M1_N1 = 0,
678 M2_N2
679};
680
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300681struct intel_dp {
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300682 uint32_t output_reg;
Paulo Zanoni9ed35ab2013-02-18 19:00:25 -0300683 uint32_t aux_ch_ctl_reg;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300684 uint32_t DP;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300685 bool has_audio;
686 enum hdmi_force_audio force_audio;
687 uint32_t color_range;
Ville Syrjälä55bc60d2013-01-17 16:31:29 +0200688 bool color_range_auto;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300689 uint8_t link_bw;
Sonika Jindala8f3ef62015-03-05 10:02:30 +0530690 uint8_t rate_select;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300691 uint8_t lane_count;
692 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
Shobhit Kumar2293bb52013-07-11 18:44:56 -0300693 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
Adam Jacksonb091cd92012-09-18 10:58:49 -0400694 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
Ville Syrjälä94ca7192015-03-13 19:40:31 +0200695 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
696 uint8_t num_sink_rates;
697 int sink_rates[DP_MAX_SUPPORTED_RATES];
Jani Nikula9d1a1032014-03-14 16:51:15 +0200698 struct drm_dp_aux aux;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300699 uint8_t train_set[4];
700 int panel_power_up_delay;
701 int panel_power_down_delay;
702 int panel_power_cycle_delay;
703 int backlight_on_delay;
704 int backlight_off_delay;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300705 struct delayed_work panel_vdd_work;
706 bool want_panel_vdd;
Paulo Zanonidce56b32013-12-19 14:29:40 -0200707 unsigned long last_power_cycle;
708 unsigned long last_power_on;
709 unsigned long last_backlight_off;
Dave Airlie5d42f822014-08-05 09:04:59 +1000710
Clint Taylor01527b32014-07-07 13:01:46 -0700711 struct notifier_block edp_notifier;
712
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300713 /*
714 * Pipe whose power sequencer is currently locked into
715 * this port. Only relevant on VLV/CHV.
716 */
717 enum pipe pps_pipe;
Ville Syrjälä36b5f422014-10-16 21:27:30 +0300718 struct edp_power_seq pps_delays;
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300719
Todd Previte06ea66b2014-01-20 10:19:39 -0700720 bool use_tps3;
Dave Airlie0e32b392014-05-02 14:02:48 +1000721 bool can_mst; /* this port supports mst */
722 bool is_mst;
723 int active_mst_links;
724 /* connector directly attached - won't be use for modeset in mst world */
Jani Nikuladd06f902012-10-19 14:51:50 +0300725 struct intel_connector *attached_connector;
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000726
Dave Airlie0e32b392014-05-02 14:02:48 +1000727 /* mst connector list */
728 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
729 struct drm_dp_mst_topology_mgr mst_mgr;
730
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000731 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
Damien Lespiau153b1102014-01-21 13:37:15 +0000732 /*
733 * This function returns the value we have to program the AUX_CTL
734 * register with to kick off an AUX transaction.
735 */
736 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
737 bool has_aux_irq,
738 int send_bytes,
739 uint32_t aux_clock_divider);
Mika Kahola4e96c972015-04-29 09:17:39 +0300740 bool train_set_valid;
Todd Previtec5d5ab72015-04-15 08:38:38 -0700741
742 /* Displayport compliance testing */
743 unsigned long compliance_test_type;
Todd Previte559be302015-05-04 07:48:20 -0700744 unsigned long compliance_test_data;
745 bool compliance_test_active;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300746};
747
Paulo Zanonida63a9f2012-10-26 19:05:46 -0200748struct intel_digital_port {
749 struct intel_encoder base;
Paulo Zanoni174edf12012-10-26 19:05:50 -0200750 enum port port;
Stéphane Marchesinbcf53de2013-07-12 13:54:41 -0700751 u32 saved_port_bits;
Paulo Zanonida63a9f2012-10-26 19:05:46 -0200752 struct intel_dp dp;
753 struct intel_hdmi hdmi;
Daniel Vetterb2c5c182015-01-23 06:00:31 +0100754 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
Paulo Zanonida63a9f2012-10-26 19:05:46 -0200755};
756
Dave Airlie0e32b392014-05-02 14:02:48 +1000757struct intel_dp_mst_encoder {
758 struct intel_encoder base;
759 enum pipe pipe;
760 struct intel_digital_port *primary;
761 void *port; /* store this opaque as its illegal to dereference it */
762};
763
Jesse Barnes89b667f2013-04-18 14:51:36 -0700764static inline int
765vlv_dport_to_channel(struct intel_digital_port *dport)
766{
767 switch (dport->port) {
768 case PORT_B:
Chon Ming Lee00fc31b2014-04-09 13:28:15 +0300769 case PORT_D:
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800770 return DPIO_CH0;
Jesse Barnes89b667f2013-04-18 14:51:36 -0700771 case PORT_C:
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800772 return DPIO_CH1;
Jesse Barnes89b667f2013-04-18 14:51:36 -0700773 default:
774 BUG();
775 }
776}
777
Chon Ming Leeeb69b0e2014-04-09 13:28:16 +0300778static inline int
779vlv_pipe_to_channel(enum pipe pipe)
780{
781 switch (pipe) {
782 case PIPE_A:
783 case PIPE_C:
784 return DPIO_CH0;
785 case PIPE_B:
786 return DPIO_CH1;
787 default:
788 BUG();
789 }
790}
791
Chris Wilsonf875c152010-09-09 15:44:14 +0100792static inline struct drm_crtc *
793intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
794{
795 struct drm_i915_private *dev_priv = dev->dev_private;
796 return dev_priv->pipe_to_crtc_mapping[pipe];
797}
798
Chris Wilson417ae142011-01-19 15:04:42 +0000799static inline struct drm_crtc *
800intel_get_crtc_for_plane(struct drm_device *dev, int plane)
801{
802 struct drm_i915_private *dev_priv = dev->dev_private;
803 return dev_priv->plane_to_crtc_mapping[plane];
804}
805
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100806struct intel_unpin_work {
807 struct work_struct work;
Chris Wilsonb4a98e52012-11-01 09:26:26 +0000808 struct drm_crtc *crtc;
Tvrtko Ursulinab8d6672015-02-02 15:44:15 +0000809 struct drm_framebuffer *old_fb;
Chris Wilson05394f32010-11-08 19:18:58 +0000810 struct drm_i915_gem_object *pending_flip_obj;
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100811 struct drm_pending_vblank_event *event;
Chris Wilsone7d841c2012-12-03 11:36:30 +0000812 atomic_t pending;
813#define INTEL_FLIP_INACTIVE 0
814#define INTEL_FLIP_PENDING 1
815#define INTEL_FLIP_COMPLETE 2
Ville Syrjälä75f7f3e2014-04-15 21:41:34 +0300816 u32 flip_count;
817 u32 gtt_offset;
John Harrisonf06cc1b2014-11-24 18:49:37 +0000818 struct drm_i915_gem_request *flip_queued_req;
Chris Wilsond6bbafa2014-09-05 07:13:24 +0100819 int flip_queued_vblank;
820 int flip_ready_vblank;
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100821 bool enable_stall_check;
822};
823
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300824struct intel_load_detect_pipe {
825 struct drm_framebuffer *release_fb;
826 bool load_detect_temp;
827 int dpms_mode;
828};
Daniel Vetterb9805142012-08-31 17:37:33 +0200829
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300830static inline struct intel_encoder *
831intel_attached_encoder(struct drm_connector *connector)
Chris Wilsondf0e9242010-09-09 16:20:55 +0100832{
833 return to_intel_connector(connector)->encoder;
834}
835
Paulo Zanonida63a9f2012-10-26 19:05:46 -0200836static inline struct intel_digital_port *
837enc_to_dig_port(struct drm_encoder *encoder)
838{
839 return container_of(encoder, struct intel_digital_port, base.base);
840}
841
Dave Airlie0e32b392014-05-02 14:02:48 +1000842static inline struct intel_dp_mst_encoder *
843enc_to_mst(struct drm_encoder *encoder)
844{
845 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
846}
847
Imre Deak9ff8c9b2013-05-08 13:14:02 +0300848static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
849{
850 return &enc_to_dig_port(encoder)->dp;
851}
852
Paulo Zanonida63a9f2012-10-26 19:05:46 -0200853static inline struct intel_digital_port *
854dp_to_dig_port(struct intel_dp *intel_dp)
855{
856 return container_of(intel_dp, struct intel_digital_port, dp);
857}
858
859static inline struct intel_digital_port *
860hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
861{
862 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
Paulo Zanoni7739c332012-10-15 15:51:29 -0300863}
864
Damien Lespiau6af31a62014-03-28 00:18:33 +0530865/*
866 * Returns the number of planes for this pipe, ie the number of sprites + 1
867 * (primary plane). This doesn't count the cursor plane then.
868 */
869static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
870{
871 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
872}
Damien Lespiaub0ea7d32012-12-13 16:09:00 +0000873
Daniel Vetter47339cd2014-09-30 10:56:46 +0200874/* intel_fifo_underrun.c */
Daniel Vettera72e4c92014-09-30 10:56:47 +0200875bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
Paulo Zanoni87440422013-09-24 15:48:31 -0300876 enum pipe pipe, bool enable);
Daniel Vettera72e4c92014-09-30 10:56:47 +0200877bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
Paulo Zanoni87440422013-09-24 15:48:31 -0300878 enum transcoder pch_transcoder,
879 bool enable);
Daniel Vetter1f7247c2014-09-30 10:56:48 +0200880void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
881 enum pipe pipe);
882void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
883 enum transcoder pch_transcoder);
Daniel Vettera72e4c92014-09-30 10:56:47 +0200884void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv);
Daniel Vetter47339cd2014-09-30 10:56:46 +0200885
886/* i915_irq.c */
Daniel Vetter480c8032014-07-16 09:49:40 +0200887void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
888void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
889void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
890void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
Imre Deak3cc134e2014-11-19 15:30:03 +0200891void gen6_reset_rps_interrupts(struct drm_device *dev);
Imre Deakb900b942014-11-05 20:48:48 +0200892void gen6_enable_rps_interrupts(struct drm_device *dev);
893void gen6_disable_rps_interrupts(struct drm_device *dev);
Imre Deak59d02a12014-12-19 19:33:26 +0200894u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
Daniel Vetterb9632912014-09-30 10:56:44 +0200895void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
896void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
Jesse Barnes9df7575f2014-06-20 09:29:20 -0700897static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
898{
899 /*
900 * We only use drm_irq_uninstall() at unload and VT switch, so
901 * this is the only thing we need to check.
902 */
Daniel Vetter2aeb7d32014-09-30 10:56:43 +0200903 return dev_priv->pm.irqs_enabled;
Jesse Barnes9df7575f2014-06-20 09:29:20 -0700904}
905
Ville Syrjäläa225f072014-04-29 13:35:45 +0300906int intel_get_crtc_scanline(struct intel_crtc *crtc);
Damien Lespiau4c6c03b2015-03-06 18:50:48 +0000907void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
908 unsigned int pipe_mask);
Jesse Barnes79e53942008-11-07 14:24:08 -0800909
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300910/* intel_crt.c */
Paulo Zanoni87440422013-09-24 15:48:31 -0300911void intel_crt_init(struct drm_device *dev);
Jesse Barnes79e53942008-11-07 14:24:08 -0800912
Jesse Barnes79e53942008-11-07 14:24:08 -0800913
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300914/* intel_ddi.c */
Paulo Zanoni87440422013-09-24 15:48:31 -0300915void intel_prepare_ddi(struct drm_device *dev);
916void hsw_fdi_link_train(struct drm_crtc *crtc);
917void intel_ddi_init(struct drm_device *dev, enum port port);
918enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
919bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
Paulo Zanoni87440422013-09-24 15:48:31 -0300920void intel_ddi_pll_init(struct drm_device *dev);
921void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
922void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
923 enum transcoder cpu_transcoder);
924void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
925void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +0200926bool intel_ddi_pll_select(struct intel_crtc *crtc,
927 struct intel_crtc_state *crtc_state);
Paulo Zanoni87440422013-09-24 15:48:31 -0300928void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
929void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
930bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
931void intel_ddi_fdi_disable(struct drm_crtc *crtc);
932void intel_ddi_get_config(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200933 struct intel_crtc_state *pipe_config);
Satheeshakrishna Mbcddf6102014-08-22 09:49:10 +0530934struct intel_encoder *
935intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
Eugeni Dodonov72662e12012-05-09 15:37:31 -0300936
Dave Airlie44905a272014-05-02 13:36:43 +1000937void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
Dave Airlie0e32b392014-05-02 14:02:48 +1000938void intel_ddi_clock_get(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200939 struct intel_crtc_state *pipe_config);
Dave Airlie0e32b392014-05-02 14:02:48 +1000940void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
Vandana Kannan96fb9f92014-11-18 15:45:27 +0530941void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
942 enum port port, int type);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -0300943
Daniel Vetterb680c372014-09-19 18:27:27 +0200944/* intel_frontbuffer.c */
Daniel Vetterf99d7062014-06-19 16:01:59 +0200945void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
Paulo Zanonia4001f12015-02-13 17:23:44 -0200946 struct intel_engine_cs *ring,
947 enum fb_op_origin origin);
Daniel Vetterf99d7062014-06-19 16:01:59 +0200948void intel_frontbuffer_flip_prepare(struct drm_device *dev,
949 unsigned frontbuffer_bits);
950void intel_frontbuffer_flip_complete(struct drm_device *dev,
951 unsigned frontbuffer_bits);
952void intel_frontbuffer_flush(struct drm_device *dev,
953 unsigned frontbuffer_bits);
954/**
Daniel Vetter5c323b22014-09-30 22:10:53 +0200955 * intel_frontbuffer_flip - synchronous frontbuffer flip
Daniel Vetterf99d7062014-06-19 16:01:59 +0200956 * @dev: DRM device
957 * @frontbuffer_bits: frontbuffer plane tracking bits
958 *
959 * This function gets called after scheduling a flip on @obj. This is for
960 * synchronous plane updates which will happen on the next vblank and which will
961 * not get delayed by pending gpu rendering.
962 *
963 * Can be called without any locks held.
964 */
965static inline
966void intel_frontbuffer_flip(struct drm_device *dev,
967 unsigned frontbuffer_bits)
968{
969 intel_frontbuffer_flush(dev, frontbuffer_bits);
970}
971
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +0000972unsigned int intel_fb_align_height(struct drm_device *dev,
973 unsigned int height,
974 uint32_t pixel_format,
975 uint64_t fb_format_modifier);
Daniel Vetterf99d7062014-06-19 16:01:59 +0200976void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
Daniel Vetterb680c372014-09-19 18:27:27 +0200977
Damien Lespiaub3218032015-02-27 11:15:18 +0000978u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
979 uint32_t pixel_format);
Daniel Vetterb680c372014-09-19 18:27:27 +0200980
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200981/* intel_audio.c */
982void intel_init_audio(struct drm_device *dev);
Jani Nikula69bfe1a2014-10-27 16:26:50 +0200983void intel_audio_codec_enable(struct intel_encoder *encoder);
984void intel_audio_codec_disable(struct intel_encoder *encoder);
Imre Deak58fddc22015-01-08 17:54:14 +0200985void i915_audio_component_init(struct drm_i915_private *dev_priv);
986void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
Jani Nikula7c10a2b2014-10-27 16:26:43 +0200987
Daniel Vetterb680c372014-09-19 18:27:27 +0200988/* intel_display.c */
Matt Roper65a3fea2015-01-21 16:35:42 -0800989extern const struct drm_plane_funcs intel_plane_funcs;
Daniel Vetterb680c372014-09-19 18:27:27 +0200990bool intel_has_pending_fb_unpin(struct drm_device *dev);
991int intel_pch_rawclk(struct drm_device *dev);
992void intel_mark_busy(struct drm_device *dev);
Paulo Zanoni87440422013-09-24 15:48:31 -0300993void intel_mark_idle(struct drm_device *dev);
994void intel_crtc_restore_mode(struct drm_crtc *crtc);
Borun Fub04c5bd2014-07-12 10:02:27 +0530995void intel_crtc_control(struct drm_crtc *crtc, bool enable);
Maarten Lankhorstce22dba2015-04-21 17:12:56 +0300996void intel_crtc_reset(struct intel_crtc *crtc);
Paulo Zanoni87440422013-09-24 15:48:31 -0300997void intel_crtc_update_dpms(struct drm_crtc *crtc);
998void intel_encoder_destroy(struct drm_encoder *encoder);
Ander Conselvan de Oliveira08d9bc92015-04-10 10:59:10 +0300999int intel_connector_init(struct intel_connector *);
1000struct intel_connector *intel_connector_alloc(void);
Paulo Zanoni87440422013-09-24 15:48:31 -03001001void intel_connector_dpms(struct drm_connector *, int mode);
1002bool intel_connector_get_hw_state(struct intel_connector *connector);
1003void intel_modeset_check_state(struct drm_device *dev);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001004bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1005 struct intel_digital_port *port);
Paulo Zanoni87440422013-09-24 15:48:31 -03001006void intel_connector_attach_encoder(struct intel_connector *connector,
1007 struct intel_encoder *encoder);
1008struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
1009struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1010 struct drm_crtc *crtc);
Jesse Barnes752aa882013-10-31 18:55:49 +02001011enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001012int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1013 struct drm_file *file_priv);
Paulo Zanoni87440422013-09-24 15:48:31 -03001014enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1015 enum pipe pipe);
Damien Lespiau40935612014-10-29 11:16:59 +00001016bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
Daniel Vetter4f905cf92014-09-15 14:12:21 +02001017static inline void
1018intel_wait_for_vblank(struct drm_device *dev, int pipe)
1019{
1020 drm_wait_one_vblank(dev, pipe);
1021}
Paulo Zanoni87440422013-09-24 15:48:31 -03001022int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001023void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
Ville Syrjälä9b6de0a2015-04-10 18:21:31 +03001024 struct intel_digital_port *dport,
1025 unsigned int expected_mask);
Paulo Zanoni87440422013-09-24 15:48:31 -03001026bool intel_get_load_detect_pipe(struct drm_connector *connector,
1027 struct drm_display_mode *mode,
Rob Clark51fd3712013-11-19 12:10:12 -05001028 struct intel_load_detect_pipe *old,
1029 struct drm_modeset_acquire_ctx *ctx);
Paulo Zanoni87440422013-09-24 15:48:31 -03001030void intel_release_load_detect_pipe(struct drm_connector *connector,
Ander Conselvan de Oliveira49172fe2015-03-20 16:18:02 +02001031 struct intel_load_detect_pipe *old,
1032 struct drm_modeset_acquire_ctx *ctx);
Tvrtko Ursulin850c4cd2014-10-30 16:39:38 +00001033int intel_pin_and_fence_fb_obj(struct drm_plane *plane,
1034 struct drm_framebuffer *fb,
Tvrtko Ursulin82bc3b22015-03-23 11:10:34 +00001035 const struct drm_plane_state *plane_state,
Oscar Mateoa4872ba2014-05-22 14:13:33 +01001036 struct intel_engine_cs *pipelined);
Daniel Vettera8bb6812014-02-10 18:00:39 +01001037struct drm_framebuffer *
1038__intel_framebuffer_create(struct drm_device *dev,
Paulo Zanoni87440422013-09-24 15:48:31 -03001039 struct drm_mode_fb_cmd2 *mode_cmd,
1040 struct drm_i915_gem_object *obj);
Paulo Zanoni87440422013-09-24 15:48:31 -03001041void intel_prepare_page_flip(struct drm_device *dev, int plane);
1042void intel_finish_page_flip(struct drm_device *dev, int pipe);
1043void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
Chris Wilsond6bbafa2014-09-05 07:13:24 +01001044void intel_check_page_flip(struct drm_device *dev, int pipe);
Matt Roper6beb8c232014-12-01 15:40:14 -08001045int intel_prepare_plane_fb(struct drm_plane *plane,
Tvrtko Ursulind136dfe2015-03-03 14:22:31 +00001046 struct drm_framebuffer *fb,
1047 const struct drm_plane_state *new_state);
Matt Roper38f3ce32014-12-02 07:45:25 -08001048void intel_cleanup_plane_fb(struct drm_plane *plane,
Tvrtko Ursulind136dfe2015-03-03 14:22:31 +00001049 struct drm_framebuffer *fb,
1050 const struct drm_plane_state *old_state);
Matt Ropera98b3432015-01-21 16:35:43 -08001051int intel_plane_atomic_get_property(struct drm_plane *plane,
1052 const struct drm_plane_state *state,
1053 struct drm_property *property,
1054 uint64_t *val);
1055int intel_plane_atomic_set_property(struct drm_plane *plane,
1056 struct drm_plane_state *state,
1057 struct drm_property *property,
1058 uint64_t val);
Daniel Vetter716c2e52014-06-25 22:02:02 +03001059
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00001060unsigned int
1061intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
1062 uint64_t fb_format_modifier);
1063
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00001064static inline bool
1065intel_rotation_90_or_270(unsigned int rotation)
1066{
1067 return rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270));
1068}
1069
Sonika Jindal3b7a5112015-04-10 14:37:29 +05301070void intel_create_rotation_property(struct drm_device *dev,
1071 struct intel_plane *plane);
1072
Tvrtko Ursulin1fc0a8f2015-03-23 11:10:38 +00001073bool intel_wm_need_update(struct drm_plane *plane,
1074 struct drm_plane_state *state);
1075
Daniel Vetter716c2e52014-06-25 22:02:02 +03001076/* shared dpll functions */
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001077struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1078void assert_shared_dpll(struct drm_i915_private *dev_priv,
1079 struct intel_shared_dpll *pll,
1080 bool state);
1081#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
1082#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001083struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1084 struct intel_crtc_state *state);
Daniel Vetter716c2e52014-06-25 22:02:02 +03001085void intel_put_shared_dpll(struct intel_crtc *crtc);
1086
Ville Syrjäläd288f652014-10-28 13:20:22 +02001087void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1088 const struct dpll *dpll);
1089void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
1090
Daniel Vetter716c2e52014-06-25 22:02:02 +03001091/* modesetting asserts */
Daniel Vetterb680c372014-09-19 18:27:27 +02001092void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1093 enum pipe pipe);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001094void assert_pll(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, bool state);
1096#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1097#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1098void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1099 enum pipe pipe, bool state);
1100#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1101#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
Paulo Zanoni87440422013-09-24 15:48:31 -03001102void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001103#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1104#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
Paulo Zanoni87440422013-09-24 15:48:31 -03001105unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1106 unsigned int tiling_mode,
1107 unsigned int bpp,
1108 unsigned int pitch);
Ville Syrjälä75147472014-11-24 18:28:11 +02001109void intel_prepare_reset(struct drm_device *dev);
1110void intel_finish_reset(struct drm_device *dev);
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03001111void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1112void hsw_disable_pc8(struct drm_i915_private *dev_priv);
Vandana Kannanf8437dd12014-11-24 13:37:39 +05301113void broxton_init_cdclk(struct drm_device *dev);
1114void broxton_uninit_cdclk(struct drm_device *dev);
1115void broxton_set_cdclk(struct drm_device *dev, int frequency);
Vandana Kannan5c6706e2014-11-24 13:37:39 +05301116void broxton_ddi_phy_init(struct drm_device *dev);
1117void broxton_ddi_phy_uninit(struct drm_device *dev);
A.Sunil Kamath664326f2014-11-24 13:37:44 +05301118void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1119void bxt_disable_dc9(struct drm_i915_private *dev_priv);
Paulo Zanoni87440422013-09-24 15:48:31 -03001120void intel_dp_get_m_n(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001121 struct intel_crtc_state *pipe_config);
Ramalingam Cfe3cd482015-02-13 15:32:59 +05301122void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
Paulo Zanoni87440422013-09-24 15:48:31 -03001123int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1124void
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001125ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001126 int dotclock);
Imre Deak5ab7b0b2015-03-06 03:29:25 +02001127bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1128 intel_clock_t *best_clock);
Paulo Zanoni87440422013-09-24 15:48:31 -03001129bool intel_crtc_active(struct drm_crtc *crtc);
Ville Syrjälä20bc86732013-10-01 18:02:17 +03001130void hsw_enable_ips(struct intel_crtc *crtc);
1131void hsw_disable_ips(struct intel_crtc *crtc);
Imre Deak319be8a2014-03-04 19:22:57 +02001132enum intel_display_power_domain
1133intel_display_port_power_domain(struct intel_encoder *intel_encoder);
Daniel Vetterf6a83282014-02-11 15:28:57 -08001134void intel_mode_from_pipe_config(struct drm_display_mode *mode,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001135 struct intel_crtc_state *pipe_config);
Ville Syrjälä46a55d32014-05-21 14:04:46 +03001136void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
Ville Syrjäläe2fcdaa2014-08-06 14:02:51 +03001137void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
Chandra Kondurua1b22782015-04-07 15:28:45 -07001138void skl_detach_scalers(struct intel_crtc *intel_crtc);
1139int skl_update_scaler_users(struct intel_crtc *intel_crtc,
1140 struct intel_crtc_state *crtc_state, struct intel_plane *intel_plane,
1141 struct intel_plane_state *plane_state, int force_detach);
Chandra Konduru6156a452015-04-27 13:48:39 -07001142int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001143
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00001144unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
1145 struct drm_i915_gem_object *obj);
Chandra Konduru6156a452015-04-27 13:48:39 -07001146u32 skl_plane_ctl_format(uint32_t pixel_format);
1147u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1148u32 skl_plane_ctl_rotation(unsigned int rotation);
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00001149
Daniel Vettereb805622015-05-04 14:58:44 +02001150/* intel_csr.c */
1151void intel_csr_ucode_init(struct drm_device *dev);
Suketu Shahdc174302015-04-17 19:46:16 +05301152enum csr_state intel_csr_load_status_get(struct drm_i915_private *dev_priv);
1153void intel_csr_load_status_set(struct drm_i915_private *dev_priv,
1154 enum csr_state state);
Daniel Vettereb805622015-05-04 14:58:44 +02001155void intel_csr_load_program(struct drm_device *dev);
1156void intel_csr_ucode_fini(struct drm_device *dev);
Suketu Shah5aefb232015-04-16 14:22:10 +05301157void assert_csr_loaded(struct drm_i915_private *dev_priv);
Daniel Vettereb805622015-05-04 14:58:44 +02001158
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001159/* intel_dp.c */
Paulo Zanoni87440422013-09-24 15:48:31 -03001160void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
1161bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1162 struct intel_connector *intel_connector);
Paulo Zanoni87440422013-09-24 15:48:31 -03001163void intel_dp_start_link_train(struct intel_dp *intel_dp);
1164void intel_dp_complete_link_train(struct intel_dp *intel_dp);
1165void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1166void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1167void intel_dp_encoder_destroy(struct drm_encoder *encoder);
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02001168int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
Paulo Zanoni87440422013-09-24 15:48:31 -03001169bool intel_dp_compute_config(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001170 struct intel_crtc_state *pipe_config);
Ville Syrjälä5d8a7752013-11-01 18:22:39 +02001171bool intel_dp_is_edp(struct drm_device *dev, enum port port);
Daniel Vetterb2c5c182015-01-23 06:00:31 +01001172enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1173 bool long_hpd);
Daniel Vetter4be73782014-01-17 14:39:48 +01001174void intel_edp_backlight_on(struct intel_dp *intel_dp);
1175void intel_edp_backlight_off(struct intel_dp *intel_dp);
Jani Nikula24f3e092014-03-17 16:43:36 +02001176void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01001177void intel_edp_panel_on(struct intel_dp *intel_dp);
1178void intel_edp_panel_off(struct intel_dp *intel_dp);
Dave Airlie0e32b392014-05-02 14:02:48 +10001179void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1180void intel_dp_mst_suspend(struct drm_device *dev);
1181void intel_dp_mst_resume(struct drm_device *dev);
Ville Syrjälä50fec212015-03-12 17:10:34 +02001182int intel_dp_max_link_rate(struct intel_dp *intel_dp);
Ville Syrjäläed4e9c12015-03-12 17:10:36 +02001183int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
Dave Airlie0e32b392014-05-02 14:02:48 +10001184void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
Ville Syrjälä773538e82014-09-04 14:54:56 +03001185void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -08001186uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
Matt Roper4a3b8762014-12-23 10:41:51 -08001187void intel_plane_destroy(struct drm_plane *plane);
Vandana Kannanc3955782015-01-22 15:17:40 +05301188void intel_edp_drrs_enable(struct intel_dp *intel_dp);
1189void intel_edp_drrs_disable(struct intel_dp *intel_dp);
Vandana Kannana93fad02015-01-10 02:25:59 +05301190void intel_edp_drrs_invalidate(struct drm_device *dev,
1191 unsigned frontbuffer_bits);
1192void intel_edp_drrs_flush(struct drm_device *dev, unsigned frontbuffer_bits);
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -08001193
Dave Airlie0e32b392014-05-02 14:02:48 +10001194/* intel_dp_mst.c */
1195int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1196void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001197/* intel_dsi.c */
Damien Lespiau4328633d2014-05-28 12:30:56 +01001198void intel_dsi_init(struct drm_device *dev);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001199
1200
1201/* intel_dvo.c */
Paulo Zanoni87440422013-09-24 15:48:31 -03001202void intel_dvo_init(struct drm_device *dev);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001203
1204
Daniel Vetter0632fef2013-10-08 17:44:49 +02001205/* legacy fbdev emulation in intel_fbdev.c */
Daniel Vetter4520f532013-10-09 09:18:51 +02001206#ifdef CONFIG_DRM_I915_FBDEV
1207extern int intel_fbdev_init(struct drm_device *dev);
Jesse Barnesd1d70672014-05-28 14:39:03 -07001208extern void intel_fbdev_initial_config(void *data, async_cookie_t cookie);
Daniel Vetter4520f532013-10-09 09:18:51 +02001209extern void intel_fbdev_fini(struct drm_device *dev);
Chris Wilson82e3b8c2014-08-13 13:09:46 +01001210extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
Daniel Vetter0632fef2013-10-08 17:44:49 +02001211extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1212extern void intel_fbdev_restore_mode(struct drm_device *dev);
Daniel Vetter4520f532013-10-09 09:18:51 +02001213#else
1214static inline int intel_fbdev_init(struct drm_device *dev)
1215{
1216 return 0;
1217}
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001218
Jesse Barnesd1d70672014-05-28 14:39:03 -07001219static inline void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
Daniel Vetter4520f532013-10-09 09:18:51 +02001220{
1221}
1222
1223static inline void intel_fbdev_fini(struct drm_device *dev)
1224{
1225}
1226
Chris Wilson82e3b8c2014-08-13 13:09:46 +01001227static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
Daniel Vetter4520f532013-10-09 09:18:51 +02001228{
1229}
1230
Daniel Vetter0632fef2013-10-08 17:44:49 +02001231static inline void intel_fbdev_restore_mode(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +02001232{
1233}
1234#endif
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001235
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001236/* intel_fbc.c */
1237bool intel_fbc_enabled(struct drm_device *dev);
1238void intel_fbc_update(struct drm_device *dev);
1239void intel_fbc_init(struct drm_i915_private *dev_priv);
1240void intel_fbc_disable(struct drm_device *dev);
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001241void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1242 unsigned int frontbuffer_bits,
1243 enum fb_op_origin origin);
1244void intel_fbc_flush(struct drm_i915_private *dev_priv,
1245 unsigned int frontbuffer_bits);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001246
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001247/* intel_hdmi.c */
Paulo Zanoni87440422013-09-24 15:48:31 -03001248void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port);
1249void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1250 struct intel_connector *intel_connector);
1251struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1252bool intel_hdmi_compute_config(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001253 struct intel_crtc_state *pipe_config);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001254
1255
1256/* intel_lvds.c */
Paulo Zanoni87440422013-09-24 15:48:31 -03001257void intel_lvds_init(struct drm_device *dev);
1258bool intel_is_dual_link_lvds(struct drm_device *dev);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001259
1260
1261/* intel_modes.c */
1262int intel_connector_update_modes(struct drm_connector *connector,
Paulo Zanoni87440422013-09-24 15:48:31 -03001263 struct edid *edid);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001264int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
Paulo Zanoni87440422013-09-24 15:48:31 -03001265void intel_attach_force_audio_property(struct drm_connector *connector);
1266void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001267
1268
1269/* intel_overlay.c */
Paulo Zanoni87440422013-09-24 15:48:31 -03001270void intel_setup_overlay(struct drm_device *dev);
1271void intel_cleanup_overlay(struct drm_device *dev);
1272int intel_overlay_switch_off(struct intel_overlay *overlay);
1273int intel_overlay_put_image(struct drm_device *dev, void *data,
1274 struct drm_file *file_priv);
1275int intel_overlay_attrs(struct drm_device *dev, void *data,
1276 struct drm_file *file_priv);
Ville Syrjälä1362b772014-11-26 17:07:29 +02001277void intel_overlay_reset(struct drm_i915_private *dev_priv);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001278
1279
1280/* intel_panel.c */
Paulo Zanoni87440422013-09-24 15:48:31 -03001281int intel_panel_init(struct intel_panel *panel,
Vandana Kannan4b6ed682014-02-11 14:26:36 +05301282 struct drm_display_mode *fixed_mode,
1283 struct drm_display_mode *downclock_mode);
Paulo Zanoni87440422013-09-24 15:48:31 -03001284void intel_panel_fini(struct intel_panel *panel);
1285void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1286 struct drm_display_mode *adjusted_mode);
1287void intel_pch_panel_fitting(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001288 struct intel_crtc_state *pipe_config,
Paulo Zanoni87440422013-09-24 15:48:31 -03001289 int fitting_mode);
1290void intel_gmch_panel_fitting(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001291 struct intel_crtc_state *pipe_config,
Paulo Zanoni87440422013-09-24 15:48:31 -03001292 int fitting_mode);
Jani Nikula6dda7302014-06-24 18:27:40 +03001293void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1294 u32 level, u32 max);
Ville Syrjälä6517d272014-11-07 11:16:02 +02001295int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
Jesse Barnes752aa882013-10-31 18:55:49 +02001296void intel_panel_enable_backlight(struct intel_connector *connector);
1297void intel_panel_disable_backlight(struct intel_connector *connector);
Jani Nikuladb31af1d2013-11-08 16:48:53 +02001298void intel_panel_destroy_backlight(struct drm_connector *connector);
Jani Nikula7bd688c2013-11-08 16:48:56 +02001299void intel_panel_init_backlight_funcs(struct drm_device *dev);
Paulo Zanoni87440422013-09-24 15:48:31 -03001300enum drm_connector_status intel_panel_detect(struct drm_device *dev);
Vandana Kannanec9ed192013-12-10 13:37:36 +05301301extern struct drm_display_mode *intel_find_panel_downclock(
1302 struct drm_device *dev,
1303 struct drm_display_mode *fixed_mode,
1304 struct drm_connector *connector);
Ville Syrjälä0962c3c2014-11-07 15:19:46 +02001305void intel_backlight_register(struct drm_device *dev);
1306void intel_backlight_unregister(struct drm_device *dev);
1307
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001308
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -08001309/* intel_psr.c */
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -08001310void intel_psr_enable(struct intel_dp *intel_dp);
1311void intel_psr_disable(struct intel_dp *intel_dp);
1312void intel_psr_invalidate(struct drm_device *dev,
1313 unsigned frontbuffer_bits);
1314void intel_psr_flush(struct drm_device *dev,
1315 unsigned frontbuffer_bits);
1316void intel_psr_init(struct drm_device *dev);
Rodrigo Vivic7240c32015-04-10 11:15:10 -07001317void intel_psr_single_frame_update(struct drm_device *dev);
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -08001318
Daniel Vetter9c065a72014-09-30 10:56:38 +02001319/* intel_runtime_pm.c */
1320int intel_power_domains_init(struct drm_i915_private *);
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001321void intel_power_domains_fini(struct drm_i915_private *);
Daniel Vetter9c065a72014-09-30 10:56:38 +02001322void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001323void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
Daniel Vetter9c065a72014-09-30 10:56:38 +02001324
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001325bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1326 enum intel_display_power_domain domain);
1327bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1328 enum intel_display_power_domain domain);
Daniel Vetter9c065a72014-09-30 10:56:38 +02001329void intel_display_power_get(struct drm_i915_private *dev_priv,
1330 enum intel_display_power_domain domain);
1331void intel_display_power_put(struct drm_i915_private *dev_priv,
1332 enum intel_display_power_domain domain);
1333void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);
1334void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
1335void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1336void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1337void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1338
Daniel Vetterd9bc89d92014-09-30 10:56:40 +02001339void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1340
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001341/* intel_pm.c */
Paulo Zanoni87440422013-09-24 15:48:31 -03001342void intel_init_clock_gating(struct drm_device *dev);
1343void intel_suspend_hw(struct drm_device *dev);
Damien Lespiau546c81f2014-05-13 15:30:26 +01001344int ilk_wm_max_level(const struct drm_device *dev);
Paulo Zanoni87440422013-09-24 15:48:31 -03001345void intel_update_watermarks(struct drm_crtc *crtc);
1346void intel_update_sprite_watermarks(struct drm_plane *plane,
1347 struct drm_crtc *crtc,
Damien Lespiaued57cb82014-07-15 09:21:24 +02001348 uint32_t sprite_width,
1349 uint32_t sprite_height,
1350 int pixel_size,
Paulo Zanoni87440422013-09-24 15:48:31 -03001351 bool enabled, bool scaled);
1352void intel_init_pm(struct drm_device *dev);
Daniel Vetterf742a552013-12-06 10:17:53 +01001353void intel_pm_setup(struct drm_device *dev);
Paulo Zanoni87440422013-09-24 15:48:31 -03001354void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1355void intel_gpu_ips_teardown(void);
Imre Deakae484342014-03-31 15:10:44 +03001356void intel_init_gt_powersave(struct drm_device *dev);
1357void intel_cleanup_gt_powersave(struct drm_device *dev);
Paulo Zanoni87440422013-09-24 15:48:31 -03001358void intel_enable_gt_powersave(struct drm_device *dev);
1359void intel_disable_gt_powersave(struct drm_device *dev);
Jesse Barnes156c7ca2014-06-12 08:35:45 -07001360void intel_suspend_gt_powersave(struct drm_device *dev);
Imre Deakc6df39b2014-04-14 20:24:29 +03001361void intel_reset_gt_powersave(struct drm_device *dev);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001362void gen6_update_ring_freq(struct drm_device *dev);
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001363void gen6_rps_busy(struct drm_i915_private *dev_priv);
1364void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
Daniel Vetter076e29f2013-10-08 19:39:29 +02001365void gen6_rps_idle(struct drm_i915_private *dev_priv);
Chris Wilson1854d5c2015-04-07 16:20:32 +01001366void gen6_rps_boost(struct drm_i915_private *dev_priv,
1367 struct drm_i915_file_private *file_priv);
Chris Wilson6ad790c2015-04-07 16:20:31 +01001368void intel_queue_rps_boost_for_request(struct drm_device *dev,
Daniel Vettereed29a52015-05-21 14:21:25 +02001369 struct drm_i915_gem_request *req);
Ville Syrjälä243e6a42013-10-14 14:55:24 +03001370void ilk_wm_get_hw_state(struct drm_device *dev);
Pradeep Bhat30789992014-11-04 17:06:45 +00001371void skl_wm_get_hw_state(struct drm_device *dev);
Damien Lespiau08db6652014-11-04 17:06:52 +00001372void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1373 struct skl_ddb_allocation *ddb /* out */);
Ville Syrjäläd2011dc2014-06-13 13:37:56 +03001374
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001375
1376/* intel_sdvo.c */
Paulo Zanoni87440422013-09-24 15:48:31 -03001377bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001378
1379
1380/* intel_sprite.c */
Paulo Zanoni87440422013-09-24 15:48:31 -03001381int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
Ville Syrjälä1dba99f2013-10-01 18:02:18 +03001382void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
Paulo Zanoni87440422013-09-24 15:48:31 -03001383 enum plane plane);
Ville Syrjäläe57465f2014-08-05 11:26:53 +05301384int intel_plane_restore(struct drm_plane *plane);
Paulo Zanoni87440422013-09-24 15:48:31 -03001385int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1386 struct drm_file *file_priv);
Ander Conselvan de Oliveira9362c7c2014-10-28 15:10:14 +02001387bool intel_pipe_update_start(struct intel_crtc *crtc,
1388 uint32_t *start_vbl_count);
1389void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001390
1391/* intel_tv.c */
Paulo Zanoni87440422013-09-24 15:48:31 -03001392void intel_tv_init(struct drm_device *dev);
Ville Syrjälä20ddf662013-09-04 18:25:25 +03001393
Matt Roperea2c67b2014-12-23 10:41:52 -08001394/* intel_atomic.c */
Matt Roper5ee67f12015-01-21 16:35:44 -08001395int intel_atomic_check(struct drm_device *dev,
1396 struct drm_atomic_state *state);
1397int intel_atomic_commit(struct drm_device *dev,
1398 struct drm_atomic_state *state,
1399 bool async);
Matt Roper2545e4a2015-01-22 16:51:27 -08001400int intel_connector_atomic_get_property(struct drm_connector *connector,
1401 const struct drm_connector_state *state,
1402 struct drm_property *property,
1403 uint64_t *val);
Matt Roper13568372015-01-21 16:35:47 -08001404struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1405void intel_crtc_destroy_state(struct drm_crtc *crtc,
1406 struct drm_crtc_state *state);
Ander Conselvan de Oliveira10f81c12015-03-20 16:18:01 +02001407static inline struct intel_crtc_state *
1408intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1409 struct intel_crtc *crtc)
1410{
1411 struct drm_crtc_state *crtc_state;
1412 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1413 if (IS_ERR(crtc_state))
Fabian Frederick0b6cc182015-04-25 11:34:29 +02001414 return ERR_CAST(crtc_state);
Ander Conselvan de Oliveira10f81c12015-03-20 16:18:01 +02001415
1416 return to_intel_crtc_state(crtc_state);
1417}
Chandra Kondurud03c93d2015-04-09 16:42:46 -07001418int intel_atomic_setup_scalers(struct drm_device *dev,
1419 struct intel_crtc *intel_crtc,
1420 struct intel_crtc_state *crtc_state);
Matt Roper5ee67f12015-01-21 16:35:44 -08001421
1422/* intel_atomic_plane.c */
Matt Roper8e7d6882015-01-21 16:35:41 -08001423struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
Matt Roperea2c67b2014-12-23 10:41:52 -08001424struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1425void intel_plane_destroy_state(struct drm_plane *plane,
1426 struct drm_plane_state *state);
1427extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1428
Jesse Barnes79e53942008-11-07 14:24:08 -08001429#endif /* __INTEL_DRV_H__ */