Maxime Ripard | 1d80c14 | 2016-06-29 21:05:23 +0200 | [diff] [blame] | 1 | config SUNXI_CCU |
2 | bool "Clock support for Allwinner SoCs" | ||||
3 | default ARCH_SUNXI | ||||
Maxime Ripard | 89a3dfb | 2016-06-29 21:05:24 +0200 | [diff] [blame] | 4 | |
5 | if SUNXI_CCU | ||||
6 | |||||
7 | # Base clock types | ||||
8 | |||||
Maxime Ripard | e9b9321 | 2016-06-29 21:05:28 +0200 | [diff] [blame^] | 9 | config SUNXI_CCU_DIV |
10 | bool | ||||
11 | select SUNXI_CCU_MUX | ||||
12 | |||||
Maxime Ripard | 89a3dfb | 2016-06-29 21:05:24 +0200 | [diff] [blame] | 13 | config SUNXI_CCU_FRAC |
14 | bool | ||||
15 | |||||
Maxime Ripard | 1a7e7c3 | 2016-06-29 21:05:25 +0200 | [diff] [blame] | 16 | config SUNXI_CCU_GATE |
17 | bool | ||||
18 | |||||
Maxime Ripard | 2a65ed4 | 2016-06-29 21:05:26 +0200 | [diff] [blame] | 19 | config SUNXI_CCU_MUX |
20 | bool | ||||
21 | |||||
Maxime Ripard | 6f9f7f8 | 2016-06-29 21:05:27 +0200 | [diff] [blame] | 22 | config SUNXI_CCU_PHASE |
23 | bool | ||||
24 | |||||
Maxime Ripard | 89a3dfb | 2016-06-29 21:05:24 +0200 | [diff] [blame] | 25 | endif |