R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 1 | /* |
Sricharan R | fa63d03 | 2013-06-07 18:52:47 +0530 | [diff] [blame] | 2 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
| 8 | /dts-v1/; |
| 9 | |
Florian Vaussard | 98ef7957 | 2013-05-31 14:32:55 +0200 | [diff] [blame] | 10 | #include "omap5.dtsi" |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
| 12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 13 | |
| 14 | / { |
Sricharan R | fa63d03 | 2013-06-07 18:52:47 +0530 | [diff] [blame] | 15 | model = "TI OMAP5 uEVM board"; |
| 16 | compatible = "ti,omap5-uevm", "ti,omap5"; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 17 | |
| 18 | memory { |
| 19 | device_type = "memory"; |
Santosh Shilimkar | 03178c6 | 2013-01-18 11:43:16 +0530 | [diff] [blame] | 20 | reg = <0x80000000 0x7F000000>; /* 2032 MB */ |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 21 | }; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 22 | |
| 23 | vmmcsd_fixed: fixedregulator-mmcsd { |
| 24 | compatible = "regulator-fixed"; |
| 25 | regulator-name = "vmmcsd_fixed"; |
| 26 | regulator-min-microvolt = <3000000>; |
| 27 | regulator-max-microvolt = <3000000>; |
| 28 | }; |
Sourav Poddar | 5449fbc | 2012-07-25 11:03:27 +0530 | [diff] [blame] | 29 | |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 30 | /* HS USB Host PHY on PORT 2 */ |
| 31 | hsusb2_phy: hsusb2_phy { |
| 32 | compatible = "usb-nop-xceiv"; |
Roger Quadros | 8ae9b59 | 2013-09-24 11:53:53 +0300 | [diff] [blame] | 33 | reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */ |
Roger Quadros | 153030c | 2013-06-18 19:04:46 +0300 | [diff] [blame] | 34 | /** |
| 35 | * FIXME |
| 36 | * Put the right clock phandle here when available |
| 37 | * clocks = <&auxclk1>; |
| 38 | * clock-names = "main_clk"; |
| 39 | */ |
| 40 | clock-frequency = <19200000>; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 41 | }; |
| 42 | |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 43 | /* HS USB Host PHY on PORT 3 */ |
| 44 | hsusb3_phy: hsusb3_phy { |
| 45 | compatible = "usb-nop-xceiv"; |
Roger Quadros | 8ae9b59 | 2013-09-24 11:53:53 +0300 | [diff] [blame] | 46 | reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */ |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 47 | }; |
| 48 | |
Dan Murphy | 6615530 | 2013-06-07 18:52:49 +0530 | [diff] [blame] | 49 | leds { |
| 50 | compatible = "gpio-leds"; |
| 51 | led@1 { |
| 52 | label = "omap5:blue:usr1"; |
| 53 | gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ |
| 54 | linux,default-trigger = "heartbeat"; |
| 55 | default-state = "off"; |
| 56 | }; |
| 57 | }; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 58 | }; |
| 59 | |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 60 | &omap5_pmx_core { |
| 61 | pinctrl-names = "default"; |
| 62 | pinctrl-0 = < |
| 63 | &twl6040_pins |
| 64 | &mcpdm_pins |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 65 | &mcbsp1_pins |
| 66 | &mcbsp2_pins |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 67 | &usbhost_pins |
Dan Murphy | 6615530 | 2013-06-07 18:52:49 +0530 | [diff] [blame] | 68 | &led_gpio_pins |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 69 | >; |
| 70 | |
| 71 | twl6040_pins: pinmux_twl6040_pins { |
| 72 | pinctrl-single,pins = < |
Peter Ujfalusi | 472e623d | 2013-10-23 12:32:19 +0300 | [diff] [blame] | 73 | 0x17e (PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 74 | >; |
| 75 | }; |
| 76 | |
| 77 | mcpdm_pins: pinmux_mcpdm_pins { |
| 78 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 79 | 0x142 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */ |
| 80 | 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */ |
| 81 | 0x15e (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */ |
| 82 | 0x160 (PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */ |
| 83 | 0x162 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 84 | >; |
| 85 | }; |
| 86 | |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 87 | mcbsp1_pins: pinmux_mcbsp1_pins { |
| 88 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 89 | 0x14c (PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */ |
| 90 | 0x14e (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */ |
| 91 | 0x150 (PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */ |
| 92 | 0x152 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 93 | >; |
| 94 | }; |
| 95 | |
| 96 | mcbsp2_pins: pinmux_mcbsp2_pins { |
| 97 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 98 | 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */ |
| 99 | 0x156 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */ |
| 100 | 0x158 (PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */ |
| 101 | 0x15a (PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */ |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 102 | >; |
| 103 | }; |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 104 | |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 105 | i2c1_pins: pinmux_i2c1_pins { |
| 106 | pinctrl-single,pins = < |
| 107 | 0x1b2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ |
| 108 | 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ |
| 109 | >; |
| 110 | }; |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 111 | |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 112 | i2c5_pins: pinmux_i2c5_pins { |
| 113 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 114 | 0x184 (PIN_INPUT | MUX_MODE0) /* i2c5_scl */ |
| 115 | 0x186 (PIN_INPUT | MUX_MODE0) /* i2c5_sda */ |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 116 | >; |
| 117 | }; |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 118 | |
| 119 | mcspi2_pins: pinmux_mcspi2_pins { |
| 120 | pinctrl-single,pins = < |
Florian Vaussard | bcd3cca | 2013-05-31 14:32:59 +0200 | [diff] [blame] | 121 | 0xbc (PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ |
| 122 | 0xbe (PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ |
| 123 | 0xc0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */ |
Eric Witcher | 05bc85d | 2013-10-18 02:42:34 -0400 | [diff] [blame] | 124 | 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */ |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 125 | >; |
| 126 | }; |
| 127 | |
| 128 | mcspi3_pins: pinmux_mcspi3_pins { |
| 129 | pinctrl-single,pins = < |
Eric Witcher | 05bc85d | 2013-10-18 02:42:34 -0400 | [diff] [blame] | 130 | 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi3_somi */ |
| 131 | 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */ |
| 132 | 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi3_simo */ |
| 133 | 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi3_clk */ |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 134 | >; |
| 135 | }; |
| 136 | |
| 137 | mcspi4_pins: pinmux_mcspi4_pins { |
| 138 | pinctrl-single,pins = < |
Eric Witcher | 05bc85d | 2013-10-18 02:42:34 -0400 | [diff] [blame] | 139 | 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi4_clk */ |
| 140 | 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi4_simo */ |
| 141 | 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi4_somi */ |
| 142 | 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi4_cs0 */ |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 143 | >; |
| 144 | }; |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 145 | |
| 146 | usbhost_pins: pinmux_usbhost_pins { |
| 147 | pinctrl-single,pins = < |
| 148 | 0x84 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ |
| 149 | 0x86 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */ |
| 150 | |
| 151 | 0x19e (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */ |
| 152 | 0x1a0 (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */ |
| 153 | |
| 154 | 0x70 (PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */ |
| 155 | 0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */ |
| 156 | >; |
| 157 | }; |
Dan Murphy | 6615530 | 2013-06-07 18:52:49 +0530 | [diff] [blame] | 158 | |
| 159 | led_gpio_pins: pinmux_led_gpio_pins { |
| 160 | pinctrl-single,pins = < |
| 161 | 0x196 (PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */ |
| 162 | >; |
| 163 | }; |
Sourav Poddar | ed22fee | 2013-06-07 18:52:50 +0530 | [diff] [blame] | 164 | |
| 165 | uart1_pins: pinmux_uart1_pins { |
| 166 | pinctrl-single,pins = < |
| 167 | 0x60 (PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */ |
| 168 | 0x62 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */ |
| 169 | 0x64 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */ |
| 170 | 0x66 (PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */ |
| 171 | >; |
| 172 | }; |
| 173 | |
| 174 | uart3_pins: pinmux_uart3_pins { |
| 175 | pinctrl-single,pins = < |
| 176 | 0x19a (PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */ |
| 177 | 0x19c (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */ |
| 178 | >; |
| 179 | }; |
| 180 | |
| 181 | uart5_pins: pinmux_uart5_pins { |
| 182 | pinctrl-single,pins = < |
| 183 | 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */ |
| 184 | 0x172 (PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */ |
| 185 | 0x174 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */ |
| 186 | 0x176 (PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */ |
| 187 | >; |
| 188 | }; |
| 189 | |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 190 | }; |
| 191 | |
| 192 | &omap5_pmx_wkup { |
| 193 | pinctrl-names = "default"; |
| 194 | pinctrl-0 = < |
| 195 | &usbhost_wkup_pins |
| 196 | >; |
| 197 | |
| 198 | usbhost_wkup_pins: pinmux_usbhost_wkup_pins { |
| 199 | pinctrl-single,pins = < |
| 200 | 0x1A (PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */ |
| 201 | >; |
| 202 | }; |
Peter Ujfalusi | 8bbacc5 | 2012-10-04 14:57:28 +0300 | [diff] [blame] | 203 | }; |
| 204 | |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 205 | &mmc1 { |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame] | 206 | vmmc-supply = <&ldo9_reg>; |
Balaji T K | 5dd18b0 | 2012-08-07 12:48:21 +0530 | [diff] [blame] | 207 | bus-width = <4>; |
| 208 | }; |
| 209 | |
| 210 | &mmc2 { |
| 211 | vmmc-supply = <&vmmcsd_fixed>; |
| 212 | bus-width = <8>; |
| 213 | ti,non-removable; |
| 214 | }; |
| 215 | |
| 216 | &mmc3 { |
| 217 | bus-width = <4>; |
| 218 | ti,non-removable; |
| 219 | }; |
| 220 | |
| 221 | &mmc4 { |
| 222 | status = "disabled"; |
| 223 | }; |
| 224 | |
| 225 | &mmc5 { |
| 226 | status = "disabled"; |
R Sricharan | 6b5de09 | 2012-05-10 19:46:00 +0530 | [diff] [blame] | 227 | }; |
Sourav Poddar | 08f3e21 | 2012-07-25 11:02:43 +0530 | [diff] [blame] | 228 | |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 229 | &i2c1 { |
| 230 | pinctrl-names = "default"; |
| 231 | pinctrl-0 = <&i2c1_pins>; |
| 232 | |
| 233 | clock-frequency = <400000>; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 234 | |
| 235 | palmas: palmas@48 { |
| 236 | compatible = "ti,palmas"; |
| 237 | interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ |
| 238 | interrupt-parent = <&gic>; |
| 239 | reg = <0x48>; |
| 240 | interrupt-controller; |
| 241 | #interrupt-cells = <2>; |
Nishanth Menon | 8658337 | 2013-09-19 14:11:36 -0500 | [diff] [blame] | 242 | ti,system-power-controller; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 243 | |
Felipe Balbi | e3a412c | 2013-08-21 20:01:32 +0530 | [diff] [blame] | 244 | extcon_usb3: palmas_usb { |
| 245 | compatible = "ti,palmas-usb-vid"; |
| 246 | ti,enable-vbus-detection; |
| 247 | ti,enable-id-detection; |
| 248 | ti,wakeup; |
| 249 | }; |
| 250 | |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 251 | palmas_pmic { |
| 252 | compatible = "ti,palmas-pmic"; |
| 253 | interrupt-parent = <&palmas>; |
| 254 | interrupts = <14 IRQ_TYPE_NONE>; |
| 255 | interrupt-name = "short-irq"; |
| 256 | |
| 257 | ti,ldo6-vibrator; |
| 258 | |
| 259 | regulators { |
| 260 | smps123_reg: smps123 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 261 | /* VDD_OPP_MPU */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 262 | regulator-name = "smps123"; |
| 263 | regulator-min-microvolt = < 600000>; |
| 264 | regulator-max-microvolt = <1500000>; |
| 265 | regulator-always-on; |
| 266 | regulator-boot-on; |
| 267 | }; |
| 268 | |
| 269 | smps45_reg: smps45 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 270 | /* VDD_OPP_MM */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 271 | regulator-name = "smps45"; |
| 272 | regulator-min-microvolt = < 600000>; |
| 273 | regulator-max-microvolt = <1310000>; |
| 274 | regulator-always-on; |
| 275 | regulator-boot-on; |
| 276 | }; |
| 277 | |
| 278 | smps6_reg: smps6 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 279 | /* VDD_DDR3 - over VDD_SMPS6 */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 280 | regulator-name = "smps6"; |
| 281 | regulator-min-microvolt = <1200000>; |
| 282 | regulator-max-microvolt = <1200000>; |
| 283 | regulator-always-on; |
| 284 | regulator-boot-on; |
| 285 | }; |
| 286 | |
| 287 | smps7_reg: smps7 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 288 | /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 289 | regulator-name = "smps7"; |
| 290 | regulator-min-microvolt = <1800000>; |
| 291 | regulator-max-microvolt = <1800000>; |
| 292 | regulator-always-on; |
| 293 | regulator-boot-on; |
| 294 | }; |
| 295 | |
| 296 | smps8_reg: smps8 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 297 | /* VDD_OPP_CORE */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 298 | regulator-name = "smps8"; |
| 299 | regulator-min-microvolt = < 600000>; |
| 300 | regulator-max-microvolt = <1310000>; |
| 301 | regulator-always-on; |
| 302 | regulator-boot-on; |
| 303 | }; |
| 304 | |
| 305 | smps9_reg: smps9 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 306 | /* VDDA_2v1_AUD over VDD_2v1 */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 307 | regulator-name = "smps9"; |
| 308 | regulator-min-microvolt = <2100000>; |
| 309 | regulator-max-microvolt = <2100000>; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 310 | ti,smps-range = <0x80>; |
| 311 | }; |
| 312 | |
Kishon Vijay Abraham I | 9448996 | 2013-08-12 15:07:01 +0530 | [diff] [blame] | 313 | smps10_out2_reg: smps10_out2 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 314 | /* VBUS_5V_OTG */ |
Kishon Vijay Abraham I | 9448996 | 2013-08-12 15:07:01 +0530 | [diff] [blame] | 315 | regulator-name = "smps10_out2"; |
| 316 | regulator-min-microvolt = <5000000>; |
| 317 | regulator-max-microvolt = <5000000>; |
| 318 | regulator-always-on; |
| 319 | regulator-boot-on; |
| 320 | }; |
| 321 | |
| 322 | smps10_out1_reg: smps10_out1 { |
| 323 | /* VBUS_5V_OTG */ |
| 324 | regulator-name = "smps10_out1"; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 325 | regulator-min-microvolt = <5000000>; |
| 326 | regulator-max-microvolt = <5000000>; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 327 | }; |
| 328 | |
| 329 | ldo1_reg: ldo1 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 330 | /* VDDAPHY_CAM: vdda_csiport */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 331 | regulator-name = "ldo1"; |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame] | 332 | regulator-min-microvolt = <1500000>; |
| 333 | regulator-max-microvolt = <1800000>; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 334 | }; |
| 335 | |
| 336 | ldo2_reg: ldo2 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 337 | /* VCC_2V8_DISP: Does not go anywhere */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 338 | regulator-name = "ldo2"; |
Nishanth Menon | bd3c554 | 2013-07-29 12:03:03 -0500 | [diff] [blame] | 339 | regulator-min-microvolt = <2800000>; |
| 340 | regulator-max-microvolt = <2800000>; |
| 341 | /* Unused */ |
| 342 | status = "disabled"; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 343 | }; |
| 344 | |
| 345 | ldo3_reg: ldo3 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 346 | /* VDDAPHY_MDM: vdda_lli */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 347 | regulator-name = "ldo3"; |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame] | 348 | regulator-min-microvolt = <1500000>; |
| 349 | regulator-max-microvolt = <1500000>; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 350 | regulator-boot-on; |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame] | 351 | /* Only if Modem is used */ |
| 352 | status = "disabled"; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 353 | }; |
| 354 | |
| 355 | ldo4_reg: ldo4 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 356 | /* VDDAPHY_DISP: vdda_dsiport/hdmi */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 357 | regulator-name = "ldo4"; |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame] | 358 | regulator-min-microvolt = <1500000>; |
| 359 | regulator-max-microvolt = <1800000>; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 360 | }; |
| 361 | |
| 362 | ldo5_reg: ldo5 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 363 | /* VDDA_1V8_PHY: usb/sata/hdmi.. */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 364 | regulator-name = "ldo5"; |
| 365 | regulator-min-microvolt = <1800000>; |
| 366 | regulator-max-microvolt = <1800000>; |
| 367 | regulator-always-on; |
| 368 | regulator-boot-on; |
| 369 | }; |
| 370 | |
| 371 | ldo6_reg: ldo6 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 372 | /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 373 | regulator-name = "ldo6"; |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame] | 374 | regulator-min-microvolt = <1200000>; |
| 375 | regulator-max-microvolt = <1200000>; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 376 | regulator-always-on; |
| 377 | regulator-boot-on; |
| 378 | }; |
| 379 | |
| 380 | ldo7_reg: ldo7 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 381 | /* VDD_VPP: vpp1 */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 382 | regulator-name = "ldo7"; |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame] | 383 | regulator-min-microvolt = <2000000>; |
| 384 | regulator-max-microvolt = <2000000>; |
| 385 | /* Only for efuse reprograming! */ |
| 386 | status = "disabled"; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 387 | }; |
| 388 | |
| 389 | ldo8_reg: ldo8 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 390 | /* VDD_3v0: Does not go anywhere */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 391 | regulator-name = "ldo8"; |
Nishanth Menon | bd3c554 | 2013-07-29 12:03:03 -0500 | [diff] [blame] | 392 | regulator-min-microvolt = <3000000>; |
| 393 | regulator-max-microvolt = <3000000>; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 394 | regulator-boot-on; |
Nishanth Menon | bd3c554 | 2013-07-29 12:03:03 -0500 | [diff] [blame] | 395 | /* Unused */ |
| 396 | status = "disabled"; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 397 | }; |
| 398 | |
| 399 | ldo9_reg: ldo9 { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 400 | /* VCC_DV_SDIO: vdds_sdcard */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 401 | regulator-name = "ldo9"; |
| 402 | regulator-min-microvolt = <1800000>; |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame] | 403 | regulator-max-microvolt = <3000000>; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 404 | regulator-boot-on; |
| 405 | }; |
| 406 | |
| 407 | ldoln_reg: ldoln { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 408 | /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 409 | regulator-name = "ldoln"; |
| 410 | regulator-min-microvolt = <1800000>; |
| 411 | regulator-max-microvolt = <1800000>; |
| 412 | regulator-always-on; |
| 413 | regulator-boot-on; |
| 414 | }; |
| 415 | |
| 416 | ldousb_reg: ldousb { |
Nishanth Menon | 3709d32 | 2013-07-29 12:03:01 -0500 | [diff] [blame] | 417 | /* VDDA_3V_USB: VDDA_USBHS33 */ |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 418 | regulator-name = "ldousb"; |
| 419 | regulator-min-microvolt = <3250000>; |
| 420 | regulator-max-microvolt = <3250000>; |
| 421 | regulator-always-on; |
| 422 | regulator-boot-on; |
| 423 | }; |
Nishanth Menon | e18235a | 2013-07-29 12:03:02 -0500 | [diff] [blame] | 424 | |
| 425 | regen3_reg: regen3 { |
| 426 | /* REGEN3 controls LDO9 supply to card */ |
| 427 | regulator-name = "regen3"; |
| 428 | regulator-always-on; |
| 429 | regulator-boot-on; |
| 430 | }; |
J Keerthy | e00c27e | 2013-06-13 10:00:11 +0530 | [diff] [blame] | 431 | }; |
| 432 | }; |
| 433 | }; |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 434 | }; |
| 435 | |
Sourav Poddar | 9be495c | 2013-02-13 14:58:22 +0530 | [diff] [blame] | 436 | &i2c5 { |
| 437 | pinctrl-names = "default"; |
| 438 | pinctrl-0 = <&i2c5_pins>; |
| 439 | |
| 440 | clock-frequency = <400000>; |
| 441 | }; |
| 442 | |
Peter Ujfalusi | 42601d5 | 2012-10-04 14:57:24 +0300 | [diff] [blame] | 443 | &mcbsp3 { |
| 444 | status = "disabled"; |
| 445 | }; |
Lokesh Vutla | 4d2750f | 2012-11-05 18:22:52 +0530 | [diff] [blame] | 446 | |
Roger Quadros | ed7f8e8 | 2013-06-07 18:52:48 +0530 | [diff] [blame] | 447 | &usbhshost { |
| 448 | port2-mode = "ehci-hsic"; |
| 449 | port3-mode = "ehci-hsic"; |
| 450 | }; |
| 451 | |
| 452 | &usbhsehci { |
| 453 | phys = <0 &hsusb2_phy &hsusb3_phy>; |
| 454 | }; |
| 455 | |
Felipe Balbi | e3a412c | 2013-08-21 20:01:32 +0530 | [diff] [blame] | 456 | &usb3 { |
| 457 | extcon = <&extcon_usb3>; |
| 458 | vbus-supply = <&smps10_out1_reg>; |
| 459 | }; |
| 460 | |
Sourav Poddar | 392adaf | 2013-02-13 14:58:44 +0530 | [diff] [blame] | 461 | &mcspi1 { |
| 462 | |
| 463 | }; |
| 464 | |
| 465 | &mcspi2 { |
| 466 | pinctrl-names = "default"; |
| 467 | pinctrl-0 = <&mcspi2_pins>; |
| 468 | }; |
| 469 | |
| 470 | &mcspi3 { |
| 471 | pinctrl-names = "default"; |
| 472 | pinctrl-0 = <&mcspi3_pins>; |
| 473 | }; |
| 474 | |
| 475 | &mcspi4 { |
| 476 | pinctrl-names = "default"; |
| 477 | pinctrl-0 = <&mcspi4_pins>; |
| 478 | }; |
Sourav Poddar | ed22fee | 2013-06-07 18:52:50 +0530 | [diff] [blame] | 479 | |
| 480 | &uart1 { |
| 481 | pinctrl-names = "default"; |
| 482 | pinctrl-0 = <&uart1_pins>; |
| 483 | }; |
| 484 | |
| 485 | &uart3 { |
| 486 | pinctrl-names = "default"; |
| 487 | pinctrl-0 = <&uart3_pins>; |
| 488 | }; |
| 489 | |
| 490 | &uart5 { |
| 491 | pinctrl-names = "default"; |
| 492 | pinctrl-0 = <&uart5_pins>; |
| 493 | }; |
Nishanth Menon | b8981d7 | 2013-10-16 10:39:04 -0500 | [diff] [blame] | 494 | |
| 495 | &cpu0 { |
| 496 | cpu0-supply = <&smps123_reg>; |
| 497 | }; |