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review.shift-gmbh.com / SHIFTPHONES / kernel / common / fa63d037283a6bd0db96078d87192d1aaa073f3c / . / arch / arm / boot / dts / omap5-uevm.dts
blob: 843a0018d541f52506c3adf1cadb5f95a55f3695 [file] [log] [blame]
R Sricharan6b5de092012-05-10 19:46:00 +0530[diff] [blame]1/*
Sricharan Rfa63d032013-06-07 18:52:47 +0530[diff] [blame^]2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
R Sricharan6b5de092012-05-10 19:46:00 +0530[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
Florian Vaussard98ef79572013-05-31 14:32:55 +0200[diff] [blame]10#include "omap5.dtsi"
R Sricharan6b5de092012-05-10 19:46:00 +0530[diff] [blame]11
12/ {
Sricharan Rfa63d032013-06-07 18:52:47 +0530[diff] [blame^]13 model = "TI OMAP5 uEVM board";
14 compatible = "ti,omap5-uevm", "ti,omap5";
R Sricharan6b5de092012-05-10 19:46:00 +0530[diff] [blame]15
16 memory {
17 device_type = "memory";
Santosh Shilimkar03178c62013-01-18 11:43:16 +0530[diff] [blame]18 reg = <0x80000000 0x7F000000>; /* 2032 MB */
R Sricharan6b5de092012-05-10 19:46:00 +0530[diff] [blame]19 };
Balaji T K5dd18b02012-08-07 12:48:21 +0530[diff] [blame]20
21 vmmcsd_fixed: fixedregulator-mmcsd {
22 compatible = "regulator-fixed";
23 regulator-name = "vmmcsd_fixed";
24 regulator-min-microvolt = <3000000>;
25 regulator-max-microvolt = <3000000>;
26 };
Sourav Poddar5449fbc2012-07-25 11:03:27 +0530[diff] [blame]27
Balaji T K5dd18b02012-08-07 12:48:21 +0530[diff] [blame]28};
29
Peter Ujfalusi8bbacc52012-10-04 14:57:28 +0300[diff] [blame]30&omap5_pmx_core {
31 pinctrl-names = "default";
32 pinctrl-0 = <
33 &twl6040_pins
34 &mcpdm_pins
35 &dmic_pins
36 &mcbsp1_pins
37 &mcbsp2_pins
38 >;
39
40 twl6040_pins: pinmux_twl6040_pins {
41 pinctrl-single,pins = <
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200[diff] [blame]42 0x18a (PIN_OUTPUT | MUX_MODE6) /* perslimbus2_clock.gpio5_145 */
Peter Ujfalusi8bbacc52012-10-04 14:57:28 +0300[diff] [blame]43 >;
44 };
45
46 mcpdm_pins: pinmux_mcpdm_pins {
47 pinctrl-single,pins = <
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200[diff] [blame]48 0x142 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */
49 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */
50 0x15e (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */
51 0x160 (PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */
52 0x162 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */
Peter Ujfalusi8bbacc52012-10-04 14:57:28 +0300[diff] [blame]53 >;
54 };
55
56 dmic_pins: pinmux_dmic_pins {
57 pinctrl-single,pins = <
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200[diff] [blame]58 0x144 (PIN_INPUT | MUX_MODE0) /* abedmic_din1.abedmic_din1 */
59 0x146 (PIN_INPUT | MUX_MODE0) /* abedmic_din2.abedmic_din2 */
60 0x148 (PIN_INPUT | MUX_MODE0) /* abedmic_din3.abedmic_din3 */
61 0x14a (PIN_OUTPUT | MUX_MODE0) /* abedmic_clk1.abedmic_clk1 */
Peter Ujfalusi8bbacc52012-10-04 14:57:28 +0300[diff] [blame]62 >;
63 };
64
65 mcbsp1_pins: pinmux_mcbsp1_pins {
66 pinctrl-single,pins = <
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200[diff] [blame]67 0x14c (PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */
68 0x14e (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */
69 0x150 (PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */
70 0x152 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */
Peter Ujfalusi8bbacc52012-10-04 14:57:28 +0300[diff] [blame]71 >;
72 };
73
74 mcbsp2_pins: pinmux_mcbsp2_pins {
75 pinctrl-single,pins = <
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200[diff] [blame]76 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */
77 0x156 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */
78 0x158 (PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */
79 0x15a (PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */
Peter Ujfalusi8bbacc52012-10-04 14:57:28 +0300[diff] [blame]80 >;
81 };
Sourav Poddar9be495c2013-02-13 14:58:22 +0530[diff] [blame]82
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200[diff] [blame]83 i2c1_pins: pinmux_i2c1_pins {
84 pinctrl-single,pins = <
85 0x1b2 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
86 0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
87 >;
88 };
Sourav Poddar9be495c2013-02-13 14:58:22 +0530[diff] [blame]89
Sourav Poddar9be495c2013-02-13 14:58:22 +0530[diff] [blame]90 i2c5_pins: pinmux_i2c5_pins {
91 pinctrl-single,pins = <
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200[diff] [blame]92 0x184 (PIN_INPUT | MUX_MODE0) /* i2c5_scl */
93 0x186 (PIN_INPUT | MUX_MODE0) /* i2c5_sda */
Sourav Poddar9be495c2013-02-13 14:58:22 +0530[diff] [blame]94 >;
95 };
Sourav Poddar392adaf2013-02-13 14:58:44 +0530[diff] [blame]96
97 mcspi2_pins: pinmux_mcspi2_pins {
98 pinctrl-single,pins = <
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200[diff] [blame]99 0xbc (PIN_INPUT | MUX_MODE0) /* mcspi2_clk */
100 0xbe (PIN_INPUT | MUX_MODE0) /* mcspi2_simo */
101 0xc0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */
102 0xc2 (PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs */
Sourav Poddar392adaf2013-02-13 14:58:44 +0530[diff] [blame]103 >;
104 };
105
106 mcspi3_pins: pinmux_mcspi3_pins {
107 pinctrl-single,pins = <
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200[diff] [blame]108 0x78 (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */
109 0x7a (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */
110 0x7c (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */
111 0x7e (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */
Sourav Poddar392adaf2013-02-13 14:58:44 +0530[diff] [blame]112 >;
113 };
114
115 mcspi4_pins: pinmux_mcspi4_pins {
116 pinctrl-single,pins = <
Florian Vaussardbcd3cca2013-05-31 14:32:59 +0200[diff] [blame]117 0x164 (PIN_INPUT | MUX_MODE1) /* mcspi2_clk */
118 0x168 (PIN_INPUT | MUX_MODE1) /* mcspi2_simo */
119 0x16a (PIN_INPUT | MUX_MODE1) /* mcspi2_somi */
120 0x16c (PIN_INPUT | MUX_MODE1) /* mcspi2_cs */
Sourav Poddar392adaf2013-02-13 14:58:44 +0530[diff] [blame]121 >;
122 };
Peter Ujfalusi8bbacc52012-10-04 14:57:28 +0300[diff] [blame]123};
124
Balaji T K5dd18b02012-08-07 12:48:21 +0530[diff] [blame]125&mmc1 {
126 vmmc-supply = <&vmmcsd_fixed>;
127 bus-width = <4>;
128};
129
130&mmc2 {
131 vmmc-supply = <&vmmcsd_fixed>;
132 bus-width = <8>;
133 ti,non-removable;
134};
135
136&mmc3 {
137 bus-width = <4>;
138 ti,non-removable;
139};
140
141&mmc4 {
142 status = "disabled";
143};
144
145&mmc5 {
146 status = "disabled";
R Sricharan6b5de092012-05-10 19:46:00 +0530[diff] [blame]147};
Sourav Poddar08f3e212012-07-25 11:02:43 +0530[diff] [blame]148
Sourav Poddar9be495c2013-02-13 14:58:22 +0530[diff] [blame]149&i2c1 {
150 pinctrl-names = "default";
151 pinctrl-0 = <&i2c1_pins>;
152
153 clock-frequency = <400000>;
154};
155
Sourav Poddar9be495c2013-02-13 14:58:22 +0530[diff] [blame]156&i2c5 {
157 pinctrl-names = "default";
158 pinctrl-0 = <&i2c5_pins>;
159
160 clock-frequency = <400000>;
161};
162
Peter Ujfalusi42601d52012-10-04 14:57:24 +0300[diff] [blame]163&mcbsp3 {
164 status = "disabled";
165};
Lokesh Vutla4d2750f2012-11-05 18:22:52 +0530[diff] [blame]166
Sourav Poddar392adaf2013-02-13 14:58:44 +0530[diff] [blame]167&mcspi1 {
168
169};
170
171&mcspi2 {
172 pinctrl-names = "default";
173 pinctrl-0 = <&mcspi2_pins>;
174};
175
176&mcspi3 {
177 pinctrl-names = "default";
178 pinctrl-0 = <&mcspi3_pins>;
179};
180
181&mcspi4 {
182 pinctrl-names = "default";
183 pinctrl-0 = <&mcspi4_pins>;
184};