blob: 72e5a842cdae0a82b4a820dde6eb0b59904b87a3 [file] [log] [blame]
Thomas Petazzonif6e916b2012-11-20 23:00:52 +01001config IRQCHIP
2 def_bool y
3 depends on OF_IRQ
4
Rob Herring81243e42012-11-20 21:21:40 -06005config ARM_GIC
6 bool
7 select IRQ_DOMAIN
Yingjoe Chen9a1091e2014-11-25 16:04:19 +08008 select IRQ_DOMAIN_HIERARCHY
Rob Herring81243e42012-11-20 21:21:40 -06009 select MULTI_IRQ_HANDLER
10
Linus Walleija27d21e2015-12-18 10:44:53 +010011config ARM_GIC_MAX_NR
12 int
13 default 2 if ARCH_REALVIEW
14 default 1
15
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +000016config ARM_GIC_V2M
17 bool
18 depends on ARM_GIC
19 depends on PCI && PCI_MSI
20 select PCI_MSI_IRQ_DOMAIN
21
Rob Herring81243e42012-11-20 21:21:40 -060022config GIC_NON_BANKED
23 bool
24
Marc Zyngier021f6532014-06-30 16:01:31 +010025config ARM_GIC_V3
26 bool
27 select IRQ_DOMAIN
28 select MULTI_IRQ_HANDLER
Marc Zyngier443acc42014-11-24 14:35:09 +000029 select IRQ_DOMAIN_HIERARCHY
Marc Zyngier021f6532014-06-30 16:01:31 +010030
Marc Zyngier19812722014-11-24 14:35:19 +000031config ARM_GIC_V3_ITS
32 bool
33 select PCI_MSI_IRQ_DOMAIN
Uwe Kleine-König292ec082013-06-26 09:18:48 +020034
Ma Jun717c3db2015-12-17 19:56:35 +080035config HISILICON_IRQ_MBIGEN
36 bool "Support mbigen interrupt controller"
37 default n
38 depends on ARM_GIC_V3 && ARM_GIC_V3_ITS && GENERIC_MSI_IRQ_DOMAIN
39 help
40 Enable the mbigen interrupt controller used on
41 Hisilicon platform.
42
Rob Herring44430ec2012-10-27 17:25:26 -050043config ARM_NVIC
44 bool
45 select IRQ_DOMAIN
Stefan Agner2d9f59f2015-05-16 11:44:16 +020046 select IRQ_DOMAIN_HIERARCHY
Rob Herring44430ec2012-10-27 17:25:26 -050047 select GENERIC_IRQ_CHIP
48
49config ARM_VIC
50 bool
51 select IRQ_DOMAIN
52 select MULTI_IRQ_HANDLER
53
54config ARM_VIC_NR
55 int
56 default 4 if ARCH_S5PV210
Rob Herring44430ec2012-10-27 17:25:26 -050057 default 2
58 depends on ARM_VIC
59 help
60 The maximum number of VICs available in the system, for
61 power management.
62
Thomas Petazzonifed6d332016-02-10 15:46:56 +010063config ARMADA_370_XP_IRQ
64 bool
Thomas Petazzonifed6d332016-02-10 15:46:56 +010065 select GENERIC_IRQ_CHIP
Thomas Petazzonifcc392d2016-02-10 15:46:57 +010066 select PCI_MSI_IRQ_DOMAIN if PCI_MSI
Thomas Petazzonifed6d332016-02-10 15:46:56 +010067
Boris BREZILLONb1479eb2014-07-10 19:14:18 +020068config ATMEL_AIC_IRQ
69 bool
70 select GENERIC_IRQ_CHIP
71 select IRQ_DOMAIN
72 select MULTI_IRQ_HANDLER
73 select SPARSE_IRQ
74
75config ATMEL_AIC5_IRQ
76 bool
77 select GENERIC_IRQ_CHIP
78 select IRQ_DOMAIN
79 select MULTI_IRQ_HANDLER
80 select SPARSE_IRQ
81
Ralf Baechle0509cfd2015-07-08 14:46:08 +020082config I8259
83 bool
84 select IRQ_DOMAIN
85
Kevin Cernekee5f7f0312014-12-25 09:49:06 -080086config BCM7038_L1_IRQ
87 bool
88 select GENERIC_IRQ_CHIP
89 select IRQ_DOMAIN
90
Kevin Cernekeea4fcbb82014-11-06 22:44:27 -080091config BCM7120_L2_IRQ
92 bool
93 select GENERIC_IRQ_CHIP
94 select IRQ_DOMAIN
95
Florian Fainelli7f646e92014-05-23 17:40:53 -070096config BRCMSTB_L2_IRQ
97 bool
Florian Fainelli7f646e92014-05-23 17:40:53 -070098 select GENERIC_IRQ_CHIP
99 select IRQ_DOMAIN
100
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200101config DW_APB_ICTL
102 bool
Jisheng Zhange1588492014-10-22 20:59:10 +0800103 select GENERIC_IRQ_CHIP
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200104 select IRQ_DOMAIN
105
James Hoganb6ef9162013-04-22 15:43:50 +0100106config IMGPDC_IRQ
107 bool
108 select GENERIC_IRQ_CHIP
109 select IRQ_DOMAIN
110
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200111config IRQ_MIPS_CPU
112 bool
113 select GENERIC_IRQ_CHIP
114 select IRQ_DOMAIN
115
Alexander Shiyanafc98d92014-02-02 12:07:46 +0400116config CLPS711X_IRQCHIP
117 bool
118 depends on ARCH_CLPS711X
119 select IRQ_DOMAIN
120 select MULTI_IRQ_HANDLER
121 select SPARSE_IRQ
122 default y
123
Stefan Kristiansson4db8e6d2014-05-26 23:31:42 +0300124config OR1K_PIC
125 bool
126 select IRQ_DOMAIN
127
Felipe Balbi85980662014-09-15 16:15:02 -0500128config OMAP_IRQCHIP
129 bool
130 select GENERIC_IRQ_CHIP
131 select IRQ_DOMAIN
132
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200133config ORION_IRQCHIP
134 bool
135 select IRQ_DOMAIN
136 select MULTI_IRQ_HANDLER
137
Cristian Birsanaaa86662016-01-13 18:15:35 -0700138config PIC32_EVIC
139 bool
140 select GENERIC_IRQ_CHIP
141 select IRQ_DOMAIN
142
Magnus Damm44358042013-02-18 23:28:34 +0900143config RENESAS_INTC_IRQPIN
144 bool
145 select IRQ_DOMAIN
146
Magnus Dammfbc83b72013-02-27 17:15:01 +0900147config RENESAS_IRQC
148 bool
Magnus Damm99c221d2015-09-28 18:42:37 +0900149 select GENERIC_IRQ_CHIP
Magnus Dammfbc83b72013-02-27 17:15:01 +0900150 select IRQ_DOMAIN
151
Lee Jones07088482015-02-18 15:13:58 +0000152config ST_IRQCHIP
153 bool
154 select REGMAP
155 select MFD_SYSCON
156 help
157 Enables SysCfg Controlled IRQs on STi based platforms.
158
Christian Ruppertb06eb012013-06-25 18:29:57 +0200159config TB10X_IRQC
160 bool
161 select IRQ_DOMAIN
162 select GENERIC_IRQ_CHIP
163
Damien Riegeld01f8632015-12-21 15:11:23 -0500164config TS4800_IRQ
165 tristate "TS-4800 IRQ controller"
166 select IRQ_DOMAIN
Richard Weinberger0df337c2016-01-25 23:24:17 +0100167 depends on HAS_IOMEM
Jean Delvared2b383d2016-02-09 11:19:20 +0100168 depends on SOC_IMX51 || COMPILE_TEST
Damien Riegeld01f8632015-12-21 15:11:23 -0500169 help
170 Support for the TS-4800 FPGA IRQ controller
171
Linus Walleij2389d502012-10-31 22:04:31 +0100172config VERSATILE_FPGA_IRQ
173 bool
174 select IRQ_DOMAIN
175
176config VERSATILE_FPGA_IRQ_NR
177 int
178 default 4
179 depends on VERSATILE_FPGA_IRQ
Max Filippov26a8e962013-12-01 12:04:57 +0400180
181config XTENSA_MX
182 bool
183 select IRQ_DOMAIN
Sricharan R96ca8482013-12-03 15:57:23 +0530184
185config IRQ_CROSSBAR
186 bool
187 help
Masanari Iidaf54619f2014-09-18 12:09:42 +0900188 Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R96ca8482013-12-03 15:57:23 +0530189 The primary irqchip invokes the crossbar's callback which inturn allocates
190 a free irq and configures the IP. Thus the peripheral interrupts are
191 routed to one of the free irqchip interrupt lines.
Grygorii Strashko89323f82014-07-23 17:40:30 +0300192
193config KEYSTONE_IRQ
194 tristate "Keystone 2 IRQ controller IP"
195 depends on ARCH_KEYSTONE
196 help
197 Support for Texas Instruments Keystone 2 IRQ controller IP which
198 is part of the Keystone 2 IPC mechanism
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700199
200config MIPS_GIC
201 bool
202 select MIPS_CM
Yoshinori Sato8a764482015-05-10 02:30:47 +0900203
Paul Burton44e08e72015-05-24 16:11:31 +0100204config INGENIC_IRQ
205 bool
206 depends on MACH_INGENIC
207 default y
Linus Torvalds78c10e52015-06-27 12:44:34 -0700208
Yoshinori Sato8a764482015-05-10 02:30:47 +0900209config RENESAS_H8300H_INTC
210 bool
211 select IRQ_DOMAIN
212
213config RENESAS_H8S_INTC
214 bool
Linus Torvalds78c10e52015-06-27 12:44:34 -0700215 select IRQ_DOMAIN
Shenwei Wange324c4d2015-08-24 14:04:15 -0500216
217config IMX_GPCV2
218 bool
219 select IRQ_DOMAIN
220 help
221 Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200222
223config IRQ_MXS
224 def_bool y if MACH_ASM9260 || ARCH_MXS
225 select IRQ_DOMAIN
226 select STMP_DEVICE