Blame - drivers/irqchip/Kconfig - SHIFTPHONES/kernel/common

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Thomas Petazzoni	f6e916b	2012-11-20 23:00:52 +0100	[diff] [blame]	1	config IRQCHIP
				2	def_bool y
				3	depends on OF_IRQ
				4
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	5	config ARM_GIC
				6	bool
				7	select IRQ_DOMAIN
Yingjoe Chen	9a1091e	2014-11-25 16:04:19 +0800	[diff] [blame]	8	select IRQ_DOMAIN_HIERARCHY
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	9	select MULTI_IRQ_HANDLER
				10
Suravee Suthikulpanit	853a33c	2014-11-25 18:47:22 +0000	[diff] [blame]	11	config ARM_GIC_V2M
				12	bool
				13	depends on ARM_GIC
				14	depends on PCI && PCI_MSI
				15	select PCI_MSI_IRQ_DOMAIN
				16
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	17	config GIC_NON_BANKED
				18	bool
				19
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	20	config ARM_GIC_V3
				21	bool
				22	select IRQ_DOMAIN
				23	select MULTI_IRQ_HANDLER
Marc Zyngier	443acc4	2014-11-24 14:35:09 +0000	[diff] [blame]	24	select IRQ_DOMAIN_HIERARCHY
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	25
Marc Zyngier	1981272	2014-11-24 14:35:19 +0000	[diff] [blame]	26	config ARM_GIC_V3_ITS
				27	bool
				28	select PCI_MSI_IRQ_DOMAIN
Uwe Kleine-König	292ec08	2013-06-26 09:18:48 +0200	[diff] [blame]	29
Ma Jun	717c3db	2015-12-17 19:56:35 +0800	[diff] [blame^]	30	config HISILICON_IRQ_MBIGEN
				31	bool "Support mbigen interrupt controller"
				32	default n
				33	depends on ARM_GIC_V3 && ARM_GIC_V3_ITS && GENERIC_MSI_IRQ_DOMAIN
				34	help
				35	Enable the mbigen interrupt controller used on
				36	Hisilicon platform.
				37
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	38	config ARM_NVIC
				39	bool
				40	select IRQ_DOMAIN
Stefan Agner	2d9f59f	2015-05-16 11:44:16 +0200	[diff] [blame]	41	select IRQ_DOMAIN_HIERARCHY
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	42	select GENERIC_IRQ_CHIP
				43
				44	config ARM_VIC
				45	bool
				46	select IRQ_DOMAIN
				47	select MULTI_IRQ_HANDLER
				48
				49	config ARM_VIC_NR
				50	int
				51	default 4 if ARCH_S5PV210
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	52	default 2
				53	depends on ARM_VIC
				54	help
				55	The maximum number of VICs available in the system, for
				56	power management.
				57
Boris BREZILLON	b1479eb	2014-07-10 19:14:18 +0200	[diff] [blame]	58	config ATMEL_AIC_IRQ
				59	bool
				60	select GENERIC_IRQ_CHIP
				61	select IRQ_DOMAIN
				62	select MULTI_IRQ_HANDLER
				63	select SPARSE_IRQ
				64
				65	config ATMEL_AIC5_IRQ
				66	bool
				67	select GENERIC_IRQ_CHIP
				68	select IRQ_DOMAIN
				69	select MULTI_IRQ_HANDLER
				70	select SPARSE_IRQ
				71
Ralf Baechle	0509cfd	2015-07-08 14:46:08 +0200	[diff] [blame]	72	config I8259
				73	bool
				74	select IRQ_DOMAIN
				75
Kevin Cernekee	5f7f031	2014-12-25 09:49:06 -0800	[diff] [blame]	76	config BCM7038_L1_IRQ
				77	bool
				78	select GENERIC_IRQ_CHIP
				79	select IRQ_DOMAIN
				80
Kevin Cernekee	a4fcbb8	2014-11-06 22:44:27 -0800	[diff] [blame]	81	config BCM7120_L2_IRQ
				82	bool
				83	select GENERIC_IRQ_CHIP
				84	select IRQ_DOMAIN
				85
Florian Fainelli	7f646e9	2014-05-23 17:40:53 -0700	[diff] [blame]	86	config BRCMSTB_L2_IRQ
				87	bool
Florian Fainelli	7f646e9	2014-05-23 17:40:53 -0700	[diff] [blame]	88	select GENERIC_IRQ_CHIP
				89	select IRQ_DOMAIN
				90
Sebastian Hesselbarth	350d71b9	2013-09-09 14:01:20 +0200	[diff] [blame]	91	config DW_APB_ICTL
				92	bool
Jisheng Zhang	e158849	2014-10-22 20:59:10 +0800	[diff] [blame]	93	select GENERIC_IRQ_CHIP
Sebastian Hesselbarth	350d71b9	2013-09-09 14:01:20 +0200	[diff] [blame]	94	select IRQ_DOMAIN
				95
James Hogan	b6ef916	2013-04-22 15:43:50 +0100	[diff] [blame]	96	config IMGPDC_IRQ
				97	bool
				98	select GENERIC_IRQ_CHIP
				99	select IRQ_DOMAIN
				100
Ralf Baechle	67e38cf	2015-05-26 18:20:06 +0200	[diff] [blame]	101	config IRQ_MIPS_CPU
				102	bool
				103	select GENERIC_IRQ_CHIP
				104	select IRQ_DOMAIN
				105
Alexander Shiyan	afc98d9	2014-02-02 12:07:46 +0400	[diff] [blame]	106	config CLPS711X_IRQCHIP
				107	bool
				108	depends on ARCH_CLPS711X
				109	select IRQ_DOMAIN
				110	select MULTI_IRQ_HANDLER
				111	select SPARSE_IRQ
				112	default y
				113
Stefan Kristiansson	4db8e6d	2014-05-26 23:31:42 +0300	[diff] [blame]	114	config OR1K_PIC
				115	bool
				116	select IRQ_DOMAIN
				117
Felipe Balbi	8598066	2014-09-15 16:15:02 -0500	[diff] [blame]	118	config OMAP_IRQCHIP
				119	bool
				120	select GENERIC_IRQ_CHIP
				121	select IRQ_DOMAIN
				122
Sebastian Hesselbarth	9dbd90f	2013-06-06 18:27:09 +0200	[diff] [blame]	123	config ORION_IRQCHIP
				124	bool
				125	select IRQ_DOMAIN
				126	select MULTI_IRQ_HANDLER
				127
Magnus Damm	4435804	2013-02-18 23:28:34 +0900	[diff] [blame]	128	config RENESAS_INTC_IRQPIN
				129	bool
				130	select IRQ_DOMAIN
				131
Magnus Damm	fbc83b7	2013-02-27 17:15:01 +0900	[diff] [blame]	132	config RENESAS_IRQC
				133	bool
Magnus Damm	99c221d	2015-09-28 18:42:37 +0900	[diff] [blame]	134	select GENERIC_IRQ_CHIP
Magnus Damm	fbc83b7	2013-02-27 17:15:01 +0900	[diff] [blame]	135	select IRQ_DOMAIN
				136
Lee Jones	0708848	2015-02-18 15:13:58 +0000	[diff] [blame]	137	config ST_IRQCHIP
				138	bool
				139	select REGMAP
				140	select MFD_SYSCON
				141	help
				142	Enables SysCfg Controlled IRQs on STi based platforms.
				143
Christian Ruppert	b06eb01	2013-06-25 18:29:57 +0200	[diff] [blame]	144	config TB10X_IRQC
				145	bool
				146	select IRQ_DOMAIN
				147	select GENERIC_IRQ_CHIP
				148
Linus Walleij	2389d50	2012-10-31 22:04:31 +0100	[diff] [blame]	149	config VERSATILE_FPGA_IRQ
				150	bool
				151	select IRQ_DOMAIN
				152
				153	config VERSATILE_FPGA_IRQ_NR
				154	int
				155	default 4
				156	depends on VERSATILE_FPGA_IRQ
Max Filippov	26a8e96	2013-12-01 12:04:57 +0400	[diff] [blame]	157
				158	config XTENSA_MX
				159	bool
				160	select IRQ_DOMAIN
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	161
				162	config IRQ_CROSSBAR
				163	bool
				164	help
Masanari Iida	f54619f	2014-09-18 12:09:42 +0900	[diff] [blame]	165	Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	166	The primary irqchip invokes the crossbar's callback which inturn allocates
				167	a free irq and configures the IP. Thus the peripheral interrupts are
				168	routed to one of the free irqchip interrupt lines.
Grygorii Strashko	89323f8	2014-07-23 17:40:30 +0300	[diff] [blame]	169
				170	config KEYSTONE_IRQ
				171	tristate "Keystone 2 IRQ controller IP"
				172	depends on ARCH_KEYSTONE
				173	help
				174	Support for Texas Instruments Keystone 2 IRQ controller IP which
				175	is part of the Keystone 2 IPC mechanism
Andrew Bresticker	8a19b8f	2014-09-18 14:47:19 -0700	[diff] [blame]	176
				177	config MIPS_GIC
				178	bool
				179	select MIPS_CM
Yoshinori Sato	8a76448	2015-05-10 02:30:47 +0900	[diff] [blame]	180
Paul Burton	44e08e7	2015-05-24 16:11:31 +0100	[diff] [blame]	181	config INGENIC_IRQ
				182	bool
				183	depends on MACH_INGENIC
				184	default y
Linus Torvalds	78c10e5	2015-06-27 12:44:34 -0700	[diff] [blame]	185
Yoshinori Sato	8a76448	2015-05-10 02:30:47 +0900	[diff] [blame]	186	config RENESAS_H8300H_INTC
				187	bool
				188	select IRQ_DOMAIN
				189
				190	config RENESAS_H8S_INTC
				191	bool
Linus Torvalds	78c10e5	2015-06-27 12:44:34 -0700	[diff] [blame]	192	select IRQ_DOMAIN
Shenwei Wang	e324c4d	2015-08-24 14:04:15 -0500	[diff] [blame]	193
				194	config IMX_GPCV2
				195	bool
				196	select IRQ_DOMAIN
				197	help
				198	Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel	7e4ac67	2015-10-12 21:15:34 +0200	[diff] [blame]	199
				200	config IRQ_MXS
				201	def_bool y if MACH_ASM9260 \|\| ARCH_MXS
				202	select IRQ_DOMAIN
				203	select STMP_DEVICE