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Catalin Marinas0aea86a2012-03-05 11:49:32 +00001/*
2 * Based on arch/arm/include/asm/uaccess.h
3 *
4 * Copyright (C) 2012 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18#ifndef __ASM_UACCESS_H
19#define __ASM_UACCESS_H
20
Catalin Marinasbd389672016-07-01 14:58:21 +010021#include <asm/alternative.h>
Catalin Marinas4b65a5d2016-07-01 16:53:00 +010022#include <asm/kernel-pgtable.h>
Catalin Marinasbd389672016-07-01 14:58:21 +010023#include <asm/sysreg.h>
24
Catalin Marinas0aea86a2012-03-05 11:49:32 +000025/*
26 * User space memory access functions
27 */
Andre Przywara87261d12016-10-19 14:40:54 +010028#include <linux/bitops.h>
Yang Shibffe1ba2016-06-08 14:40:56 -070029#include <linux/kasan-checks.h>
Catalin Marinas0aea86a2012-03-05 11:49:32 +000030#include <linux/string.h>
31#include <linux/thread_info.h>
32
James Morse338d4f42015-07-22 19:05:54 +010033#include <asm/cpufeature.h>
Catalin Marinas0aea86a2012-03-05 11:49:32 +000034#include <asm/ptrace.h>
35#include <asm/errno.h>
36#include <asm/memory.h>
37#include <asm/compiler.h>
38
39#define VERIFY_READ 0
40#define VERIFY_WRITE 1
41
42/*
Ard Biesheuvel6c94f272016-01-01 15:02:12 +010043 * The exception table consists of pairs of relative offsets: the first
44 * is the relative offset to an instruction that is allowed to fault,
45 * and the second is the relative offset at which the program should
46 * continue. No registers are modified, so it is entirely up to the
47 * continuation code to figure out what to do.
Catalin Marinas0aea86a2012-03-05 11:49:32 +000048 *
49 * All the routines below use bits of fixup code that are out of line
50 * with the main instruction path. This means when everything is well,
51 * we don't even have to jump over them. Further, they do not intrude
52 * on our cache or tlb entries.
53 */
54
55struct exception_table_entry
56{
Ard Biesheuvel6c94f272016-01-01 15:02:12 +010057 int insn, fixup;
Catalin Marinas0aea86a2012-03-05 11:49:32 +000058};
59
Ard Biesheuvel6c94f272016-01-01 15:02:12 +010060#define ARCH_HAS_RELATIVE_EXTABLE
61
Catalin Marinas0aea86a2012-03-05 11:49:32 +000062extern int fixup_exception(struct pt_regs *regs);
63
64#define KERNEL_DS (-1UL)
65#define get_ds() (KERNEL_DS)
66
67#define USER_DS TASK_SIZE_64
68#define get_fs() (current_thread_info()->addr_limit)
69
70static inline void set_fs(mm_segment_t fs)
71{
72 current_thread_info()->addr_limit = fs;
James Morse57f49592016-02-05 14:58:48 +000073
74 /*
75 * Enable/disable UAO so that copy_to_user() etc can access
76 * kernel memory with the unprivileged instructions.
77 */
78 if (IS_ENABLED(CONFIG_ARM64_UAO) && fs == KERNEL_DS)
79 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO));
80 else
81 asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO,
82 CONFIG_ARM64_UAO));
Catalin Marinas0aea86a2012-03-05 11:49:32 +000083}
84
Michael S. Tsirkin967f0e52015-01-06 15:11:13 +020085#define segment_eq(a, b) ((a) == (b))
Catalin Marinas0aea86a2012-03-05 11:49:32 +000086
87/*
Catalin Marinas0aea86a2012-03-05 11:49:32 +000088 * Test whether a block of memory is a valid user space address.
89 * Returns 1 if the range is valid, 0 otherwise.
90 *
91 * This is equivalent to the following test:
Christopher Covington31b1e942014-03-19 16:29:37 +000092 * (u65)addr + (u65)size <= current->addr_limit
Catalin Marinas0aea86a2012-03-05 11:49:32 +000093 *
94 * This needs 65-bit arithmetic.
95 */
96#define __range_ok(addr, size) \
97({ \
Mark Rutlanda06040d2017-05-03 16:09:35 +010098 unsigned long __addr = (unsigned long __force)(addr); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +000099 unsigned long flag, roksum; \
100 __chk_user_ptr(addr); \
Christopher Covington31b1e942014-03-19 16:29:37 +0000101 asm("adds %1, %1, %3; ccmp %1, %4, #2, cc; cset %0, ls" \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000102 : "=&r" (flag), "=&r" (roksum) \
Mark Rutlanda06040d2017-05-03 16:09:35 +0100103 : "1" (__addr), "Ir" (size), \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000104 "r" (current_thread_info()->addr_limit) \
105 : "cc"); \
106 flag; \
107})
108
Andre Przywara87261d12016-10-19 14:40:54 +0100109/*
Kristina Martsenko7dcd9dd82017-05-03 16:37:46 +0100110 * When dealing with data aborts, watchpoints, or instruction traps we may end
111 * up with a tagged userland pointer. Clear the tag to get a sane pointer to
112 * pass on to access_ok(), for instance.
Andre Przywara87261d12016-10-19 14:40:54 +0100113 */
114#define untagged_addr(addr) sign_extend64(addr, 55)
115
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000116#define access_ok(type, addr, size) __range_ok(addr, size)
Will Deacon12a0ef72013-11-06 17:20:22 +0000117#define user_addr_max get_fs
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000118
Ard Biesheuvel6c94f272016-01-01 15:02:12 +0100119#define _ASM_EXTABLE(from, to) \
120 " .pushsection __ex_table, \"a\"\n" \
121 " .align 3\n" \
122 " .long (" #from " - .), (" #to " - .)\n" \
123 " .popsection\n"
124
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000125/*
Catalin Marinasbd389672016-07-01 14:58:21 +0100126 * User access enabling/disabling.
127 */
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100128#ifdef CONFIG_ARM64_SW_TTBR0_PAN
129static inline void __uaccess_ttbr0_disable(void)
130{
131 unsigned long ttbr;
132
133 /* reserved_ttbr0 placed at the end of swapper_pg_dir */
134 ttbr = read_sysreg(ttbr1_el1) + SWAPPER_DIR_SIZE;
135 write_sysreg(ttbr, ttbr0_el1);
136 isb();
137}
138
139static inline void __uaccess_ttbr0_enable(void)
140{
141 unsigned long flags;
142
143 /*
144 * Disable interrupts to avoid preemption between reading the 'ttbr0'
145 * variable and the MSR. A context switch could trigger an ASID
146 * roll-over and an update of 'ttbr0'.
147 */
148 local_irq_save(flags);
149 write_sysreg(current_thread_info()->ttbr0, ttbr0_el1);
150 isb();
151 local_irq_restore(flags);
152}
153
154static inline bool uaccess_ttbr0_disable(void)
155{
156 if (!system_uses_ttbr0_pan())
157 return false;
158 __uaccess_ttbr0_disable();
159 return true;
160}
161
162static inline bool uaccess_ttbr0_enable(void)
163{
164 if (!system_uses_ttbr0_pan())
165 return false;
166 __uaccess_ttbr0_enable();
167 return true;
168}
169#else
170static inline bool uaccess_ttbr0_disable(void)
171{
172 return false;
173}
174
175static inline bool uaccess_ttbr0_enable(void)
176{
177 return false;
178}
179#endif
180
Catalin Marinasbd389672016-07-01 14:58:21 +0100181#define __uaccess_disable(alt) \
182do { \
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100183 if (!uaccess_ttbr0_disable()) \
184 asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), alt, \
185 CONFIG_ARM64_PAN)); \
Catalin Marinasbd389672016-07-01 14:58:21 +0100186} while (0)
187
188#define __uaccess_enable(alt) \
189do { \
Marc Zyngier75037122016-12-12 13:50:26 +0000190 if (!uaccess_ttbr0_enable()) \
Catalin Marinas4b65a5d2016-07-01 16:53:00 +0100191 asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), alt, \
192 CONFIG_ARM64_PAN)); \
Catalin Marinasbd389672016-07-01 14:58:21 +0100193} while (0)
194
195static inline void uaccess_disable(void)
196{
197 __uaccess_disable(ARM64_HAS_PAN);
198}
199
200static inline void uaccess_enable(void)
201{
202 __uaccess_enable(ARM64_HAS_PAN);
203}
204
205/*
206 * These functions are no-ops when UAO is present.
207 */
208static inline void uaccess_disable_not_uao(void)
209{
210 __uaccess_disable(ARM64_ALT_PAN_NOT_UAO);
211}
212
213static inline void uaccess_enable_not_uao(void)
214{
215 __uaccess_enable(ARM64_ALT_PAN_NOT_UAO);
216}
217
218/*
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000219 * The "__xxx" versions of the user access functions do not verify the address
220 * space - it must have been done previously with a separate "access_ok()"
221 * call.
222 *
223 * The "__xxx_error" versions set the third argument to -EFAULT if an error
224 * occurs, and leave it unchanged on success.
225 */
James Morse57f49592016-02-05 14:58:48 +0000226#define __get_user_asm(instr, alt_instr, reg, x, addr, err, feature) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000227 asm volatile( \
James Morse57f49592016-02-05 14:58:48 +0000228 "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \
229 alt_instr " " reg "1, [%2]\n", feature) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000230 "2:\n" \
231 " .section .fixup, \"ax\"\n" \
232 " .align 2\n" \
233 "3: mov %w0, %3\n" \
234 " mov %1, #0\n" \
235 " b 2b\n" \
236 " .previous\n" \
Ard Biesheuvel6c94f272016-01-01 15:02:12 +0100237 _ASM_EXTABLE(1b, 3b) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000238 : "+r" (err), "=&r" (x) \
239 : "r" (addr), "i" (-EFAULT))
240
241#define __get_user_err(x, ptr, err) \
242do { \
243 unsigned long __gu_val; \
244 __chk_user_ptr(ptr); \
Catalin Marinasbd389672016-07-01 14:58:21 +0100245 uaccess_enable_not_uao(); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000246 switch (sizeof(*(ptr))) { \
247 case 1: \
James Morse57f49592016-02-05 14:58:48 +0000248 __get_user_asm("ldrb", "ldtrb", "%w", __gu_val, (ptr), \
249 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000250 break; \
251 case 2: \
James Morse57f49592016-02-05 14:58:48 +0000252 __get_user_asm("ldrh", "ldtrh", "%w", __gu_val, (ptr), \
253 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000254 break; \
255 case 4: \
James Morse57f49592016-02-05 14:58:48 +0000256 __get_user_asm("ldr", "ldtr", "%w", __gu_val, (ptr), \
257 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000258 break; \
259 case 8: \
Mark Rutlandd135b8b2017-05-03 16:09:38 +0100260 __get_user_asm("ldr", "ldtr", "%x", __gu_val, (ptr), \
James Morse57f49592016-02-05 14:58:48 +0000261 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000262 break; \
263 default: \
264 BUILD_BUG(); \
265 } \
Catalin Marinasbd389672016-07-01 14:58:21 +0100266 uaccess_disable_not_uao(); \
Michael S. Tsirkin58fff512014-12-12 01:56:04 +0200267 (x) = (__force __typeof__(*(ptr)))__gu_val; \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000268} while (0)
269
270#define __get_user(x, ptr) \
271({ \
272 int __gu_err = 0; \
273 __get_user_err((x), (ptr), __gu_err); \
274 __gu_err; \
275})
276
277#define __get_user_error(x, ptr, err) \
278({ \
279 __get_user_err((x), (ptr), (err)); \
280 (void)0; \
281})
282
283#define __get_user_unaligned __get_user
284
285#define get_user(x, ptr) \
286({ \
AKASHI Takahiro1f65c132013-09-24 10:00:50 +0100287 __typeof__(*(ptr)) __user *__p = (ptr); \
Michael S. Tsirkin56d2ef72013-05-26 17:30:42 +0300288 might_fault(); \
AKASHI Takahiro1f65c132013-09-24 10:00:50 +0100289 access_ok(VERIFY_READ, __p, sizeof(*__p)) ? \
290 __get_user((x), __p) : \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000291 ((x) = 0, -EFAULT); \
292})
293
James Morse57f49592016-02-05 14:58:48 +0000294#define __put_user_asm(instr, alt_instr, reg, x, addr, err, feature) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000295 asm volatile( \
James Morse57f49592016-02-05 14:58:48 +0000296 "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \
297 alt_instr " " reg "1, [%2]\n", feature) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000298 "2:\n" \
299 " .section .fixup,\"ax\"\n" \
300 " .align 2\n" \
301 "3: mov %w0, %3\n" \
302 " b 2b\n" \
303 " .previous\n" \
Ard Biesheuvel6c94f272016-01-01 15:02:12 +0100304 _ASM_EXTABLE(1b, 3b) \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000305 : "+r" (err) \
306 : "r" (x), "r" (addr), "i" (-EFAULT))
307
308#define __put_user_err(x, ptr, err) \
309do { \
310 __typeof__(*(ptr)) __pu_val = (x); \
311 __chk_user_ptr(ptr); \
Catalin Marinasbd389672016-07-01 14:58:21 +0100312 uaccess_enable_not_uao(); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000313 switch (sizeof(*(ptr))) { \
314 case 1: \
James Morse57f49592016-02-05 14:58:48 +0000315 __put_user_asm("strb", "sttrb", "%w", __pu_val, (ptr), \
316 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000317 break; \
318 case 2: \
James Morse57f49592016-02-05 14:58:48 +0000319 __put_user_asm("strh", "sttrh", "%w", __pu_val, (ptr), \
320 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000321 break; \
322 case 4: \
James Morse57f49592016-02-05 14:58:48 +0000323 __put_user_asm("str", "sttr", "%w", __pu_val, (ptr), \
324 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000325 break; \
326 case 8: \
Mark Rutlandd135b8b2017-05-03 16:09:38 +0100327 __put_user_asm("str", "sttr", "%x", __pu_val, (ptr), \
James Morse57f49592016-02-05 14:58:48 +0000328 (err), ARM64_HAS_UAO); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000329 break; \
330 default: \
331 BUILD_BUG(); \
332 } \
Catalin Marinasbd389672016-07-01 14:58:21 +0100333 uaccess_disable_not_uao(); \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000334} while (0)
335
336#define __put_user(x, ptr) \
337({ \
338 int __pu_err = 0; \
339 __put_user_err((x), (ptr), __pu_err); \
340 __pu_err; \
341})
342
343#define __put_user_error(x, ptr, err) \
344({ \
345 __put_user_err((x), (ptr), (err)); \
346 (void)0; \
347})
348
349#define __put_user_unaligned __put_user
350
351#define put_user(x, ptr) \
352({ \
AKASHI Takahiro1f65c132013-09-24 10:00:50 +0100353 __typeof__(*(ptr)) __user *__p = (ptr); \
Michael S. Tsirkin56d2ef72013-05-26 17:30:42 +0300354 might_fault(); \
AKASHI Takahiro1f65c132013-09-24 10:00:50 +0100355 access_ok(VERIFY_WRITE, __p, sizeof(*__p)) ? \
356 __put_user((x), __p) : \
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000357 -EFAULT; \
358})
359
Yang Shibffe1ba2016-06-08 14:40:56 -0700360extern unsigned long __must_check __arch_copy_from_user(void *to, const void __user *from, unsigned long n);
361extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n);
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000362extern unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n);
363extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n);
364
Yang Shibffe1ba2016-06-08 14:40:56 -0700365static inline unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n)
366{
367 kasan_check_write(to, n);
Kees Cookfaf5b632016-06-23 15:59:42 -0700368 check_object_size(to, n, false);
369 return __arch_copy_from_user(to, from, n);
Yang Shibffe1ba2016-06-08 14:40:56 -0700370}
371
372static inline unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n)
373{
374 kasan_check_read(from, n);
Kees Cookfaf5b632016-06-23 15:59:42 -0700375 check_object_size(from, n, true);
376 return __arch_copy_to_user(to, from, n);
Yang Shibffe1ba2016-06-08 14:40:56 -0700377}
378
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000379static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n)
380{
Al Viro4855bd22016-09-10 16:50:00 -0400381 unsigned long res = n;
Yang Shibffe1ba2016-06-08 14:40:56 -0700382 kasan_check_write(to, n);
Mark Rutland76624172017-02-07 12:33:55 +0000383 check_object_size(to, n, false);
Yang Shibffe1ba2016-06-08 14:40:56 -0700384
Kees Cookfaf5b632016-06-23 15:59:42 -0700385 if (access_ok(VERIFY_READ, from, n)) {
Al Viro4855bd22016-09-10 16:50:00 -0400386 res = __arch_copy_from_user(to, from, n);
387 }
388 if (unlikely(res))
389 memset(to + (n - res), 0, res);
390 return res;
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000391}
392
393static inline unsigned long __must_check copy_to_user(void __user *to, const void *from, unsigned long n)
394{
Yang Shibffe1ba2016-06-08 14:40:56 -0700395 kasan_check_read(from, n);
Mark Rutland76624172017-02-07 12:33:55 +0000396 check_object_size(from, n, true);
Yang Shibffe1ba2016-06-08 14:40:56 -0700397
Kees Cookfaf5b632016-06-23 15:59:42 -0700398 if (access_ok(VERIFY_WRITE, to, n)) {
Yang Shibffe1ba2016-06-08 14:40:56 -0700399 n = __arch_copy_to_user(to, from, n);
Kees Cookfaf5b632016-06-23 15:59:42 -0700400 }
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000401 return n;
402}
403
404static inline unsigned long __must_check copy_in_user(void __user *to, const void __user *from, unsigned long n)
405{
406 if (access_ok(VERIFY_READ, from, n) && access_ok(VERIFY_WRITE, to, n))
407 n = __copy_in_user(to, from, n);
408 return n;
409}
410
411#define __copy_to_user_inatomic __copy_to_user
412#define __copy_from_user_inatomic __copy_from_user
413
414static inline unsigned long __must_check clear_user(void __user *to, unsigned long n)
415{
416 if (access_ok(VERIFY_WRITE, to, n))
417 n = __clear_user(to, n);
418 return n;
419}
420
Will Deacon12a0ef72013-11-06 17:20:22 +0000421extern long strncpy_from_user(char *dest, const char __user *src, long count);
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000422
Will Deacon12a0ef72013-11-06 17:20:22 +0000423extern __must_check long strlen_user(const char __user *str);
424extern __must_check long strnlen_user(const char __user *str, long n);
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000425
Catalin Marinas0aea86a2012-03-05 11:49:32 +0000426#endif /* __ASM_UACCESS_H */