blob: 4eb5b19d2344066fc972aeb18302b6c09564b938 [file] [log] [blame]
Thomas Gleixner2874c5f2019-05-27 08:55:01 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Graeme Gregory518fb722011-05-02 16:20:08 -05002/*
3 * tps65910.c -- TI tps65910
4 *
5 * Copyright 2010 Texas Instruments Inc.
6 *
7 * Author: Graeme Gregory <gg@slimlogic.co.uk>
8 * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
Graeme Gregory518fb722011-05-02 16:20:08 -05009 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/err.h>
Geert Uytterhoevend16da512015-03-15 14:03:50 +010015#include <linux/of.h>
Graeme Gregory518fb722011-05-02 16:20:08 -050016#include <linux/platform_device.h>
17#include <linux/regulator/driver.h>
18#include <linux/regulator/machine.h>
Graeme Gregory518fb722011-05-02 16:20:08 -050019#include <linux/slab.h>
20#include <linux/gpio.h>
21#include <linux/mfd/tps65910.h>
Rhyland Klein67901782012-05-08 11:42:41 -070022#include <linux/regulator/of_regulator.h>
Graeme Gregory518fb722011-05-02 16:20:08 -050023
Graeme Gregory518fb722011-05-02 16:20:08 -050024#define TPS65910_SUPPLY_STATE_ENABLED 0x1
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +053025#define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \
26 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \
Laxman Dewanganf30b0712012-03-07 18:21:49 +053027 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \
28 TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
Graeme Gregory518fb722011-05-02 16:20:08 -050029
Axel Lind9fe28f2012-06-21 18:48:00 +080030/* supported VIO voltages in microvolts */
31static const unsigned int VIO_VSEL_table[] = {
32 1500000, 1800000, 2500000, 3300000,
Graeme Gregory518fb722011-05-02 16:20:08 -050033};
34
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -050035/* VSEL tables for TPS65910 specific LDOs and dcdc's */
36
AnilKumar Cha9a56592012-10-15 17:45:58 +053037/* supported VRTC voltages in microvolts */
38static const unsigned int VRTC_VSEL_table[] = {
39 1800000,
40};
41
Axel Lind9fe28f2012-06-21 18:48:00 +080042/* supported VDD3 voltages in microvolts */
43static const unsigned int VDD3_VSEL_table[] = {
44 5000000,
Graeme Gregory518fb722011-05-02 16:20:08 -050045};
46
Axel Lind9fe28f2012-06-21 18:48:00 +080047/* supported VDIG1 voltages in microvolts */
48static const unsigned int VDIG1_VSEL_table[] = {
49 1200000, 1500000, 1800000, 2700000,
Graeme Gregory518fb722011-05-02 16:20:08 -050050};
51
Axel Lind9fe28f2012-06-21 18:48:00 +080052/* supported VDIG2 voltages in microvolts */
53static const unsigned int VDIG2_VSEL_table[] = {
54 1000000, 1100000, 1200000, 1800000,
Graeme Gregory518fb722011-05-02 16:20:08 -050055};
56
Axel Lind9fe28f2012-06-21 18:48:00 +080057/* supported VPLL voltages in microvolts */
58static const unsigned int VPLL_VSEL_table[] = {
59 1000000, 1100000, 1800000, 2500000,
Graeme Gregory518fb722011-05-02 16:20:08 -050060};
61
Axel Lind9fe28f2012-06-21 18:48:00 +080062/* supported VDAC voltages in microvolts */
63static const unsigned int VDAC_VSEL_table[] = {
64 1800000, 2600000, 2800000, 2850000,
Graeme Gregory518fb722011-05-02 16:20:08 -050065};
66
Axel Lind9fe28f2012-06-21 18:48:00 +080067/* supported VAUX1 voltages in microvolts */
68static const unsigned int VAUX1_VSEL_table[] = {
69 1800000, 2500000, 2800000, 2850000,
Graeme Gregory518fb722011-05-02 16:20:08 -050070};
71
Axel Lind9fe28f2012-06-21 18:48:00 +080072/* supported VAUX2 voltages in microvolts */
73static const unsigned int VAUX2_VSEL_table[] = {
74 1800000, 2800000, 2900000, 3300000,
Graeme Gregory518fb722011-05-02 16:20:08 -050075};
76
Axel Lind9fe28f2012-06-21 18:48:00 +080077/* supported VAUX33 voltages in microvolts */
78static const unsigned int VAUX33_VSEL_table[] = {
79 1800000, 2000000, 2800000, 3300000,
Graeme Gregory518fb722011-05-02 16:20:08 -050080};
81
Axel Lind9fe28f2012-06-21 18:48:00 +080082/* supported VMMC voltages in microvolts */
83static const unsigned int VMMC_VSEL_table[] = {
84 1800000, 2800000, 3000000, 3300000,
Graeme Gregory518fb722011-05-02 16:20:08 -050085};
86
Markus Pargmann03746dc2013-12-20 12:43:27 +010087/* supported BBCH voltages in microvolts */
88static const unsigned int VBB_VSEL_table[] = {
89 3000000, 2520000, 3150000, 5000000,
90};
91
Graeme Gregory518fb722011-05-02 16:20:08 -050092struct tps_info {
93 const char *name;
Laxman Dewangan19228a62012-07-06 14:13:12 +053094 const char *vin_name;
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +053095 u8 n_voltages;
Axel Lind9fe28f2012-06-21 18:48:00 +080096 const unsigned int *voltage_table;
Laxman Dewangan0651eed2012-03-13 11:35:20 +053097 int enable_time_us;
Graeme Gregory518fb722011-05-02 16:20:08 -050098};
99
100static struct tps_info tps65910_regs[] = {
101 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530102 .name = "vrtc",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530103 .vin_name = "vcc7",
AnilKumar Cha9a56592012-10-15 17:45:58 +0530104 .n_voltages = ARRAY_SIZE(VRTC_VSEL_table),
105 .voltage_table = VRTC_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530106 .enable_time_us = 2200,
Graeme Gregory518fb722011-05-02 16:20:08 -0500107 },
108 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530109 .name = "vio",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530110 .vin_name = "vccio",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530111 .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
112 .voltage_table = VIO_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530113 .enable_time_us = 350,
Graeme Gregory518fb722011-05-02 16:20:08 -0500114 },
115 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530116 .name = "vdd1",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530117 .vin_name = "vcc1",
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530118 .enable_time_us = 350,
Graeme Gregory518fb722011-05-02 16:20:08 -0500119 },
120 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530121 .name = "vdd2",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530122 .vin_name = "vcc2",
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530123 .enable_time_us = 350,
Graeme Gregory518fb722011-05-02 16:20:08 -0500124 },
125 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530126 .name = "vdd3",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530127 .n_voltages = ARRAY_SIZE(VDD3_VSEL_table),
128 .voltage_table = VDD3_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530129 .enable_time_us = 200,
Graeme Gregory518fb722011-05-02 16:20:08 -0500130 },
131 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530132 .name = "vdig1",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530133 .vin_name = "vcc6",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530134 .n_voltages = ARRAY_SIZE(VDIG1_VSEL_table),
135 .voltage_table = VDIG1_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530136 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500137 },
138 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530139 .name = "vdig2",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530140 .vin_name = "vcc6",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530141 .n_voltages = ARRAY_SIZE(VDIG2_VSEL_table),
142 .voltage_table = VDIG2_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530143 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500144 },
145 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530146 .name = "vpll",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530147 .vin_name = "vcc5",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530148 .n_voltages = ARRAY_SIZE(VPLL_VSEL_table),
149 .voltage_table = VPLL_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530150 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500151 },
152 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530153 .name = "vdac",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530154 .vin_name = "vcc5",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530155 .n_voltages = ARRAY_SIZE(VDAC_VSEL_table),
156 .voltage_table = VDAC_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530157 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500158 },
159 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530160 .name = "vaux1",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530161 .vin_name = "vcc4",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530162 .n_voltages = ARRAY_SIZE(VAUX1_VSEL_table),
163 .voltage_table = VAUX1_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530164 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500165 },
166 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530167 .name = "vaux2",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530168 .vin_name = "vcc4",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530169 .n_voltages = ARRAY_SIZE(VAUX2_VSEL_table),
170 .voltage_table = VAUX2_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530171 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500172 },
173 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530174 .name = "vaux33",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530175 .vin_name = "vcc3",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530176 .n_voltages = ARRAY_SIZE(VAUX33_VSEL_table),
177 .voltage_table = VAUX33_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530178 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500179 },
180 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530181 .name = "vmmc",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530182 .vin_name = "vcc3",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530183 .n_voltages = ARRAY_SIZE(VMMC_VSEL_table),
184 .voltage_table = VMMC_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530185 .enable_time_us = 100,
Graeme Gregory518fb722011-05-02 16:20:08 -0500186 },
Markus Pargmann03746dc2013-12-20 12:43:27 +0100187 {
188 .name = "vbb",
189 .vin_name = "vcc7",
190 .n_voltages = ARRAY_SIZE(VBB_VSEL_table),
191 .voltage_table = VBB_VSEL_table,
192 },
Graeme Gregory518fb722011-05-02 16:20:08 -0500193};
194
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500195static struct tps_info tps65911_regs[] = {
196 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530197 .name = "vrtc",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530198 .vin_name = "vcc7",
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530199 .enable_time_us = 2200,
Laxman Dewanganc2f8efd2012-01-18 20:46:56 +0530200 },
201 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530202 .name = "vio",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530203 .vin_name = "vccio",
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +0530204 .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
205 .voltage_table = VIO_VSEL_table,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530206 .enable_time_us = 350,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500207 },
208 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530209 .name = "vdd1",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530210 .vin_name = "vcc1",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530211 .n_voltages = 0x4C,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530212 .enable_time_us = 350,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500213 },
214 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530215 .name = "vdd2",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530216 .vin_name = "vcc2",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530217 .n_voltages = 0x4C,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530218 .enable_time_us = 350,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500219 },
220 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530221 .name = "vddctrl",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530222 .n_voltages = 0x44,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530223 .enable_time_us = 900,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500224 },
225 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530226 .name = "ldo1",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530227 .vin_name = "vcc6",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530228 .n_voltages = 0x33,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530229 .enable_time_us = 420,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500230 },
231 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530232 .name = "ldo2",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530233 .vin_name = "vcc6",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530234 .n_voltages = 0x33,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530235 .enable_time_us = 420,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500236 },
237 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530238 .name = "ldo3",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530239 .vin_name = "vcc5",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530240 .n_voltages = 0x1A,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530241 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500242 },
243 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530244 .name = "ldo4",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530245 .vin_name = "vcc5",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530246 .n_voltages = 0x33,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530247 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500248 },
249 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530250 .name = "ldo5",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530251 .vin_name = "vcc4",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530252 .n_voltages = 0x1A,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530253 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500254 },
255 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530256 .name = "ldo6",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530257 .vin_name = "vcc3",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530258 .n_voltages = 0x1A,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530259 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500260 },
261 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530262 .name = "ldo7",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530263 .vin_name = "vcc3",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530264 .n_voltages = 0x1A,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530265 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500266 },
267 {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530268 .name = "ldo8",
Laxman Dewangan19228a62012-07-06 14:13:12 +0530269 .vin_name = "vcc3",
Laxman Dewangan7be53182012-07-09 20:27:13 +0530270 .n_voltages = 0x1A,
Laxman Dewangan0651eed2012-03-13 11:35:20 +0530271 .enable_time_us = 230,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500272 },
273};
274
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530275#define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits))
276static unsigned int tps65910_ext_sleep_control[] = {
277 0,
278 EXT_CONTROL_REG_BITS(VIO, 1, 0),
279 EXT_CONTROL_REG_BITS(VDD1, 1, 1),
280 EXT_CONTROL_REG_BITS(VDD2, 1, 2),
281 EXT_CONTROL_REG_BITS(VDD3, 1, 3),
282 EXT_CONTROL_REG_BITS(VDIG1, 0, 1),
283 EXT_CONTROL_REG_BITS(VDIG2, 0, 2),
284 EXT_CONTROL_REG_BITS(VPLL, 0, 6),
285 EXT_CONTROL_REG_BITS(VDAC, 0, 7),
286 EXT_CONTROL_REG_BITS(VAUX1, 0, 3),
287 EXT_CONTROL_REG_BITS(VAUX2, 0, 4),
288 EXT_CONTROL_REG_BITS(VAUX33, 0, 5),
289 EXT_CONTROL_REG_BITS(VMMC, 0, 0),
290};
291
292static unsigned int tps65911_ext_sleep_control[] = {
293 0,
294 EXT_CONTROL_REG_BITS(VIO, 1, 0),
295 EXT_CONTROL_REG_BITS(VDD1, 1, 1),
296 EXT_CONTROL_REG_BITS(VDD2, 1, 2),
297 EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3),
298 EXT_CONTROL_REG_BITS(LDO1, 0, 1),
299 EXT_CONTROL_REG_BITS(LDO2, 0, 2),
300 EXT_CONTROL_REG_BITS(LDO3, 0, 7),
301 EXT_CONTROL_REG_BITS(LDO4, 0, 6),
302 EXT_CONTROL_REG_BITS(LDO5, 0, 3),
303 EXT_CONTROL_REG_BITS(LDO6, 0, 0),
304 EXT_CONTROL_REG_BITS(LDO7, 0, 5),
305 EXT_CONTROL_REG_BITS(LDO8, 0, 4),
306};
307
Graeme Gregory518fb722011-05-02 16:20:08 -0500308struct tps65910_reg {
Axel Lin39aa9b62011-07-11 09:57:43 +0800309 struct regulator_desc *desc;
Graeme Gregory518fb722011-05-02 16:20:08 -0500310 struct tps65910 *mfd;
Axel Lin39aa9b62011-07-11 09:57:43 +0800311 struct regulator_dev **rdev;
312 struct tps_info **info;
Axel Lin39aa9b62011-07-11 09:57:43 +0800313 int num_regulators;
Graeme Gregory518fb722011-05-02 16:20:08 -0500314 int mode;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500315 int (*get_ctrl_reg)(int);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530316 unsigned int *ext_sleep_control;
317 unsigned int board_ext_control[TPS65910_NUM_REGS];
Graeme Gregory518fb722011-05-02 16:20:08 -0500318};
319
Graeme Gregory518fb722011-05-02 16:20:08 -0500320static int tps65910_get_ctrl_register(int id)
321{
322 switch (id) {
323 case TPS65910_REG_VRTC:
324 return TPS65910_VRTC;
325 case TPS65910_REG_VIO:
326 return TPS65910_VIO;
327 case TPS65910_REG_VDD1:
328 return TPS65910_VDD1;
329 case TPS65910_REG_VDD2:
330 return TPS65910_VDD2;
331 case TPS65910_REG_VDD3:
332 return TPS65910_VDD3;
333 case TPS65910_REG_VDIG1:
334 return TPS65910_VDIG1;
335 case TPS65910_REG_VDIG2:
336 return TPS65910_VDIG2;
337 case TPS65910_REG_VPLL:
338 return TPS65910_VPLL;
339 case TPS65910_REG_VDAC:
340 return TPS65910_VDAC;
341 case TPS65910_REG_VAUX1:
342 return TPS65910_VAUX1;
343 case TPS65910_REG_VAUX2:
344 return TPS65910_VAUX2;
345 case TPS65910_REG_VAUX33:
346 return TPS65910_VAUX33;
347 case TPS65910_REG_VMMC:
348 return TPS65910_VMMC;
Markus Pargmann03746dc2013-12-20 12:43:27 +0100349 case TPS65910_REG_VBB:
350 return TPS65910_BBCH;
Graeme Gregory518fb722011-05-02 16:20:08 -0500351 default:
352 return -EINVAL;
353 }
354}
355
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500356static int tps65911_get_ctrl_register(int id)
357{
358 switch (id) {
359 case TPS65910_REG_VRTC:
360 return TPS65910_VRTC;
361 case TPS65910_REG_VIO:
362 return TPS65910_VIO;
363 case TPS65910_REG_VDD1:
364 return TPS65910_VDD1;
365 case TPS65910_REG_VDD2:
366 return TPS65910_VDD2;
367 case TPS65911_REG_VDDCTRL:
368 return TPS65911_VDDCTRL;
369 case TPS65911_REG_LDO1:
370 return TPS65911_LDO1;
371 case TPS65911_REG_LDO2:
372 return TPS65911_LDO2;
373 case TPS65911_REG_LDO3:
374 return TPS65911_LDO3;
375 case TPS65911_REG_LDO4:
376 return TPS65911_LDO4;
377 case TPS65911_REG_LDO5:
378 return TPS65911_LDO5;
379 case TPS65911_REG_LDO6:
380 return TPS65911_LDO6;
381 case TPS65911_REG_LDO7:
382 return TPS65911_LDO7;
383 case TPS65911_REG_LDO8:
384 return TPS65911_LDO8;
385 default:
386 return -EINVAL;
387 }
388}
389
Graeme Gregory518fb722011-05-02 16:20:08 -0500390static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode)
391{
392 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
393 struct tps65910 *mfd = pmic->mfd;
394 int reg, value, id = rdev_get_id(dev);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500395
396 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500397 if (reg < 0)
398 return reg;
399
400 switch (mode) {
401 case REGULATOR_MODE_NORMAL:
Axel Linfaa95fd2012-07-11 19:44:13 +0800402 return tps65910_reg_update_bits(pmic->mfd, reg,
403 LDO_ST_MODE_BIT | LDO_ST_ON_BIT,
404 LDO_ST_ON_BIT);
Graeme Gregory518fb722011-05-02 16:20:08 -0500405 case REGULATOR_MODE_IDLE:
406 value = LDO_ST_ON_BIT | LDO_ST_MODE_BIT;
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700407 return tps65910_reg_set_bits(mfd, reg, value);
Graeme Gregory518fb722011-05-02 16:20:08 -0500408 case REGULATOR_MODE_STANDBY:
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700409 return tps65910_reg_clear_bits(mfd, reg, LDO_ST_ON_BIT);
Graeme Gregory518fb722011-05-02 16:20:08 -0500410 }
411
412 return -EINVAL;
413}
414
415static unsigned int tps65910_get_mode(struct regulator_dev *dev)
416{
417 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
Axel Linfaa95fd2012-07-11 19:44:13 +0800418 int ret, reg, value, id = rdev_get_id(dev);
Graeme Gregory518fb722011-05-02 16:20:08 -0500419
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500420 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500421 if (reg < 0)
422 return reg;
423
Axel Linfaa95fd2012-07-11 19:44:13 +0800424 ret = tps65910_reg_read(pmic->mfd, reg, &value);
425 if (ret < 0)
426 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500427
Axel Lin58599392012-03-13 07:15:27 +0800428 if (!(value & LDO_ST_ON_BIT))
Graeme Gregory518fb722011-05-02 16:20:08 -0500429 return REGULATOR_MODE_STANDBY;
430 else if (value & LDO_ST_MODE_BIT)
431 return REGULATOR_MODE_IDLE;
432 else
433 return REGULATOR_MODE_NORMAL;
434}
435
Laxman Dewangan18039e02012-03-14 13:00:58 +0530436static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev)
Graeme Gregory518fb722011-05-02 16:20:08 -0500437{
438 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
Axel Linfaa95fd2012-07-11 19:44:13 +0800439 int ret, id = rdev_get_id(dev);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500440 int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0;
Graeme Gregory518fb722011-05-02 16:20:08 -0500441
442 switch (id) {
443 case TPS65910_REG_VDD1:
Axel Linfaa95fd2012-07-11 19:44:13 +0800444 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1_OP, &opvsel);
445 if (ret < 0)
446 return ret;
447 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1, &mult);
448 if (ret < 0)
449 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500450 mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT;
Axel Linfaa95fd2012-07-11 19:44:13 +0800451 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD1_SR, &srvsel);
452 if (ret < 0)
453 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500454 sr = opvsel & VDD1_OP_CMD_MASK;
455 opvsel &= VDD1_OP_SEL_MASK;
456 srvsel &= VDD1_SR_SEL_MASK;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500457 vselmax = 75;
Graeme Gregory518fb722011-05-02 16:20:08 -0500458 break;
459 case TPS65910_REG_VDD2:
Axel Linfaa95fd2012-07-11 19:44:13 +0800460 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2_OP, &opvsel);
461 if (ret < 0)
462 return ret;
463 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2, &mult);
464 if (ret < 0)
465 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500466 mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT;
Axel Linfaa95fd2012-07-11 19:44:13 +0800467 ret = tps65910_reg_read(pmic->mfd, TPS65910_VDD2_SR, &srvsel);
468 if (ret < 0)
469 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500470 sr = opvsel & VDD2_OP_CMD_MASK;
471 opvsel &= VDD2_OP_SEL_MASK;
472 srvsel &= VDD2_SR_SEL_MASK;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500473 vselmax = 75;
474 break;
475 case TPS65911_REG_VDDCTRL:
Axel Linfaa95fd2012-07-11 19:44:13 +0800476 ret = tps65910_reg_read(pmic->mfd, TPS65911_VDDCTRL_OP,
477 &opvsel);
478 if (ret < 0)
479 return ret;
480 ret = tps65910_reg_read(pmic->mfd, TPS65911_VDDCTRL_SR,
481 &srvsel);
482 if (ret < 0)
483 return ret;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500484 sr = opvsel & VDDCTRL_OP_CMD_MASK;
485 opvsel &= VDDCTRL_OP_SEL_MASK;
486 srvsel &= VDDCTRL_SR_SEL_MASK;
487 vselmax = 64;
Graeme Gregory518fb722011-05-02 16:20:08 -0500488 break;
489 }
490
491 /* multiplier 0 == 1 but 2,3 normal */
492 if (!mult)
Jingoo Han4b579272013-10-14 17:53:40 +0900493 mult = 1;
Graeme Gregory518fb722011-05-02 16:20:08 -0500494
495 if (sr) {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500496 /* normalise to valid range */
497 if (srvsel < 3)
498 srvsel = 3;
499 if (srvsel > vselmax)
500 srvsel = vselmax;
Laxman Dewangan18039e02012-03-14 13:00:58 +0530501 return srvsel - 3;
Graeme Gregory518fb722011-05-02 16:20:08 -0500502 } else {
503
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500504 /* normalise to valid range*/
505 if (opvsel < 3)
506 opvsel = 3;
507 if (opvsel > vselmax)
508 opvsel = vselmax;
Laxman Dewangan18039e02012-03-14 13:00:58 +0530509 return opvsel - 3;
Graeme Gregory518fb722011-05-02 16:20:08 -0500510 }
Laxman Dewangan18039e02012-03-14 13:00:58 +0530511 return -EINVAL;
Graeme Gregory518fb722011-05-02 16:20:08 -0500512}
513
Axel Lin1f904fd2012-05-09 09:22:47 +0800514static int tps65910_get_voltage_sel(struct regulator_dev *dev)
Graeme Gregory518fb722011-05-02 16:20:08 -0500515{
516 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
Axel Linfaa95fd2012-07-11 19:44:13 +0800517 int ret, reg, value, id = rdev_get_id(dev);
Graeme Gregory518fb722011-05-02 16:20:08 -0500518
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500519 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500520 if (reg < 0)
521 return reg;
522
Axel Linfaa95fd2012-07-11 19:44:13 +0800523 ret = tps65910_reg_read(pmic->mfd, reg, &value);
524 if (ret < 0)
525 return ret;
Graeme Gregory518fb722011-05-02 16:20:08 -0500526
527 switch (id) {
528 case TPS65910_REG_VIO:
529 case TPS65910_REG_VDIG1:
530 case TPS65910_REG_VDIG2:
531 case TPS65910_REG_VPLL:
532 case TPS65910_REG_VDAC:
533 case TPS65910_REG_VAUX1:
534 case TPS65910_REG_VAUX2:
535 case TPS65910_REG_VAUX33:
536 case TPS65910_REG_VMMC:
537 value &= LDO_SEL_MASK;
538 value >>= LDO_SEL_SHIFT;
539 break;
Markus Pargmann03746dc2013-12-20 12:43:27 +0100540 case TPS65910_REG_VBB:
541 value &= BBCH_BBSEL_MASK;
542 value >>= BBCH_BBSEL_SHIFT;
543 break;
Graeme Gregory518fb722011-05-02 16:20:08 -0500544 default:
545 return -EINVAL;
546 }
547
Axel Lin1f904fd2012-05-09 09:22:47 +0800548 return value;
Graeme Gregory518fb722011-05-02 16:20:08 -0500549}
550
551static int tps65910_get_voltage_vdd3(struct regulator_dev *dev)
552{
Axel Lind9fe28f2012-06-21 18:48:00 +0800553 return dev->desc->volt_table[0];
Graeme Gregory518fb722011-05-02 16:20:08 -0500554}
555
Axel Lin1f904fd2012-05-09 09:22:47 +0800556static int tps65911_get_voltage_sel(struct regulator_dev *dev)
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500557{
558 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
Axel Linfaa95fd2012-07-11 19:44:13 +0800559 int ret, id = rdev_get_id(dev);
560 unsigned int value, reg;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500561
562 reg = pmic->get_ctrl_reg(id);
563
Axel Linfaa95fd2012-07-11 19:44:13 +0800564 ret = tps65910_reg_read(pmic->mfd, reg, &value);
565 if (ret < 0)
566 return ret;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500567
568 switch (id) {
569 case TPS65911_REG_LDO1:
570 case TPS65911_REG_LDO2:
571 case TPS65911_REG_LDO4:
572 value &= LDO1_SEL_MASK;
573 value >>= LDO_SEL_SHIFT;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500574 break;
575 case TPS65911_REG_LDO3:
576 case TPS65911_REG_LDO5:
577 case TPS65911_REG_LDO6:
578 case TPS65911_REG_LDO7:
579 case TPS65911_REG_LDO8:
580 value &= LDO3_SEL_MASK;
581 value >>= LDO_SEL_SHIFT;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500582 break;
583 case TPS65910_REG_VIO:
Laxman Dewangane882eae2012-02-17 18:56:11 +0530584 value &= LDO_SEL_MASK;
585 value >>= LDO_SEL_SHIFT;
Axel Lin1f904fd2012-05-09 09:22:47 +0800586 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500587 default:
588 return -EINVAL;
589 }
590
Axel Lin1f904fd2012-05-09 09:22:47 +0800591 return value;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500592}
593
Axel Lin94732b92012-03-09 10:22:20 +0800594static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev,
595 unsigned selector)
Graeme Gregory518fb722011-05-02 16:20:08 -0500596{
597 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
598 int id = rdev_get_id(dev), vsel;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500599 int dcdc_mult = 0;
Graeme Gregory518fb722011-05-02 16:20:08 -0500600
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500601 switch (id) {
602 case TPS65910_REG_VDD1:
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530603 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500604 if (dcdc_mult == 1)
605 dcdc_mult--;
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530606 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
Graeme Gregory518fb722011-05-02 16:20:08 -0500607
Axel Linfaa95fd2012-07-11 19:44:13 +0800608 tps65910_reg_update_bits(pmic->mfd, TPS65910_VDD1,
609 VDD1_VGAIN_SEL_MASK,
610 dcdc_mult << VDD1_VGAIN_SEL_SHIFT);
611 tps65910_reg_write(pmic->mfd, TPS65910_VDD1_OP, vsel);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500612 break;
613 case TPS65910_REG_VDD2:
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530614 dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500615 if (dcdc_mult == 1)
616 dcdc_mult--;
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530617 vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500618
Axel Linfaa95fd2012-07-11 19:44:13 +0800619 tps65910_reg_update_bits(pmic->mfd, TPS65910_VDD2,
620 VDD1_VGAIN_SEL_MASK,
621 dcdc_mult << VDD2_VGAIN_SEL_SHIFT);
622 tps65910_reg_write(pmic->mfd, TPS65910_VDD2_OP, vsel);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500623 break;
624 case TPS65911_REG_VDDCTRL:
Laxman Dewanganc4632ae2012-03-07 16:39:05 +0530625 vsel = selector + 3;
Axel Linfaa95fd2012-07-11 19:44:13 +0800626 tps65910_reg_write(pmic->mfd, TPS65911_VDDCTRL_OP, vsel);
Graeme Gregory518fb722011-05-02 16:20:08 -0500627 }
628
629 return 0;
630}
631
Axel Lin94732b92012-03-09 10:22:20 +0800632static int tps65910_set_voltage_sel(struct regulator_dev *dev,
633 unsigned selector)
Graeme Gregory518fb722011-05-02 16:20:08 -0500634{
635 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
636 int reg, id = rdev_get_id(dev);
637
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500638 reg = pmic->get_ctrl_reg(id);
Graeme Gregory518fb722011-05-02 16:20:08 -0500639 if (reg < 0)
640 return reg;
641
642 switch (id) {
643 case TPS65910_REG_VIO:
644 case TPS65910_REG_VDIG1:
645 case TPS65910_REG_VDIG2:
646 case TPS65910_REG_VPLL:
647 case TPS65910_REG_VDAC:
648 case TPS65910_REG_VAUX1:
649 case TPS65910_REG_VAUX2:
650 case TPS65910_REG_VAUX33:
651 case TPS65910_REG_VMMC:
Axel Linfaa95fd2012-07-11 19:44:13 +0800652 return tps65910_reg_update_bits(pmic->mfd, reg, LDO_SEL_MASK,
653 selector << LDO_SEL_SHIFT);
Markus Pargmann03746dc2013-12-20 12:43:27 +0100654 case TPS65910_REG_VBB:
655 return tps65910_reg_update_bits(pmic->mfd, reg, BBCH_BBSEL_MASK,
656 selector << BBCH_BBSEL_SHIFT);
Graeme Gregory518fb722011-05-02 16:20:08 -0500657 }
658
659 return -EINVAL;
660}
661
Axel Lin94732b92012-03-09 10:22:20 +0800662static int tps65911_set_voltage_sel(struct regulator_dev *dev,
663 unsigned selector)
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500664{
665 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
666 int reg, id = rdev_get_id(dev);
667
668 reg = pmic->get_ctrl_reg(id);
669 if (reg < 0)
670 return reg;
671
672 switch (id) {
673 case TPS65911_REG_LDO1:
674 case TPS65911_REG_LDO2:
675 case TPS65911_REG_LDO4:
Axel Linfaa95fd2012-07-11 19:44:13 +0800676 return tps65910_reg_update_bits(pmic->mfd, reg, LDO1_SEL_MASK,
677 selector << LDO_SEL_SHIFT);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500678 case TPS65911_REG_LDO3:
679 case TPS65911_REG_LDO5:
680 case TPS65911_REG_LDO6:
681 case TPS65911_REG_LDO7:
682 case TPS65911_REG_LDO8:
Axel Linfaa95fd2012-07-11 19:44:13 +0800683 return tps65910_reg_update_bits(pmic->mfd, reg, LDO3_SEL_MASK,
684 selector << LDO_SEL_SHIFT);
Laxman Dewangane882eae2012-02-17 18:56:11 +0530685 case TPS65910_REG_VIO:
Axel Linfaa95fd2012-07-11 19:44:13 +0800686 return tps65910_reg_update_bits(pmic->mfd, reg, LDO_SEL_MASK,
687 selector << LDO_SEL_SHIFT);
Markus Pargmann03746dc2013-12-20 12:43:27 +0100688 case TPS65910_REG_VBB:
689 return tps65910_reg_update_bits(pmic->mfd, reg, BBCH_BBSEL_MASK,
690 selector << BBCH_BBSEL_SHIFT);
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500691 }
692
693 return -EINVAL;
694}
695
696
Graeme Gregory518fb722011-05-02 16:20:08 -0500697static int tps65910_list_voltage_dcdc(struct regulator_dev *dev,
698 unsigned selector)
699{
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500700 int volt, mult = 1, id = rdev_get_id(dev);
Graeme Gregory518fb722011-05-02 16:20:08 -0500701
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500702 switch (id) {
703 case TPS65910_REG_VDD1:
704 case TPS65910_REG_VDD2:
Afzal Mohammed780dc9b2011-11-08 18:54:10 +0530705 mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500706 volt = VDD1_2_MIN_VOLT +
Jingoo Han4b579272013-10-14 17:53:40 +0900707 (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET;
Axel Lind04156b2011-07-10 21:44:09 +0800708 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500709 case TPS65911_REG_VDDCTRL:
710 volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET);
Axel Lind04156b2011-07-10 21:44:09 +0800711 break;
712 default:
713 BUG();
714 return -EINVAL;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500715 }
Graeme Gregory518fb722011-05-02 16:20:08 -0500716
717 return volt * 100 * mult;
718}
719
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500720static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector)
721{
722 struct tps65910_reg *pmic = rdev_get_drvdata(dev);
723 int step_mv = 0, id = rdev_get_id(dev);
724
Jingoo Han4b579272013-10-14 17:53:40 +0900725 switch (id) {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500726 case TPS65911_REG_LDO1:
727 case TPS65911_REG_LDO2:
728 case TPS65911_REG_LDO4:
729 /* The first 5 values of the selector correspond to 1V */
730 if (selector < 5)
731 selector = 0;
732 else
733 selector -= 4;
734
735 step_mv = 50;
736 break;
737 case TPS65911_REG_LDO3:
738 case TPS65911_REG_LDO5:
739 case TPS65911_REG_LDO6:
740 case TPS65911_REG_LDO7:
741 case TPS65911_REG_LDO8:
742 /* The first 3 values of the selector correspond to 1V */
743 if (selector < 3)
744 selector = 0;
745 else
746 selector -= 2;
747
748 step_mv = 100;
749 break;
750 case TPS65910_REG_VIO:
Axel Lind9fe28f2012-06-21 18:48:00 +0800751 return pmic->info[id]->voltage_table[selector];
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500752 default:
753 return -EINVAL;
754 }
755
756 return (LDO_MIN_VOLT + selector * step_mv) * 1000;
757}
758
Graeme Gregory518fb722011-05-02 16:20:08 -0500759/* Regulator ops (except VRTC) */
760static struct regulator_ops tps65910_ops_dcdc = {
Axel Lina40a9c42012-04-17 14:34:46 +0800761 .is_enabled = regulator_is_enabled_regmap,
762 .enable = regulator_enable_regmap,
763 .disable = regulator_disable_regmap,
Graeme Gregory518fb722011-05-02 16:20:08 -0500764 .set_mode = tps65910_set_mode,
765 .get_mode = tps65910_get_mode,
Laxman Dewangan18039e02012-03-14 13:00:58 +0530766 .get_voltage_sel = tps65910_get_voltage_dcdc_sel,
Axel Lin94732b92012-03-09 10:22:20 +0800767 .set_voltage_sel = tps65910_set_voltage_dcdc_sel,
Axel Lin01bc3a12012-06-20 22:40:10 +0800768 .set_voltage_time_sel = regulator_set_voltage_time_sel,
Graeme Gregory518fb722011-05-02 16:20:08 -0500769 .list_voltage = tps65910_list_voltage_dcdc,
Axel Lin9fa81752013-04-20 10:30:17 +0800770 .map_voltage = regulator_map_voltage_ascend,
Graeme Gregory518fb722011-05-02 16:20:08 -0500771};
772
773static struct regulator_ops tps65910_ops_vdd3 = {
Axel Lina40a9c42012-04-17 14:34:46 +0800774 .is_enabled = regulator_is_enabled_regmap,
775 .enable = regulator_enable_regmap,
776 .disable = regulator_disable_regmap,
Graeme Gregory518fb722011-05-02 16:20:08 -0500777 .set_mode = tps65910_set_mode,
778 .get_mode = tps65910_get_mode,
779 .get_voltage = tps65910_get_voltage_vdd3,
Axel Lind9fe28f2012-06-21 18:48:00 +0800780 .list_voltage = regulator_list_voltage_table,
Axel Lin9fa81752013-04-20 10:30:17 +0800781 .map_voltage = regulator_map_voltage_ascend,
Graeme Gregory518fb722011-05-02 16:20:08 -0500782};
783
Markus Pargmann03746dc2013-12-20 12:43:27 +0100784static struct regulator_ops tps65910_ops_vbb = {
785 .is_enabled = regulator_is_enabled_regmap,
786 .enable = regulator_enable_regmap,
787 .disable = regulator_disable_regmap,
788 .set_mode = tps65910_set_mode,
789 .get_mode = tps65910_get_mode,
790 .get_voltage_sel = tps65910_get_voltage_sel,
791 .set_voltage_sel = tps65910_set_voltage_sel,
792 .list_voltage = regulator_list_voltage_table,
793 .map_voltage = regulator_map_voltage_iterate,
794};
795
Graeme Gregory518fb722011-05-02 16:20:08 -0500796static struct regulator_ops tps65910_ops = {
Axel Lina40a9c42012-04-17 14:34:46 +0800797 .is_enabled = regulator_is_enabled_regmap,
798 .enable = regulator_enable_regmap,
799 .disable = regulator_disable_regmap,
Graeme Gregory518fb722011-05-02 16:20:08 -0500800 .set_mode = tps65910_set_mode,
801 .get_mode = tps65910_get_mode,
Axel Lin1f904fd2012-05-09 09:22:47 +0800802 .get_voltage_sel = tps65910_get_voltage_sel,
Axel Lin94732b92012-03-09 10:22:20 +0800803 .set_voltage_sel = tps65910_set_voltage_sel,
Axel Lind9fe28f2012-06-21 18:48:00 +0800804 .list_voltage = regulator_list_voltage_table,
Axel Lin9fa81752013-04-20 10:30:17 +0800805 .map_voltage = regulator_map_voltage_ascend,
Graeme Gregory518fb722011-05-02 16:20:08 -0500806};
807
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500808static struct regulator_ops tps65911_ops = {
Axel Lina40a9c42012-04-17 14:34:46 +0800809 .is_enabled = regulator_is_enabled_regmap,
810 .enable = regulator_enable_regmap,
811 .disable = regulator_disable_regmap,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500812 .set_mode = tps65910_set_mode,
813 .get_mode = tps65910_get_mode,
Axel Lin1f904fd2012-05-09 09:22:47 +0800814 .get_voltage_sel = tps65911_get_voltage_sel,
Axel Lin94732b92012-03-09 10:22:20 +0800815 .set_voltage_sel = tps65911_set_voltage_sel,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500816 .list_voltage = tps65911_list_voltage,
Axel Lin9fa81752013-04-20 10:30:17 +0800817 .map_voltage = regulator_map_voltage_ascend,
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -0500818};
819
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530820static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic,
821 int id, int ext_sleep_config)
822{
823 struct tps65910 *mfd = pmic->mfd;
824 u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF;
825 u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF);
826 int ret;
827
828 /*
829 * Regulator can not be control from multiple external input EN1, EN2
830 * and EN3 together.
831 */
832 if (ext_sleep_config & EXT_SLEEP_CONTROL) {
833 int en_count;
834 en_count = ((ext_sleep_config &
835 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0);
836 en_count += ((ext_sleep_config &
837 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0);
838 en_count += ((ext_sleep_config &
839 TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0);
Laxman Dewanganf30b0712012-03-07 18:21:49 +0530840 en_count += ((ext_sleep_config &
841 TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530842 if (en_count > 1) {
843 dev_err(mfd->dev,
844 "External sleep control flag is not proper\n");
845 return -EINVAL;
846 }
847 }
848
849 pmic->board_ext_control[id] = ext_sleep_config;
850
851 /* External EN1 control */
852 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1)
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700853 ret = tps65910_reg_set_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530854 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
855 else
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700856 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530857 TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
858 if (ret < 0) {
859 dev_err(mfd->dev,
860 "Error in configuring external control EN1\n");
861 return ret;
862 }
863
864 /* External EN2 control */
865 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2)
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700866 ret = tps65910_reg_set_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530867 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
868 else
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700869 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530870 TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
871 if (ret < 0) {
872 dev_err(mfd->dev,
873 "Error in configuring external control EN2\n");
874 return ret;
875 }
876
877 /* External EN3 control for TPS65910 LDO only */
878 if ((tps65910_chip_id(mfd) == TPS65910) &&
879 (id >= TPS65910_REG_VDIG1)) {
880 if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3)
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700881 ret = tps65910_reg_set_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530882 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
883 else
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700884 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530885 TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
886 if (ret < 0) {
887 dev_err(mfd->dev,
888 "Error in configuring external control EN3\n");
889 return ret;
890 }
891 }
892
893 /* Return if no external control is selected */
894 if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) {
895 /* Clear all sleep controls */
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700896 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530897 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
898 if (!ret)
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700899 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530900 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
901 if (ret < 0)
902 dev_err(mfd->dev,
903 "Error in configuring SLEEP register\n");
904 return ret;
905 }
906
907 /*
908 * For regulator that has separate operational and sleep register make
909 * sure that operational is used and clear sleep register to turn
910 * regulator off when external control is inactive
911 */
912 if ((id == TPS65910_REG_VDD1) ||
913 (id == TPS65910_REG_VDD2) ||
914 ((id == TPS65911_REG_VDDCTRL) &&
915 (tps65910_chip_id(mfd) == TPS65911))) {
916 int op_reg_add = pmic->get_ctrl_reg(id) + 1;
917 int sr_reg_add = pmic->get_ctrl_reg(id) + 2;
Axel Linfaa95fd2012-07-11 19:44:13 +0800918 int opvsel, srvsel;
919
920 ret = tps65910_reg_read(pmic->mfd, op_reg_add, &opvsel);
921 if (ret < 0)
922 return ret;
923 ret = tps65910_reg_read(pmic->mfd, sr_reg_add, &srvsel);
924 if (ret < 0)
925 return ret;
926
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530927 if (opvsel & VDD1_OP_CMD_MASK) {
928 u8 reg_val = srvsel & VDD1_OP_SEL_MASK;
Axel Linfaa95fd2012-07-11 19:44:13 +0800929
930 ret = tps65910_reg_write(pmic->mfd, op_reg_add,
931 reg_val);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530932 if (ret < 0) {
933 dev_err(mfd->dev,
934 "Error in configuring op register\n");
935 return ret;
936 }
937 }
Axel Linfaa95fd2012-07-11 19:44:13 +0800938 ret = tps65910_reg_write(pmic->mfd, sr_reg_add, 0);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530939 if (ret < 0) {
Masanari Iida6d3be302013-09-30 23:19:09 +0900940 dev_err(mfd->dev, "Error in setting sr register\n");
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530941 return ret;
942 }
943 }
944
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700945 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530946 TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
Laxman Dewanganf30b0712012-03-07 18:21:49 +0530947 if (!ret) {
948 if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700949 ret = tps65910_reg_set_bits(mfd,
Laxman Dewanganf30b0712012-03-07 18:21:49 +0530950 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
951 else
Rhyland Klein3f7e8272012-05-08 11:42:38 -0700952 ret = tps65910_reg_clear_bits(mfd,
Laxman Dewanganf30b0712012-03-07 18:21:49 +0530953 TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
954 }
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530955 if (ret < 0)
956 dev_err(mfd->dev,
957 "Error in configuring SLEEP register\n");
Laxman Dewanganf30b0712012-03-07 18:21:49 +0530958
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +0530959 return ret;
960}
961
Rhyland Klein67901782012-05-08 11:42:41 -0700962#ifdef CONFIG_OF
963
964static struct of_regulator_match tps65910_matches[] = {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530965 { .name = "vrtc", .driver_data = (void *) &tps65910_regs[0] },
966 { .name = "vio", .driver_data = (void *) &tps65910_regs[1] },
967 { .name = "vdd1", .driver_data = (void *) &tps65910_regs[2] },
968 { .name = "vdd2", .driver_data = (void *) &tps65910_regs[3] },
969 { .name = "vdd3", .driver_data = (void *) &tps65910_regs[4] },
970 { .name = "vdig1", .driver_data = (void *) &tps65910_regs[5] },
971 { .name = "vdig2", .driver_data = (void *) &tps65910_regs[6] },
972 { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] },
973 { .name = "vdac", .driver_data = (void *) &tps65910_regs[8] },
974 { .name = "vaux1", .driver_data = (void *) &tps65910_regs[9] },
975 { .name = "vaux2", .driver_data = (void *) &tps65910_regs[10] },
976 { .name = "vaux33", .driver_data = (void *) &tps65910_regs[11] },
977 { .name = "vmmc", .driver_data = (void *) &tps65910_regs[12] },
Markus Pargmann03746dc2013-12-20 12:43:27 +0100978 { .name = "vbb", .driver_data = (void *) &tps65910_regs[13] },
Rhyland Klein67901782012-05-08 11:42:41 -0700979};
980
981static struct of_regulator_match tps65911_matches[] = {
Laxman Dewangan33a69432012-05-19 20:04:06 +0530982 { .name = "vrtc", .driver_data = (void *) &tps65911_regs[0] },
983 { .name = "vio", .driver_data = (void *) &tps65911_regs[1] },
984 { .name = "vdd1", .driver_data = (void *) &tps65911_regs[2] },
985 { .name = "vdd2", .driver_data = (void *) &tps65911_regs[3] },
986 { .name = "vddctrl", .driver_data = (void *) &tps65911_regs[4] },
987 { .name = "ldo1", .driver_data = (void *) &tps65911_regs[5] },
988 { .name = "ldo2", .driver_data = (void *) &tps65911_regs[6] },
989 { .name = "ldo3", .driver_data = (void *) &tps65911_regs[7] },
990 { .name = "ldo4", .driver_data = (void *) &tps65911_regs[8] },
991 { .name = "ldo5", .driver_data = (void *) &tps65911_regs[9] },
992 { .name = "ldo6", .driver_data = (void *) &tps65911_regs[10] },
993 { .name = "ldo7", .driver_data = (void *) &tps65911_regs[11] },
994 { .name = "ldo8", .driver_data = (void *) &tps65911_regs[12] },
Rhyland Klein67901782012-05-08 11:42:41 -0700995};
996
997static struct tps65910_board *tps65910_parse_dt_reg_data(
Laxman Dewangan84df8c12012-05-20 21:48:50 +0530998 struct platform_device *pdev,
999 struct of_regulator_match **tps65910_reg_matches)
Rhyland Klein67901782012-05-08 11:42:41 -07001000{
1001 struct tps65910_board *pmic_plat_data;
1002 struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
Axel Linc92f5dd2013-01-27 21:16:56 +08001003 struct device_node *np, *regulators;
Rhyland Klein67901782012-05-08 11:42:41 -07001004 struct of_regulator_match *matches;
1005 unsigned int prop;
1006 int idx = 0, ret, count;
1007
1008 pmic_plat_data = devm_kzalloc(&pdev->dev, sizeof(*pmic_plat_data),
1009 GFP_KERNEL);
Sachin Kamatbcb2c0d2014-02-20 14:23:18 +05301010 if (!pmic_plat_data)
Rhyland Klein67901782012-05-08 11:42:41 -07001011 return NULL;
Rhyland Klein67901782012-05-08 11:42:41 -07001012
Guodong Xub8b27a42014-09-10 11:50:39 +08001013 np = pdev->dev.parent->of_node;
Laxman Dewangan4ae1ff72013-10-08 19:31:04 +05301014 regulators = of_get_child_by_name(np, "regulators");
Laxman Dewangan92ab9532012-05-20 21:48:49 +05301015 if (!regulators) {
1016 dev_err(&pdev->dev, "regulator node not found\n");
1017 return NULL;
1018 }
Rhyland Klein67901782012-05-08 11:42:41 -07001019
1020 switch (tps65910_chip_id(tps65910)) {
1021 case TPS65910:
1022 count = ARRAY_SIZE(tps65910_matches);
1023 matches = tps65910_matches;
1024 break;
1025 case TPS65911:
1026 count = ARRAY_SIZE(tps65911_matches);
1027 matches = tps65911_matches;
1028 break;
1029 default:
Axel Linc92f5dd2013-01-27 21:16:56 +08001030 of_node_put(regulators);
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301031 dev_err(&pdev->dev, "Invalid tps chip version\n");
Rhyland Klein67901782012-05-08 11:42:41 -07001032 return NULL;
1033 }
1034
Axel Lin08337fd2013-01-24 10:31:45 +08001035 ret = of_regulator_match(&pdev->dev, regulators, matches, count);
Axel Linc92f5dd2013-01-27 21:16:56 +08001036 of_node_put(regulators);
Rhyland Klein67901782012-05-08 11:42:41 -07001037 if (ret < 0) {
1038 dev_err(&pdev->dev, "Error parsing regulator init data: %d\n",
1039 ret);
1040 return NULL;
1041 }
1042
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301043 *tps65910_reg_matches = matches;
1044
Rhyland Klein67901782012-05-08 11:42:41 -07001045 for (idx = 0; idx < count; idx++) {
Axel Lin23b11342014-02-18 21:11:48 +08001046 if (!matches[idx].of_node)
Rhyland Klein67901782012-05-08 11:42:41 -07001047 continue;
1048
1049 pmic_plat_data->tps65910_pmic_init_data[idx] =
1050 matches[idx].init_data;
1051
1052 ret = of_property_read_u32(matches[idx].of_node,
1053 "ti,regulator-ext-sleep-control", &prop);
1054 if (!ret)
1055 pmic_plat_data->regulator_ext_sleep_control[idx] = prop;
Laxman Dewangan19228a62012-07-06 14:13:12 +05301056
Rhyland Klein67901782012-05-08 11:42:41 -07001057 }
1058
1059 return pmic_plat_data;
1060}
1061#else
1062static inline struct tps65910_board *tps65910_parse_dt_reg_data(
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301063 struct platform_device *pdev,
1064 struct of_regulator_match **tps65910_reg_matches)
Rhyland Klein67901782012-05-08 11:42:41 -07001065{
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301066 *tps65910_reg_matches = NULL;
Mark Brown74ea0e52012-06-15 19:04:33 +01001067 return NULL;
Rhyland Klein67901782012-05-08 11:42:41 -07001068}
1069#endif
1070
Bill Pembertona5023572012-11-19 13:22:22 -05001071static int tps65910_probe(struct platform_device *pdev)
Graeme Gregory518fb722011-05-02 16:20:08 -05001072{
1073 struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
Mark Brownc1727082012-04-04 00:50:22 +01001074 struct regulator_config config = { };
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001075 struct tps_info *info;
Graeme Gregory518fb722011-05-02 16:20:08 -05001076 struct regulator_dev *rdev;
1077 struct tps65910_reg *pmic;
1078 struct tps65910_board *pmic_plat_data;
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301079 struct of_regulator_match *tps65910_reg_matches = NULL;
Graeme Gregory518fb722011-05-02 16:20:08 -05001080 int i, err;
1081
1082 pmic_plat_data = dev_get_platdata(tps65910->dev);
Rhyland Klein67901782012-05-08 11:42:41 -07001083 if (!pmic_plat_data && tps65910->dev->of_node)
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301084 pmic_plat_data = tps65910_parse_dt_reg_data(pdev,
1085 &tps65910_reg_matches);
Rhyland Klein67901782012-05-08 11:42:41 -07001086
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301087 if (!pmic_plat_data) {
1088 dev_err(&pdev->dev, "Platform data not found\n");
Graeme Gregory518fb722011-05-02 16:20:08 -05001089 return -EINVAL;
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301090 }
Graeme Gregory518fb722011-05-02 16:20:08 -05001091
Axel Lin9eb0c422012-04-11 14:40:18 +08001092 pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
Sachin Kamatbcb2c0d2014-02-20 14:23:18 +05301093 if (!pmic)
Graeme Gregory518fb722011-05-02 16:20:08 -05001094 return -ENOMEM;
1095
Graeme Gregory518fb722011-05-02 16:20:08 -05001096 pmic->mfd = tps65910;
1097 platform_set_drvdata(pdev, pmic);
1098
1099 /* Give control of all register to control port */
Kangjie Lucd07e372018-12-21 00:29:19 -06001100 err = tps65910_reg_set_bits(pmic->mfd, TPS65910_DEVCTRL,
Graeme Gregory518fb722011-05-02 16:20:08 -05001101 DEVCTRL_SR_CTL_I2C_SEL_MASK);
Kangjie Lucd07e372018-12-21 00:29:19 -06001102 if (err < 0)
1103 return err;
Graeme Gregory518fb722011-05-02 16:20:08 -05001104
Jingoo Han4b579272013-10-14 17:53:40 +09001105 switch (tps65910_chip_id(tps65910)) {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001106 case TPS65910:
Michał Mirosławfe953902017-06-13 16:41:56 +02001107 BUILD_BUG_ON(TPS65910_NUM_REGS < ARRAY_SIZE(tps65910_regs));
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001108 pmic->get_ctrl_reg = &tps65910_get_ctrl_register;
Axel Lin39aa9b62011-07-11 09:57:43 +08001109 pmic->num_regulators = ARRAY_SIZE(tps65910_regs);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301110 pmic->ext_sleep_control = tps65910_ext_sleep_control;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001111 info = tps65910_regs;
Jan Remmet8f9165c2016-09-23 10:52:00 +02001112 /* Work around silicon erratum SWCZ010: output programmed
1113 * voltage level can go higher than expected or crash
1114 * Workaround: use no synchronization of DCDC clocks
1115 */
1116 tps65910_reg_clear_bits(pmic->mfd, TPS65910_DCDCCTRL,
1117 DCDCCTRL_DCDCCKSYNC_MASK);
Axel Lind04156b2011-07-10 21:44:09 +08001118 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001119 case TPS65911:
Michał Mirosławfe953902017-06-13 16:41:56 +02001120 BUILD_BUG_ON(TPS65910_NUM_REGS < ARRAY_SIZE(tps65911_regs));
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001121 pmic->get_ctrl_reg = &tps65911_get_ctrl_register;
Axel Lin39aa9b62011-07-11 09:57:43 +08001122 pmic->num_regulators = ARRAY_SIZE(tps65911_regs);
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301123 pmic->ext_sleep_control = tps65911_ext_sleep_control;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001124 info = tps65911_regs;
Axel Lind04156b2011-07-10 21:44:09 +08001125 break;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001126 default:
Laxman Dewangan7e9a57e2012-05-20 21:48:48 +05301127 dev_err(&pdev->dev, "Invalid tps chip version\n");
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001128 return -ENODEV;
1129 }
1130
Kees Cooka86854d2018-06-12 14:07:58 -07001131 pmic->desc = devm_kcalloc(&pdev->dev,
1132 pmic->num_regulators,
1133 sizeof(struct regulator_desc),
1134 GFP_KERNEL);
Sachin Kamatbcb2c0d2014-02-20 14:23:18 +05301135 if (!pmic->desc)
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301136 return -ENOMEM;
Axel Lin39aa9b62011-07-11 09:57:43 +08001137
Kees Cooka86854d2018-06-12 14:07:58 -07001138 pmic->info = devm_kcalloc(&pdev->dev,
1139 pmic->num_regulators,
1140 sizeof(struct tps_info *),
1141 GFP_KERNEL);
Sachin Kamatbcb2c0d2014-02-20 14:23:18 +05301142 if (!pmic->info)
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301143 return -ENOMEM;
Axel Lin39aa9b62011-07-11 09:57:43 +08001144
Kees Cooka86854d2018-06-12 14:07:58 -07001145 pmic->rdev = devm_kcalloc(&pdev->dev,
1146 pmic->num_regulators,
1147 sizeof(struct regulator_dev *),
1148 GFP_KERNEL);
Sachin Kamatbcb2c0d2014-02-20 14:23:18 +05301149 if (!pmic->rdev)
Laxman Dewangan68d8c1c2012-05-19 20:04:09 +05301150 return -ENOMEM;
Axel Lin39aa9b62011-07-11 09:57:43 +08001151
Michał Mirosławfe953902017-06-13 16:41:56 +02001152 for (i = 0; i < pmic->num_regulators; i++, info++) {
Graeme Gregory518fb722011-05-02 16:20:08 -05001153 /* Register the regulators */
1154 pmic->info[i] = info;
1155
1156 pmic->desc[i].name = info->name;
Laxman Dewangand2cfdb02012-07-17 11:34:06 +05301157 pmic->desc[i].supply_name = info->vin_name;
Axel Lin77fa44d2011-05-12 13:47:50 +08001158 pmic->desc[i].id = i;
Laxman Dewangan7d38a3c2012-01-20 16:36:22 +05301159 pmic->desc[i].n_voltages = info->n_voltages;
Axel Lin94f48ab2012-07-04 09:59:17 +08001160 pmic->desc[i].enable_time = info->enable_time_us;
Graeme Gregory518fb722011-05-02 16:20:08 -05001161
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001162 if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) {
Graeme Gregory518fb722011-05-02 16:20:08 -05001163 pmic->desc[i].ops = &tps65910_ops_dcdc;
Afzal Mohammed780dc9b2011-11-08 18:54:10 +05301164 pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE *
1165 VDD1_2_NUM_VOLT_COARSE;
Axel Lin01bc3a12012-06-20 22:40:10 +08001166 pmic->desc[i].ramp_delay = 12500;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001167 } else if (i == TPS65910_REG_VDD3) {
Axel Lin01bc3a12012-06-20 22:40:10 +08001168 if (tps65910_chip_id(tps65910) == TPS65910) {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001169 pmic->desc[i].ops = &tps65910_ops_vdd3;
Axel Lind9fe28f2012-06-21 18:48:00 +08001170 pmic->desc[i].volt_table = info->voltage_table;
Axel Lin01bc3a12012-06-20 22:40:10 +08001171 } else {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001172 pmic->desc[i].ops = &tps65910_ops_dcdc;
Axel Lin01bc3a12012-06-20 22:40:10 +08001173 pmic->desc[i].ramp_delay = 5000;
1174 }
Markus Pargmann03746dc2013-12-20 12:43:27 +01001175 } else if (i == TPS65910_REG_VBB &&
1176 tps65910_chip_id(tps65910) == TPS65910) {
1177 pmic->desc[i].ops = &tps65910_ops_vbb;
1178 pmic->desc[i].volt_table = info->voltage_table;
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001179 } else {
Axel Lind9fe28f2012-06-21 18:48:00 +08001180 if (tps65910_chip_id(tps65910) == TPS65910) {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001181 pmic->desc[i].ops = &tps65910_ops;
Axel Lind9fe28f2012-06-21 18:48:00 +08001182 pmic->desc[i].volt_table = info->voltage_table;
1183 } else {
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001184 pmic->desc[i].ops = &tps65911_ops;
Axel Lind9fe28f2012-06-21 18:48:00 +08001185 }
Jorge Eduardo Candelariaa320e3c2011-05-16 18:35:03 -05001186 }
Graeme Gregory518fb722011-05-02 16:20:08 -05001187
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301188 err = tps65910_set_ext_sleep_config(pmic, i,
1189 pmic_plat_data->regulator_ext_sleep_control[i]);
1190 /*
1191 * Failing on regulator for configuring externally control
1192 * is not a serious issue, just throw warning.
1193 */
1194 if (err < 0)
1195 dev_warn(tps65910->dev,
1196 "Failed to initialise ext control config\n");
1197
Graeme Gregory518fb722011-05-02 16:20:08 -05001198 pmic->desc[i].type = REGULATOR_VOLTAGE;
1199 pmic->desc[i].owner = THIS_MODULE;
Axel Lina40a9c42012-04-17 14:34:46 +08001200 pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i);
Axel Linb8903eb2013-12-29 17:00:20 +08001201 pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED;
Graeme Gregory518fb722011-05-02 16:20:08 -05001202
Mark Brownc1727082012-04-04 00:50:22 +01001203 config.dev = tps65910->dev;
Axel Lin23b11342014-02-18 21:11:48 +08001204 config.init_data = pmic_plat_data->tps65910_pmic_init_data[i];
Mark Brownc1727082012-04-04 00:50:22 +01001205 config.driver_data = pmic;
Axel Lina40a9c42012-04-17 14:34:46 +08001206 config.regmap = tps65910->regmap;
Mark Brownc1727082012-04-04 00:50:22 +01001207
Laxman Dewangan84df8c12012-05-20 21:48:50 +05301208 if (tps65910_reg_matches)
1209 config.of_node = tps65910_reg_matches[i].of_node;
Rhyland Klein67901782012-05-08 11:42:41 -07001210
Sachin Kamat95095e42013-09-04 17:17:51 +05301211 rdev = devm_regulator_register(&pdev->dev, &pmic->desc[i],
1212 &config);
Graeme Gregory518fb722011-05-02 16:20:08 -05001213 if (IS_ERR(rdev)) {
1214 dev_err(tps65910->dev,
1215 "failed to register %s regulator\n",
1216 pdev->name);
Sachin Kamat95095e42013-09-04 17:17:51 +05301217 return PTR_ERR(rdev);
Graeme Gregory518fb722011-05-02 16:20:08 -05001218 }
1219
1220 /* Save regulator for cleanup */
1221 pmic->rdev[i] = rdev;
1222 }
1223 return 0;
Graeme Gregory518fb722011-05-02 16:20:08 -05001224}
1225
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301226static void tps65910_shutdown(struct platform_device *pdev)
1227{
1228 struct tps65910_reg *pmic = platform_get_drvdata(pdev);
1229 int i;
1230
1231 /*
1232 * Before bootloader jumps to kernel, it makes sure that required
1233 * external control signals are in desired state so that given rails
1234 * can be configure accordingly.
1235 * If rails are configured to be controlled from external control
1236 * then before shutting down/rebooting the system, the external
1237 * control configuration need to be remove from the rails so that
1238 * its output will be available as per register programming even
1239 * if external controls are removed. This is require when the POR
1240 * value of the control signals are not in active state and before
1241 * bootloader initializes it, the system requires the rail output
1242 * to be active for booting.
1243 */
1244 for (i = 0; i < pmic->num_regulators; i++) {
1245 int err;
1246 if (!pmic->rdev[i])
1247 continue;
1248
1249 err = tps65910_set_ext_sleep_config(pmic, i, 0);
1250 if (err < 0)
1251 dev_err(&pdev->dev,
1252 "Error in clearing external control\n");
1253 }
1254}
1255
Graeme Gregory518fb722011-05-02 16:20:08 -05001256static struct platform_driver tps65910_driver = {
1257 .driver = {
1258 .name = "tps65910-pmic",
Graeme Gregory518fb722011-05-02 16:20:08 -05001259 },
1260 .probe = tps65910_probe,
Laxman Dewangan1e0c66f2012-01-28 15:07:57 +05301261 .shutdown = tps65910_shutdown,
Graeme Gregory518fb722011-05-02 16:20:08 -05001262};
1263
1264static int __init tps65910_init(void)
1265{
1266 return platform_driver_register(&tps65910_driver);
1267}
1268subsys_initcall(tps65910_init);
1269
1270static void __exit tps65910_cleanup(void)
1271{
1272 platform_driver_unregister(&tps65910_driver);
1273}
1274module_exit(tps65910_cleanup);
1275
1276MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
Axel Linae0e6542012-02-21 10:14:55 +08001277MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver");
Graeme Gregory518fb722011-05-02 16:20:08 -05001278MODULE_LICENSE("GPL v2");
1279MODULE_ALIAS("platform:tps65910-pmic");