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review.shift-gmbh.com / SHIFTPHONES / kernel / common / b0d46cb598bed0b03921090ba5fb84ceb4c6f707 / . / drivers / pinctrl / meson / pinctrl-meson8.c
blob: 086082aeb7967bd708c311990a3d531c270d7afe [file] [log] [blame]
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]1/*
Martin Blumenstinglb0d46cb2018-04-22 12:53:29 +0200[diff] [blame^]2 * Pin controller and GPIO driver for Amlogic Meson8 and Meson8m2.
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
12 */
13
14#include <dt-bindings/gpio/meson8-gpio.h>
15#include "pinctrl-meson.h"
Jerome Brunetce385aa2017-10-12 14:40:26 +0200[diff] [blame]16#include "pinctrl-meson8-pmx.h"
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]17
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]18static const struct pinctrl_pin_desc meson8_cbus_pins[] = {
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]19 MESON_PIN(GPIOX_0),
20 MESON_PIN(GPIOX_1),
21 MESON_PIN(GPIOX_2),
22 MESON_PIN(GPIOX_3),
23 MESON_PIN(GPIOX_4),
24 MESON_PIN(GPIOX_5),
25 MESON_PIN(GPIOX_6),
26 MESON_PIN(GPIOX_7),
27 MESON_PIN(GPIOX_8),
28 MESON_PIN(GPIOX_9),
29 MESON_PIN(GPIOX_10),
30 MESON_PIN(GPIOX_11),
31 MESON_PIN(GPIOX_12),
32 MESON_PIN(GPIOX_13),
33 MESON_PIN(GPIOX_14),
34 MESON_PIN(GPIOX_15),
35 MESON_PIN(GPIOX_16),
36 MESON_PIN(GPIOX_17),
37 MESON_PIN(GPIOX_18),
38 MESON_PIN(GPIOX_19),
39 MESON_PIN(GPIOX_20),
40 MESON_PIN(GPIOX_21),
41 MESON_PIN(GPIOY_0),
42 MESON_PIN(GPIOY_1),
43 MESON_PIN(GPIOY_2),
44 MESON_PIN(GPIOY_3),
45 MESON_PIN(GPIOY_4),
46 MESON_PIN(GPIOY_5),
47 MESON_PIN(GPIOY_6),
48 MESON_PIN(GPIOY_7),
49 MESON_PIN(GPIOY_8),
50 MESON_PIN(GPIOY_9),
51 MESON_PIN(GPIOY_10),
52 MESON_PIN(GPIOY_11),
53 MESON_PIN(GPIOY_12),
54 MESON_PIN(GPIOY_13),
55 MESON_PIN(GPIOY_14),
56 MESON_PIN(GPIOY_15),
57 MESON_PIN(GPIOY_16),
58 MESON_PIN(GPIODV_0),
59 MESON_PIN(GPIODV_1),
60 MESON_PIN(GPIODV_2),
61 MESON_PIN(GPIODV_3),
62 MESON_PIN(GPIODV_4),
63 MESON_PIN(GPIODV_5),
64 MESON_PIN(GPIODV_6),
65 MESON_PIN(GPIODV_7),
66 MESON_PIN(GPIODV_8),
67 MESON_PIN(GPIODV_9),
68 MESON_PIN(GPIODV_10),
69 MESON_PIN(GPIODV_11),
70 MESON_PIN(GPIODV_12),
71 MESON_PIN(GPIODV_13),
72 MESON_PIN(GPIODV_14),
73 MESON_PIN(GPIODV_15),
74 MESON_PIN(GPIODV_16),
75 MESON_PIN(GPIODV_17),
76 MESON_PIN(GPIODV_18),
77 MESON_PIN(GPIODV_19),
78 MESON_PIN(GPIODV_20),
79 MESON_PIN(GPIODV_21),
80 MESON_PIN(GPIODV_22),
81 MESON_PIN(GPIODV_23),
82 MESON_PIN(GPIODV_24),
83 MESON_PIN(GPIODV_25),
84 MESON_PIN(GPIODV_26),
85 MESON_PIN(GPIODV_27),
86 MESON_PIN(GPIODV_28),
87 MESON_PIN(GPIODV_29),
88 MESON_PIN(GPIOH_0),
89 MESON_PIN(GPIOH_1),
90 MESON_PIN(GPIOH_2),
91 MESON_PIN(GPIOH_3),
92 MESON_PIN(GPIOH_4),
93 MESON_PIN(GPIOH_5),
94 MESON_PIN(GPIOH_6),
95 MESON_PIN(GPIOH_7),
96 MESON_PIN(GPIOH_8),
97 MESON_PIN(GPIOH_9),
98 MESON_PIN(GPIOZ_0),
99 MESON_PIN(GPIOZ_1),
100 MESON_PIN(GPIOZ_2),
101 MESON_PIN(GPIOZ_3),
102 MESON_PIN(GPIOZ_4),
103 MESON_PIN(GPIOZ_5),
104 MESON_PIN(GPIOZ_6),
105 MESON_PIN(GPIOZ_7),
106 MESON_PIN(GPIOZ_8),
107 MESON_PIN(GPIOZ_9),
108 MESON_PIN(GPIOZ_10),
109 MESON_PIN(GPIOZ_11),
110 MESON_PIN(GPIOZ_12),
111 MESON_PIN(GPIOZ_13),
112 MESON_PIN(GPIOZ_14),
113 MESON_PIN(CARD_0),
114 MESON_PIN(CARD_1),
115 MESON_PIN(CARD_2),
116 MESON_PIN(CARD_3),
117 MESON_PIN(CARD_4),
118 MESON_PIN(CARD_5),
119 MESON_PIN(CARD_6),
120 MESON_PIN(BOOT_0),
121 MESON_PIN(BOOT_1),
122 MESON_PIN(BOOT_2),
123 MESON_PIN(BOOT_3),
124 MESON_PIN(BOOT_4),
125 MESON_PIN(BOOT_5),
126 MESON_PIN(BOOT_6),
127 MESON_PIN(BOOT_7),
128 MESON_PIN(BOOT_8),
129 MESON_PIN(BOOT_9),
130 MESON_PIN(BOOT_10),
131 MESON_PIN(BOOT_11),
132 MESON_PIN(BOOT_12),
133 MESON_PIN(BOOT_13),
134 MESON_PIN(BOOT_14),
135 MESON_PIN(BOOT_15),
136 MESON_PIN(BOOT_16),
137 MESON_PIN(BOOT_17),
138 MESON_PIN(BOOT_18),
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]139};
140
141static const struct pinctrl_pin_desc meson8_aobus_pins[] = {
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]142 MESON_PIN(GPIOAO_0),
143 MESON_PIN(GPIOAO_1),
144 MESON_PIN(GPIOAO_2),
145 MESON_PIN(GPIOAO_3),
146 MESON_PIN(GPIOAO_4),
147 MESON_PIN(GPIOAO_5),
148 MESON_PIN(GPIOAO_6),
149 MESON_PIN(GPIOAO_7),
150 MESON_PIN(GPIOAO_8),
151 MESON_PIN(GPIOAO_9),
152 MESON_PIN(GPIOAO_10),
153 MESON_PIN(GPIOAO_11),
154 MESON_PIN(GPIOAO_12),
155 MESON_PIN(GPIOAO_13),
156 MESON_PIN(GPIO_BSD_EN),
157 MESON_PIN(GPIO_TEST_N),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]158};
159
160/* bank X */
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]161static const unsigned int sd_d0_a_pins[] = { GPIOX_0 };
162static const unsigned int sd_d1_a_pins[] = { GPIOX_1 };
163static const unsigned int sd_d2_a_pins[] = { GPIOX_2 };
164static const unsigned int sd_d3_a_pins[] = { GPIOX_3 };
165static const unsigned int sd_clk_a_pins[] = { GPIOX_8 };
166static const unsigned int sd_cmd_a_pins[] = { GPIOX_9 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]167
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]168static const unsigned int sdxc_d0_a_pins[] = { GPIOX_0 };
169static const unsigned int sdxc_d13_a_pins[] = { GPIOX_1, GPIOX_2, GPIOX_3 };
170static const unsigned int sdxc_d47_a_pins[] = { GPIOX_4, GPIOX_5, GPIOX_6,
171 GPIOX_7 };
172static const unsigned int sdxc_clk_a_pins[] = { GPIOX_8 };
173static const unsigned int sdxc_cmd_a_pins[] = { GPIOX_9 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]174
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]175static const unsigned int pcm_out_a_pins[] = { GPIOX_4 };
176static const unsigned int pcm_in_a_pins[] = { GPIOX_5 };
177static const unsigned int pcm_fs_a_pins[] = { GPIOX_6 };
178static const unsigned int pcm_clk_a_pins[] = { GPIOX_7 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]179
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]180static const unsigned int uart_tx_a0_pins[] = { GPIOX_4 };
181static const unsigned int uart_rx_a0_pins[] = { GPIOX_5 };
182static const unsigned int uart_cts_a0_pins[] = { GPIOX_6 };
183static const unsigned int uart_rts_a0_pins[] = { GPIOX_7 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]184
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]185static const unsigned int uart_tx_a1_pins[] = { GPIOX_12 };
186static const unsigned int uart_rx_a1_pins[] = { GPIOX_13 };
187static const unsigned int uart_cts_a1_pins[] = { GPIOX_14 };
188static const unsigned int uart_rts_a1_pins[] = { GPIOX_15 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]189
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]190static const unsigned int uart_tx_b0_pins[] = { GPIOX_16 };
191static const unsigned int uart_rx_b0_pins[] = { GPIOX_17 };
192static const unsigned int uart_cts_b0_pins[] = { GPIOX_18 };
193static const unsigned int uart_rts_b0_pins[] = { GPIOX_19 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]194
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]195static const unsigned int iso7816_det_pins[] = { GPIOX_16 };
196static const unsigned int iso7816_reset_pins[] = { GPIOX_17 };
197static const unsigned int iso7816_clk_pins[] = { GPIOX_18 };
198static const unsigned int iso7816_data_pins[] = { GPIOX_19 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]199
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]200static const unsigned int i2c_sda_d0_pins[] = { GPIOX_16 };
201static const unsigned int i2c_sck_d0_pins[] = { GPIOX_17 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]202
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]203static const unsigned int xtal_32k_out_pins[] = { GPIOX_10 };
204static const unsigned int xtal_24m_out_pins[] = { GPIOX_11 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]205
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]206static const unsigned int pwm_e_pins[] = { GPIOX_10 };
207static const unsigned int pwm_b_x_pins[] = { GPIOX_11 };
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]208
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]209/* bank Y */
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]210static const unsigned int uart_tx_c_pins[] = { GPIOY_0 };
211static const unsigned int uart_rx_c_pins[] = { GPIOY_1 };
212static const unsigned int uart_cts_c_pins[] = { GPIOY_2 };
213static const unsigned int uart_rts_c_pins[] = { GPIOY_3 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]214
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]215static const unsigned int pcm_out_b_pins[] = { GPIOY_4 };
216static const unsigned int pcm_in_b_pins[] = { GPIOY_5 };
217static const unsigned int pcm_fs_b_pins[] = { GPIOY_6 };
218static const unsigned int pcm_clk_b_pins[] = { GPIOY_7 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]219
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]220static const unsigned int i2c_sda_c0_pins[] = { GPIOY_0 };
221static const unsigned int i2c_sck_c0_pins[] = { GPIOY_1 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]222
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]223static const unsigned int pwm_a_y_pins[] = { GPIOY_16 };
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]224
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]225static const unsigned int i2s_out_ch45_pins[] = { GPIOY_0 };
226static const unsigned int i2s_out_ch23_pins[] = { GPIOY_1 };
227static const unsigned int i2s_out_ch01_pins[] = { GPIOY_4 };
228static const unsigned int i2s_in_ch01_pins[] = { GPIOY_5 };
229static const unsigned int i2s_lr_clk_in_pins[] = { GPIOY_6 };
230static const unsigned int i2s_ao_clk_in_pins[] = { GPIOY_7 };
231static const unsigned int i2s_am_clk_pins[] = { GPIOY_8 };
232static const unsigned int i2s_out_ch78_pins[] = { GPIOY_9 };
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]233
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]234static const unsigned int spdif_in_pins[] = { GPIOY_2 };
235static const unsigned int spdif_out_pins[] = { GPIOY_3 };
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]236
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]237/* bank DV */
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]238static const unsigned int dvin_rgb_pins[] = {
239 GPIODV_0, GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5,
240 GPIODV_6, GPIODV_7, GPIODV_8, GPIODV_9, GPIODV_10, GPIODV_11,
241 GPIODV_12, GPIODV_13, GPIODV_14, GPIODV_15, GPIODV_16, GPIODV_17,
242 GPIODV_18, GPIODV_19, GPIODV_20, GPIODV_21, GPIODV_22, GPIODV_23
243};
244static const unsigned int dvin_vs_pins[] = { GPIODV_24 };
245static const unsigned int dvin_hs_pins[] = { GPIODV_25 };
246static const unsigned int dvin_clk_pins[] = { GPIODV_26 };
247static const unsigned int dvin_de_pins[] = { GPIODV_27 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]248
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]249static const unsigned int enc_0_pins[] = { GPIODV_0 };
250static const unsigned int enc_1_pins[] = { GPIODV_1 };
251static const unsigned int enc_2_pins[] = { GPIODV_2 };
252static const unsigned int enc_3_pins[] = { GPIODV_3 };
253static const unsigned int enc_4_pins[] = { GPIODV_4 };
254static const unsigned int enc_5_pins[] = { GPIODV_5 };
255static const unsigned int enc_6_pins[] = { GPIODV_6 };
256static const unsigned int enc_7_pins[] = { GPIODV_7 };
257static const unsigned int enc_8_pins[] = { GPIODV_8 };
258static const unsigned int enc_9_pins[] = { GPIODV_9 };
259static const unsigned int enc_10_pins[] = { GPIODV_10 };
260static const unsigned int enc_11_pins[] = { GPIODV_11 };
261static const unsigned int enc_12_pins[] = { GPIODV_12 };
262static const unsigned int enc_13_pins[] = { GPIODV_13 };
263static const unsigned int enc_14_pins[] = { GPIODV_14 };
264static const unsigned int enc_15_pins[] = { GPIODV_15 };
265static const unsigned int enc_16_pins[] = { GPIODV_16 };
266static const unsigned int enc_17_pins[] = { GPIODV_17 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]267
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]268static const unsigned int uart_tx_b1_pins[] = { GPIODV_24 };
269static const unsigned int uart_rx_b1_pins[] = { GPIODV_25 };
270static const unsigned int uart_cts_b1_pins[] = { GPIODV_26 };
271static const unsigned int uart_rts_b1_pins[] = { GPIODV_27 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]272
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]273static const unsigned int vga_vs_pins[] = { GPIODV_24 };
274static const unsigned int vga_hs_pins[] = { GPIODV_25 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]275
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]276static const unsigned int pwm_c_dv9_pins[] = { GPIODV_9 };
277static const unsigned int pwm_c_dv29_pins[] = { GPIODV_29 };
278static const unsigned int pwm_d_pins[] = { GPIODV_28 };
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]279
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]280/* bank H */
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]281static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 };
282static const unsigned int hdmi_sda_pins[] = { GPIOH_1 };
283static const unsigned int hdmi_scl_pins[] = { GPIOH_2 };
284static const unsigned int hdmi_cec_pins[] = { GPIOH_3 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]285
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]286static const unsigned int spi_ss0_0_pins[] = { GPIOH_3 };
287static const unsigned int spi_miso_0_pins[] = { GPIOH_4 };
288static const unsigned int spi_mosi_0_pins[] = { GPIOH_5 };
289static const unsigned int spi_sclk_0_pins[] = { GPIOH_6 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]290
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]291static const unsigned int i2c_sda_d1_pins[] = { GPIOH_7 };
292static const unsigned int i2c_sck_d1_pins[] = { GPIOH_8 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]293
294/* bank Z */
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]295static const unsigned int spi_ss0_1_pins[] = { GPIOZ_9 };
296static const unsigned int spi_ss1_1_pins[] = { GPIOZ_10 };
297static const unsigned int spi_sclk_1_pins[] = { GPIOZ_11 };
298static const unsigned int spi_mosi_1_pins[] = { GPIOZ_12 };
299static const unsigned int spi_miso_1_pins[] = { GPIOZ_13 };
300static const unsigned int spi_ss2_1_pins[] = { GPIOZ_14 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]301
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]302static const unsigned int eth_tx_clk_50m_pins[] = { GPIOZ_4 };
303static const unsigned int eth_tx_en_pins[] = { GPIOZ_5 };
304static const unsigned int eth_txd1_pins[] = { GPIOZ_6 };
305static const unsigned int eth_txd0_pins[] = { GPIOZ_7 };
306static const unsigned int eth_rx_clk_in_pins[] = { GPIOZ_8 };
307static const unsigned int eth_rx_dv_pins[] = { GPIOZ_9 };
308static const unsigned int eth_rxd1_pins[] = { GPIOZ_10 };
309static const unsigned int eth_rxd0_pins[] = { GPIOZ_11 };
310static const unsigned int eth_mdio_pins[] = { GPIOZ_12 };
311static const unsigned int eth_mdc_pins[] = { GPIOZ_13 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]312
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]313static const unsigned int i2c_sda_a0_pins[] = { GPIOZ_0 };
314static const unsigned int i2c_sck_a0_pins[] = { GPIOZ_1 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]315
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]316static const unsigned int i2c_sda_b_pins[] = { GPIOZ_2 };
317static const unsigned int i2c_sck_b_pins[] = { GPIOZ_3 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]318
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]319static const unsigned int i2c_sda_c1_pins[] = { GPIOZ_4 };
320static const unsigned int i2c_sck_c1_pins[] = { GPIOZ_5 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]321
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]322static const unsigned int i2c_sda_a1_pins[] = { GPIOZ_0 };
323static const unsigned int i2c_sck_a1_pins[] = { GPIOZ_1 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]324
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]325static const unsigned int i2c_sda_a2_pins[] = { GPIOZ_0 };
326static const unsigned int i2c_sck_a2_pins[] = { GPIOZ_1 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]327
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]328static const unsigned int pwm_a_z0_pins[] = { GPIOZ_0 };
329static const unsigned int pwm_a_z7_pins[] = { GPIOZ_7 };
330static const unsigned int pwm_b_z_pins[] = { GPIOZ_1 };
331static const unsigned int pwm_c_z_pins[] = { GPIOZ_8 };
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]332
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]333/* bank BOOT */
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]334static const unsigned int sd_d0_c_pins[] = { BOOT_0 };
335static const unsigned int sd_d1_c_pins[] = { BOOT_1 };
336static const unsigned int sd_d2_c_pins[] = { BOOT_2 };
337static const unsigned int sd_d3_c_pins[] = { BOOT_3 };
338static const unsigned int sd_cmd_c_pins[] = { BOOT_16 };
339static const unsigned int sd_clk_c_pins[] = { BOOT_17 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]340
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]341static const unsigned int sdxc_d0_c_pins[] = { BOOT_0};
342static const unsigned int sdxc_d13_c_pins[] = { BOOT_1, BOOT_2, BOOT_3 };
343static const unsigned int sdxc_d47_c_pins[] = { BOOT_4, BOOT_5, BOOT_6,
344 BOOT_7 };
345static const unsigned int sdxc_cmd_c_pins[] = { BOOT_16 };
346static const unsigned int sdxc_clk_c_pins[] = { BOOT_17 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]347
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]348static const unsigned int nand_io_pins[] = {
349 BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7
350};
351static const unsigned int nand_io_ce0_pins[] = { BOOT_8 };
352static const unsigned int nand_io_ce1_pins[] = { BOOT_9 };
353static const unsigned int nand_io_rb0_pins[] = { BOOT_10 };
354static const unsigned int nand_ale_pins[] = { BOOT_11 };
355static const unsigned int nand_cle_pins[] = { BOOT_12 };
356static const unsigned int nand_wen_clk_pins[] = { BOOT_13 };
357static const unsigned int nand_ren_clk_pins[] = { BOOT_14 };
358static const unsigned int nand_dqs_pins[] = { BOOT_15 };
359static const unsigned int nand_ce2_pins[] = { BOOT_16 };
360static const unsigned int nand_ce3_pins[] = { BOOT_17 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]361
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]362static const unsigned int nor_d_pins[] = { BOOT_11 };
363static const unsigned int nor_q_pins[] = { BOOT_12 };
364static const unsigned int nor_c_pins[] = { BOOT_13 };
365static const unsigned int nor_cs_pins[] = { BOOT_18 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]366
367/* bank CARD */
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]368static const unsigned int sd_d1_b_pins[] = { CARD_0 };
369static const unsigned int sd_d0_b_pins[] = { CARD_1 };
370static const unsigned int sd_clk_b_pins[] = { CARD_2 };
371static const unsigned int sd_cmd_b_pins[] = { CARD_3 };
372static const unsigned int sd_d3_b_pins[] = { CARD_4 };
373static const unsigned int sd_d2_b_pins[] = { CARD_5 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]374
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]375static const unsigned int sdxc_d13_b_pins[] = { CARD_0, CARD_4, CARD_5 };
376static const unsigned int sdxc_d0_b_pins[] = { CARD_1 };
377static const unsigned int sdxc_clk_b_pins[] = { CARD_2 };
378static const unsigned int sdxc_cmd_b_pins[] = { CARD_3 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]379
380/* bank AO */
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]381static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 };
382static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 };
383static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 };
384static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]385
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]386static const unsigned int remote_input_pins[] = { GPIOAO_7 };
387static const unsigned int remote_output_ao_pins[] = { GPIOAO_13 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]388
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]389static const unsigned int i2c_slave_sck_ao_pins[] = { GPIOAO_4 };
390static const unsigned int i2c_slave_sda_ao_pins[] = { GPIOAO_5 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]391
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]392static const unsigned int uart_tx_ao_b0_pins[] = { GPIOAO_0 };
393static const unsigned int uart_rx_ao_b0_pins[] = { GPIOAO_1 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]394
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]395static const unsigned int uart_tx_ao_b1_pins[] = { GPIOAO_4 };
396static const unsigned int uart_rx_ao_b1_pins[] = { GPIOAO_5 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]397
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]398static const unsigned int i2c_mst_sck_ao_pins[] = { GPIOAO_4 };
399static const unsigned int i2c_mst_sda_ao_pins[] = { GPIOAO_5 };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]400
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]401static const unsigned int pwm_f_ao_pins[] = { GPIO_TEST_N };
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]402
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]403static const unsigned int i2s_am_clk_out_ao_pins[] = { GPIOAO_8 };
404static const unsigned int i2s_ao_clk_out_ao_pins[] = { GPIOAO_9 };
405static const unsigned int i2s_lr_clk_out_ao_pins[] = { GPIOAO_10 };
406static const unsigned int i2s_out_ch01_ao_pins[] = { GPIOAO_11 };
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]407
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]408static const unsigned int hdmi_cec_ao_pins[] = { GPIOAO_12 };
Martin Blumenstinglc21b4322017-05-06 18:57:51 +0200[diff] [blame]409
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]410static struct meson_pmx_group meson8_cbus_groups[] = {
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]411 GPIO_GROUP(GPIOX_0),
412 GPIO_GROUP(GPIOX_1),
413 GPIO_GROUP(GPIOX_2),
414 GPIO_GROUP(GPIOX_3),
415 GPIO_GROUP(GPIOX_4),
416 GPIO_GROUP(GPIOX_5),
417 GPIO_GROUP(GPIOX_6),
418 GPIO_GROUP(GPIOX_7),
419 GPIO_GROUP(GPIOX_8),
420 GPIO_GROUP(GPIOX_9),
421 GPIO_GROUP(GPIOX_10),
422 GPIO_GROUP(GPIOX_11),
423 GPIO_GROUP(GPIOX_12),
424 GPIO_GROUP(GPIOX_13),
425 GPIO_GROUP(GPIOX_14),
426 GPIO_GROUP(GPIOX_15),
427 GPIO_GROUP(GPIOX_16),
428 GPIO_GROUP(GPIOX_17),
429 GPIO_GROUP(GPIOX_18),
430 GPIO_GROUP(GPIOX_19),
431 GPIO_GROUP(GPIOX_20),
432 GPIO_GROUP(GPIOX_21),
433 GPIO_GROUP(GPIOY_0),
434 GPIO_GROUP(GPIOY_1),
435 GPIO_GROUP(GPIOY_2),
436 GPIO_GROUP(GPIOY_3),
437 GPIO_GROUP(GPIOY_4),
438 GPIO_GROUP(GPIOY_5),
439 GPIO_GROUP(GPIOY_6),
440 GPIO_GROUP(GPIOY_7),
441 GPIO_GROUP(GPIOY_8),
442 GPIO_GROUP(GPIOY_9),
443 GPIO_GROUP(GPIOY_10),
444 GPIO_GROUP(GPIOY_11),
445 GPIO_GROUP(GPIOY_12),
446 GPIO_GROUP(GPIOY_13),
447 GPIO_GROUP(GPIOY_14),
448 GPIO_GROUP(GPIOY_15),
449 GPIO_GROUP(GPIOY_16),
450 GPIO_GROUP(GPIODV_0),
451 GPIO_GROUP(GPIODV_1),
452 GPIO_GROUP(GPIODV_2),
453 GPIO_GROUP(GPIODV_3),
454 GPIO_GROUP(GPIODV_4),
455 GPIO_GROUP(GPIODV_5),
456 GPIO_GROUP(GPIODV_6),
457 GPIO_GROUP(GPIODV_7),
458 GPIO_GROUP(GPIODV_8),
459 GPIO_GROUP(GPIODV_9),
460 GPIO_GROUP(GPIODV_10),
461 GPIO_GROUP(GPIODV_11),
462 GPIO_GROUP(GPIODV_12),
463 GPIO_GROUP(GPIODV_13),
464 GPIO_GROUP(GPIODV_14),
465 GPIO_GROUP(GPIODV_15),
466 GPIO_GROUP(GPIODV_16),
467 GPIO_GROUP(GPIODV_17),
468 GPIO_GROUP(GPIODV_18),
469 GPIO_GROUP(GPIODV_19),
470 GPIO_GROUP(GPIODV_20),
471 GPIO_GROUP(GPIODV_21),
472 GPIO_GROUP(GPIODV_22),
473 GPIO_GROUP(GPIODV_23),
474 GPIO_GROUP(GPIODV_24),
475 GPIO_GROUP(GPIODV_25),
476 GPIO_GROUP(GPIODV_26),
477 GPIO_GROUP(GPIODV_27),
478 GPIO_GROUP(GPIODV_28),
479 GPIO_GROUP(GPIODV_29),
480 GPIO_GROUP(GPIOH_0),
481 GPIO_GROUP(GPIOH_1),
482 GPIO_GROUP(GPIOH_2),
483 GPIO_GROUP(GPIOH_3),
484 GPIO_GROUP(GPIOH_4),
485 GPIO_GROUP(GPIOH_5),
486 GPIO_GROUP(GPIOH_6),
487 GPIO_GROUP(GPIOH_7),
488 GPIO_GROUP(GPIOH_8),
489 GPIO_GROUP(GPIOH_9),
490 GPIO_GROUP(GPIOZ_0),
491 GPIO_GROUP(GPIOZ_1),
492 GPIO_GROUP(GPIOZ_2),
493 GPIO_GROUP(GPIOZ_3),
494 GPIO_GROUP(GPIOZ_4),
495 GPIO_GROUP(GPIOZ_5),
496 GPIO_GROUP(GPIOZ_6),
497 GPIO_GROUP(GPIOZ_7),
498 GPIO_GROUP(GPIOZ_8),
499 GPIO_GROUP(GPIOZ_9),
500 GPIO_GROUP(GPIOZ_10),
501 GPIO_GROUP(GPIOZ_11),
502 GPIO_GROUP(GPIOZ_12),
503 GPIO_GROUP(GPIOZ_13),
504 GPIO_GROUP(GPIOZ_14),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]505
506 /* bank X */
507 GROUP(sd_d0_a, 8, 5),
508 GROUP(sd_d1_a, 8, 4),
509 GROUP(sd_d2_a, 8, 3),
510 GROUP(sd_d3_a, 8, 2),
511 GROUP(sd_clk_a, 8, 1),
512 GROUP(sd_cmd_a, 8, 0),
513
514 GROUP(sdxc_d0_a, 5, 14),
515 GROUP(sdxc_d13_a, 5, 13),
516 GROUP(sdxc_d47_a, 5, 12),
517 GROUP(sdxc_clk_a, 5, 11),
518 GROUP(sdxc_cmd_a, 5, 10),
519
520 GROUP(pcm_out_a, 3, 30),
521 GROUP(pcm_in_a, 3, 29),
522 GROUP(pcm_fs_a, 3, 28),
523 GROUP(pcm_clk_a, 3, 27),
524
525 GROUP(uart_tx_a0, 4, 17),
526 GROUP(uart_rx_a0, 4, 16),
527 GROUP(uart_cts_a0, 4, 15),
528 GROUP(uart_rts_a0, 4, 14),
529
530 GROUP(uart_tx_a1, 4, 13),
531 GROUP(uart_rx_a1, 4, 12),
532 GROUP(uart_cts_a1, 4, 11),
533 GROUP(uart_rts_a1, 4, 10),
534
535 GROUP(uart_tx_b0, 4, 9),
536 GROUP(uart_rx_b0, 4, 8),
537 GROUP(uart_cts_b0, 4, 7),
538 GROUP(uart_rts_b0, 4, 6),
539
540 GROUP(iso7816_det, 4, 21),
541 GROUP(iso7816_reset, 4, 20),
542 GROUP(iso7816_clk, 4, 19),
543 GROUP(iso7816_data, 4, 18),
544
545 GROUP(i2c_sda_d0, 4, 5),
546 GROUP(i2c_sck_d0, 4, 4),
547
548 GROUP(xtal_32k_out, 3, 22),
549 GROUP(xtal_24m_out, 3, 23),
550
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]551 GROUP(pwm_e, 9, 19),
552 GROUP(pwm_b_x, 2, 3),
553
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]554 /* bank Y */
555 GROUP(uart_tx_c, 1, 19),
556 GROUP(uart_rx_c, 1, 18),
557 GROUP(uart_cts_c, 1, 17),
558 GROUP(uart_rts_c, 1, 16),
559
560 GROUP(pcm_out_b, 4, 25),
561 GROUP(pcm_in_b, 4, 24),
562 GROUP(pcm_fs_b, 4, 23),
563 GROUP(pcm_clk_b, 4, 22),
564
565 GROUP(i2c_sda_c0, 1, 15),
566 GROUP(i2c_sck_c0, 1, 14),
567
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]568 GROUP(pwm_a_y, 9, 14),
569
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]570 GROUP(i2s_out_ch45, 1, 10),
571 GROUP(i2s_out_ch23, 1, 19),
572 GROUP(i2s_out_ch01, 1, 6),
573 GROUP(i2s_in_ch01, 1, 5),
574 GROUP(i2s_lr_clk_in, 1, 4),
575 GROUP(i2s_ao_clk_in, 1, 2),
576 GROUP(i2s_am_clk, 1, 0),
577 GROUP(i2s_out_ch78, 1, 11),
578
579 GROUP(spdif_in, 1, 8),
580 GROUP(spdif_out, 1, 7),
581
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]582 /* bank DV */
583 GROUP(dvin_rgb, 0, 6),
584 GROUP(dvin_vs, 0, 9),
585 GROUP(dvin_hs, 0, 8),
586 GROUP(dvin_clk, 0, 7),
587 GROUP(dvin_de, 0, 10),
588
589 GROUP(enc_0, 7, 0),
590 GROUP(enc_1, 7, 1),
591 GROUP(enc_2, 7, 2),
592 GROUP(enc_3, 7, 3),
593 GROUP(enc_4, 7, 4),
594 GROUP(enc_5, 7, 5),
595 GROUP(enc_6, 7, 6),
596 GROUP(enc_7, 7, 7),
597 GROUP(enc_8, 7, 8),
598 GROUP(enc_9, 7, 9),
599 GROUP(enc_10, 7, 10),
600 GROUP(enc_11, 7, 11),
601 GROUP(enc_12, 7, 12),
602 GROUP(enc_13, 7, 13),
603 GROUP(enc_14, 7, 14),
604 GROUP(enc_15, 7, 15),
605 GROUP(enc_16, 7, 16),
606 GROUP(enc_17, 7, 17),
607
608 GROUP(uart_tx_b1, 6, 23),
609 GROUP(uart_rx_b1, 6, 22),
610 GROUP(uart_cts_b1, 6, 21),
611 GROUP(uart_rts_b1, 6, 20),
612
613 GROUP(vga_vs, 0, 21),
614 GROUP(vga_hs, 0, 20),
615
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]616 GROUP(pwm_c_dv9, 3, 24),
617 GROUP(pwm_c_dv29, 3, 25),
618 GROUP(pwm_d, 3, 26),
619
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]620 /* bank H */
621 GROUP(hdmi_hpd, 1, 26),
622 GROUP(hdmi_sda, 1, 25),
623 GROUP(hdmi_scl, 1, 24),
624 GROUP(hdmi_cec, 1, 23),
625
626 GROUP(spi_ss0_0, 9, 13),
627 GROUP(spi_miso_0, 9, 12),
628 GROUP(spi_mosi_0, 9, 11),
629 GROUP(spi_sclk_0, 9, 10),
630
631 GROUP(i2c_sda_d1, 4, 3),
632 GROUP(i2c_sck_d1, 4, 2),
633
634 /* bank Z */
635 GROUP(spi_ss0_1, 8, 16),
636 GROUP(spi_ss1_1, 8, 12),
637 GROUP(spi_sclk_1, 8, 15),
638 GROUP(spi_mosi_1, 8, 14),
639 GROUP(spi_miso_1, 8, 13),
640 GROUP(spi_ss2_1, 8, 17),
641
642 GROUP(eth_tx_clk_50m, 6, 15),
643 GROUP(eth_tx_en, 6, 14),
644 GROUP(eth_txd1, 6, 13),
645 GROUP(eth_txd0, 6, 12),
646 GROUP(eth_rx_clk_in, 6, 10),
647 GROUP(eth_rx_dv, 6, 11),
648 GROUP(eth_rxd1, 6, 8),
649 GROUP(eth_rxd0, 6, 7),
650 GROUP(eth_mdio, 6, 6),
651 GROUP(eth_mdc, 6, 5),
652
653 GROUP(i2c_sda_a0, 5, 31),
654 GROUP(i2c_sck_a0, 5, 30),
655
656 GROUP(i2c_sda_b, 5, 27),
657 GROUP(i2c_sck_b, 5, 26),
658
659 GROUP(i2c_sda_c1, 5, 25),
660 GROUP(i2c_sck_c1, 5, 24),
661
662 GROUP(i2c_sda_a1, 5, 9),
663 GROUP(i2c_sck_a1, 5, 8),
664
665 GROUP(i2c_sda_a2, 5, 7),
666 GROUP(i2c_sck_a2, 5, 6),
667
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]668 GROUP(pwm_a_z0, 9, 16),
669 GROUP(pwm_a_z7, 2, 0),
670 GROUP(pwm_b_z, 9, 15),
671 GROUP(pwm_c_z, 2, 1),
672
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]673 /* bank BOOT */
674 GROUP(sd_d0_c, 6, 29),
675 GROUP(sd_d1_c, 6, 28),
676 GROUP(sd_d2_c, 6, 27),
677 GROUP(sd_d3_c, 6, 26),
678 GROUP(sd_cmd_c, 6, 25),
679 GROUP(sd_clk_c, 6, 24),
680
681 GROUP(sdxc_d0_c, 4, 30),
682 GROUP(sdxc_d13_c, 4, 29),
683 GROUP(sdxc_d47_c, 4, 28),
684 GROUP(sdxc_cmd_c, 4, 27),
685 GROUP(sdxc_clk_c, 4, 26),
686
687 GROUP(nand_io, 2, 26),
688 GROUP(nand_io_ce0, 2, 25),
689 GROUP(nand_io_ce1, 2, 24),
690 GROUP(nand_io_rb0, 2, 17),
691 GROUP(nand_ale, 2, 21),
692 GROUP(nand_cle, 2, 20),
693 GROUP(nand_wen_clk, 2, 19),
694 GROUP(nand_ren_clk, 2, 18),
695 GROUP(nand_dqs, 2, 27),
696 GROUP(nand_ce2, 2, 23),
697 GROUP(nand_ce3, 2, 22),
698
699 GROUP(nor_d, 5, 1),
700 GROUP(nor_q, 5, 3),
701 GROUP(nor_c, 5, 2),
702 GROUP(nor_cs, 5, 0),
703
704 /* bank CARD */
705 GROUP(sd_d1_b, 2, 14),
706 GROUP(sd_d0_b, 2, 15),
707 GROUP(sd_clk_b, 2, 11),
708 GROUP(sd_cmd_b, 2, 10),
709 GROUP(sd_d3_b, 2, 12),
710 GROUP(sd_d2_b, 2, 13),
711
712 GROUP(sdxc_d13_b, 2, 6),
713 GROUP(sdxc_d0_b, 2, 7),
714 GROUP(sdxc_clk_b, 2, 5),
715 GROUP(sdxc_cmd_b, 2, 4),
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]716};
717
718static struct meson_pmx_group meson8_aobus_groups[] = {
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]719 GPIO_GROUP(GPIOAO_0),
720 GPIO_GROUP(GPIOAO_1),
721 GPIO_GROUP(GPIOAO_2),
722 GPIO_GROUP(GPIOAO_3),
723 GPIO_GROUP(GPIOAO_4),
724 GPIO_GROUP(GPIOAO_5),
725 GPIO_GROUP(GPIOAO_6),
726 GPIO_GROUP(GPIOAO_7),
727 GPIO_GROUP(GPIOAO_8),
728 GPIO_GROUP(GPIOAO_9),
729 GPIO_GROUP(GPIOAO_10),
730 GPIO_GROUP(GPIOAO_11),
731 GPIO_GROUP(GPIOAO_12),
732 GPIO_GROUP(GPIOAO_13),
733 GPIO_GROUP(GPIO_BSD_EN),
734 GPIO_GROUP(GPIO_TEST_N),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]735
736 /* bank AO */
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]737 GROUP(uart_tx_ao_a, 0, 12),
738 GROUP(uart_rx_ao_a, 0, 11),
739 GROUP(uart_cts_ao_a, 0, 10),
740 GROUP(uart_rts_ao_a, 0, 9),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]741
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]742 GROUP(remote_input, 0, 0),
Martin Blumenstingle70a3842017-05-06 18:57:50 +0200[diff] [blame]743 GROUP(remote_output_ao, 0, 31),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]744
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]745 GROUP(i2c_slave_sck_ao, 0, 2),
746 GROUP(i2c_slave_sda_ao, 0, 1),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]747
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]748 GROUP(uart_tx_ao_b0, 0, 26),
749 GROUP(uart_rx_ao_b0, 0, 25),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]750
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]751 GROUP(uart_tx_ao_b1, 0, 24),
752 GROUP(uart_rx_ao_b1, 0, 23),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]753
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]754 GROUP(i2c_mst_sck_ao, 0, 6),
755 GROUP(i2c_mst_sda_ao, 0, 5),
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]756
757 GROUP(pwm_f_ao, 0, 19),
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]758
759 GROUP(i2s_am_clk_out_ao, 0, 30),
760 GROUP(i2s_ao_clk_out_ao, 0, 29),
761 GROUP(i2s_lr_clk_out_ao, 0, 28),
762 GROUP(i2s_out_ch01_ao, 0, 27),
Martin Blumenstinglc21b4322017-05-06 18:57:51 +0200[diff] [blame]763
764 GROUP(hdmi_cec_ao, 0, 17),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]765};
766
767static const char * const gpio_groups[] = {
768 "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
769 "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
770 "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
771 "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
772 "GPIOX_20", "GPIOX_21",
773
774 "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
775 "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
776 "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
777 "GPIOY_15", "GPIOY_16",
778
779 "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4",
780 "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9",
781 "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14",
782 "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19",
783 "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24",
784 "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29",
785
786 "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
787 "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9",
788
789 "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
790 "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
791 "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14",
792
793 "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
794 "CARD_5", "CARD_6",
795
796 "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
797 "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
798 "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
799 "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18",
800
801 "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3",
802 "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7",
803 "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11",
804 "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N"
805};
806
807static const char * const sd_a_groups[] = {
808 "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a", "sd_cmd_a"
809};
810
811static const char * const sdxc_a_groups[] = {
812 "sdxc_d0_a", "sdxc_d13_a", "sdxc_d47_a", "sdxc_clk_a", "sdxc_cmd_a"
813};
814
815static const char * const pcm_a_groups[] = {
816 "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a"
817};
818
819static const char * const uart_a_groups[] = {
820 "uart_tx_a0", "uart_rx_a0", "uart_cts_a0", "uart_rts_a0",
821 "uart_tx_a1", "uart_rx_a1", "uart_cts_a1", "uart_rts_a1"
822};
823
824static const char * const uart_b_groups[] = {
825 "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0",
826 "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1"
827};
828
829static const char * const iso7816_groups[] = {
830 "iso7816_det", "iso7816_reset", "iso7816_clk", "iso7816_data"
831};
832
833static const char * const i2c_d_groups[] = {
834 "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1"
835};
836
837static const char * const xtal_groups[] = {
838 "xtal_32k_out", "xtal_24m_out"
839};
840
841static const char * const uart_c_groups[] = {
842 "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c"
843};
844
845static const char * const pcm_b_groups[] = {
846 "pcm_out_b", "pcm_in_b", "pcm_fs_b", "pcm_clk_b"
847};
848
849static const char * const i2c_c_groups[] = {
850 "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1"
851};
852
853static const char * const dvin_groups[] = {
854 "dvin_rgb", "dvin_vs", "dvin_hs", "dvin_clk", "dvin_de"
855};
856
857static const char * const enc_groups[] = {
858 "enc_0", "enc_1", "enc_2", "enc_3", "enc_4", "enc_5",
859 "enc_6", "enc_7", "enc_8", "enc_9", "enc_10", "enc_11",
860 "enc_12", "enc_13", "enc_14", "enc_15", "enc_16", "enc_17"
861};
862
863static const char * const vga_groups[] = {
864 "vga_vs", "vga_hs"
865};
866
867static const char * const hdmi_groups[] = {
868 "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec"
869};
870
871static const char * const spi_groups[] = {
872 "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0",
873 "spi_ss0_1", "spi_ss1_1", "spi_sclk_1", "spi_mosi_1",
874 "spi_miso_1", "spi_ss2_1"
875};
876
877static const char * const ethernet_groups[] = {
878 "eth_tx_clk_50m", "eth_tx_en", "eth_txd1",
879 "eth_txd0", "eth_rx_clk_in", "eth_rx_dv",
880 "eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc"
881};
882
883static const char * const i2c_a_groups[] = {
884 "i2c_sda_a0", "i2c_sck_a0", "i2c_sda_a1", "i2c_sck_a1",
885 "i2c_sda_a2", "i2c_sck_a2"
886};
887
888static const char * const i2c_b_groups[] = {
889 "i2c_sda_b", "i2c_sck_b"
890};
891
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]892static const char * const i2s_groups[] = {
893 "i2s_out_ch45", "i2s_out_ch23_pins", "i2s_out_ch01_pins",
894 "i2s_in_ch01_pins", "i2s_lr_clk_in_pins", "i2s_ao_clk_in_pins",
895 "i2s_am_clk_pins", "i2s_out_ch78_pins"
896};
897
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]898static const char * const sd_c_groups[] = {
899 "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c",
900 "sd_cmd_c", "sd_clk_c"
901};
902
903static const char * const sdxc_c_groups[] = {
904 "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c",
905 "sdxc_clk_c"
906};
907
908static const char * const nand_groups[] = {
909 "nand_io", "nand_io_ce0", "nand_io_ce1",
910 "nand_io_rb0", "nand_ale", "nand_cle",
911 "nand_wen_clk", "nand_ren_clk", "nand_dqs",
912 "nand_ce2", "nand_ce3"
913};
914
915static const char * const nor_groups[] = {
916 "nor_d", "nor_q", "nor_c", "nor_cs"
917};
918
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]919static const char * const pwm_a_groups[] = {
920 "pwm_a_y", "pwm_a_z0", "pwm_a_z7"
921};
922
923static const char * const pwm_b_groups[] = {
924 "pwm_b_x", "pwm_b_z"
925};
926
927static const char * const pwm_c_groups[] = {
928 "pwm_c_dv9", "pwm_c_dv29", "pwm_c_z"
929};
930
931static const char * const pwm_d_groups[] = {
932 "pwm_d"
933};
934
935static const char * const pwm_e_groups[] = {
936 "pwm_e"
937};
938
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]939static const char * const sd_b_groups[] = {
940 "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b",
941 "sd_d3_b", "sd_d2_b"
942};
943
944static const char * const sdxc_b_groups[] = {
945 "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b"
946};
947
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]948static const char * const spdif_groups[] = {
949 "spdif_in", "spdif_out"
950};
951
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]952static const char * const uart_ao_groups[] = {
953 "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a"
954};
955
956static const char * const remote_groups[] = {
Martin Blumenstingle70a3842017-05-06 18:57:50 +0200[diff] [blame]957 "remote_input", "remote_output_ao"
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]958};
959
960static const char * const i2c_slave_ao_groups[] = {
961 "i2c_slave_sck_ao", "i2c_slave_sda_ao"
962};
963
964static const char * const uart_ao_b_groups[] = {
965 "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1"
966};
967
968static const char * const i2c_mst_ao_groups[] = {
969 "i2c_mst_sck_ao", "i2c_mst_sda_ao"
970};
971
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]972static const char * const pwm_f_ao_groups[] = {
973 "pwm_f_ao"
974};
975
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]976static const char * const i2s_ao_groups[] = {
977 "i2s_am_clk_out_ao", "i2s_ao_clk_out_ao", "i2s_lr_clk_out_ao",
978 "i2s_out_ch01_ao"
979};
980
Martin Blumenstinglc21b4322017-05-06 18:57:51 +0200[diff] [blame]981static const char * const hdmi_cec_ao_groups[] = {
982 "hdmi_cec_ao"
983};
984
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]985static struct meson_pmx_func meson8_cbus_functions[] = {
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]986 FUNCTION(gpio),
987 FUNCTION(sd_a),
988 FUNCTION(sdxc_a),
989 FUNCTION(pcm_a),
990 FUNCTION(uart_a),
991 FUNCTION(uart_b),
992 FUNCTION(iso7816),
993 FUNCTION(i2c_d),
994 FUNCTION(xtal),
995 FUNCTION(uart_c),
996 FUNCTION(pcm_b),
997 FUNCTION(i2c_c),
998 FUNCTION(dvin),
999 FUNCTION(enc),
1000 FUNCTION(vga),
1001 FUNCTION(hdmi),
1002 FUNCTION(spi),
1003 FUNCTION(ethernet),
1004 FUNCTION(i2c_a),
1005 FUNCTION(i2c_b),
1006 FUNCTION(sd_c),
1007 FUNCTION(sdxc_c),
1008 FUNCTION(nand),
1009 FUNCTION(nor),
1010 FUNCTION(sd_b),
1011 FUNCTION(sdxc_b),
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]1012 FUNCTION(pwm_a),
1013 FUNCTION(pwm_b),
1014 FUNCTION(pwm_c),
1015 FUNCTION(pwm_d),
1016 FUNCTION(pwm_e),
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]1017 FUNCTION(i2s),
1018 FUNCTION(spdif),
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]1019};
1020
1021static struct meson_pmx_func meson8_aobus_functions[] = {
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]1022 FUNCTION(uart_ao),
1023 FUNCTION(remote),
1024 FUNCTION(i2c_slave_ao),
1025 FUNCTION(uart_ao_b),
1026 FUNCTION(i2c_mst_ao),
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200[diff] [blame]1027 FUNCTION(pwm_f_ao),
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200[diff] [blame]1028 FUNCTION(i2s_ao),
Martin Blumenstinglc21b4322017-05-06 18:57:51 +0200[diff] [blame]1029 FUNCTION(hdmi_cec_ao),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]1030};
1031
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]1032static struct meson_bank meson8_cbus_banks[] = {
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]1033 /* name first last irq pullen pull dir out in */
1034 BANK("X", GPIOX_0, GPIOX_21, 112, 133, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
1035 BANK("Y", GPIOY_0, GPIOY_16, 95, 111, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
1036 BANK("DV", GPIODV_0, GPIODV_29, 65, 94, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
1037 BANK("H", GPIOH_0, GPIOH_9, 29, 38, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
1038 BANK("Z", GPIOZ_0, GPIOZ_14, 14, 28, 1, 0, 1, 0, 3, 17, 4, 17, 5, 17),
1039 BANK("CARD", CARD_0, CARD_6, 58, 64, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
1040 BANK("BOOT", BOOT_0, BOOT_18, 39, 57, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]1041};
1042
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]1043static struct meson_bank meson8_aobus_banks[] = {
Jerome Brunet634e40b2017-09-20 15:39:20 +0200[diff] [blame]1044 /* name first last irq pullen pull dir out in */
1045 BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]1046};
1047
Jerome Brunet277d14e2017-10-12 14:40:25 +0200[diff] [blame]1048static struct meson_pinctrl_data meson8_cbus_pinctrl_data = {
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200[diff] [blame]1049 .name = "cbus-banks",
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]1050 .pins = meson8_cbus_pins,
1051 .groups = meson8_cbus_groups,
1052 .funcs = meson8_cbus_functions,
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200[diff] [blame]1053 .banks = meson8_cbus_banks,
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]1054 .num_pins = ARRAY_SIZE(meson8_cbus_pins),
1055 .num_groups = ARRAY_SIZE(meson8_cbus_groups),
1056 .num_funcs = ARRAY_SIZE(meson8_cbus_functions),
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200[diff] [blame]1057 .num_banks = ARRAY_SIZE(meson8_cbus_banks),
Jerome Brunetce385aa2017-10-12 14:40:26 +0200[diff] [blame]1058 .pmx_ops = &meson8_pmx_ops,
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]1059};
1060
Jerome Brunet277d14e2017-10-12 14:40:25 +0200[diff] [blame]1061static struct meson_pinctrl_data meson8_aobus_pinctrl_data = {
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200[diff] [blame]1062 .name = "ao-bank",
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]1063 .pins = meson8_aobus_pins,
1064 .groups = meson8_aobus_groups,
1065 .funcs = meson8_aobus_functions,
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200[diff] [blame]1066 .banks = meson8_aobus_banks,
Carlo Caione9dab1862016-03-01 23:04:34 +0100[diff] [blame]1067 .num_pins = ARRAY_SIZE(meson8_aobus_pins),
1068 .num_groups = ARRAY_SIZE(meson8_aobus_groups),
1069 .num_funcs = ARRAY_SIZE(meson8_aobus_functions),
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +0200[diff] [blame]1070 .num_banks = ARRAY_SIZE(meson8_aobus_banks),
Jerome Brunetce385aa2017-10-12 14:40:26 +0200[diff] [blame]1071 .pmx_ops = &meson8_pmx_ops,
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100[diff] [blame]1072};
Jerome Brunet277d14e2017-10-12 14:40:25 +0200[diff] [blame]1073
1074static const struct of_device_id meson8_pinctrl_dt_match[] = {
1075 {
1076 .compatible = "amlogic,meson8-cbus-pinctrl",
1077 .data = &meson8_cbus_pinctrl_data,
1078 },
1079 {
1080 .compatible = "amlogic,meson8-aobus-pinctrl",
1081 .data = &meson8_aobus_pinctrl_data,
1082 },
Martin Blumenstinglb0d46cb2018-04-22 12:53:29 +0200[diff] [blame^]1083 {
1084 .compatible = "amlogic,meson8m2-cbus-pinctrl",
1085 .data = &meson8_cbus_pinctrl_data,
1086 },
1087 {
1088 .compatible = "amlogic,meson8m2-aobus-pinctrl",
1089 .data = &meson8_aobus_pinctrl_data,
1090 },
Jerome Brunet277d14e2017-10-12 14:40:25 +0200[diff] [blame]1091 { },
1092};
1093
1094static struct platform_driver meson8_pinctrl_driver = {
1095 .probe = meson_pinctrl_probe,
1096 .driver = {
1097 .name = "meson8-pinctrl",
1098 .of_match_table = meson8_pinctrl_dt_match,
1099 },
1100};
1101builtin_platform_driver(meson8_pinctrl_driver);