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Beniamino Galvani6ac73092015-01-17 19:15:14 +01001/*
2 * Pin controller and GPIO driver for Amlogic Meson8.
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
12 */
13
14#include <dt-bindings/gpio/meson8-gpio.h>
15#include "pinctrl-meson.h"
16
Carlo Caione0cf6f3c2015-03-19 22:34:10 +010017#define AO_OFF 120
Beniamino Galvani6ac73092015-01-17 19:15:14 +010018
Carlo Caione9dab1862016-03-01 23:04:34 +010019static const struct pinctrl_pin_desc meson8_cbus_pins[] = {
Carlo Caione0cf6f3c2015-03-19 22:34:10 +010020 MESON_PIN(GPIOX_0, 0),
21 MESON_PIN(GPIOX_1, 0),
22 MESON_PIN(GPIOX_2, 0),
23 MESON_PIN(GPIOX_3, 0),
24 MESON_PIN(GPIOX_4, 0),
25 MESON_PIN(GPIOX_5, 0),
26 MESON_PIN(GPIOX_6, 0),
27 MESON_PIN(GPIOX_7, 0),
28 MESON_PIN(GPIOX_8, 0),
29 MESON_PIN(GPIOX_9, 0),
30 MESON_PIN(GPIOX_10, 0),
31 MESON_PIN(GPIOX_11, 0),
32 MESON_PIN(GPIOX_12, 0),
33 MESON_PIN(GPIOX_13, 0),
34 MESON_PIN(GPIOX_14, 0),
35 MESON_PIN(GPIOX_15, 0),
36 MESON_PIN(GPIOX_16, 0),
37 MESON_PIN(GPIOX_17, 0),
38 MESON_PIN(GPIOX_18, 0),
39 MESON_PIN(GPIOX_19, 0),
40 MESON_PIN(GPIOX_20, 0),
41 MESON_PIN(GPIOX_21, 0),
42 MESON_PIN(GPIOY_0, 0),
43 MESON_PIN(GPIOY_1, 0),
44 MESON_PIN(GPIOY_2, 0),
45 MESON_PIN(GPIOY_3, 0),
46 MESON_PIN(GPIOY_4, 0),
47 MESON_PIN(GPIOY_5, 0),
48 MESON_PIN(GPIOY_6, 0),
49 MESON_PIN(GPIOY_7, 0),
50 MESON_PIN(GPIOY_8, 0),
51 MESON_PIN(GPIOY_9, 0),
52 MESON_PIN(GPIOY_10, 0),
53 MESON_PIN(GPIOY_11, 0),
54 MESON_PIN(GPIOY_12, 0),
55 MESON_PIN(GPIOY_13, 0),
56 MESON_PIN(GPIOY_14, 0),
57 MESON_PIN(GPIOY_15, 0),
58 MESON_PIN(GPIOY_16, 0),
59 MESON_PIN(GPIODV_0, 0),
60 MESON_PIN(GPIODV_1, 0),
61 MESON_PIN(GPIODV_2, 0),
62 MESON_PIN(GPIODV_3, 0),
63 MESON_PIN(GPIODV_4, 0),
64 MESON_PIN(GPIODV_5, 0),
65 MESON_PIN(GPIODV_6, 0),
66 MESON_PIN(GPIODV_7, 0),
67 MESON_PIN(GPIODV_8, 0),
68 MESON_PIN(GPIODV_9, 0),
69 MESON_PIN(GPIODV_10, 0),
70 MESON_PIN(GPIODV_11, 0),
71 MESON_PIN(GPIODV_12, 0),
72 MESON_PIN(GPIODV_13, 0),
73 MESON_PIN(GPIODV_14, 0),
74 MESON_PIN(GPIODV_15, 0),
75 MESON_PIN(GPIODV_16, 0),
76 MESON_PIN(GPIODV_17, 0),
77 MESON_PIN(GPIODV_18, 0),
78 MESON_PIN(GPIODV_19, 0),
79 MESON_PIN(GPIODV_20, 0),
80 MESON_PIN(GPIODV_21, 0),
81 MESON_PIN(GPIODV_22, 0),
82 MESON_PIN(GPIODV_23, 0),
83 MESON_PIN(GPIODV_24, 0),
84 MESON_PIN(GPIODV_25, 0),
85 MESON_PIN(GPIODV_26, 0),
86 MESON_PIN(GPIODV_27, 0),
87 MESON_PIN(GPIODV_28, 0),
88 MESON_PIN(GPIODV_29, 0),
89 MESON_PIN(GPIOH_0, 0),
90 MESON_PIN(GPIOH_1, 0),
91 MESON_PIN(GPIOH_2, 0),
92 MESON_PIN(GPIOH_3, 0),
93 MESON_PIN(GPIOH_4, 0),
94 MESON_PIN(GPIOH_5, 0),
95 MESON_PIN(GPIOH_6, 0),
96 MESON_PIN(GPIOH_7, 0),
97 MESON_PIN(GPIOH_8, 0),
98 MESON_PIN(GPIOH_9, 0),
99 MESON_PIN(GPIOZ_0, 0),
100 MESON_PIN(GPIOZ_1, 0),
101 MESON_PIN(GPIOZ_2, 0),
102 MESON_PIN(GPIOZ_3, 0),
103 MESON_PIN(GPIOZ_4, 0),
104 MESON_PIN(GPIOZ_5, 0),
105 MESON_PIN(GPIOZ_6, 0),
106 MESON_PIN(GPIOZ_7, 0),
107 MESON_PIN(GPIOZ_8, 0),
108 MESON_PIN(GPIOZ_9, 0),
109 MESON_PIN(GPIOZ_10, 0),
110 MESON_PIN(GPIOZ_11, 0),
111 MESON_PIN(GPIOZ_12, 0),
112 MESON_PIN(GPIOZ_13, 0),
113 MESON_PIN(GPIOZ_14, 0),
114 MESON_PIN(CARD_0, 0),
115 MESON_PIN(CARD_1, 0),
116 MESON_PIN(CARD_2, 0),
117 MESON_PIN(CARD_3, 0),
118 MESON_PIN(CARD_4, 0),
119 MESON_PIN(CARD_5, 0),
120 MESON_PIN(CARD_6, 0),
121 MESON_PIN(BOOT_0, 0),
122 MESON_PIN(BOOT_1, 0),
123 MESON_PIN(BOOT_2, 0),
124 MESON_PIN(BOOT_3, 0),
125 MESON_PIN(BOOT_4, 0),
126 MESON_PIN(BOOT_5, 0),
127 MESON_PIN(BOOT_6, 0),
128 MESON_PIN(BOOT_7, 0),
129 MESON_PIN(BOOT_8, 0),
130 MESON_PIN(BOOT_9, 0),
131 MESON_PIN(BOOT_10, 0),
132 MESON_PIN(BOOT_11, 0),
133 MESON_PIN(BOOT_12, 0),
134 MESON_PIN(BOOT_13, 0),
135 MESON_PIN(BOOT_14, 0),
136 MESON_PIN(BOOT_15, 0),
137 MESON_PIN(BOOT_16, 0),
138 MESON_PIN(BOOT_17, 0),
139 MESON_PIN(BOOT_18, 0),
Carlo Caione9dab1862016-03-01 23:04:34 +0100140};
141
142static const struct pinctrl_pin_desc meson8_aobus_pins[] = {
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100143 MESON_PIN(GPIOAO_0, AO_OFF),
144 MESON_PIN(GPIOAO_1, AO_OFF),
145 MESON_PIN(GPIOAO_2, AO_OFF),
146 MESON_PIN(GPIOAO_3, AO_OFF),
147 MESON_PIN(GPIOAO_4, AO_OFF),
148 MESON_PIN(GPIOAO_5, AO_OFF),
149 MESON_PIN(GPIOAO_6, AO_OFF),
150 MESON_PIN(GPIOAO_7, AO_OFF),
151 MESON_PIN(GPIOAO_8, AO_OFF),
152 MESON_PIN(GPIOAO_9, AO_OFF),
153 MESON_PIN(GPIOAO_10, AO_OFF),
154 MESON_PIN(GPIOAO_11, AO_OFF),
155 MESON_PIN(GPIOAO_12, AO_OFF),
156 MESON_PIN(GPIOAO_13, AO_OFF),
157 MESON_PIN(GPIO_BSD_EN, AO_OFF),
158 MESON_PIN(GPIO_TEST_N, AO_OFF),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100159};
160
161/* bank X */
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100162static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, 0) };
163static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, 0) };
164static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, 0) };
165static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, 0) };
166static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, 0) };
167static const unsigned int sd_cmd_a_pins[] = { PIN(GPIOX_9, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100168
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100169static const unsigned int sdxc_d0_a_pins[] = { PIN(GPIOX_0, 0) };
170static const unsigned int sdxc_d13_a_pins[] = { PIN(GPIOX_1, 0), PIN(GPIOX_2, 0),
171 PIN(GPIOX_3, 0) };
172static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, 0), PIN(GPIOX_5, 0),
173 PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) };
174static const unsigned int sdxc_clk_a_pins[] = { PIN(GPIOX_8, 0) };
175static const unsigned int sdxc_cmd_a_pins[] = { PIN(GPIOX_9, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100176
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100177static const unsigned int pcm_out_a_pins[] = { PIN(GPIOX_4, 0) };
178static const unsigned int pcm_in_a_pins[] = { PIN(GPIOX_5, 0) };
179static const unsigned int pcm_fs_a_pins[] = { PIN(GPIOX_6, 0) };
180static const unsigned int pcm_clk_a_pins[] = { PIN(GPIOX_7, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100181
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100182static const unsigned int uart_tx_a0_pins[] = { PIN(GPIOX_4, 0) };
183static const unsigned int uart_rx_a0_pins[] = { PIN(GPIOX_5, 0) };
184static const unsigned int uart_cts_a0_pins[] = { PIN(GPIOX_6, 0) };
185static const unsigned int uart_rts_a0_pins[] = { PIN(GPIOX_7, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100186
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100187static const unsigned int uart_tx_a1_pins[] = { PIN(GPIOX_12, 0) };
188static const unsigned int uart_rx_a1_pins[] = { PIN(GPIOX_13, 0) };
189static const unsigned int uart_cts_a1_pins[] = { PIN(GPIOX_14, 0) };
190static const unsigned int uart_rts_a1_pins[] = { PIN(GPIOX_15, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100191
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100192static const unsigned int uart_tx_b0_pins[] = { PIN(GPIOX_16, 0) };
193static const unsigned int uart_rx_b0_pins[] = { PIN(GPIOX_17, 0) };
194static const unsigned int uart_cts_b0_pins[] = { PIN(GPIOX_18, 0) };
195static const unsigned int uart_rts_b0_pins[] = { PIN(GPIOX_19, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100196
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100197static const unsigned int iso7816_det_pins[] = { PIN(GPIOX_16, 0) };
198static const unsigned int iso7816_reset_pins[] = { PIN(GPIOX_17, 0) };
199static const unsigned int iso7816_clk_pins[] = { PIN(GPIOX_18, 0) };
200static const unsigned int iso7816_data_pins[] = { PIN(GPIOX_19, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100201
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100202static const unsigned int i2c_sda_d0_pins[] = { PIN(GPIOX_16, 0) };
203static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100204
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100205static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) };
206static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100207
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200208static const unsigned int pwm_e_pins[] = { PIN(GPIOX_10, 0) };
209static const unsigned int pwm_b_x_pins[] = { PIN(GPIOX_11, 0) };
210
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100211/* bank Y */
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100212static const unsigned int uart_tx_c_pins[] = { PIN(GPIOY_0, 0) };
213static const unsigned int uart_rx_c_pins[] = { PIN(GPIOY_1, 0) };
214static const unsigned int uart_cts_c_pins[] = { PIN(GPIOY_2, 0) };
215static const unsigned int uart_rts_c_pins[] = { PIN(GPIOY_3, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100216
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100217static const unsigned int pcm_out_b_pins[] = { PIN(GPIOY_4, 0) };
218static const unsigned int pcm_in_b_pins[] = { PIN(GPIOY_5, 0) };
219static const unsigned int pcm_fs_b_pins[] = { PIN(GPIOY_6, 0) };
220static const unsigned int pcm_clk_b_pins[] = { PIN(GPIOY_7, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100221
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100222static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIOY_0, 0) };
223static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIOY_1, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100224
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200225static const unsigned int pwm_a_y_pins[] = { PIN(GPIOY_16, 0) };
226
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200227static const unsigned int i2s_out_ch45_pins[] = { PIN(GPIOY_0, 0) };
228static const unsigned int i2s_out_ch23_pins[] = { PIN(GPIOY_1, 0) };
229static const unsigned int i2s_out_ch01_pins[] = { PIN(GPIOY_4, 0) };
230static const unsigned int i2s_in_ch01_pins[] = { PIN(GPIOY_5, 0) };
231static const unsigned int i2s_lr_clk_in_pins[] = { PIN(GPIOY_6, 0) };
232static const unsigned int i2s_ao_clk_in_pins[] = { PIN(GPIOY_7, 0) };
233static const unsigned int i2s_am_clk_pins[] = { PIN(GPIOY_8, 0) };
234static const unsigned int i2s_out_ch78_pins[] = { PIN(GPIOY_9, 0) };
235
236static const unsigned int spdif_in_pins[] = { PIN(GPIOY_2, 0) };
237static const unsigned int spdif_out_pins[] = { PIN(GPIOY_3, 0) };
238
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100239/* bank DV */
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100240static const unsigned int dvin_rgb_pins[] = { PIN(GPIODV_0, 0), PIN(GPIODV_1, 0),
241 PIN(GPIODV_2, 0), PIN(GPIODV_3, 0),
242 PIN(GPIODV_4, 0), PIN(GPIODV_5, 0),
243 PIN(GPIODV_6, 0), PIN(GPIODV_7, 0),
244 PIN(GPIODV_8, 0), PIN(GPIODV_9, 0),
245 PIN(GPIODV_10, 0), PIN(GPIODV_11, 0),
246 PIN(GPIODV_12, 0), PIN(GPIODV_13, 0),
247 PIN(GPIODV_14, 0), PIN(GPIODV_15, 0),
248 PIN(GPIODV_16, 0), PIN(GPIODV_17, 0),
249 PIN(GPIODV_18, 0), PIN(GPIODV_19, 0),
250 PIN(GPIODV_20, 0), PIN(GPIODV_21, 0),
251 PIN(GPIODV_22, 0), PIN(GPIODV_23, 0) };
252static const unsigned int dvin_vs_pins[] = { PIN(GPIODV_24, 0) };
253static const unsigned int dvin_hs_pins[] = { PIN(GPIODV_25, 0) };
254static const unsigned int dvin_clk_pins[] = { PIN(GPIODV_26, 0) };
255static const unsigned int dvin_de_pins[] = { PIN(GPIODV_27, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100256
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100257static const unsigned int enc_0_pins[] = { PIN(GPIODV_0, 0) };
258static const unsigned int enc_1_pins[] = { PIN(GPIODV_1, 0) };
259static const unsigned int enc_2_pins[] = { PIN(GPIODV_2, 0) };
260static const unsigned int enc_3_pins[] = { PIN(GPIODV_3, 0) };
261static const unsigned int enc_4_pins[] = { PIN(GPIODV_4, 0) };
262static const unsigned int enc_5_pins[] = { PIN(GPIODV_5, 0) };
263static const unsigned int enc_6_pins[] = { PIN(GPIODV_6, 0) };
264static const unsigned int enc_7_pins[] = { PIN(GPIODV_7, 0) };
265static const unsigned int enc_8_pins[] = { PIN(GPIODV_8, 0) };
266static const unsigned int enc_9_pins[] = { PIN(GPIODV_9, 0) };
267static const unsigned int enc_10_pins[] = { PIN(GPIODV_10, 0) };
268static const unsigned int enc_11_pins[] = { PIN(GPIODV_11, 0) };
269static const unsigned int enc_12_pins[] = { PIN(GPIODV_12, 0) };
270static const unsigned int enc_13_pins[] = { PIN(GPIODV_13, 0) };
271static const unsigned int enc_14_pins[] = { PIN(GPIODV_14, 0) };
272static const unsigned int enc_15_pins[] = { PIN(GPIODV_15, 0) };
273static const unsigned int enc_16_pins[] = { PIN(GPIODV_16, 0) };
274static const unsigned int enc_17_pins[] = { PIN(GPIODV_17, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100275
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100276static const unsigned int uart_tx_b1_pins[] = { PIN(GPIODV_24, 0) };
277static const unsigned int uart_rx_b1_pins[] = { PIN(GPIODV_25, 0) };
278static const unsigned int uart_cts_b1_pins[] = { PIN(GPIODV_26, 0) };
279static const unsigned int uart_rts_b1_pins[] = { PIN(GPIODV_27, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100280
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100281static const unsigned int vga_vs_pins[] = { PIN(GPIODV_24, 0) };
282static const unsigned int vga_hs_pins[] = { PIN(GPIODV_25, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100283
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200284static const unsigned int pwm_c_dv9_pins[] = { PIN(GPIODV_9, 0) };
285static const unsigned int pwm_c_dv29_pins[] = { PIN(GPIODV_29, 0) };
286static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, 0) };
287
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100288/* bank H */
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100289static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) };
290static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) };
291static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, 0) };
292static const unsigned int hdmi_cec_pins[] = { PIN(GPIOH_3, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100293
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100294static const unsigned int spi_ss0_0_pins[] = { PIN(GPIOH_3, 0) };
295static const unsigned int spi_miso_0_pins[] = { PIN(GPIOH_4, 0) };
296static const unsigned int spi_mosi_0_pins[] = { PIN(GPIOH_5, 0) };
297static const unsigned int spi_sclk_0_pins[] = { PIN(GPIOH_6, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100298
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100299static const unsigned int i2c_sda_d1_pins[] = { PIN(GPIOH_7, 0) };
300static const unsigned int i2c_sck_d1_pins[] = { PIN(GPIOH_8, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100301
302/* bank Z */
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100303static const unsigned int spi_ss0_1_pins[] = { PIN(GPIOZ_9, 0) };
304static const unsigned int spi_ss1_1_pins[] = { PIN(GPIOZ_10, 0) };
305static const unsigned int spi_sclk_1_pins[] = { PIN(GPIOZ_11, 0) };
306static const unsigned int spi_mosi_1_pins[] = { PIN(GPIOZ_12, 0) };
307static const unsigned int spi_miso_1_pins[] = { PIN(GPIOZ_13, 0) };
308static const unsigned int spi_ss2_1_pins[] = { PIN(GPIOZ_14, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100309
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100310static const unsigned int eth_tx_clk_50m_pins[] = { PIN(GPIOZ_4, 0) };
311static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_5, 0) };
312static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_6, 0) };
313static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_7, 0) };
314static const unsigned int eth_rx_clk_in_pins[] = { PIN(GPIOZ_8, 0) };
315static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_9, 0) };
316static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_10, 0) };
317static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_11, 0) };
318static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_12, 0) };
319static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_13, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100320
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100321static const unsigned int i2c_sda_a0_pins[] = { PIN(GPIOZ_0, 0) };
322static const unsigned int i2c_sck_a0_pins[] = { PIN(GPIOZ_1, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100323
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100324static const unsigned int i2c_sda_b_pins[] = { PIN(GPIOZ_2, 0) };
325static const unsigned int i2c_sck_b_pins[] = { PIN(GPIOZ_3, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100326
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100327static const unsigned int i2c_sda_c1_pins[] = { PIN(GPIOZ_4, 0) };
328static const unsigned int i2c_sck_c1_pins[] = { PIN(GPIOZ_5, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100329
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100330static const unsigned int i2c_sda_a1_pins[] = { PIN(GPIOZ_0, 0) };
331static const unsigned int i2c_sck_a1_pins[] = { PIN(GPIOZ_1, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100332
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100333static const unsigned int i2c_sda_a2_pins[] = { PIN(GPIOZ_0, 0) };
334static const unsigned int i2c_sck_a2_pins[] = { PIN(GPIOZ_1, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100335
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200336static const unsigned int pwm_a_z0_pins[] = { PIN(GPIOZ_0, 0) };
337static const unsigned int pwm_a_z7_pins[] = { PIN(GPIOZ_7, 0) };
338static const unsigned int pwm_b_z_pins[] = { PIN(GPIOZ_1, 0) };
339static const unsigned int pwm_c_z_pins[] = { PIN(GPIOZ_8, 0) };
340
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100341/* bank BOOT */
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100342static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) };
343static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) };
344static const unsigned int sd_d2_c_pins[] = { PIN(BOOT_2, 0) };
345static const unsigned int sd_d3_c_pins[] = { PIN(BOOT_3, 0) };
346static const unsigned int sd_cmd_c_pins[] = { PIN(BOOT_16, 0) };
347static const unsigned int sd_clk_c_pins[] = { PIN(BOOT_17, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100348
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100349static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)};
350static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), PIN(BOOT_2, 0),
351 PIN(BOOT_3, 0) };
352static const unsigned int sdxc_d47_c_pins[] = { PIN(BOOT_4, 0), PIN(BOOT_5, 0),
353 PIN(BOOT_6, 0), PIN(BOOT_7, 0) };
354static const unsigned int sdxc_cmd_c_pins[] = { PIN(BOOT_16, 0) };
355static const unsigned int sdxc_clk_c_pins[] = { PIN(BOOT_17, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100356
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100357static const unsigned int nand_io_pins[] = { PIN(BOOT_0, 0), PIN(BOOT_1, 0),
358 PIN(BOOT_2, 0), PIN(BOOT_3, 0),
359 PIN(BOOT_4, 0), PIN(BOOT_5, 0),
360 PIN(BOOT_6, 0), PIN(BOOT_7, 0) };
361static const unsigned int nand_io_ce0_pins[] = { PIN(BOOT_8, 0) };
362static const unsigned int nand_io_ce1_pins[] = { PIN(BOOT_9, 0) };
363static const unsigned int nand_io_rb0_pins[] = { PIN(BOOT_10, 0) };
364static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, 0) };
365static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) };
366static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) };
367static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) };
368static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, 0) };
369static const unsigned int nand_ce2_pins[] = { PIN(BOOT_16, 0) };
370static const unsigned int nand_ce3_pins[] = { PIN(BOOT_17, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100371
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100372static const unsigned int nor_d_pins[] = { PIN(BOOT_11, 0) };
373static const unsigned int nor_q_pins[] = { PIN(BOOT_12, 0) };
374static const unsigned int nor_c_pins[] = { PIN(BOOT_13, 0) };
375static const unsigned int nor_cs_pins[] = { PIN(BOOT_18, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100376
377/* bank CARD */
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100378static const unsigned int sd_d1_b_pins[] = { PIN(CARD_0, 0) };
379static const unsigned int sd_d0_b_pins[] = { PIN(CARD_1, 0) };
380static const unsigned int sd_clk_b_pins[] = { PIN(CARD_2, 0) };
381static const unsigned int sd_cmd_b_pins[] = { PIN(CARD_3, 0) };
382static const unsigned int sd_d3_b_pins[] = { PIN(CARD_4, 0) };
383static const unsigned int sd_d2_b_pins[] = { PIN(CARD_5, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100384
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100385static const unsigned int sdxc_d13_b_pins[] = { PIN(CARD_0, 0), PIN(CARD_4, 0),
386 PIN(CARD_5, 0) };
387static const unsigned int sdxc_d0_b_pins[] = { PIN(CARD_1, 0) };
388static const unsigned int sdxc_clk_b_pins[] = { PIN(CARD_2, 0) };
389static const unsigned int sdxc_cmd_b_pins[] = { PIN(CARD_3, 0) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100390
391/* bank AO */
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100392static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, AO_OFF) };
393static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, AO_OFF) };
394static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, AO_OFF) };
395static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100396
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100397static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100398
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100399static const unsigned int i2c_slave_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
400static const unsigned int i2c_slave_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100401
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100402static const unsigned int uart_tx_ao_b0_pins[] = { PIN(GPIOAO_0, AO_OFF) };
403static const unsigned int uart_rx_ao_b0_pins[] = { PIN(GPIOAO_1, AO_OFF) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100404
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100405static const unsigned int uart_tx_ao_b1_pins[] = { PIN(GPIOAO_4, AO_OFF) };
406static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100407
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100408static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
409static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100410
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200411static const unsigned int pwm_f_ao_pins[] = { PIN(GPIO_TEST_N, AO_OFF) };
412
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200413static const unsigned int i2s_am_clk_out_ao_pins[] = { PIN(GPIOAO_8, AO_OFF) };
414static const unsigned int i2s_ao_clk_out_ao_pins[] = { PIN(GPIOAO_9, AO_OFF) };
415static const unsigned int i2s_lr_clk_out_ao_pins[] = { PIN(GPIOAO_10, AO_OFF) };
416static const unsigned int i2s_out_ch01_ao_pins[] = { PIN(GPIOAO_11, AO_OFF) };
417
Carlo Caione9dab1862016-03-01 23:04:34 +0100418static struct meson_pmx_group meson8_cbus_groups[] = {
Carlo Caione0cf6f3c2015-03-19 22:34:10 +0100419 GPIO_GROUP(GPIOX_0, 0),
420 GPIO_GROUP(GPIOX_1, 0),
421 GPIO_GROUP(GPIOX_2, 0),
422 GPIO_GROUP(GPIOX_3, 0),
423 GPIO_GROUP(GPIOX_4, 0),
424 GPIO_GROUP(GPIOX_5, 0),
425 GPIO_GROUP(GPIOX_6, 0),
426 GPIO_GROUP(GPIOX_7, 0),
427 GPIO_GROUP(GPIOX_8, 0),
428 GPIO_GROUP(GPIOX_9, 0),
429 GPIO_GROUP(GPIOX_10, 0),
430 GPIO_GROUP(GPIOX_11, 0),
431 GPIO_GROUP(GPIOX_12, 0),
432 GPIO_GROUP(GPIOX_13, 0),
433 GPIO_GROUP(GPIOX_14, 0),
434 GPIO_GROUP(GPIOX_15, 0),
435 GPIO_GROUP(GPIOX_16, 0),
436 GPIO_GROUP(GPIOX_17, 0),
437 GPIO_GROUP(GPIOX_18, 0),
438 GPIO_GROUP(GPIOX_19, 0),
439 GPIO_GROUP(GPIOX_20, 0),
440 GPIO_GROUP(GPIOX_21, 0),
441 GPIO_GROUP(GPIOY_0, 0),
442 GPIO_GROUP(GPIOY_1, 0),
443 GPIO_GROUP(GPIOY_2, 0),
444 GPIO_GROUP(GPIOY_3, 0),
445 GPIO_GROUP(GPIOY_4, 0),
446 GPIO_GROUP(GPIOY_5, 0),
447 GPIO_GROUP(GPIOY_6, 0),
448 GPIO_GROUP(GPIOY_7, 0),
449 GPIO_GROUP(GPIOY_8, 0),
450 GPIO_GROUP(GPIOY_9, 0),
451 GPIO_GROUP(GPIOY_10, 0),
452 GPIO_GROUP(GPIOY_11, 0),
453 GPIO_GROUP(GPIOY_12, 0),
454 GPIO_GROUP(GPIOY_13, 0),
455 GPIO_GROUP(GPIOY_14, 0),
456 GPIO_GROUP(GPIOY_15, 0),
457 GPIO_GROUP(GPIOY_16, 0),
458 GPIO_GROUP(GPIODV_0, 0),
459 GPIO_GROUP(GPIODV_1, 0),
460 GPIO_GROUP(GPIODV_2, 0),
461 GPIO_GROUP(GPIODV_3, 0),
462 GPIO_GROUP(GPIODV_4, 0),
463 GPIO_GROUP(GPIODV_5, 0),
464 GPIO_GROUP(GPIODV_6, 0),
465 GPIO_GROUP(GPIODV_7, 0),
466 GPIO_GROUP(GPIODV_8, 0),
467 GPIO_GROUP(GPIODV_9, 0),
468 GPIO_GROUP(GPIODV_10, 0),
469 GPIO_GROUP(GPIODV_11, 0),
470 GPIO_GROUP(GPIODV_12, 0),
471 GPIO_GROUP(GPIODV_13, 0),
472 GPIO_GROUP(GPIODV_14, 0),
473 GPIO_GROUP(GPIODV_15, 0),
474 GPIO_GROUP(GPIODV_16, 0),
475 GPIO_GROUP(GPIODV_17, 0),
476 GPIO_GROUP(GPIODV_18, 0),
477 GPIO_GROUP(GPIODV_19, 0),
478 GPIO_GROUP(GPIODV_20, 0),
479 GPIO_GROUP(GPIODV_21, 0),
480 GPIO_GROUP(GPIODV_22, 0),
481 GPIO_GROUP(GPIODV_23, 0),
482 GPIO_GROUP(GPIODV_24, 0),
483 GPIO_GROUP(GPIODV_25, 0),
484 GPIO_GROUP(GPIODV_26, 0),
485 GPIO_GROUP(GPIODV_27, 0),
486 GPIO_GROUP(GPIODV_28, 0),
487 GPIO_GROUP(GPIODV_29, 0),
488 GPIO_GROUP(GPIOH_0, 0),
489 GPIO_GROUP(GPIOH_1, 0),
490 GPIO_GROUP(GPIOH_2, 0),
491 GPIO_GROUP(GPIOH_3, 0),
492 GPIO_GROUP(GPIOH_4, 0),
493 GPIO_GROUP(GPIOH_5, 0),
494 GPIO_GROUP(GPIOH_6, 0),
495 GPIO_GROUP(GPIOH_7, 0),
496 GPIO_GROUP(GPIOH_8, 0),
497 GPIO_GROUP(GPIOH_9, 0),
498 GPIO_GROUP(GPIOZ_0, 0),
499 GPIO_GROUP(GPIOZ_1, 0),
500 GPIO_GROUP(GPIOZ_2, 0),
501 GPIO_GROUP(GPIOZ_3, 0),
502 GPIO_GROUP(GPIOZ_4, 0),
503 GPIO_GROUP(GPIOZ_5, 0),
504 GPIO_GROUP(GPIOZ_6, 0),
505 GPIO_GROUP(GPIOZ_7, 0),
506 GPIO_GROUP(GPIOZ_8, 0),
507 GPIO_GROUP(GPIOZ_9, 0),
508 GPIO_GROUP(GPIOZ_10, 0),
509 GPIO_GROUP(GPIOZ_11, 0),
510 GPIO_GROUP(GPIOZ_12, 0),
511 GPIO_GROUP(GPIOZ_13, 0),
512 GPIO_GROUP(GPIOZ_14, 0),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100513
514 /* bank X */
515 GROUP(sd_d0_a, 8, 5),
516 GROUP(sd_d1_a, 8, 4),
517 GROUP(sd_d2_a, 8, 3),
518 GROUP(sd_d3_a, 8, 2),
519 GROUP(sd_clk_a, 8, 1),
520 GROUP(sd_cmd_a, 8, 0),
521
522 GROUP(sdxc_d0_a, 5, 14),
523 GROUP(sdxc_d13_a, 5, 13),
524 GROUP(sdxc_d47_a, 5, 12),
525 GROUP(sdxc_clk_a, 5, 11),
526 GROUP(sdxc_cmd_a, 5, 10),
527
528 GROUP(pcm_out_a, 3, 30),
529 GROUP(pcm_in_a, 3, 29),
530 GROUP(pcm_fs_a, 3, 28),
531 GROUP(pcm_clk_a, 3, 27),
532
533 GROUP(uart_tx_a0, 4, 17),
534 GROUP(uart_rx_a0, 4, 16),
535 GROUP(uart_cts_a0, 4, 15),
536 GROUP(uart_rts_a0, 4, 14),
537
538 GROUP(uart_tx_a1, 4, 13),
539 GROUP(uart_rx_a1, 4, 12),
540 GROUP(uart_cts_a1, 4, 11),
541 GROUP(uart_rts_a1, 4, 10),
542
543 GROUP(uart_tx_b0, 4, 9),
544 GROUP(uart_rx_b0, 4, 8),
545 GROUP(uart_cts_b0, 4, 7),
546 GROUP(uart_rts_b0, 4, 6),
547
548 GROUP(iso7816_det, 4, 21),
549 GROUP(iso7816_reset, 4, 20),
550 GROUP(iso7816_clk, 4, 19),
551 GROUP(iso7816_data, 4, 18),
552
553 GROUP(i2c_sda_d0, 4, 5),
554 GROUP(i2c_sck_d0, 4, 4),
555
556 GROUP(xtal_32k_out, 3, 22),
557 GROUP(xtal_24m_out, 3, 23),
558
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200559 GROUP(pwm_e, 9, 19),
560 GROUP(pwm_b_x, 2, 3),
561
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100562 /* bank Y */
563 GROUP(uart_tx_c, 1, 19),
564 GROUP(uart_rx_c, 1, 18),
565 GROUP(uart_cts_c, 1, 17),
566 GROUP(uart_rts_c, 1, 16),
567
568 GROUP(pcm_out_b, 4, 25),
569 GROUP(pcm_in_b, 4, 24),
570 GROUP(pcm_fs_b, 4, 23),
571 GROUP(pcm_clk_b, 4, 22),
572
573 GROUP(i2c_sda_c0, 1, 15),
574 GROUP(i2c_sck_c0, 1, 14),
575
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200576 GROUP(pwm_a_y, 9, 14),
577
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200578 GROUP(i2s_out_ch45, 1, 10),
579 GROUP(i2s_out_ch23, 1, 19),
580 GROUP(i2s_out_ch01, 1, 6),
581 GROUP(i2s_in_ch01, 1, 5),
582 GROUP(i2s_lr_clk_in, 1, 4),
583 GROUP(i2s_ao_clk_in, 1, 2),
584 GROUP(i2s_am_clk, 1, 0),
585 GROUP(i2s_out_ch78, 1, 11),
586
587 GROUP(spdif_in, 1, 8),
588 GROUP(spdif_out, 1, 7),
589
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100590 /* bank DV */
591 GROUP(dvin_rgb, 0, 6),
592 GROUP(dvin_vs, 0, 9),
593 GROUP(dvin_hs, 0, 8),
594 GROUP(dvin_clk, 0, 7),
595 GROUP(dvin_de, 0, 10),
596
597 GROUP(enc_0, 7, 0),
598 GROUP(enc_1, 7, 1),
599 GROUP(enc_2, 7, 2),
600 GROUP(enc_3, 7, 3),
601 GROUP(enc_4, 7, 4),
602 GROUP(enc_5, 7, 5),
603 GROUP(enc_6, 7, 6),
604 GROUP(enc_7, 7, 7),
605 GROUP(enc_8, 7, 8),
606 GROUP(enc_9, 7, 9),
607 GROUP(enc_10, 7, 10),
608 GROUP(enc_11, 7, 11),
609 GROUP(enc_12, 7, 12),
610 GROUP(enc_13, 7, 13),
611 GROUP(enc_14, 7, 14),
612 GROUP(enc_15, 7, 15),
613 GROUP(enc_16, 7, 16),
614 GROUP(enc_17, 7, 17),
615
616 GROUP(uart_tx_b1, 6, 23),
617 GROUP(uart_rx_b1, 6, 22),
618 GROUP(uart_cts_b1, 6, 21),
619 GROUP(uart_rts_b1, 6, 20),
620
621 GROUP(vga_vs, 0, 21),
622 GROUP(vga_hs, 0, 20),
623
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200624 GROUP(pwm_c_dv9, 3, 24),
625 GROUP(pwm_c_dv29, 3, 25),
626 GROUP(pwm_d, 3, 26),
627
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100628 /* bank H */
629 GROUP(hdmi_hpd, 1, 26),
630 GROUP(hdmi_sda, 1, 25),
631 GROUP(hdmi_scl, 1, 24),
632 GROUP(hdmi_cec, 1, 23),
633
634 GROUP(spi_ss0_0, 9, 13),
635 GROUP(spi_miso_0, 9, 12),
636 GROUP(spi_mosi_0, 9, 11),
637 GROUP(spi_sclk_0, 9, 10),
638
639 GROUP(i2c_sda_d1, 4, 3),
640 GROUP(i2c_sck_d1, 4, 2),
641
642 /* bank Z */
643 GROUP(spi_ss0_1, 8, 16),
644 GROUP(spi_ss1_1, 8, 12),
645 GROUP(spi_sclk_1, 8, 15),
646 GROUP(spi_mosi_1, 8, 14),
647 GROUP(spi_miso_1, 8, 13),
648 GROUP(spi_ss2_1, 8, 17),
649
650 GROUP(eth_tx_clk_50m, 6, 15),
651 GROUP(eth_tx_en, 6, 14),
652 GROUP(eth_txd1, 6, 13),
653 GROUP(eth_txd0, 6, 12),
654 GROUP(eth_rx_clk_in, 6, 10),
655 GROUP(eth_rx_dv, 6, 11),
656 GROUP(eth_rxd1, 6, 8),
657 GROUP(eth_rxd0, 6, 7),
658 GROUP(eth_mdio, 6, 6),
659 GROUP(eth_mdc, 6, 5),
660
661 GROUP(i2c_sda_a0, 5, 31),
662 GROUP(i2c_sck_a0, 5, 30),
663
664 GROUP(i2c_sda_b, 5, 27),
665 GROUP(i2c_sck_b, 5, 26),
666
667 GROUP(i2c_sda_c1, 5, 25),
668 GROUP(i2c_sck_c1, 5, 24),
669
670 GROUP(i2c_sda_a1, 5, 9),
671 GROUP(i2c_sck_a1, 5, 8),
672
673 GROUP(i2c_sda_a2, 5, 7),
674 GROUP(i2c_sck_a2, 5, 6),
675
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200676 GROUP(pwm_a_z0, 9, 16),
677 GROUP(pwm_a_z7, 2, 0),
678 GROUP(pwm_b_z, 9, 15),
679 GROUP(pwm_c_z, 2, 1),
680
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100681 /* bank BOOT */
682 GROUP(sd_d0_c, 6, 29),
683 GROUP(sd_d1_c, 6, 28),
684 GROUP(sd_d2_c, 6, 27),
685 GROUP(sd_d3_c, 6, 26),
686 GROUP(sd_cmd_c, 6, 25),
687 GROUP(sd_clk_c, 6, 24),
688
689 GROUP(sdxc_d0_c, 4, 30),
690 GROUP(sdxc_d13_c, 4, 29),
691 GROUP(sdxc_d47_c, 4, 28),
692 GROUP(sdxc_cmd_c, 4, 27),
693 GROUP(sdxc_clk_c, 4, 26),
694
695 GROUP(nand_io, 2, 26),
696 GROUP(nand_io_ce0, 2, 25),
697 GROUP(nand_io_ce1, 2, 24),
698 GROUP(nand_io_rb0, 2, 17),
699 GROUP(nand_ale, 2, 21),
700 GROUP(nand_cle, 2, 20),
701 GROUP(nand_wen_clk, 2, 19),
702 GROUP(nand_ren_clk, 2, 18),
703 GROUP(nand_dqs, 2, 27),
704 GROUP(nand_ce2, 2, 23),
705 GROUP(nand_ce3, 2, 22),
706
707 GROUP(nor_d, 5, 1),
708 GROUP(nor_q, 5, 3),
709 GROUP(nor_c, 5, 2),
710 GROUP(nor_cs, 5, 0),
711
712 /* bank CARD */
713 GROUP(sd_d1_b, 2, 14),
714 GROUP(sd_d0_b, 2, 15),
715 GROUP(sd_clk_b, 2, 11),
716 GROUP(sd_cmd_b, 2, 10),
717 GROUP(sd_d3_b, 2, 12),
718 GROUP(sd_d2_b, 2, 13),
719
720 GROUP(sdxc_d13_b, 2, 6),
721 GROUP(sdxc_d0_b, 2, 7),
722 GROUP(sdxc_clk_b, 2, 5),
723 GROUP(sdxc_cmd_b, 2, 4),
Carlo Caione9dab1862016-03-01 23:04:34 +0100724};
725
726static struct meson_pmx_group meson8_aobus_groups[] = {
727 GPIO_GROUP(GPIOAO_0, AO_OFF),
728 GPIO_GROUP(GPIOAO_1, AO_OFF),
729 GPIO_GROUP(GPIOAO_2, AO_OFF),
730 GPIO_GROUP(GPIOAO_3, AO_OFF),
731 GPIO_GROUP(GPIOAO_4, AO_OFF),
732 GPIO_GROUP(GPIOAO_5, AO_OFF),
733 GPIO_GROUP(GPIOAO_6, AO_OFF),
734 GPIO_GROUP(GPIOAO_7, AO_OFF),
735 GPIO_GROUP(GPIOAO_8, AO_OFF),
736 GPIO_GROUP(GPIOAO_9, AO_OFF),
737 GPIO_GROUP(GPIOAO_10, AO_OFF),
738 GPIO_GROUP(GPIOAO_11, AO_OFF),
739 GPIO_GROUP(GPIOAO_12, AO_OFF),
740 GPIO_GROUP(GPIOAO_13, AO_OFF),
741 GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
742 GPIO_GROUP(GPIO_TEST_N, AO_OFF),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100743
744 /* bank AO */
Carlo Caione9dab1862016-03-01 23:04:34 +0100745 GROUP(uart_tx_ao_a, 0, 12),
746 GROUP(uart_rx_ao_a, 0, 11),
747 GROUP(uart_cts_ao_a, 0, 10),
748 GROUP(uart_rts_ao_a, 0, 9),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100749
Carlo Caione9dab1862016-03-01 23:04:34 +0100750 GROUP(remote_input, 0, 0),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100751
Carlo Caione9dab1862016-03-01 23:04:34 +0100752 GROUP(i2c_slave_sck_ao, 0, 2),
753 GROUP(i2c_slave_sda_ao, 0, 1),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100754
Carlo Caione9dab1862016-03-01 23:04:34 +0100755 GROUP(uart_tx_ao_b0, 0, 26),
756 GROUP(uart_rx_ao_b0, 0, 25),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100757
Carlo Caione9dab1862016-03-01 23:04:34 +0100758 GROUP(uart_tx_ao_b1, 0, 24),
759 GROUP(uart_rx_ao_b1, 0, 23),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100760
Carlo Caione9dab1862016-03-01 23:04:34 +0100761 GROUP(i2c_mst_sck_ao, 0, 6),
762 GROUP(i2c_mst_sda_ao, 0, 5),
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200763
764 GROUP(pwm_f_ao, 0, 19),
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200765
766 GROUP(i2s_am_clk_out_ao, 0, 30),
767 GROUP(i2s_ao_clk_out_ao, 0, 29),
768 GROUP(i2s_lr_clk_out_ao, 0, 28),
769 GROUP(i2s_out_ch01_ao, 0, 27),
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100770};
771
772static const char * const gpio_groups[] = {
773 "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
774 "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
775 "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
776 "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
777 "GPIOX_20", "GPIOX_21",
778
779 "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4",
780 "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9",
781 "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14",
782 "GPIOY_15", "GPIOY_16",
783
784 "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4",
785 "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9",
786 "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14",
787 "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19",
788 "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24",
789 "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29",
790
791 "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
792 "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9",
793
794 "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
795 "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
796 "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14",
797
798 "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
799 "CARD_5", "CARD_6",
800
801 "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
802 "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
803 "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
804 "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18",
805
806 "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3",
807 "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7",
808 "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11",
809 "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N"
810};
811
812static const char * const sd_a_groups[] = {
813 "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a", "sd_cmd_a"
814};
815
816static const char * const sdxc_a_groups[] = {
817 "sdxc_d0_a", "sdxc_d13_a", "sdxc_d47_a", "sdxc_clk_a", "sdxc_cmd_a"
818};
819
820static const char * const pcm_a_groups[] = {
821 "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a"
822};
823
824static const char * const uart_a_groups[] = {
825 "uart_tx_a0", "uart_rx_a0", "uart_cts_a0", "uart_rts_a0",
826 "uart_tx_a1", "uart_rx_a1", "uart_cts_a1", "uart_rts_a1"
827};
828
829static const char * const uart_b_groups[] = {
830 "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0",
831 "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1"
832};
833
834static const char * const iso7816_groups[] = {
835 "iso7816_det", "iso7816_reset", "iso7816_clk", "iso7816_data"
836};
837
838static const char * const i2c_d_groups[] = {
839 "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1"
840};
841
842static const char * const xtal_groups[] = {
843 "xtal_32k_out", "xtal_24m_out"
844};
845
846static const char * const uart_c_groups[] = {
847 "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c"
848};
849
850static const char * const pcm_b_groups[] = {
851 "pcm_out_b", "pcm_in_b", "pcm_fs_b", "pcm_clk_b"
852};
853
854static const char * const i2c_c_groups[] = {
855 "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1"
856};
857
858static const char * const dvin_groups[] = {
859 "dvin_rgb", "dvin_vs", "dvin_hs", "dvin_clk", "dvin_de"
860};
861
862static const char * const enc_groups[] = {
863 "enc_0", "enc_1", "enc_2", "enc_3", "enc_4", "enc_5",
864 "enc_6", "enc_7", "enc_8", "enc_9", "enc_10", "enc_11",
865 "enc_12", "enc_13", "enc_14", "enc_15", "enc_16", "enc_17"
866};
867
868static const char * const vga_groups[] = {
869 "vga_vs", "vga_hs"
870};
871
872static const char * const hdmi_groups[] = {
873 "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec"
874};
875
876static const char * const spi_groups[] = {
877 "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0",
878 "spi_ss0_1", "spi_ss1_1", "spi_sclk_1", "spi_mosi_1",
879 "spi_miso_1", "spi_ss2_1"
880};
881
882static const char * const ethernet_groups[] = {
883 "eth_tx_clk_50m", "eth_tx_en", "eth_txd1",
884 "eth_txd0", "eth_rx_clk_in", "eth_rx_dv",
885 "eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc"
886};
887
888static const char * const i2c_a_groups[] = {
889 "i2c_sda_a0", "i2c_sck_a0", "i2c_sda_a1", "i2c_sck_a1",
890 "i2c_sda_a2", "i2c_sck_a2"
891};
892
893static const char * const i2c_b_groups[] = {
894 "i2c_sda_b", "i2c_sck_b"
895};
896
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200897static const char * const i2s_groups[] = {
898 "i2s_out_ch45", "i2s_out_ch23_pins", "i2s_out_ch01_pins",
899 "i2s_in_ch01_pins", "i2s_lr_clk_in_pins", "i2s_ao_clk_in_pins",
900 "i2s_am_clk_pins", "i2s_out_ch78_pins"
901};
902
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100903static const char * const sd_c_groups[] = {
904 "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c",
905 "sd_cmd_c", "sd_clk_c"
906};
907
908static const char * const sdxc_c_groups[] = {
909 "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c",
910 "sdxc_clk_c"
911};
912
913static const char * const nand_groups[] = {
914 "nand_io", "nand_io_ce0", "nand_io_ce1",
915 "nand_io_rb0", "nand_ale", "nand_cle",
916 "nand_wen_clk", "nand_ren_clk", "nand_dqs",
917 "nand_ce2", "nand_ce3"
918};
919
920static const char * const nor_groups[] = {
921 "nor_d", "nor_q", "nor_c", "nor_cs"
922};
923
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200924static const char * const pwm_a_groups[] = {
925 "pwm_a_y", "pwm_a_z0", "pwm_a_z7"
926};
927
928static const char * const pwm_b_groups[] = {
929 "pwm_b_x", "pwm_b_z"
930};
931
932static const char * const pwm_c_groups[] = {
933 "pwm_c_dv9", "pwm_c_dv29", "pwm_c_z"
934};
935
936static const char * const pwm_d_groups[] = {
937 "pwm_d"
938};
939
940static const char * const pwm_e_groups[] = {
941 "pwm_e"
942};
943
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100944static const char * const sd_b_groups[] = {
945 "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b",
946 "sd_d3_b", "sd_d2_b"
947};
948
949static const char * const sdxc_b_groups[] = {
950 "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b"
951};
952
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200953static const char * const spdif_groups[] = {
954 "spdif_in", "spdif_out"
955};
956
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100957static const char * const uart_ao_groups[] = {
958 "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a"
959};
960
961static const char * const remote_groups[] = {
962 "remote_input"
963};
964
965static const char * const i2c_slave_ao_groups[] = {
966 "i2c_slave_sck_ao", "i2c_slave_sda_ao"
967};
968
969static const char * const uart_ao_b_groups[] = {
970 "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1"
971};
972
973static const char * const i2c_mst_ao_groups[] = {
974 "i2c_mst_sck_ao", "i2c_mst_sda_ao"
975};
976
Martin Blumenstinglc1f29552017-05-06 18:57:48 +0200977static const char * const pwm_f_ao_groups[] = {
978 "pwm_f_ao"
979};
980
Martin Blumenstingl64f6d072017-05-06 18:57:49 +0200981static const char * const i2s_ao_groups[] = {
982 "i2s_am_clk_out_ao", "i2s_ao_clk_out_ao", "i2s_lr_clk_out_ao",
983 "i2s_out_ch01_ao"
984};
985
Carlo Caione9dab1862016-03-01 23:04:34 +0100986static struct meson_pmx_func meson8_cbus_functions[] = {
Beniamino Galvani6ac73092015-01-17 19:15:14 +0100987 FUNCTION(gpio),
988 FUNCTION(sd_a),
989 FUNCTION(sdxc_a),
990 FUNCTION(pcm_a),
991 FUNCTION(uart_a),
992 FUNCTION(uart_b),
993 FUNCTION(iso7816),
994 FUNCTION(i2c_d),
995 FUNCTION(xtal),
996 FUNCTION(uart_c),
997 FUNCTION(pcm_b),
998 FUNCTION(i2c_c),
999 FUNCTION(dvin),
1000 FUNCTION(enc),
1001 FUNCTION(vga),
1002 FUNCTION(hdmi),
1003 FUNCTION(spi),
1004 FUNCTION(ethernet),
1005 FUNCTION(i2c_a),
1006 FUNCTION(i2c_b),
1007 FUNCTION(sd_c),
1008 FUNCTION(sdxc_c),
1009 FUNCTION(nand),
1010 FUNCTION(nor),
1011 FUNCTION(sd_b),
1012 FUNCTION(sdxc_b),
Martin Blumenstinglc1f29552017-05-06 18:57:48 +02001013 FUNCTION(pwm_a),
1014 FUNCTION(pwm_b),
1015 FUNCTION(pwm_c),
1016 FUNCTION(pwm_d),
1017 FUNCTION(pwm_e),
Martin Blumenstingl64f6d072017-05-06 18:57:49 +02001018 FUNCTION(i2s),
1019 FUNCTION(spdif),
Carlo Caione9dab1862016-03-01 23:04:34 +01001020};
1021
1022static struct meson_pmx_func meson8_aobus_functions[] = {
Beniamino Galvani6ac73092015-01-17 19:15:14 +01001023 FUNCTION(uart_ao),
1024 FUNCTION(remote),
1025 FUNCTION(i2c_slave_ao),
1026 FUNCTION(uart_ao_b),
1027 FUNCTION(i2c_mst_ao),
Martin Blumenstinglc1f29552017-05-06 18:57:48 +02001028 FUNCTION(pwm_f_ao),
Martin Blumenstingl64f6d072017-05-06 18:57:49 +02001029 FUNCTION(i2s_ao),
Beniamino Galvani6ac73092015-01-17 19:15:14 +01001030};
1031
Carlo Caione9dab1862016-03-01 23:04:34 +01001032static struct meson_bank meson8_cbus_banks[] = {
Carlo Caione0cf6f3c2015-03-19 22:34:10 +01001033 /* name first last pullen pull dir out in */
1034 BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
1035 BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_16, 0), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
1036 BANK("DV", PIN(GPIODV_0, 0), PIN(GPIODV_29, 0), 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
1037 BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
1038 BANK("Z", PIN(GPIOZ_0, 0), PIN(GPIOZ_14, 0), 1, 0, 1, 0, 3, 17, 4, 17, 5, 17),
1039 BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
1040 BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
Beniamino Galvani6ac73092015-01-17 19:15:14 +01001041};
1042
Carlo Caione9dab1862016-03-01 23:04:34 +01001043static struct meson_bank meson8_aobus_banks[] = {
Carlo Caione0cf6f3c2015-03-19 22:34:10 +01001044 /* name first last pullen pull dir out in */
1045 BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
Beniamino Galvani6ac73092015-01-17 19:15:14 +01001046};
1047
Carlo Caione9dab1862016-03-01 23:04:34 +01001048struct meson_pinctrl_data meson8_cbus_pinctrl_data = {
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +02001049 .name = "cbus-banks",
1050 .pin_base = 0,
Carlo Caione9dab1862016-03-01 23:04:34 +01001051 .pins = meson8_cbus_pins,
1052 .groups = meson8_cbus_groups,
1053 .funcs = meson8_cbus_functions,
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +02001054 .banks = meson8_cbus_banks,
Carlo Caione9dab1862016-03-01 23:04:34 +01001055 .num_pins = ARRAY_SIZE(meson8_cbus_pins),
1056 .num_groups = ARRAY_SIZE(meson8_cbus_groups),
1057 .num_funcs = ARRAY_SIZE(meson8_cbus_functions),
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +02001058 .num_banks = ARRAY_SIZE(meson8_cbus_banks),
Carlo Caione9dab1862016-03-01 23:04:34 +01001059};
1060
1061struct meson_pinctrl_data meson8_aobus_pinctrl_data = {
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +02001062 .name = "ao-bank",
1063 .pin_base = 120,
Carlo Caione9dab1862016-03-01 23:04:34 +01001064 .pins = meson8_aobus_pins,
1065 .groups = meson8_aobus_groups,
1066 .funcs = meson8_aobus_functions,
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +02001067 .banks = meson8_aobus_banks,
Carlo Caione9dab1862016-03-01 23:04:34 +01001068 .num_pins = ARRAY_SIZE(meson8_aobus_pins),
1069 .num_groups = ARRAY_SIZE(meson8_aobus_groups),
1070 .num_funcs = ARRAY_SIZE(meson8_aobus_functions),
Beniamino Galvanidb80f0e2016-08-13 19:41:18 +02001071 .num_banks = ARRAY_SIZE(meson8_aobus_banks),
Beniamino Galvani6ac73092015-01-17 19:15:14 +01001072};