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review.shift-gmbh.com / SHIFTPHONES / kernel / common / a6ba44e8799230e36c8ab06fda7f77f421e9e795 / . / arch / powerpc / include / asm / cputable.h
blob: c67b94f3334c9ca1b9700f81223124563e96d73b [file] [log] [blame]
Greg Kroah-Hartmanb2441312017-11-01 15:07:57 +0100[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]2#ifndef __ASM_POWERPC_CPUTABLE_H
3#define __ASM_POWERPC_CPUTABLE_H
4
Adrian Bunkd1cdcf22008-06-24 03:48:21 +1000[diff] [blame]5
Michael Ellerman6574ba92016-07-27 13:35:15 +1000[diff] [blame]6#include <linux/types.h>
David Howellsc3617f72012-10-09 09:47:26 +0100[diff] [blame]7#include <uapi/asm/cputable.h>
Christophe Leroyec0c4642018-07-05 16:24:57 +0000[diff] [blame]8#include <asm/asm-const.h>
Adrian Bunkd1cdcf22008-06-24 03:48:21 +1000[diff] [blame]9
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]10#ifndef __ASSEMBLY__
11
12/* This structure can grow, it's real size is used by head.S code
13 * via the mkdefs mechanism.
14 */
15struct cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]16
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]17typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame]18typedef void (*cpu_restore_t)(void);
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]19
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]20enum powerpc_oprofile_type {
Andy Whitcroft7a45fb12006-01-13 12:35:49 +0000[diff] [blame]21 PPC_OPROFILE_INVALID = 0,
22 PPC_OPROFILE_RS64 = 1,
23 PPC_OPROFILE_POWER4 = 2,
24 PPC_OPROFILE_G4 = 3,
Andy Fleming39aef682008-02-04 18:27:55 -0600[diff] [blame]25 PPC_OPROFILE_FSL_EMB = 4,
Maynard Johnson18f21902006-11-20 18:45:16 +0100[diff] [blame]26 PPC_OPROFILE_CELL = 5,
Olof Johansson25fc5302007-04-18 16:38:21 +1000[diff] [blame]27 PPC_OPROFILE_PA6T = 6,
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]28};
29
Olof Johansson1bd2e5a2007-01-28 21:23:54 -0600[diff] [blame]30enum powerpc_pmc_type {
31 PPC_PMC_DEFAULT = 0,
32 PPC_PMC_IBM = 1,
33 PPC_PMC_PA6T = 2,
Benjamin Herrenschmidtb950bdd2008-08-18 14:23:51 +1000[diff] [blame]34 PPC_PMC_G4 = 3,
Olof Johansson1bd2e5a2007-01-28 21:23:54 -0600[diff] [blame]35};
36
Benjamin Herrenschmidt47c0bd12007-12-21 15:39:21 +1100[diff] [blame]37struct pt_regs;
38
39extern int machine_check_generic(struct pt_regs *regs);
40extern int machine_check_4xx(struct pt_regs *regs);
41extern int machine_check_440A(struct pt_regs *regs);
Scott Woodfe04b112010-04-08 00:38:22 -0500[diff] [blame]42extern int machine_check_e500mc(struct pt_regs *regs);
Benjamin Herrenschmidt47c0bd12007-12-21 15:39:21 +1100[diff] [blame]43extern int machine_check_e500(struct pt_regs *regs);
44extern int machine_check_e200(struct pt_regs *regs);
Dave Kleikampfc5e7092010-03-05 03:43:18 +0000[diff] [blame]45extern int machine_check_47x(struct pt_regs *regs);
Christophe Leroye627f8d2016-09-16 10:23:11 +0200[diff] [blame]46int machine_check_8xx(struct pt_regs *regs);
Christophe Leroy0deae392018-12-10 11:41:29 +0000[diff] [blame]47int machine_check_83xx(struct pt_regs *regs);
Benjamin Herrenschmidt47c0bd12007-12-21 15:39:21 +1100[diff] [blame]48
chenhui zhaoe7affb12015-11-20 17:13:58 +0800[diff] [blame]49extern void cpu_down_flush_e500v2(void);
50extern void cpu_down_flush_e500mc(void);
51extern void cpu_down_flush_e5500(void);
52extern void cpu_down_flush_e6500(void);
53
Paul Mackerras87a72f92007-10-04 14:18:01 +1000[diff] [blame]54/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]55struct cpu_spec {
56 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
57 unsigned int pvr_mask;
58 unsigned int pvr_value;
59
60 char *cpu_name;
61 unsigned long cpu_features; /* Kernel features */
62 unsigned int cpu_user_features; /* Userland features */
Michael Neuling21713642013-04-17 17:33:11 +0000[diff] [blame]63 unsigned int cpu_user_features2; /* Userland features v2 */
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]64 unsigned int mmu_features; /* MMU features */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]65
66 /* cache line sizes */
67 unsigned int icache_bsize;
68 unsigned int dcache_bsize;
69
chenhui zhaoe7affb12015-11-20 17:13:58 +0800[diff] [blame]70 /* flush caches inside the current cpu */
71 void (*cpu_down_flush)(void);
72
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]73 /* number of performance monitor counters */
74 unsigned int num_pmcs;
Olof Johansson1bd2e5a2007-01-28 21:23:54 -0600[diff] [blame]75 enum powerpc_pmc_type pmc_type;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]76
77 /* this is called to initialize various CPU bits like L1 cache,
78 * BHT, SPD, etc... from head.S before branching to identify_machine
79 */
80 cpu_setup_t cpu_setup;
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame]81 /* Used to restore cpu setup on secondary processors and at resume */
82 cpu_restore_t cpu_restore;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]83
84 /* Used by oprofile userspace to select the right counters */
85 char *oprofile_cpu_type;
86
87 /* Processor specific oprofile operations */
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]88 enum powerpc_oprofile_type oprofile_type;
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]89
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]90 /* Bit locations inside the mmcra change */
91 unsigned long oprofile_mmcra_sihv;
92 unsigned long oprofile_mmcra_sipr;
93
94 /* Bits to clear during an oprofile exception */
95 unsigned long oprofile_mmcra_clear;
96
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]97 /* Name of processor class, for the ELF AT_PLATFORM entry */
98 char *platform;
Benjamin Herrenschmidt47c0bd12007-12-21 15:39:21 +1100[diff] [blame]99
100 /* Processor specific machine check handling. Return negative
101 * if the error is fatal, 1 if it was fully recovered and 0 to
102 * pass up (not CPU originated) */
103 int (*machine_check)(struct pt_regs *regs);
Mahesh Salgaonkar4c703412013-10-30 20:04:40 +0530[diff] [blame]104
105 /*
106 * Processor specific early machine check handler which is
107 * called in real mode to handle SLB and TLB errors.
108 */
109 long (*machine_check_early)(struct pt_regs *regs);
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]110};
111
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]112extern struct cpu_spec *cur_cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]113
Benjamin Herrenschmidt42c4aaa2006-10-24 16:42:40 +1000[diff] [blame]114extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
115
Nicholas Piggin5a61ef72017-05-09 13:16:52 +1000[diff] [blame]116extern void set_cur_cpu_spec(struct cpu_spec *s);
Paul Mackerras974a76f2006-11-10 20:38:53 +1100[diff] [blame]117extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
Nicholas Piggin5a61ef72017-05-09 13:16:52 +1000[diff] [blame]118extern void identify_cpu_name(unsigned int pvr);
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]119extern void do_feature_fixups(unsigned long value, void *fixup_start,
120 void *fixup_end);
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000[diff] [blame]121
Nathan Lynch9115d132008-07-16 09:58:51 +1000[diff] [blame]122extern const char *powerpc_base_platform;
123
Kevin Hao4db73272016-07-23 14:42:41 +0530[diff] [blame]124#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
125extern void cpu_feature_keys_init(void);
126#else
127static inline void cpu_feature_keys_init(void) { }
128#endif
129
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]130#endif /* __ASSEMBLY__ */
131
132/* CPU kernel features */
133
Paul Mackerras9bbf0b52018-03-20 08:46:13 +1100[diff] [blame]134/* Definitions for features that we have on both 32-bit and 64-bit chips */
Michael Neulingcde4d492012-12-20 14:06:39 +0000[diff] [blame]135#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
Paul Mackerras9bbf0b52018-03-20 08:46:13 +1100[diff] [blame]136#define CPU_FTR_ALTIVEC ASM_CONST(0x00000002)
137#define CPU_FTR_DBELL ASM_CONST(0x00000004)
138#define CPU_FTR_CAN_NAP ASM_CONST(0x00000008)
139#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010)
140#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00000020)
141#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040)
142#define CPU_FTR_LWSYNC ASM_CONST(0x00000080)
143#define CPU_FTR_NOEXECUTE ASM_CONST(0x00000100)
144#define CPU_FTR_EMB_HV ASM_CONST(0x00000200)
145
146/* Definitions for features that only exist on 32-bit chips */
147#ifdef CONFIG_PPC32
Paul Mackerras9bbf0b52018-03-20 08:46:13 +1100[diff] [blame]148#define CPU_FTR_L2CR ASM_CONST(0x00002000)
149#define CPU_FTR_SPEC7450 ASM_CONST(0x00004000)
150#define CPU_FTR_TAU ASM_CONST(0x00008000)
151#define CPU_FTR_CAN_DOZE ASM_CONST(0x00010000)
Paul Mackerras9bbf0b52018-03-20 08:46:13 +1100[diff] [blame]152#define CPU_FTR_L3CR ASM_CONST(0x00040000)
153#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00080000)
154#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00100000)
155#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00200000)
156#define CPU_FTR_NO_DPM ASM_CONST(0x00400000)
157#define CPU_FTR_476_DD2 ASM_CONST(0x00800000)
158#define CPU_FTR_NEED_COHERENT ASM_CONST(0x01000000)
159#define CPU_FTR_NO_BTIC ASM_CONST(0x02000000)
160#define CPU_FTR_PPC_LE ASM_CONST(0x04000000)
Paul Mackerras9bbf0b52018-03-20 08:46:13 +1100[diff] [blame]161#define CPU_FTR_SPE ASM_CONST(0x10000000)
162#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x20000000)
163#define CPU_FTR_INDEXED_DCR ASM_CONST(0x40000000)
164
165#else /* CONFIG_PPC32 */
166/* Define these to 0 for the sake of tests in common code */
Paul Mackerras9bbf0b52018-03-20 08:46:13 +1100[diff] [blame]167#define CPU_FTR_PPC_LE (0)
168#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]169
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]170/*
Paul Mackerras9bbf0b52018-03-20 08:46:13 +1100[diff] [blame]171 * Definitions for the 64-bit processor unique features;
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]172 * on 32-bit, make the names available but defined to be 0.
173 */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]174#ifdef __powerpc64__
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]175#define LONG_ASM_CONST(x) ASM_CONST(x)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]176#else
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]177#define LONG_ASM_CONST(x) 0
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]178#endif
179
Paul Mackerras9bbf0b52018-03-20 08:46:13 +1100[diff] [blame]180#define CPU_FTR_REAL_LE LONG_ASM_CONST(0x0000000000001000)
181#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000000002000)
Paul Mackerras9bbf0b52018-03-20 08:46:13 +1100[diff] [blame]182#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000000008000)
183#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000000010000)
184#define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000000000020000)
185#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000000000040000)
186#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000000000080000)
187#define CPU_FTR_SMT LONG_ASM_CONST(0x0000000000100000)
188#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000000000200000)
189#define CPU_FTR_PURR LONG_ASM_CONST(0x0000000000400000)
190#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000000000800000)
191#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000)
192#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000)
193#define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000)
194#define CPU_FTR_SAO LONG_ASM_CONST(0x0000000008000000)
195#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000)
196#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000)
197#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000)
198#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000)
199#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0000000100000000)
200#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0000000200000000)
201#define CPU_FTR_PKEY LONG_ASM_CONST(0x0000000400000000)
202#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0000000800000000)
203#define CPU_FTR_TM LONG_ASM_CONST(0x0000001000000000)
204#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000002000000000)
205#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0000004000000000)
206#define CPU_FTR_DAWR LONG_ASM_CONST(0x0000008000000000)
207#define CPU_FTR_DABRX LONG_ASM_CONST(0x0000010000000000)
208#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x0000020000000000)
Paul Mackerras9bbf0b52018-03-20 08:46:13 +1100[diff] [blame]209#define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000)
Paul Mackerrasb5af4f22018-03-21 21:31:59 +1100[diff] [blame]210#define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000)
211#define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000)
Aneesh Kumar K.V09ce98c2019-09-24 09:22:52 +0530[diff] [blame]212#define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000)
Alastair D'Silva81984422018-05-11 16:12:57 +1000[diff] [blame]213#define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000)
Aneesh Kumar K.V047e6572019-09-24 09:22:53 +0530[diff] [blame]214#define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001000000000000)
Jordan Niethe736bcdd2019-12-06 14:17:22 +1100[diff] [blame]215#define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002000000000000)
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]216
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]217#ifndef __ASSEMBLY__
218
Matt Evans44ae3ab2011-04-06 19:48:50 +0000[diff] [blame]219#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
220
Michael Ellerman13b3d132014-07-10 12:29:20 +1000[diff] [blame]221#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]222
223/* We only set the altivec features if the kernel was compiled with altivec
224 * support
225 */
226#ifdef CONFIG_ALTIVEC
227#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
228#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
229#else
230#define CPU_FTR_ALTIVEC_COMP 0
231#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
232#endif
233
Michael Neulingb962ce92008-06-25 14:07:18 +1000[diff] [blame]234/* We only set the VSX features if the kernel was compiled with VSX
235 * support
236 */
237#ifdef CONFIG_VSX
238#define CPU_FTR_VSX_COMP CPU_FTR_VSX
239#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
240#else
241#define CPU_FTR_VSX_COMP 0
242#define PPC_FEATURE_HAS_VSX_COMP 0
243#endif
244
Kumar Gala5e14d212007-09-13 01:44:20 -0500[diff] [blame]245/* We only set the spe features if the kernel was compiled with spe
246 * support
247 */
248#ifdef CONFIG_SPE
249#define CPU_FTR_SPE_COMP CPU_FTR_SPE
250#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
251#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
252#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
253#else
254#define CPU_FTR_SPE_COMP 0
255#define PPC_FEATURE_HAS_SPE_COMP 0
256#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
257#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
258#endif
259
Michael Neuling6a6d5412013-02-13 16:21:29 +0000[diff] [blame]260/* We only set the TM feature if the kernel was compiled with TM supprt */
261#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
Sam bobroffb4b56f92015-06-12 11:06:32 +1000[diff] [blame]262#define CPU_FTR_TM_COMP CPU_FTR_TM
263#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
264#define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
Michael Neuling6a6d5412013-02-13 16:21:29 +0000[diff] [blame]265#else
Sam bobroffb4b56f92015-06-12 11:06:32 +1000[diff] [blame]266#define CPU_FTR_TM_COMP 0
267#define PPC_FEATURE2_HTM_COMP 0
268#define PPC_FEATURE2_HTM_NOSC_COMP 0
Michael Neuling6a6d5412013-02-13 16:21:29 +0000[diff] [blame]269#endif
270
Scott Wood11af1192007-09-14 15:32:14 -0500[diff] [blame]271/* We need to mark all pages as being coherent if we're SMP or we have a
272 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
273 * require it for PCI "streaming/prefetch" to work properly.
Piotr Ziecikc9310922009-03-17 09:17:50 -0600[diff] [blame]274 * This is also required by 52xx family.
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]275 */
Kumar Gala1775dbb2006-02-22 09:46:02 -0600[diff] [blame]276#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
Piotr Ziecikc9310922009-03-17 09:17:50 -0600[diff] [blame]277 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
278 || defined(CONFIG_PPC_MPC52xx)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]279#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
280#else
281#define CPU_FTR_COMMON 0
282#endif
283
284/* The powersave features NAP & DOZE seems to confuse BDI when
285 debugging. So if a BDI is used, disable theses
286 */
287#ifndef CONFIG_BDI_SWITCH
288#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
289#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
290#else
291#define CPU_FTR_MAYBE_CAN_DOZE 0
292#define CPU_FTR_MAYBE_CAN_NAP 0
293#endif
294
Christophe Leroy12c3f1f2019-08-26 15:52:14 +0000[diff] [blame]295#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | \
Christophe Leroye0291f12019-08-26 15:52:18 +0000[diff] [blame]296 CPU_FTR_COHERENT_ICACHE)
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]297#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
Christophe Leroy385e89d2018-11-28 17:21:10 +0000[diff] [blame]298 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE)
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]299#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]300#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]301 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]302 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]303#define CPU_FTRS_740 (CPU_FTR_COMMON | \
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]304 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]305 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]306 CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]307#define CPU_FTRS_750 (CPU_FTR_COMMON | \
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]308 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]309 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]310 CPU_FTR_PPC_LE)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]311#define CPU_FTRS_750CL (CPU_FTRS_750)
Josh Boyerb6f41cc2007-07-03 02:06:53 +1000[diff] [blame]312#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
313#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]314#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
Josh Boyerb6f41cc2007-07-03 02:06:53 +1000[diff] [blame]315#define CPU_FTRS_750GX (CPU_FTRS_750FX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]316#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]317 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]318 CPU_FTR_ALTIVEC_COMP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]319 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]320#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]321 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]322 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]323 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]324#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]325 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]326 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]327 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]328#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]329 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]330 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]331 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]332 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]333#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]334 CPU_FTR_NEED_PAIRED_STWCX | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]335 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]336 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]337 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]338#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]339 CPU_FTR_NEED_PAIRED_STWCX | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]340 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]341 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]342#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]343 CPU_FTR_NEED_PAIRED_STWCX | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]344 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]345 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]346 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]347 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]348#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]349 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]350 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]351 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]352#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]353 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]354 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]355 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
356 CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]357#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]358 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]359 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]360 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]361#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]362 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]363 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]364 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]365#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
James.Yang3d372542007-05-02 16:34:43 -0500[diff] [blame]366 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]367 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]368 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
Christophe Leroy385e89d2018-11-28 17:21:10 +0000[diff] [blame]369#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE)
Scott Wood11af1192007-09-14 15:32:14 -0500[diff] [blame]370#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]371 CPU_FTR_MAYBE_CAN_NAP)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]372#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]373 CPU_FTR_MAYBE_CAN_NAP | \
Christophe Leroy385e89d2018-11-28 17:21:10 +0000[diff] [blame]374 CPU_FTR_COMMON | CPU_FTR_NOEXECUTE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]375#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]376 CPU_FTR_MAYBE_CAN_NAP | \
Christophe Leroy385e89d2018-11-28 17:21:10 +0000[diff] [blame]377 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE | CPU_FTR_NOEXECUTE)
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]378#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON)
379#define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE)
380#define CPU_FTRS_40X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
381#define CPU_FTRS_44X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
382#define CPU_FTRS_440x6 (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
Benjamin Herrenschmidt6d2170b2008-12-18 19:13:22 +0000[diff] [blame]383 CPU_FTR_INDEXED_DCR)
Dave Kleikampe7f75ad2010-03-05 10:43:12 +0000[diff] [blame]384#define CPU_FTRS_47X (CPU_FTRS_440x6)
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]385#define CPU_FTRS_E200 (CPU_FTR_SPE_COMP | \
Kumar Gala5e14d212007-09-13 01:44:20 -0500[diff] [blame]386 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
Christophe Leroye0291f12019-08-26 15:52:18 +0000[diff] [blame]387 CPU_FTR_NOEXECUTE | \
Scott Wood52b066f2011-12-20 15:34:12 +0000[diff] [blame]388 CPU_FTR_DEBUG_LVL_EXC)
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]389#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | \
Benjamin Herrenschmidt8309ce722008-12-12 17:33:25 +1100[diff] [blame]390 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
391 CPU_FTR_NOEXECUTE)
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]392#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]393 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
Benjamin Herrenschmidt8309ce722008-12-12 17:33:25 +1100[diff] [blame]394 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]395#define CPU_FTRS_E500MC (CPU_FTR_NODSISRALIGN | \
Paul Mackerrasdd0efb32018-03-20 08:46:12 +1100[diff] [blame]396 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
Scott Wood73196cd32011-12-20 15:34:47 +0000[diff] [blame]397 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
Scott Woodd52459c2013-07-23 20:21:11 -0500[diff] [blame]398/*
399 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
400 * same workaround as CPU_FTR_CELL_TB_BUG.
401 */
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]402#define CPU_FTRS_E5500 (CPU_FTR_NODSISRALIGN | \
Paul Mackerrasdd0efb32018-03-20 08:46:12 +1100[diff] [blame]403 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
Kumar Galad36b4c42011-04-06 00:18:48 -0500[diff] [blame]404 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
Scott Woodd52459c2013-07-23 20:21:11 -0500[diff] [blame]405 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]406#define CPU_FTRS_E6500 (CPU_FTR_NODSISRALIGN | \
Paul Mackerrasdd0efb32018-03-20 08:46:12 +1100[diff] [blame]407 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
Kumar Gala10241842011-11-06 11:51:07 -0600[diff] [blame]408 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
Scott Woodd52459c2013-07-23 20:21:11 -0500[diff] [blame]409 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
Andy Fleminge16c8762011-12-08 01:20:27 -0600[diff] [blame]410 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]411#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
Michael Ellerman0b8e2e12006-11-23 00:46:46 +0100[diff] [blame]412
413/* 64-bit CPUs */
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]414#define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \
Nicholas Piggin3735eb82018-02-21 05:08:28 +1000[diff] [blame]415 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Mark Nelson2a929432008-08-22 14:36:19 +1000[diff] [blame]416 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
Paul Mackerras969391c2011-06-29 00:26:11 +0000[diff] [blame]417 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
Michael Neuling82a9f162013-05-16 20:27:31 +0000[diff] [blame]418 CPU_FTR_HVMODE | CPU_FTR_DABRX)
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]419#define CPU_FTRS_POWER5 (CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]420 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]421 CPU_FTR_MMCRA | CPU_FTR_SMT | \
Matt Evans44ae3ab2011-04-06 19:48:50 +0000[diff] [blame]422 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
Michael Neuling82a9f162013-05-16 20:27:31 +0000[diff] [blame]423 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]424#define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]425 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]426 CPU_FTR_MMCRA | CPU_FTR_SMT | \
Matt Evans44ae3ab2011-04-06 19:48:50 +0000[diff] [blame]427 CPU_FTR_COHERENT_ICACHE | \
Anton Blanchard4c1985572006-12-08 17:46:58 +1100[diff] [blame]428 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
Anton Blanchardf89451f2010-08-11 01:40:27 +0000[diff] [blame]429 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
Michael Neuling82a9f162013-05-16 20:27:31 +0000[diff] [blame]430 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
431 CPU_FTR_DABRX)
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]432#define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \
Paul Mackerras969391c2011-06-29 00:26:11 +0000[diff] [blame]433 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
Michael Neulinge952e6c2008-06-18 10:47:26 +1000[diff] [blame]434 CPU_FTR_MMCRA | CPU_FTR_SMT | \
Matt Evans44ae3ab2011-04-06 19:48:50 +0000[diff] [blame]435 CPU_FTR_COHERENT_ICACHE | \
Michael Neulinge952e6c2008-06-18 10:47:26 +1000[diff] [blame]436 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
Anton Blanchardf89451f2010-08-11 01:40:27 +0000[diff] [blame]437 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
Tseng-Hui (Frank) Lin851d2e22011-05-02 20:43:04 +0000[diff] [blame]438 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
Michael Ellermanc1807e32017-10-19 15:08:19 +1100[diff] [blame]439 CPU_FTR_CFAR | CPU_FTR_HVMODE | \
Ram Paicf43d3b2018-01-18 17:50:44 -0800[diff] [blame]440 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX | CPU_FTR_PKEY)
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]441#define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \
Michael Neuling71e18492012-10-30 19:34:15 +0000[diff] [blame]442 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
443 CPU_FTR_MMCRA | CPU_FTR_SMT | \
444 CPU_FTR_COHERENT_ICACHE | \
445 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
446 CPU_FTR_DSCR | CPU_FTR_SAO | \
447 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
Michael Ellermanc1807e32017-10-19 15:08:19 +1100[diff] [blame]448 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
Michael Ellerman1de2bd42013-04-30 20:17:02 +0000[diff] [blame]449 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
Ram Paicf43d3b2018-01-18 17:50:44 -0800[diff] [blame]450 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_PKEY)
Michael Ellerman68f2f0d2014-03-14 16:00:28 +1100[diff] [blame]451#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]452#define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \
Michael Neulingc3ab3002016-02-19 11:16:24 +1100[diff] [blame]453 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
454 CPU_FTR_MMCRA | CPU_FTR_SMT | \
455 CPU_FTR_COHERENT_ICACHE | \
456 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
457 CPU_FTR_DSCR | CPU_FTR_SAO | \
458 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
Nicholas Piggin2384d2d2017-04-19 12:27:37 +1000[diff] [blame]459 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
Michael Neuling96541532018-03-27 15:37:24 +1100[diff] [blame]460 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
Michael Ellerman95dff482018-03-28 22:59:50 +1100[diff] [blame]461 CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_PKEY | \
Aneesh Kumar K.V047e6572019-09-24 09:22:53 +0530[diff] [blame]462 CPU_FTR_P9_TLBIE_STQ_BUG | CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR)
Jordan Niethe736bcdd2019-12-06 14:17:22 +1100[diff] [blame]463#define CPU_FTRS_POWER9_DD2_0 (CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG)
464#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | \
465 CPU_FTR_P9_RADIX_PREFETCH_BUG | \
466 CPU_FTR_POWER9_DD2_1)
Nicholas Piggin3a52f602018-04-05 15:57:55 +1000[diff] [blame]467#define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
468 CPU_FTR_P9_TM_HV_ASSIST | \
Paul Mackerrasb5af4f22018-03-21 21:31:59 +1100[diff] [blame]469 CPU_FTR_P9_TM_XER_SO_BUG)
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]470#define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
Benjamin Herrenschmidt7c03d652008-12-18 19:13:32 +0000[diff] [blame]471 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]472 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
Matt Evans44ae3ab2011-04-06 19:48:50 +0000[diff] [blame]473 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
Michael Neuling82a9f162013-05-16 20:27:31 +0000[diff] [blame]474 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]475#define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \
Matt Evans44ae3ab2011-04-06 19:48:50 +0000[diff] [blame]476 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
Michael Neuling82a9f162013-05-16 20:27:31 +0000[diff] [blame]477 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
Paul Mackerrasc0d64cf2018-03-20 08:46:11 +1100[diff] [blame]478#define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]479
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]480#ifdef __powerpc64__
Kumar Gala11ed0db2011-04-06 00:11:06 -0500[diff] [blame]481#ifdef CONFIG_PPC_BOOK3E
Michael Ellerman90029642014-08-06 18:26:28 +1000[diff] [blame]482#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
Kumar Gala11ed0db2011-04-06 00:11:06 -0500[diff] [blame]483#else
Nicholas Piggindb5ae1c2018-02-21 05:08:31 +1000[diff] [blame]484#ifdef CONFIG_CPU_LITTLE_ENDIAN
485#define CPU_FTRS_POSSIBLE \
486 (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
Joel Stanleye11b64b2018-07-11 16:02:58 +1000[diff] [blame]487 CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
Michael Ellermance57c662018-07-19 14:37:57 +1000[diff] [blame]488 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
Nicholas Piggindb5ae1c2018-02-21 05:08:31 +1000[diff] [blame]489#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]490#define CPU_FTRS_POSSIBLE \
Nicholas Piggin471d7ff2018-02-21 05:08:29 +1000[diff] [blame]491 (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
Michael Ellerman468a3302014-07-10 12:29:18 +1000[diff] [blame]492 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
Joel Stanleye11b64b2018-07-11 16:02:58 +1000[diff] [blame]493 CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
494 CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
Michael Ellermance57c662018-07-19 14:37:57 +1000[diff] [blame]495 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2)
Nicholas Piggindb5ae1c2018-02-21 05:08:31 +1000[diff] [blame]496#endif /* CONFIG_CPU_LITTLE_ENDIAN */
Kumar Gala11ed0db2011-04-06 00:11:06 -0500[diff] [blame]497#endif
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]498#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]499enum {
500 CPU_FTRS_POSSIBLE =
Christophe Leroy12c3f1f2019-08-26 15:52:14 +0000[diff] [blame]501#ifdef CONFIG_PPC_BOOK3S_601
502 CPU_FTRS_PPC601 |
503#elif defined(CONFIG_PPC_BOOK3S_32)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]504 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
505 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
506 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
507 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
508 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
509 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
510 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
Kim Phillipsaa42c692006-12-08 02:43:30 -0600[diff] [blame]511 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
512 CPU_FTRS_CLASSIC32 |
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]513#else
514 CPU_FTRS_GENERIC_32 |
515#endif
Christophe Leroy968159c2017-08-08 13:58:54 +0200[diff] [blame]516#ifdef CONFIG_PPC_8xx
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]517 CPU_FTRS_8XX |
518#endif
519#ifdef CONFIG_40x
520 CPU_FTRS_40X |
521#endif
522#ifdef CONFIG_44x
Benjamin Herrenschmidt6d2170b2008-12-18 19:13:22 +0000[diff] [blame]523 CPU_FTRS_44X | CPU_FTRS_440x6 |
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]524#endif
Dave Kleikampe7f75ad2010-03-05 10:43:12 +0000[diff] [blame]525#ifdef CONFIG_PPC_47x
Dave Kleikampc48d0db2011-01-26 06:17:58 +0000[diff] [blame]526 CPU_FTRS_47X | CPU_FTR_476_DD2 |
Dave Kleikampe7f75ad2010-03-05 10:43:12 +0000[diff] [blame]527#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]528#ifdef CONFIG_E200
529 CPU_FTRS_E200 |
530#endif
531#ifdef CONFIG_E500
Scott Wood06aae862011-12-20 15:34:14 +0000[diff] [blame]532 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
533#endif
534#ifdef CONFIG_PPC_E500MC
535 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]536#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]537 0,
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]538};
539#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]540
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]541#ifdef __powerpc64__
Kumar Gala11ed0db2011-04-06 00:11:06 -0500[diff] [blame]542#ifdef CONFIG_PPC_BOOK3E
Michael Ellerman90029642014-08-06 18:26:28 +1000[diff] [blame]543#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
Kumar Gala11ed0db2011-04-06 00:11:06 -0500[diff] [blame]544#else
Michael Ellerman81b654c2018-04-12 22:24:45 +1000[diff] [blame]545
546#ifdef CONFIG_PPC_DT_CPU_FTRS
547#define CPU_FTRS_DT_CPU_BASE \
548 (CPU_FTR_LWSYNC | \
549 CPU_FTR_FPU_UNAVAILABLE | \
550 CPU_FTR_NODSISRALIGN | \
551 CPU_FTR_NOEXECUTE | \
552 CPU_FTR_COHERENT_ICACHE | \
553 CPU_FTR_STCX_CHECKS_ADDRESS | \
554 CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
555 CPU_FTR_DAWR | \
556 CPU_FTR_ARCH_206 | \
557 CPU_FTR_ARCH_207S)
558#else
559#define CPU_FTRS_DT_CPU_BASE (~0ul)
560#endif
561
Nicholas Piggindb5ae1c2018-02-21 05:08:31 +1000[diff] [blame]562#ifdef CONFIG_CPU_LITTLE_ENDIAN
563#define CPU_FTRS_ALWAYS \
564 (CPU_FTRS_POSSIBLE & ~CPU_FTR_HVMODE & CPU_FTRS_POWER7 & \
Michael Ellermance57c662018-07-19 14:37:57 +1000[diff] [blame]565 CPU_FTRS_POWER8E & CPU_FTRS_POWER8 & CPU_FTRS_POWER9 & \
566 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE)
Nicholas Piggindb5ae1c2018-02-21 05:08:31 +1000[diff] [blame]567#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]568#define CPU_FTRS_ALWAYS \
Nicholas Piggin471d7ff2018-02-21 05:08:29 +1000[diff] [blame]569 (CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
Michael Ellerman468a3302014-07-10 12:29:18 +1000[diff] [blame]570 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
Michael Ellerman3609e092014-08-06 15:42:17 +1000[diff] [blame]571 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
Michael Ellermance57c662018-07-19 14:37:57 +1000[diff] [blame]572 ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & CPU_FTRS_POWER9 & \
573 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE)
Nicholas Piggindb5ae1c2018-02-21 05:08:31 +1000[diff] [blame]574#endif /* CONFIG_CPU_LITTLE_ENDIAN */
Kumar Gala11ed0db2011-04-06 00:11:06 -0500[diff] [blame]575#endif
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]576#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]577enum {
578 CPU_FTRS_ALWAYS =
Christophe Leroy12c3f1f2019-08-26 15:52:14 +0000[diff] [blame]579#ifdef CONFIG_PPC_BOOK3S_601
580 CPU_FTRS_PPC601 &
581#elif defined(CONFIG_PPC_BOOK3S_32)
582 CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]583 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
584 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
585 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
586 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
587 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
588 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
Kim Phillipsaa42c692006-12-08 02:43:30 -0600[diff] [blame]589 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
590 CPU_FTRS_CLASSIC32 &
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]591#else
592 CPU_FTRS_GENERIC_32 &
593#endif
Christophe Leroy968159c2017-08-08 13:58:54 +0200[diff] [blame]594#ifdef CONFIG_PPC_8xx
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]595 CPU_FTRS_8XX &
596#endif
597#ifdef CONFIG_40x
598 CPU_FTRS_40X &
599#endif
600#ifdef CONFIG_44x
Benjamin Herrenschmidt6d2170b2008-12-18 19:13:22 +0000[diff] [blame]601 CPU_FTRS_44X & CPU_FTRS_440x6 &
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]602#endif
603#ifdef CONFIG_E200
604 CPU_FTRS_E200 &
605#endif
606#ifdef CONFIG_E500
Scott Wood06aae862011-12-20 15:34:14 +0000[diff] [blame]607 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
608#endif
609#ifdef CONFIG_PPC_E500MC
610 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]611#endif
Scott Wood73196cd32011-12-20 15:34:47 +0000[diff] [blame]612 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]613 CPU_FTRS_POSSIBLE,
614};
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]615#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]616
Ravi Bangoriaa6ba44e2020-05-14 16:47:28 +0530[diff] [blame^]617/*
618 * Maximum number of hw breakpoint supported on powerpc. Number of
619 * breakpoints supported by actual hw might be less than this.
620 */
621#define HBP_NUM_MAX 1
K.Prasad5aae8a52010-06-15 11:35:19 +0530[diff] [blame]622
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]623#endif /* !__ASSEMBLY__ */
624
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]625#endif /* __ASM_POWERPC_CPUTABLE_H */