Blame - arch/powerpc/include/asm/cputable.h - SHIFTPHONES/kernel/common

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Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	1	#ifndef __ASM_POWERPC_CPUTABLE_H
				2	#define __ASM_POWERPC_CPUTABLE_H
				3
Adrian Bunk	d1cdcf2	2008-06-24 03:48:21 +1000	[diff] [blame]	4
				5	#include <asm/asm-compat.h>
Michael Ellerman	c5157e5	2008-06-24 11:32:39 +1000	[diff] [blame]	6	#include <asm/feature-fixups.h>
David Howells	c3617f7	2012-10-09 09:47:26 +0100	[diff] [blame]	7	#include <uapi/asm/cputable.h>
Adrian Bunk	d1cdcf2	2008-06-24 03:48:21 +1000	[diff] [blame]	8
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	9	#ifndef __ASSEMBLY__
				10
				11	/* This structure can grow, it's real size is used by head.S code
				12	* via the mkdefs mechanism.
				13	*/
				14	struct cpu_spec;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	15
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	16	typedef void (cpu_setup_t)(unsigned long offset, struct cpu_spec spec);
Olof Johansson	f39b7a5	2006-08-11 00:07:08 -0500	[diff] [blame]	17	typedef void (*cpu_restore_t)(void);
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	18
Anton Blanchard	32a3399	2006-01-09 15:41:31 +1100	[diff] [blame]	19	enum powerpc_oprofile_type {
Andy Whitcroft	7a45fb1	2006-01-13 12:35:49 +0000	[diff] [blame]	20	PPC_OPROFILE_INVALID = 0,
				21	PPC_OPROFILE_RS64 = 1,
				22	PPC_OPROFILE_POWER4 = 2,
				23	PPC_OPROFILE_G4 = 3,
Andy Fleming	39aef68	2008-02-04 18:27:55 -0600	[diff] [blame]	24	PPC_OPROFILE_FSL_EMB = 4,
Maynard Johnson	18f2190	2006-11-20 18:45:16 +0100	[diff] [blame]	25	PPC_OPROFILE_CELL = 5,
Olof Johansson	25fc530	2007-04-18 16:38:21 +1000	[diff] [blame]	26	PPC_OPROFILE_PA6T = 6,
Anton Blanchard	32a3399	2006-01-09 15:41:31 +1100	[diff] [blame]	27	};
				28
Olof Johansson	1bd2e5a	2007-01-28 21:23:54 -0600	[diff] [blame]	29	enum powerpc_pmc_type {
				30	PPC_PMC_DEFAULT = 0,
				31	PPC_PMC_IBM = 1,
				32	PPC_PMC_PA6T = 2,
Benjamin Herrenschmidt	b950bdd	2008-08-18 14:23:51 +1000	[diff] [blame]	33	PPC_PMC_G4 = 3,
Olof Johansson	1bd2e5a	2007-01-28 21:23:54 -0600	[diff] [blame]	34	};
				35
Benjamin Herrenschmidt	47c0bd1	2007-12-21 15:39:21 +1100	[diff] [blame]	36	struct pt_regs;
				37
				38	extern int machine_check_generic(struct pt_regs *regs);
				39	extern int machine_check_4xx(struct pt_regs *regs);
				40	extern int machine_check_440A(struct pt_regs *regs);
Scott Wood	fe04b11	2010-04-08 00:38:22 -0500	[diff] [blame]	41	extern int machine_check_e500mc(struct pt_regs *regs);
Benjamin Herrenschmidt	47c0bd1	2007-12-21 15:39:21 +1100	[diff] [blame]	42	extern int machine_check_e500(struct pt_regs *regs);
				43	extern int machine_check_e200(struct pt_regs *regs);
Dave Kleikamp	fc5e709	2010-03-05 03:43:18 +0000	[diff] [blame]	44	extern int machine_check_47x(struct pt_regs *regs);
Benjamin Herrenschmidt	47c0bd1	2007-12-21 15:39:21 +1100	[diff] [blame]	45
Paul Mackerras	87a72f9	2007-10-04 14:18:01 +1000	[diff] [blame]	46	/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	47	struct cpu_spec {
				48	/* CPU is matched via (PVR & pvr_mask) == pvr_value */
				49	unsigned int pvr_mask;
				50	unsigned int pvr_value;
				51
				52	char *cpu_name;
				53	unsigned long cpu_features; /* Kernel features */
				54	unsigned int cpu_user_features; /* Userland features */
Michael Neuling	2171364	2013-04-17 17:33:11 +0000	[diff] [blame^]	55	unsigned int cpu_user_features2; /* Userland features v2 */
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	56	unsigned int mmu_features; /* MMU features */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	57
				58	/* cache line sizes */
				59	unsigned int icache_bsize;
				60	unsigned int dcache_bsize;
				61
				62	/* number of performance monitor counters */
				63	unsigned int num_pmcs;
Olof Johansson	1bd2e5a	2007-01-28 21:23:54 -0600	[diff] [blame]	64	enum powerpc_pmc_type pmc_type;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	65
				66	/* this is called to initialize various CPU bits like L1 cache,
				67	* BHT, SPD, etc... from head.S before branching to identify_machine
				68	*/
				69	cpu_setup_t cpu_setup;
Olof Johansson	f39b7a5	2006-08-11 00:07:08 -0500	[diff] [blame]	70	/* Used to restore cpu setup on secondary processors and at resume */
				71	cpu_restore_t cpu_restore;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	72
				73	/* Used by oprofile userspace to select the right counters */
				74	char *oprofile_cpu_type;
				75
				76	/* Processor specific oprofile operations */
Anton Blanchard	32a3399	2006-01-09 15:41:31 +1100	[diff] [blame]	77	enum powerpc_oprofile_type oprofile_type;
Paul Mackerras	80f15dc	2006-01-14 10:11:39 +1100	[diff] [blame]	78
Michael Neuling	e78dbc8	2006-06-08 14:42:34 +1000	[diff] [blame]	79	/* Bit locations inside the mmcra change */
				80	unsigned long oprofile_mmcra_sihv;
				81	unsigned long oprofile_mmcra_sipr;
				82
				83	/* Bits to clear during an oprofile exception */
				84	unsigned long oprofile_mmcra_clear;
				85
Paul Mackerras	80f15dc	2006-01-14 10:11:39 +1100	[diff] [blame]	86	/* Name of processor class, for the ELF AT_PLATFORM entry */
				87	char *platform;
Benjamin Herrenschmidt	47c0bd1	2007-12-21 15:39:21 +1100	[diff] [blame]	88
				89	/* Processor specific machine check handling. Return negative
				90	* if the error is fatal, 1 if it was fully recovered and 0 to
				91	* pass up (not CPU originated) */
				92	int (machine_check)(struct pt_regs regs);
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	93	};
				94
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	95	extern struct cpu_spec *cur_cpu_spec;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	96
Benjamin Herrenschmidt	42c4aaa	2006-10-24 16:42:40 +1000	[diff] [blame]	97	extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
				98
Paul Mackerras	974a76f	2006-11-10 20:38:53 +1100	[diff] [blame]	99	extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
Benjamin Herrenschmidt	0909c8c	2006-10-20 11:47:18 +1000	[diff] [blame]	100	extern void do_feature_fixups(unsigned long value, void *fixup_start,
				101	void *fixup_end);
Paul Mackerras	9b6b563	2005-10-06 12:06:20 +1000	[diff] [blame]	102
Nathan Lynch	9115d13	2008-07-16 09:58:51 +1000	[diff] [blame]	103	extern const char *powerpc_base_platform;
				104
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	105	#endif /* __ASSEMBLY__ */
				106
				107	/* CPU kernel features */
				108
				109	/* Retain the 32b definitions all use bottom half of word */
Michael Neuling	cde4d49	2012-12-20 14:06:39 +0000	[diff] [blame]	110	#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
				111	#define CPU_FTR_L2CR ASM_CONST(0x00000002)
				112	#define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
				113	#define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
				114	#define CPU_FTR_TAU ASM_CONST(0x00000010)
				115	#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
				116	#define CPU_FTR_USE_TB ASM_CONST(0x00000040)
				117	#define CPU_FTR_L2CSR ASM_CONST(0x00000080)
				118	#define CPU_FTR_601 ASM_CONST(0x00000100)
				119	#define CPU_FTR_DBELL ASM_CONST(0x00000200)
				120	#define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
				121	#define CPU_FTR_L3CR ASM_CONST(0x00000800)
				122	#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
				123	#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
				124	#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
				125	#define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
				126	#define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
				127	#define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
				128	#define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
				129	#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
				130	#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
				131	#define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
				132	#define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
				133	#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
				134	#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
				135	#define CPU_FTR_SPE ASM_CONST(0x02000000)
				136	#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
				137	#define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
				138	#define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
				139	#define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
				140	#define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	141
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	142	/*
				143	* Add the 64-bit processor unique features in the top half of the word;
				144	* on 32-bit, make the names available but defined to be 0.
				145	*/
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	146	#ifdef __powerpc64__
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	147	#define LONG_ASM_CONST(x) ASM_CONST(x)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	148	#else
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	149	#define LONG_ASM_CONST(x) 0
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	150	#endif
				151
Michael Neuling	1580b3b	2012-12-20 14:06:40 +0000	[diff] [blame]	152	#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
				153	#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
				154	#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
				155	#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000000800000000)
				156	#define CPU_FTR_IABR LONG_ASM_CONST(0x0000001000000000)
				157	#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
				158	#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
				159	#define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
				160	#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
				161	#define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
				162	#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
				163	#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
				164	#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
				165	#define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
				166	#define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
				167	#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
				168	#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
				169	#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
				170	#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
				171	#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
				172	#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
				173	#define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000)
				174	#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
				175	#define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
				176	#define CPU_FTR_BCTAR LONG_ASM_CONST(0x0100000000000000)
				177	#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
Michael Neuling	79879c1	2012-12-20 14:06:42 +0000	[diff] [blame]	178	#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	179
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	180	#ifndef __ASSEMBLY__
				181
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	182	#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE \| CPU_FTR_NODSISRALIGN)
				183
				184	#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB \| MMU_FTR_TLBIEL \| \
				185	MMU_FTR_16M_PAGE)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	186
				187	/* We only set the altivec features if the kernel was compiled with altivec
				188	* support
				189	*/
				190	#ifdef CONFIG_ALTIVEC
				191	#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
				192	#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
				193	#else
				194	#define CPU_FTR_ALTIVEC_COMP 0
				195	#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
				196	#endif
				197
Michael Neuling	b962ce9	2008-06-25 14:07:18 +1000	[diff] [blame]	198	/* We only set the VSX features if the kernel was compiled with VSX
				199	* support
				200	*/
				201	#ifdef CONFIG_VSX
				202	#define CPU_FTR_VSX_COMP CPU_FTR_VSX
				203	#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
				204	#else
				205	#define CPU_FTR_VSX_COMP 0
				206	#define PPC_FEATURE_HAS_VSX_COMP 0
				207	#endif
				208
Kumar Gala	5e14d21	2007-09-13 01:44:20 -0500	[diff] [blame]	209	/* We only set the spe features if the kernel was compiled with spe
				210	* support
				211	*/
				212	#ifdef CONFIG_SPE
				213	#define CPU_FTR_SPE_COMP CPU_FTR_SPE
				214	#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
				215	#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
				216	#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
				217	#else
				218	#define CPU_FTR_SPE_COMP 0
				219	#define PPC_FEATURE_HAS_SPE_COMP 0
				220	#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
				221	#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
				222	#endif
				223
Michael Neuling	6a6d541	2013-02-13 16:21:29 +0000	[diff] [blame]	224	/* We only set the TM feature if the kernel was compiled with TM supprt */
				225	#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
				226	#define CPU_FTR_TM_COMP CPU_FTR_TM
				227	#else
				228	#define CPU_FTR_TM_COMP 0
				229	#endif
				230
Scott Wood	11af119	2007-09-14 15:32:14 -0500	[diff] [blame]	231	/* We need to mark all pages as being coherent if we're SMP or we have a
				232	* 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
				233	* require it for PCI "streaming/prefetch" to work properly.
Piotr Ziecik	c931092	2009-03-17 09:17:50 -0600	[diff] [blame]	234	* This is also required by 52xx family.
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	235	*/
Kumar Gala	1775dbb	2006-02-22 09:46:02 -0600	[diff] [blame]	236	#if defined(CONFIG_SMP) \|\| defined(CONFIG_MPC10X_BRIDGE) \
Piotr Ziecik	c931092	2009-03-17 09:17:50 -0600	[diff] [blame]	237	\|\| defined(CONFIG_PPC_83xx) \|\| defined(CONFIG_8260) \
				238	\|\| defined(CONFIG_PPC_MPC52xx)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	239	#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
				240	#else
				241	#define CPU_FTR_COMMON 0
				242	#endif
				243
				244	/* The powersave features NAP & DOZE seems to confuse BDI when
				245	debugging. So if a BDI is used, disable theses
				246	*/
				247	#ifndef CONFIG_BDI_SWITCH
				248	#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
				249	#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
				250	#else
				251	#define CPU_FTR_MAYBE_CAN_DOZE 0
				252	#define CPU_FTR_MAYBE_CAN_NAP 0
				253	#endif
				254
				255	#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
				256	!defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
				257	!defined(CONFIG_BOOKE))
				258
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	259	#define CPU_FTRS_PPC601 (CPU_FTR_COMMON \| CPU_FTR_601 \| \
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	260	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_UNIFIED_ID_CACHE)
				261	#define CPU_FTRS_603 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	262	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	263	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	264	#define CPU_FTRS_604 (CPU_FTR_COMMON \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	265	CPU_FTR_USE_TB \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	266	#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	267	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	268	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	269	#define CPU_FTRS_740 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	270	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	271	CPU_FTR_TAU \| CPU_FTR_MAYBE_CAN_NAP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	272	CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	273	#define CPU_FTRS_750 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	274	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	275	CPU_FTR_TAU \| CPU_FTR_MAYBE_CAN_NAP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	276	CPU_FTR_PPC_LE)
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	277	#define CPU_FTRS_750CL (CPU_FTRS_750)
Josh Boyer	b6f41cc	2007-07-03 02:06:53 +1000	[diff] [blame]	278	#define CPU_FTRS_750FX1 (CPU_FTRS_750 \| CPU_FTR_DUAL_PLL_750FX \| CPU_FTR_NO_DPM)
				279	#define CPU_FTRS_750FX2 (CPU_FTRS_750 \| CPU_FTR_NO_DPM)
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	280	#define CPU_FTRS_750FX (CPU_FTRS_750 \| CPU_FTR_DUAL_PLL_750FX)
Josh Boyer	b6f41cc	2007-07-03 02:06:53 +1000	[diff] [blame]	281	#define CPU_FTRS_750GX (CPU_FTRS_750FX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	282	#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	283	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	284	CPU_FTR_ALTIVEC_COMP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	285	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	286	#define CPU_FTRS_7400 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	287	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	288	CPU_FTR_TAU \| CPU_FTR_ALTIVEC_COMP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	289	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	290	#define CPU_FTRS_7450_20 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	291	CPU_FTR_USE_TB \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	292	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	293	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	294	#define CPU_FTRS_7450_21 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	295	CPU_FTR_USE_TB \| \
				296	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	297	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	298	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_L3_DISABLE_NAP \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	299	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	300	#define CPU_FTRS_7450_23 (CPU_FTR_COMMON \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	301	CPU_FTR_USE_TB \| CPU_FTR_NEED_PAIRED_STWCX \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	302	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	303	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	304	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	305	#define CPU_FTRS_7455_1 (CPU_FTR_COMMON \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	306	CPU_FTR_USE_TB \| CPU_FTR_NEED_PAIRED_STWCX \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	307	CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| CPU_FTR_L3CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	308	CPU_FTR_SPEC7450 \| CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	309	#define CPU_FTRS_7455_20 (CPU_FTR_COMMON \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	310	CPU_FTR_USE_TB \| CPU_FTR_NEED_PAIRED_STWCX \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	311	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	312	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	313	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_L3_DISABLE_NAP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	314	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	315	#define CPU_FTRS_7455 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	316	CPU_FTR_USE_TB \| \
				317	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	318	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| CPU_FTR_NAP_DISABLE_L2_PR \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	319	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	320	#define CPU_FTRS_7447_10 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	321	CPU_FTR_USE_TB \| \
				322	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	323	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| CPU_FTR_NAP_DISABLE_L2_PR \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	324	CPU_FTR_NEED_COHERENT \| CPU_FTR_NO_BTIC \| CPU_FTR_PPC_LE \| \
				325	CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	326	#define CPU_FTRS_7447 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	327	CPU_FTR_USE_TB \| \
				328	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	329	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| CPU_FTR_NAP_DISABLE_L2_PR \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	330	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	331	#define CPU_FTRS_7447A (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	332	CPU_FTR_USE_TB \| \
				333	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	334	CPU_FTR_SPEC7450 \| CPU_FTR_NAP_DISABLE_L2_PR \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	335	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	336	#define CPU_FTRS_7448 (CPU_FTR_COMMON \| \
James.Yang	3d37254	2007-05-02 16:34:43 -0500	[diff] [blame]	337	CPU_FTR_USE_TB \| \
				338	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	339	CPU_FTR_SPEC7450 \| CPU_FTR_NAP_DISABLE_L2_PR \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	340	CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	341	#define CPU_FTRS_82XX (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	342	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB)
Scott Wood	11af119	2007-09-14 15:32:14 -0500	[diff] [blame]	343	#define CPU_FTRS_G2_LE (CPU_FTR_COMMON \| CPU_FTR_MAYBE_CAN_DOZE \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	344	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	345	#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	346	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	347	CPU_FTR_COMMON)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	348	#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	349	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP \| \
Kim Phillips	aa42c69	2006-12-08 02:43:30 -0600	[diff] [blame]	350	CPU_FTR_COMMON \| CPU_FTR_FPU_UNAVAILABLE)
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	351	#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON \| CPU_FTR_USE_TB)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	352	#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
Benjamin Herrenschmidt	8309ce72	2008-12-12 17:33:25 +1100	[diff] [blame]	353	#define CPU_FTRS_40X (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| CPU_FTR_NOEXECUTE)
				354	#define CPU_FTRS_44X (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| CPU_FTR_NOEXECUTE)
Benjamin Herrenschmidt	6d2170b	2008-12-18 19:13:22 +0000	[diff] [blame]	355	#define CPU_FTRS_440x6 (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| CPU_FTR_NOEXECUTE \| \
				356	CPU_FTR_INDEXED_DCR)
Dave Kleikamp	e7f75ad	2010-03-05 10:43:12 +0000	[diff] [blame]	357	#define CPU_FTRS_47X (CPU_FTRS_440x6)
Kumar Gala	5e14d21	2007-09-13 01:44:20 -0500	[diff] [blame]	358	#define CPU_FTRS_E200 (CPU_FTR_USE_TB \| CPU_FTR_SPE_COMP \| \
				359	CPU_FTR_NODSISRALIGN \| CPU_FTR_COHERENT_ICACHE \| \
Scott Wood	52b066f	2011-12-20 15:34:12 +0000	[diff] [blame]	360	CPU_FTR_UNIFIED_ID_CACHE \| CPU_FTR_NOEXECUTE \| \
				361	CPU_FTR_DEBUG_LVL_EXC)
Kumar Gala	fc4033b	2008-06-18 16:26:52 -0500	[diff] [blame]	362	#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| \
Benjamin Herrenschmidt	8309ce72	2008-12-12 17:33:25 +1100	[diff] [blame]	363	CPU_FTR_SPE_COMP \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_NODSISRALIGN \| \
				364	CPU_FTR_NOEXECUTE)
Kumar Gala	fc4033b	2008-06-18 16:26:52 -0500	[diff] [blame]	365	#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	366	CPU_FTR_SPE_COMP \| CPU_FTR_MAYBE_CAN_NAP \| \
Benjamin Herrenschmidt	8309ce72	2008-12-12 17:33:25 +1100	[diff] [blame]	367	CPU_FTR_NODSISRALIGN \| CPU_FTR_NOEXECUTE)
Scott Wood	d51ad91	2010-05-27 17:35:12 -0500	[diff] [blame]	368	#define CPU_FTRS_E500MC (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| \
Kumar Gala	620165f	2009-02-12 13:54:53 +0000	[diff] [blame]	369	CPU_FTR_L2CSR \| CPU_FTR_LWSYNC \| CPU_FTR_NOEXECUTE \| \
Scott Wood	73196cd3	2011-12-20 15:34:47 +0000	[diff] [blame]	370	CPU_FTR_DBELL \| CPU_FTR_DEBUG_LVL_EXC \| CPU_FTR_EMB_HV)
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	371	#define CPU_FTRS_E5500 (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| \
				372	CPU_FTR_L2CSR \| CPU_FTR_LWSYNC \| CPU_FTR_NOEXECUTE \| \
Kumar Gala	d36b4c4	2011-04-06 00:18:48 -0500	[diff] [blame]	373	CPU_FTR_DBELL \| CPU_FTR_POPCNTB \| CPU_FTR_POPCNTD \| \
Scott Wood	73196cd3	2011-12-20 15:34:47 +0000	[diff] [blame]	374	CPU_FTR_DEBUG_LVL_EXC \| CPU_FTR_EMB_HV)
Kumar Gala	1024184	2011-11-06 11:51:07 -0600	[diff] [blame]	375	#define CPU_FTRS_E6500 (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| \
				376	CPU_FTR_L2CSR \| CPU_FTR_LWSYNC \| CPU_FTR_NOEXECUTE \| \
				377	CPU_FTR_DBELL \| CPU_FTR_POPCNTB \| CPU_FTR_POPCNTD \| \
Scott Wood	9de6fe9	2012-04-11 15:27:52 -0500	[diff] [blame]	378	CPU_FTR_DEBUG_LVL_EXC \| CPU_FTR_EMB_HV)
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	379	#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON \| CPU_FTR_NODSISRALIGN)
Michael Ellerman	0b8e2e1	2006-11-23 00:46:46 +0100	[diff] [blame]	380
				381	/* 64-bit CPUs */
Anton Blanchard	5a0e9b5	2010-02-10 01:10:25 +0000	[diff] [blame]	382	#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	383	CPU_FTR_IABR \| CPU_FTR_PPC_LE)
Anton Blanchard	5a0e9b5	2010-02-10 01:10:25 +0000	[diff] [blame]	384	#define CPU_FTRS_RS64 (CPU_FTR_USE_TB \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	385	CPU_FTR_IABR \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	386	CPU_FTR_MMCRA \| CPU_FTR_CTRL)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	387	#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	388	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Anton Blanchard	f89451f	2010-08-11 01:40:27 +0000	[diff] [blame]	389	CPU_FTR_MMCRA \| CPU_FTR_CP_USE_DCBTZ \| \
				390	CPU_FTR_STCX_CHECKS_ADDRESS)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	391	#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Paul Mackerras	969391c	2011-06-29 00:26:11 +0000	[diff] [blame]	392	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| CPU_FTR_ARCH_201 \| \
Mark Nelson	2a92943	2008-08-22 14:36:19 +1000	[diff] [blame]	393	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_CAN_NAP \| CPU_FTR_MMCRA \| \
Paul Mackerras	969391c	2011-06-29 00:26:11 +0000	[diff] [blame]	394	CPU_FTR_CP_USE_DCBTZ \| CPU_FTR_STCX_CHECKS_ADDRESS \| \
				395	CPU_FTR_HVMODE)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	396	#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	397	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	398	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	399	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_PURR \| \
				400	CPU_FTR_STCX_CHECKS_ADDRESS \| CPU_FTR_POPCNTB)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	401	#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	402	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Anton Blanchard	03054d5	2006-04-29 09:51:06 +1000	[diff] [blame]	403	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	404	CPU_FTR_COHERENT_ICACHE \| \
Anton Blanchard	4c198557	2006-12-08 17:46:58 +1100	[diff] [blame]	405	CPU_FTR_PURR \| CPU_FTR_SPURR \| CPU_FTR_REAL_LE \| \
Anton Blanchard	f89451f	2010-08-11 01:40:27 +0000	[diff] [blame]	406	CPU_FTR_DSCR \| CPU_FTR_UNALIGNED_LD_STD \| \
Paul Mackerras	48404f2	2011-05-01 19:48:20 +0000	[diff] [blame]	407	CPU_FTR_STCX_CHECKS_ADDRESS \| CPU_FTR_POPCNTB \| CPU_FTR_CFAR)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	408	#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Paul Mackerras	969391c	2011-06-29 00:26:11 +0000	[diff] [blame]	409	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| CPU_FTR_ARCH_206 \|\
Michael Neuling	e952e6c	2008-06-18 10:47:26 +1000	[diff] [blame]	410	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	411	CPU_FTR_COHERENT_ICACHE \| \
Michael Neuling	e952e6c	2008-06-18 10:47:26 +1000	[diff] [blame]	412	CPU_FTR_PURR \| CPU_FTR_SPURR \| CPU_FTR_REAL_LE \| \
Anton Blanchard	f89451f	2010-08-11 01:40:27 +0000	[diff] [blame]	413	CPU_FTR_DSCR \| CPU_FTR_SAO \| CPU_FTR_ASYM_SMT \| \
Tseng-Hui (Frank) Lin	851d2e2	2011-05-02 20:43:04 +0000	[diff] [blame]	414	CPU_FTR_STCX_CHECKS_ADDRESS \| CPU_FTR_POPCNTB \| CPU_FTR_POPCNTD \| \
Haren Myneni	d2613868	2012-12-06 21:47:42 +0000	[diff] [blame]	415	CPU_FTR_ICSWX \| CPU_FTR_CFAR \| CPU_FTR_HVMODE \| \
				416	CPU_FTR_VMX_COPY \| CPU_FTR_HAS_PPR)
Michael Neuling	71e1849	2012-10-30 19:34:15 +0000	[diff] [blame]	417	#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
				418	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| CPU_FTR_ARCH_206 \|\
				419	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
				420	CPU_FTR_COHERENT_ICACHE \| \
				421	CPU_FTR_PURR \| CPU_FTR_SPURR \| CPU_FTR_REAL_LE \| \
				422	CPU_FTR_DSCR \| CPU_FTR_SAO \| \
				423	CPU_FTR_STCX_CHECKS_ADDRESS \| CPU_FTR_POPCNTB \| CPU_FTR_POPCNTD \| \
Ian Munsie	e5e84f0	2012-11-14 18:49:50 +0000	[diff] [blame]	424	CPU_FTR_ICSWX \| CPU_FTR_CFAR \| CPU_FTR_HVMODE \| CPU_FTR_VMX_COPY \| \
Michael Neuling	b9eaee5	2013-02-13 16:21:42 +0000	[diff] [blame]	425	CPU_FTR_DBELL \| CPU_FTR_HAS_PPR \| CPU_FTR_DAWR \| CPU_FTR_BCTAR \| \
				426	CPU_FTR_TM_COMP)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	427	#define CPU_FTRS_CELL (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	428	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	429	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	430	CPU_FTR_PAUSE_ZERO \| CPU_FTR_CELL_TB_BUG \| CPU_FTR_CP_USE_DCBTZ \| \
Mark Nelson	4ec577a	2008-10-27 00:43:02 +0000	[diff] [blame]	431	CPU_FTR_UNALIGNED_LD_STD)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	432	#define CPU_FTRS_PA6T (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	433	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_ALTIVEC_COMP \| \
				434	CPU_FTR_PURR \| CPU_FTR_REAL_LE)
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	435	#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB \| CPU_FTR_PPCAS_ARCH_V2)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	436
Benjamin Herrenschmidt	76b4eda	2011-04-14 22:32:01 +0000	[diff] [blame]	437	#define CPU_FTRS_A2 (CPU_FTR_USE_TB \| CPU_FTR_SMT \| CPU_FTR_DBELL \| \
Jimi Xenidis	fac26ad	2011-09-29 10:55:13 +0000	[diff] [blame]	438	CPU_FTR_NOEXECUTE \| CPU_FTR_NODSISRALIGN \| CPU_FTR_ICSWX)
Benjamin Herrenschmidt	76b4eda	2011-04-14 22:32:01 +0000	[diff] [blame]	439
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	440	#ifdef __powerpc64__
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	441	#ifdef CONFIG_PPC_BOOK3E
Kumar Gala	1024184	2011-11-06 11:51:07 -0600	[diff] [blame]	442	#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 \| CPU_FTRS_E5500 \| CPU_FTRS_A2)
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	443	#else
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	444	#define CPU_FTRS_POSSIBLE \
				445	(CPU_FTRS_POWER3 \| CPU_FTRS_RS64 \| CPU_FTRS_POWER4 \| \
Anton Blanchard	03054d5	2006-04-29 09:51:06 +1000	[diff] [blame]	446	CPU_FTRS_PPC970 \| CPU_FTRS_POWER5 \| CPU_FTRS_POWER6 \| \
Michael Neuling	71e1849	2012-10-30 19:34:15 +0000	[diff] [blame]	447	CPU_FTRS_POWER7 \| CPU_FTRS_POWER8 \| CPU_FTRS_CELL \| \
				448	CPU_FTRS_PA6T \| CPU_FTR_VSX)
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	449	#endif
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	450	#else
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	451	enum {
				452	CPU_FTRS_POSSIBLE =
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	453	#if CLASSIC_PPC
				454	CPU_FTRS_PPC601 \| CPU_FTRS_603 \| CPU_FTRS_604 \| CPU_FTRS_740_NOTAU \|
				455	CPU_FTRS_740 \| CPU_FTRS_750 \| CPU_FTRS_750FX1 \|
				456	CPU_FTRS_750FX2 \| CPU_FTRS_750FX \| CPU_FTRS_750GX \|
				457	CPU_FTRS_7400_NOTAU \| CPU_FTRS_7400 \| CPU_FTRS_7450_20 \|
				458	CPU_FTRS_7450_21 \| CPU_FTRS_7450_23 \| CPU_FTRS_7455_1 \|
				459	CPU_FTRS_7455_20 \| CPU_FTRS_7455 \| CPU_FTRS_7447_10 \|
				460	CPU_FTRS_7447 \| CPU_FTRS_7447A \| CPU_FTRS_82XX \|
Kim Phillips	aa42c69	2006-12-08 02:43:30 -0600	[diff] [blame]	461	CPU_FTRS_G2_LE \| CPU_FTRS_E300 \| CPU_FTRS_E300C2 \|
				462	CPU_FTRS_CLASSIC32 \|
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	463	#else
				464	CPU_FTRS_GENERIC_32 \|
				465	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	466	#ifdef CONFIG_8xx
				467	CPU_FTRS_8XX \|
				468	#endif
				469	#ifdef CONFIG_40x
				470	CPU_FTRS_40X \|
				471	#endif
				472	#ifdef CONFIG_44x
Benjamin Herrenschmidt	6d2170b	2008-12-18 19:13:22 +0000	[diff] [blame]	473	CPU_FTRS_44X \| CPU_FTRS_440x6 \|
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	474	#endif
Dave Kleikamp	e7f75ad	2010-03-05 10:43:12 +0000	[diff] [blame]	475	#ifdef CONFIG_PPC_47x
Dave Kleikamp	c48d0db	2011-01-26 06:17:58 +0000	[diff] [blame]	476	CPU_FTRS_47X \| CPU_FTR_476_DD2 \|
Dave Kleikamp	e7f75ad	2010-03-05 10:43:12 +0000	[diff] [blame]	477	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	478	#ifdef CONFIG_E200
				479	CPU_FTRS_E200 \|
				480	#endif
				481	#ifdef CONFIG_E500
Scott Wood	06aae86	2011-12-20 15:34:14 +0000	[diff] [blame]	482	CPU_FTRS_E500 \| CPU_FTRS_E500_2 \|
				483	#endif
				484	#ifdef CONFIG_PPC_E500MC
				485	CPU_FTRS_E500MC \| CPU_FTRS_E5500 \| CPU_FTRS_E6500 \|
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	486	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	487	0,
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	488	};
				489	#endif /* __powerpc64__ */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	490
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	491	#ifdef __powerpc64__
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	492	#ifdef CONFIG_PPC_BOOK3E
Kumar Gala	1024184	2011-11-06 11:51:07 -0600	[diff] [blame]	493	#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2)
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	494	#else
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	495	#define CPU_FTRS_ALWAYS \
				496	(CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
Anton Blanchard	03054d5	2006-04-29 09:51:06 +1000	[diff] [blame]	497	CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
Michael Neuling	e952e6c	2008-06-18 10:47:26 +1000	[diff] [blame]	498	CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	499	#endif
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	500	#else
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	501	enum {
				502	CPU_FTRS_ALWAYS =
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	503	#if CLASSIC_PPC
				504	CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
				505	CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
				506	CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
				507	CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
				508	CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
				509	CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
				510	CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
Kim Phillips	aa42c69	2006-12-08 02:43:30 -0600	[diff] [blame]	511	CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
				512	CPU_FTRS_CLASSIC32 &
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	513	#else
				514	CPU_FTRS_GENERIC_32 &
				515	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	516	#ifdef CONFIG_8xx
				517	CPU_FTRS_8XX &
				518	#endif
				519	#ifdef CONFIG_40x
				520	CPU_FTRS_40X &
				521	#endif
				522	#ifdef CONFIG_44x
Benjamin Herrenschmidt	6d2170b	2008-12-18 19:13:22 +0000	[diff] [blame]	523	CPU_FTRS_44X & CPU_FTRS_440x6 &
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	524	#endif
				525	#ifdef CONFIG_E200
				526	CPU_FTRS_E200 &
				527	#endif
				528	#ifdef CONFIG_E500
Scott Wood	06aae86	2011-12-20 15:34:14 +0000	[diff] [blame]	529	CPU_FTRS_E500 & CPU_FTRS_E500_2 &
				530	#endif
				531	#ifdef CONFIG_PPC_E500MC
				532	CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	533	#endif
Scott Wood	73196cd3	2011-12-20 15:34:47 +0000	[diff] [blame]	534	~CPU_FTR_EMB_HV & /* can be removed at runtime */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	535	CPU_FTRS_POSSIBLE,
				536	};
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	537	#endif /* __powerpc64__ */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	538
				539	static inline int cpu_has_feature(unsigned long feature)
				540	{
				541	return (CPU_FTRS_ALWAYS & feature) \|\|
				542	(CPU_FTRS_POSSIBLE
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	543	& cur_cpu_spec->cpu_features
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	544	& feature);
				545	}
				546
K.Prasad	5aae8a5	2010-06-15 11:35:19 +0530	[diff] [blame]	547	#define HBP_NUM 1
K.Prasad	5aae8a5	2010-06-15 11:35:19 +0530	[diff] [blame]	548
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	549	#endif /* !__ASSEMBLY__ */
				550
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	551	#endif /* __ASM_POWERPC_CPUTABLE_H */