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Greg Kroah-Hartmane3b3d0f2017-11-06 18:11:51 +01001// SPDX-License-Identifier: GPL-2.0
Linus Torvalds1da177e2005-04-16 15:20:36 -07002/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07003 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
Paul Mundtf43dc232011-01-13 15:06:28 +09005 * Copyright (C) 2002 - 2011 Paul Mundt
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01006 * Copyright (C) 2015 Glider bvba
Markus Brunner3ea6bc32007-08-20 08:59:33 +09007 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
Magnus Dammd89ddd12007-07-25 11:42:56 +090016 * Removed SH7300 support (Jul 2007).
Linus Torvalds1da177e2005-04-16 15:20:36 -070017 */
Paul Mundt0b3d4ef2007-03-14 13:22:37 +090018#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19#define SUPPORT_SYSRQ
20#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070021
22#undef DEBUG
23
Paul Mundt85f094e2008-04-25 16:04:20 +090024#include <linux/clk.h>
Laurent Pinchart8fb96312013-12-06 10:59:10 +010025#include <linux/console.h>
Paul Mundtfa5da2f2007-03-08 17:27:37 +090026#include <linux/ctype.h>
Laurent Pinchart8fb96312013-12-06 10:59:10 +010027#include <linux/cpufreq.h>
28#include <linux/delay.h>
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +090029#include <linux/dmaengine.h>
Magnus Damm5beabc72011-08-02 09:42:54 +000030#include <linux/dma-mapping.h>
Laurent Pinchart8fb96312013-12-06 10:59:10 +010031#include <linux/err.h>
32#include <linux/errno.h>
Laurent Pinchart8fb96312013-12-06 10:59:10 +010033#include <linux/init.h>
34#include <linux/interrupt.h>
35#include <linux/ioport.h>
Ulrich Hechtb96408b2018-02-15 13:02:41 +010036#include <linux/ktime.h>
Laurent Pinchart8fb96312013-12-06 10:59:10 +010037#include <linux/major.h>
38#include <linux/module.h>
39#include <linux/mm.h>
Bastian Hecht20bdcab2013-12-06 10:59:54 +010040#include <linux/of.h>
Geert Uytterhoeven6e605a02017-10-04 14:21:56 +020041#include <linux/of_device.h>
Laurent Pinchart8fb96312013-12-06 10:59:10 +010042#include <linux/platform_device.h>
43#include <linux/pm_runtime.h>
44#include <linux/scatterlist.h>
45#include <linux/serial.h>
46#include <linux/serial_sci.h>
47#include <linux/sh_dma.h>
48#include <linux/slab.h>
49#include <linux/string.h>
50#include <linux/sysrq.h>
51#include <linux/timer.h>
52#include <linux/tty.h>
53#include <linux/tty_flip.h>
Paul Mundt85f094e2008-04-25 16:04:20 +090054
55#ifdef CONFIG_SUPERH
Paul Mundte108b2c2006-09-27 16:32:13 +090056#include <asm/sh_bios.h>
Paul Mundtb7a76e42006-02-01 03:06:06 -080057#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070058
Geert Uytterhoevenf907c9e2016-06-03 12:00:04 +020059#include "serial_mctrl_gpio.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070060#include "sh-sci.h"
61
Laurent Pinchart89b5c1a2013-12-06 10:59:52 +010062/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
Chris Brandt628c5342018-07-31 05:41:39 -050068 SCIx_DRI_IRQ,
69 SCIx_TEI_IRQ,
Laurent Pinchart89b5c1a2013-12-06 10:59:52 +010070 SCIx_NR_IRQS,
71
72 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73};
74
75#define SCIx_IRQ_IS_MUXED(port) \
76 ((port)->irqs[SCIx_ERI_IRQ] == \
77 (port)->irqs[SCIx_RXI_IRQ]) || \
78 ((port)->irqs[SCIx_ERI_IRQ] && \
79 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +010081enum SCI_CLKS {
82 SCI_FCK, /* Functional Clock */
Geert Uytterhoeven6af27bf2015-11-18 11:12:26 +010083 SCI_SCK, /* Optional External Clock */
Geert Uytterhoeven1270f862015-11-18 11:25:53 +010084 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
85 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +010086 SCI_NUM_CLKS
87};
88
Geert Uytterhoeven69eee8e2016-01-04 14:45:21 +010089/* Bit x set means sampling rate x + 1 is supported */
90#define SCI_SR(x) BIT((x) - 1)
91#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
92
Geert Uytterhoeven92a05742016-01-04 14:45:22 +010093#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
94 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
95 SCI_SR(19) | SCI_SR(27)
96
Geert Uytterhoeven69eee8e2016-01-04 14:45:21 +010097#define min_sr(_port) ffs((_port)->sampling_rate_mask)
98#define max_sr(_port) fls((_port)->sampling_rate_mask)
99
100/* Iterate over all supported sampling rates, from high to low */
101#define for_each_sr(_sr, _port) \
102 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
103 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
104
Laurent Pincharte095ee62017-01-11 16:43:34 +0200105struct plat_sci_reg {
106 u8 offset, size;
107};
108
109struct sci_port_params {
110 const struct plat_sci_reg regs[SCIx_NR_REGS];
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200111 unsigned int fifosize;
112 unsigned int overrun_reg;
113 unsigned int overrun_mask;
114 unsigned int sampling_rate_mask;
115 unsigned int error_mask;
116 unsigned int error_clear;
Laurent Pincharte095ee62017-01-11 16:43:34 +0200117};
118
Paul Mundte108b2c2006-09-27 16:32:13 +0900119struct sci_port {
120 struct uart_port port;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700121
Paul Mundtce6738b2011-01-19 15:24:40 +0900122 /* Platform configuration */
Laurent Pincharte095ee62017-01-11 16:43:34 +0200123 const struct sci_port_params *params;
Laurent Pinchartdaf5a892017-01-11 16:43:35 +0200124 const struct plat_sci_port *cfg;
Geert Uytterhoeven69eee8e2016-01-04 14:45:21 +0100125 unsigned int sampling_rate_mask;
Yoshinori Satoe4d6f912015-05-16 23:57:31 +0900126 resource_size_t reg_size;
Geert Uytterhoevenf907c9e2016-06-03 12:00:04 +0200127 struct mctrl_gpios *gpios;
Paul Mundte108b2c2006-09-27 16:32:13 +0900128
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +0100129 /* Clocks */
130 struct clk *clks[SCI_NUM_CLKS];
131 unsigned long clk_rates[SCI_NUM_CLKS];
Paul Mundtedad1f22009-11-25 16:23:35 +0900132
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +0100133 int irqs[SCIx_NR_IRQS];
Paul Mundt9174fc82011-06-28 15:25:36 +0900134 char *irqstr[SCIx_NR_IRQS];
135
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +0900136 struct dma_chan *chan_tx;
137 struct dma_chan *chan_rx;
Paul Mundtf43dc232011-01-13 15:06:28 +0900138
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +0900139#ifdef CONFIG_SERIAL_SH_SCI_DMA
Geert Uytterhoeven2c4ee232018-07-06 11:05:41 +0200140 struct dma_chan *chan_tx_saved;
141 struct dma_chan *chan_rx_saved;
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +0900142 dma_cookie_t cookie_tx;
143 dma_cookie_t cookie_rx[2];
144 dma_cookie_t active_rx;
Geert Uytterhoeven79904422015-08-21 20:02:42 +0200145 dma_addr_t tx_dma_addr;
146 unsigned int tx_dma_len;
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +0900147 struct scatterlist sg_rx[2];
Yoshihiro Shimoda7b39d902015-08-21 20:02:54 +0200148 void *rx_buf[2];
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +0900149 size_t buf_len_rx;
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +0900150 struct work_struct work_tx;
Ulrich Hechtb96408b2018-02-15 13:02:41 +0100151 struct hrtimer rx_timer;
152 unsigned int rx_timeout; /* microseconds */
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +0900153#endif
Ulrich Hecht03940372017-02-03 11:38:18 +0100154 unsigned int rx_frame;
Ulrich Hecht18e8cf12017-02-03 11:38:17 +0100155 int rx_trigger;
Ulrich Hecht03940372017-02-03 11:38:18 +0100156 struct timer_list rx_fifo_timer;
157 int rx_fifo_timeout;
Ulrich Hechtfa2abb02017-09-29 15:08:53 +0200158 u16 hscif_tot;
Geert Uytterhoeven33f50ff2016-06-03 12:00:10 +0200159
Laurent Pinchart97ed9792017-01-11 16:43:39 +0200160 bool has_rtscts;
Geert Uytterhoeven33f50ff2016-06-03 12:00:10 +0200161 bool autorts;
Paul Mundte108b2c2006-09-27 16:32:13 +0900162};
163
Paul Mundte108b2c2006-09-27 16:32:13 +0900164#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
165
166static struct sci_port sci_ports[SCI_NPORTS];
Geert Uytterhoeven7678f4c2018-03-05 18:17:40 +0100167static unsigned long sci_ports_in_use;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168static struct uart_driver sci_uart_driver;
169
Michael Trimarchie7c98dc2008-11-13 18:18:35 +0900170static inline struct sci_port *
171to_sci_port(struct uart_port *uart)
172{
173 return container_of(uart, struct sci_port, port);
174}
175
Laurent Pincharte095ee62017-01-11 16:43:34 +0200176static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
Paul Mundt61a69762011-06-14 12:40:19 +0900177 /*
178 * Common SCI definitions, dependent on the port's regshift
179 * value.
180 */
181 [SCIx_SCI_REGTYPE] = {
Laurent Pincharte095ee62017-01-11 16:43:34 +0200182 .regs = {
183 [SCSMR] = { 0x00, 8 },
184 [SCBRR] = { 0x01, 8 },
185 [SCSCR] = { 0x02, 8 },
186 [SCxTDR] = { 0x03, 8 },
187 [SCxSR] = { 0x04, 8 },
188 [SCxRDR] = { 0x05, 8 },
189 },
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200190 .fifosize = 1,
191 .overrun_reg = SCxSR,
192 .overrun_mask = SCI_ORER,
193 .sampling_rate_mask = SCI_SR(32),
194 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
195 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
Paul Mundt61a69762011-06-14 12:40:19 +0900196 },
197
198 /*
Laurent Pincharta752ba12017-01-11 16:43:32 +0200199 * Common definitions for legacy IrDA ports.
Paul Mundt61a69762011-06-14 12:40:19 +0900200 */
201 [SCIx_IRDA_REGTYPE] = {
Laurent Pincharte095ee62017-01-11 16:43:34 +0200202 .regs = {
203 [SCSMR] = { 0x00, 8 },
204 [SCBRR] = { 0x02, 8 },
205 [SCSCR] = { 0x04, 8 },
206 [SCxTDR] = { 0x06, 8 },
207 [SCxSR] = { 0x08, 16 },
208 [SCxRDR] = { 0x0a, 8 },
209 [SCFCR] = { 0x0c, 8 },
210 [SCFDR] = { 0x0e, 16 },
211 },
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200212 .fifosize = 1,
213 .overrun_reg = SCxSR,
214 .overrun_mask = SCI_ORER,
215 .sampling_rate_mask = SCI_SR(32),
216 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
217 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
Paul Mundt61a69762011-06-14 12:40:19 +0900218 },
219
220 /*
221 * Common SCIFA definitions.
222 */
223 [SCIx_SCIFA_REGTYPE] = {
Laurent Pincharte095ee62017-01-11 16:43:34 +0200224 .regs = {
225 [SCSMR] = { 0x00, 16 },
226 [SCBRR] = { 0x04, 8 },
227 [SCSCR] = { 0x08, 16 },
228 [SCxTDR] = { 0x20, 8 },
229 [SCxSR] = { 0x14, 16 },
230 [SCxRDR] = { 0x24, 8 },
231 [SCFCR] = { 0x18, 16 },
232 [SCFDR] = { 0x1c, 16 },
233 [SCPCR] = { 0x30, 16 },
234 [SCPDR] = { 0x34, 16 },
235 },
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200236 .fifosize = 64,
237 .overrun_reg = SCxSR,
238 .overrun_mask = SCIFA_ORER,
239 .sampling_rate_mask = SCI_SR_SCIFAB,
240 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
241 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
Paul Mundt61a69762011-06-14 12:40:19 +0900242 },
243
244 /*
245 * Common SCIFB definitions.
246 */
247 [SCIx_SCIFB_REGTYPE] = {
Laurent Pincharte095ee62017-01-11 16:43:34 +0200248 .regs = {
249 [SCSMR] = { 0x00, 16 },
250 [SCBRR] = { 0x04, 8 },
251 [SCSCR] = { 0x08, 16 },
252 [SCxTDR] = { 0x40, 8 },
253 [SCxSR] = { 0x14, 16 },
254 [SCxRDR] = { 0x60, 8 },
255 [SCFCR] = { 0x18, 16 },
256 [SCTFDR] = { 0x38, 16 },
257 [SCRFDR] = { 0x3c, 16 },
258 [SCPCR] = { 0x30, 16 },
259 [SCPDR] = { 0x34, 16 },
260 },
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200261 .fifosize = 256,
262 .overrun_reg = SCxSR,
263 .overrun_mask = SCIFA_ORER,
264 .sampling_rate_mask = SCI_SR_SCIFAB,
265 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
266 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
Paul Mundt61a69762011-06-14 12:40:19 +0900267 },
268
269 /*
Phil Edworthy3af1f8a2011-10-03 15:16:47 +0100270 * Common SH-2(A) SCIF definitions for ports with FIFO data
271 * count registers.
272 */
273 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
Laurent Pincharte095ee62017-01-11 16:43:34 +0200274 .regs = {
275 [SCSMR] = { 0x00, 16 },
276 [SCBRR] = { 0x04, 8 },
277 [SCSCR] = { 0x08, 16 },
278 [SCxTDR] = { 0x0c, 8 },
279 [SCxSR] = { 0x10, 16 },
280 [SCxRDR] = { 0x14, 8 },
281 [SCFCR] = { 0x18, 16 },
282 [SCFDR] = { 0x1c, 16 },
283 [SCSPTR] = { 0x20, 16 },
284 [SCLSR] = { 0x24, 16 },
285 },
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200286 .fifosize = 16,
287 .overrun_reg = SCLSR,
288 .overrun_mask = SCLSR_ORER,
289 .sampling_rate_mask = SCI_SR(32),
290 .error_mask = SCIF_DEFAULT_ERROR_MASK,
291 .error_clear = SCIF_ERROR_CLEAR,
Phil Edworthy3af1f8a2011-10-03 15:16:47 +0100292 },
293
294 /*
Geert Uytterhoeven10c63442018-08-30 14:54:03 +0200295 * The "SCIFA" that is in RZ/T and RZ/A2.
296 * It looks like a normal SCIF with FIFO data, but with a
297 * compressed address space. Also, the break out of interrupts
298 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
299 */
300 [SCIx_RZ_SCIFA_REGTYPE] = {
301 .regs = {
302 [SCSMR] = { 0x00, 16 },
303 [SCBRR] = { 0x02, 8 },
304 [SCSCR] = { 0x04, 16 },
305 [SCxTDR] = { 0x06, 8 },
306 [SCxSR] = { 0x08, 16 },
307 [SCxRDR] = { 0x0A, 8 },
308 [SCFCR] = { 0x0C, 16 },
309 [SCFDR] = { 0x0E, 16 },
310 [SCSPTR] = { 0x10, 16 },
311 [SCLSR] = { 0x12, 16 },
312 },
313 .fifosize = 16,
314 .overrun_reg = SCLSR,
315 .overrun_mask = SCLSR_ORER,
316 .sampling_rate_mask = SCI_SR(32),
317 .error_mask = SCIF_DEFAULT_ERROR_MASK,
318 .error_clear = SCIF_ERROR_CLEAR,
319 },
320
321 /*
Paul Mundt61a69762011-06-14 12:40:19 +0900322 * Common SH-3 SCIF definitions.
323 */
324 [SCIx_SH3_SCIF_REGTYPE] = {
Laurent Pincharte095ee62017-01-11 16:43:34 +0200325 .regs = {
326 [SCSMR] = { 0x00, 8 },
327 [SCBRR] = { 0x02, 8 },
328 [SCSCR] = { 0x04, 8 },
329 [SCxTDR] = { 0x06, 8 },
330 [SCxSR] = { 0x08, 16 },
331 [SCxRDR] = { 0x0a, 8 },
332 [SCFCR] = { 0x0c, 8 },
333 [SCFDR] = { 0x0e, 16 },
334 },
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200335 .fifosize = 16,
336 .overrun_reg = SCLSR,
337 .overrun_mask = SCLSR_ORER,
338 .sampling_rate_mask = SCI_SR(32),
339 .error_mask = SCIF_DEFAULT_ERROR_MASK,
340 .error_clear = SCIF_ERROR_CLEAR,
Paul Mundt61a69762011-06-14 12:40:19 +0900341 },
342
343 /*
344 * Common SH-4(A) SCIF(B) definitions.
345 */
346 [SCIx_SH4_SCIF_REGTYPE] = {
Laurent Pincharte095ee62017-01-11 16:43:34 +0200347 .regs = {
348 [SCSMR] = { 0x00, 16 },
Geert Uytterhoevena1c2fd72018-08-30 14:54:04 +0200349 [SCBRR] = { 0x04, 8 },
350 [SCSCR] = { 0x08, 16 },
351 [SCxTDR] = { 0x0c, 8 },
352 [SCxSR] = { 0x10, 16 },
353 [SCxRDR] = { 0x14, 8 },
354 [SCFCR] = { 0x18, 16 },
355 [SCFDR] = { 0x1c, 16 },
356 [SCSPTR] = { 0x20, 16 },
357 [SCLSR] = { 0x24, 16 },
Laurent Pincharte095ee62017-01-11 16:43:34 +0200358 },
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200359 .fifosize = 16,
360 .overrun_reg = SCLSR,
361 .overrun_mask = SCLSR_ORER,
362 .sampling_rate_mask = SCI_SR(32),
363 .error_mask = SCIF_DEFAULT_ERROR_MASK,
364 .error_clear = SCIF_ERROR_CLEAR,
Geert Uytterhoevenb8bbd6b2015-11-12 13:36:06 +0100365 },
366
367 /*
368 * Common SCIF definitions for ports with a Baud Rate Generator for
369 * External Clock (BRG).
370 */
371 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
Laurent Pincharte095ee62017-01-11 16:43:34 +0200372 .regs = {
373 [SCSMR] = { 0x00, 16 },
374 [SCBRR] = { 0x04, 8 },
375 [SCSCR] = { 0x08, 16 },
376 [SCxTDR] = { 0x0c, 8 },
377 [SCxSR] = { 0x10, 16 },
378 [SCxRDR] = { 0x14, 8 },
379 [SCFCR] = { 0x18, 16 },
380 [SCFDR] = { 0x1c, 16 },
381 [SCSPTR] = { 0x20, 16 },
382 [SCLSR] = { 0x24, 16 },
383 [SCDL] = { 0x30, 16 },
384 [SCCKS] = { 0x34, 16 },
385 },
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200386 .fifosize = 16,
387 .overrun_reg = SCLSR,
388 .overrun_mask = SCLSR_ORER,
389 .sampling_rate_mask = SCI_SR(32),
390 .error_mask = SCIF_DEFAULT_ERROR_MASK,
391 .error_clear = SCIF_ERROR_CLEAR,
Ulrich Hechtf303b362013-05-31 17:57:01 +0200392 },
393
394 /*
395 * Common HSCIF definitions.
396 */
397 [SCIx_HSCIF_REGTYPE] = {
Laurent Pincharte095ee62017-01-11 16:43:34 +0200398 .regs = {
399 [SCSMR] = { 0x00, 16 },
400 [SCBRR] = { 0x04, 8 },
401 [SCSCR] = { 0x08, 16 },
402 [SCxTDR] = { 0x0c, 8 },
403 [SCxSR] = { 0x10, 16 },
404 [SCxRDR] = { 0x14, 8 },
405 [SCFCR] = { 0x18, 16 },
406 [SCFDR] = { 0x1c, 16 },
407 [SCSPTR] = { 0x20, 16 },
408 [SCLSR] = { 0x24, 16 },
409 [HSSRR] = { 0x40, 16 },
410 [SCDL] = { 0x30, 16 },
411 [SCCKS] = { 0x34, 16 },
Ulrich Hecht54e14ae2017-02-02 18:10:14 +0100412 [HSRTRGR] = { 0x54, 16 },
413 [HSTTRGR] = { 0x58, 16 },
Laurent Pincharte095ee62017-01-11 16:43:34 +0200414 },
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200415 .fifosize = 128,
416 .overrun_reg = SCLSR,
417 .overrun_mask = SCLSR_ORER,
418 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
419 .error_mask = SCIF_DEFAULT_ERROR_MASK,
420 .error_clear = SCIF_ERROR_CLEAR,
Paul Mundt61a69762011-06-14 12:40:19 +0900421 },
422
423 /*
424 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
425 * register.
426 */
427 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
Laurent Pincharte095ee62017-01-11 16:43:34 +0200428 .regs = {
429 [SCSMR] = { 0x00, 16 },
430 [SCBRR] = { 0x04, 8 },
431 [SCSCR] = { 0x08, 16 },
432 [SCxTDR] = { 0x0c, 8 },
433 [SCxSR] = { 0x10, 16 },
434 [SCxRDR] = { 0x14, 8 },
435 [SCFCR] = { 0x18, 16 },
436 [SCFDR] = { 0x1c, 16 },
437 [SCLSR] = { 0x24, 16 },
438 },
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200439 .fifosize = 16,
440 .overrun_reg = SCLSR,
441 .overrun_mask = SCLSR_ORER,
442 .sampling_rate_mask = SCI_SR(32),
443 .error_mask = SCIF_DEFAULT_ERROR_MASK,
444 .error_clear = SCIF_ERROR_CLEAR,
Paul Mundt61a69762011-06-14 12:40:19 +0900445 },
446
447 /*
448 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
449 * count registers.
450 */
451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
Laurent Pincharte095ee62017-01-11 16:43:34 +0200452 .regs = {
453 [SCSMR] = { 0x00, 16 },
454 [SCBRR] = { 0x04, 8 },
455 [SCSCR] = { 0x08, 16 },
456 [SCxTDR] = { 0x0c, 8 },
457 [SCxSR] = { 0x10, 16 },
458 [SCxRDR] = { 0x14, 8 },
459 [SCFCR] = { 0x18, 16 },
460 [SCFDR] = { 0x1c, 16 },
461 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
462 [SCRFDR] = { 0x20, 16 },
463 [SCSPTR] = { 0x24, 16 },
464 [SCLSR] = { 0x28, 16 },
465 },
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200466 .fifosize = 16,
467 .overrun_reg = SCLSR,
468 .overrun_mask = SCLSR_ORER,
469 .sampling_rate_mask = SCI_SR(32),
470 .error_mask = SCIF_DEFAULT_ERROR_MASK,
471 .error_clear = SCIF_ERROR_CLEAR,
Paul Mundt61a69762011-06-14 12:40:19 +0900472 },
473
474 /*
475 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
476 * registers.
477 */
478 [SCIx_SH7705_SCIF_REGTYPE] = {
Laurent Pincharte095ee62017-01-11 16:43:34 +0200479 .regs = {
480 [SCSMR] = { 0x00, 16 },
481 [SCBRR] = { 0x04, 8 },
482 [SCSCR] = { 0x08, 16 },
483 [SCxTDR] = { 0x20, 8 },
484 [SCxSR] = { 0x14, 16 },
485 [SCxRDR] = { 0x24, 8 },
486 [SCFCR] = { 0x18, 16 },
487 [SCFDR] = { 0x1c, 16 },
488 },
Ulrich Hecht18e8cf12017-02-03 11:38:17 +0100489 .fifosize = 64,
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200490 .overrun_reg = SCxSR,
491 .overrun_mask = SCIFA_ORER,
492 .sampling_rate_mask = SCI_SR(16),
493 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
494 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
Paul Mundt61a69762011-06-14 12:40:19 +0900495 },
496};
497
Laurent Pincharte095ee62017-01-11 16:43:34 +0200498#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
Paul Mundt72b294c2011-06-14 17:38:19 +0900499
Paul Mundt61a69762011-06-14 12:40:19 +0900500/*
501 * The "offset" here is rather misleading, in that it refers to an enum
502 * value relative to the port mapping rather than the fixed offset
503 * itself, which needs to be manually retrieved from the platform's
504 * register map for the given port.
505 */
506static unsigned int sci_serial_in(struct uart_port *p, int offset)
507{
Geert Uytterhoevend3184e62015-08-21 20:02:33 +0200508 const struct plat_sci_reg *reg = sci_getreg(p, offset);
Paul Mundt61a69762011-06-14 12:40:19 +0900509
510 if (reg->size == 8)
511 return ioread8(p->membase + (reg->offset << p->regshift));
512 else if (reg->size == 16)
513 return ioread16(p->membase + (reg->offset << p->regshift));
514 else
515 WARN(1, "Invalid register access\n");
516
517 return 0;
518}
519
520static void sci_serial_out(struct uart_port *p, int offset, int value)
521{
Geert Uytterhoevend3184e62015-08-21 20:02:33 +0200522 const struct plat_sci_reg *reg = sci_getreg(p, offset);
Paul Mundt61a69762011-06-14 12:40:19 +0900523
524 if (reg->size == 8)
525 iowrite8(value, p->membase + (reg->offset << p->regshift));
526 else if (reg->size == 16)
527 iowrite16(value, p->membase + (reg->offset << p->regshift));
528 else
529 WARN(1, "Invalid register access\n");
530}
531
Paul Mundt23241d42011-06-28 13:55:31 +0900532static void sci_port_enable(struct sci_port *sci_port)
533{
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +0100534 unsigned int i;
535
Paul Mundt23241d42011-06-28 13:55:31 +0900536 if (!sci_port->port.dev)
537 return;
538
539 pm_runtime_get_sync(sci_port->port.dev);
540
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +0100541 for (i = 0; i < SCI_NUM_CLKS; i++) {
542 clk_prepare_enable(sci_port->clks[i]);
543 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
544 }
545 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
Paul Mundt23241d42011-06-28 13:55:31 +0900546}
547
548static void sci_port_disable(struct sci_port *sci_port)
549{
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +0100550 unsigned int i;
551
Paul Mundt23241d42011-06-28 13:55:31 +0900552 if (!sci_port->port.dev)
553 return;
554
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +0100555 for (i = SCI_NUM_CLKS; i-- > 0; )
556 clk_disable_unprepare(sci_port->clks[i]);
Paul Mundt23241d42011-06-28 13:55:31 +0900557
558 pm_runtime_put_sync(sci_port->port.dev);
559}
560
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +0200561static inline unsigned long port_rx_irq_mask(struct uart_port *port)
562{
563 /*
564 * Not all ports (such as SCIFA) will support REIE. Rather than
565 * special-casing the port type, we check the port initialization
566 * IRQ enable mask to see whether the IRQ is desired at all. If
567 * it's unset, it's logically inferred that there's no point in
568 * testing for it.
569 */
570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
571}
572
573static void sci_start_tx(struct uart_port *port)
574{
575 struct sci_port *s = to_sci_port(port);
576 unsigned short ctrl;
577
578#ifdef CONFIG_SERIAL_SH_SCI_DMA
579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
580 u16 new, scr = serial_port_in(port, SCSCR);
581 if (s->chan_tx)
582 new = scr | SCSCR_TDRQE;
583 else
584 new = scr & ~SCSCR_TDRQE;
585 if (new != scr)
586 serial_port_out(port, SCSCR, new);
587 }
588
589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
590 dma_submit_error(s->cookie_tx)) {
591 s->cookie_tx = 0;
592 schedule_work(&s->work_tx);
593 }
594#endif
595
596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
597 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
598 ctrl = serial_port_in(port, SCSCR);
599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
600 }
601}
602
603static void sci_stop_tx(struct uart_port *port)
604{
605 unsigned short ctrl;
606
607 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
608 ctrl = serial_port_in(port, SCSCR);
609
610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
611 ctrl &= ~SCSCR_TDRQE;
612
613 ctrl &= ~SCSCR_TIE;
614
615 serial_port_out(port, SCSCR, ctrl);
616}
617
618static void sci_start_rx(struct uart_port *port)
619{
620 unsigned short ctrl;
621
622 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
623
624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
625 ctrl &= ~SCSCR_RDRQE;
626
627 serial_port_out(port, SCSCR, ctrl);
628}
629
630static void sci_stop_rx(struct uart_port *port)
631{
632 unsigned short ctrl;
633
634 ctrl = serial_port_in(port, SCSCR);
635
636 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
637 ctrl &= ~SCSCR_RDRQE;
638
639 ctrl &= ~port_rx_irq_mask(port);
640
641 serial_port_out(port, SCSCR, ctrl);
642}
643
Geert Uytterhoevena1b5b432015-08-21 20:02:25 +0200644static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
645{
646 if (port->type == PORT_SCI) {
647 /* Just store the mask */
648 serial_port_out(port, SCxSR, mask);
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200649 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
Geert Uytterhoevena1b5b432015-08-21 20:02:25 +0200650 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
651 /* Only clear the status bits we want to clear */
652 serial_port_out(port, SCxSR,
653 serial_port_in(port, SCxSR) & mask);
654 } else {
655 /* Store the mask, clear parity/framing errors */
656 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
657 }
658}
659
Yoshinori Sato0b0cced2015-12-24 11:24:48 +0100660#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
661 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
Paul Mundt1f6fd5c2008-12-17 14:53:24 +0900662
663#ifdef CONFIG_CONSOLE_POLL
Paul Mundt07d2a1a2008-12-11 19:06:43 +0900664static int sci_poll_get_char(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700666 unsigned short status;
667 int c;
668
Paul Mundte108b2c2006-09-27 16:32:13 +0900669 do {
Paul Mundtb12bb292012-03-30 19:50:15 +0900670 status = serial_port_in(port, SCxSR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671 if (status & SCxSR_ERRORS(port)) {
Geert Uytterhoevena1b5b432015-08-21 20:02:25 +0200672 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673 continue;
674 }
Jason Wessel3f255eb2010-05-20 21:04:23 -0500675 break;
676 } while (1);
677
678 if (!(status & SCxSR_RDxF(port)))
679 return NO_POLL_CHAR;
Paul Mundt07d2a1a2008-12-11 19:06:43 +0900680
Paul Mundtb12bb292012-03-30 19:50:15 +0900681 c = serial_port_in(port, SCxRDR);
Paul Mundt07d2a1a2008-12-11 19:06:43 +0900682
Michael Trimarchie7c98dc2008-11-13 18:18:35 +0900683 /* Dummy read */
Paul Mundtb12bb292012-03-30 19:50:15 +0900684 serial_port_in(port, SCxSR);
Geert Uytterhoevena1b5b432015-08-21 20:02:25 +0200685 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700686
687 return c;
688}
Paul Mundt1f6fd5c2008-12-17 14:53:24 +0900689#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700690
Paul Mundt07d2a1a2008-12-11 19:06:43 +0900691static void sci_poll_put_char(struct uart_port *port, unsigned char c)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700692{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700693 unsigned short status;
694
Linus Torvalds1da177e2005-04-16 15:20:36 -0700695 do {
Paul Mundtb12bb292012-03-30 19:50:15 +0900696 status = serial_port_in(port, SCxSR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700697 } while (!(status & SCxSR_TDxE(port)));
698
Paul Mundtb12bb292012-03-30 19:50:15 +0900699 serial_port_out(port, SCxTDR, c);
Geert Uytterhoevena1b5b432015-08-21 20:02:25 +0200700 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700701}
Yoshinori Sato0b0cced2015-12-24 11:24:48 +0100702#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
703 CONFIG_SERIAL_SH_SCI_EARLYCON */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700704
Paul Mundt61a69762011-06-14 12:40:19 +0900705static void sci_init_pins(struct uart_port *port, unsigned int cflag)
Paul Mundte108b2c2006-09-27 16:32:13 +0900706{
Paul Mundt61a69762011-06-14 12:40:19 +0900707 struct sci_port *s = to_sci_port(port);
Markus Brunner3ea6bc32007-08-20 08:59:33 +0900708
Paul Mundt61a69762011-06-14 12:40:19 +0900709 /*
710 * Use port-specific handler if provided.
711 */
712 if (s->cfg->ops && s->cfg->ops->init_pins) {
713 s->cfg->ops->init_pins(port, cflag);
714 return;
Markus Brunner3ea6bc32007-08-20 08:59:33 +0900715 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716
Geert Uytterhoevene9d7a452016-06-03 12:00:09 +0200717 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
Geert Uytterhoevencfa6eb22017-03-28 11:13:46 +0200718 u16 data = serial_port_in(port, SCPDR);
Geert Uytterhoevene9d7a452016-06-03 12:00:09 +0200719 u16 ctrl = serial_port_in(port, SCPCR);
720
721 /* Enable RXD and TXD pin functions */
722 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
Laurent Pinchart97ed9792017-01-11 16:43:39 +0200723 if (to_sci_port(port)->has_rtscts) {
Geert Uytterhoevencfa6eb22017-03-28 11:13:46 +0200724 /* RTS# is output, active low, unless autorts */
725 if (!(port->mctrl & TIOCM_RTS)) {
726 ctrl |= SCPCR_RTSC;
727 data |= SCPDR_RTSD;
728 } else if (!s->autorts) {
729 ctrl |= SCPCR_RTSC;
730 data &= ~SCPDR_RTSD;
731 } else {
732 /* Enable RTS# pin function */
733 ctrl &= ~SCPCR_RTSC;
734 }
Geert Uytterhoevene9d7a452016-06-03 12:00:09 +0200735 /* Enable CTS# pin function */
736 ctrl &= ~SCPCR_CTSC;
737 }
Geert Uytterhoevencfa6eb22017-03-28 11:13:46 +0200738 serial_port_out(port, SCPDR, data);
Geert Uytterhoevene9d7a452016-06-03 12:00:09 +0200739 serial_port_out(port, SCPCR, ctrl);
740 } else if (sci_getreg(port, SCSPTR)->size) {
Geert Uytterhoevend2b97752016-06-03 12:00:08 +0200741 u16 status = serial_port_in(port, SCSPTR);
Paul Mundtb7a76e42006-02-01 03:06:06 -0800742
Geert Uytterhoevencfa6eb22017-03-28 11:13:46 +0200743 /* RTS# is always output; and active low, unless autorts */
744 status |= SCSPTR_RTSIO;
745 if (!(port->mctrl & TIOCM_RTS))
746 status |= SCSPTR_RTSDT;
747 else if (!s->autorts)
748 status &= ~SCSPTR_RTSDT;
Geert Uytterhoevend2b97752016-06-03 12:00:08 +0200749 /* CTS# and SCK are inputs */
750 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
751 serial_port_out(port, SCSPTR, status);
Paul Mundtfaf02f82011-12-02 17:44:50 +0900752 }
Paul Mundtd5701642008-12-16 20:07:27 +0900753}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700754
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +0900755static int sci_txfill(struct uart_port *port)
Paul Mundte108b2c2006-09-27 16:32:13 +0900756{
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200757 struct sci_port *s = to_sci_port(port);
758 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
Geert Uytterhoevend3184e62015-08-21 20:02:33 +0200759 const struct plat_sci_reg *reg;
Paul Mundt72b294c2011-06-14 17:38:19 +0900760
761 reg = sci_getreg(port, SCTFDR);
762 if (reg->size)
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200763 return serial_port_in(port, SCTFDR) & fifo_mask;
Paul Mundt72b294c2011-06-14 17:38:19 +0900764
765 reg = sci_getreg(port, SCFDR);
766 if (reg->size)
Paul Mundtb12bb292012-03-30 19:50:15 +0900767 return serial_port_in(port, SCFDR) >> 8;
Paul Mundt72b294c2011-06-14 17:38:19 +0900768
Paul Mundtb12bb292012-03-30 19:50:15 +0900769 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
Paul Mundte108b2c2006-09-27 16:32:13 +0900770}
771
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +0900772static int sci_txroom(struct uart_port *port)
773{
Paul Mundt72b294c2011-06-14 17:38:19 +0900774 return port->fifosize - sci_txfill(port);
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +0900775}
776
777static int sci_rxfill(struct uart_port *port)
Paul Mundte108b2c2006-09-27 16:32:13 +0900778{
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200779 struct sci_port *s = to_sci_port(port);
780 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
Geert Uytterhoevend3184e62015-08-21 20:02:33 +0200781 const struct plat_sci_reg *reg;
Paul Mundt72b294c2011-06-14 17:38:19 +0900782
783 reg = sci_getreg(port, SCRFDR);
784 if (reg->size)
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200785 return serial_port_in(port, SCRFDR) & fifo_mask;
Paul Mundt72b294c2011-06-14 17:38:19 +0900786
787 reg = sci_getreg(port, SCFDR);
788 if (reg->size)
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200789 return serial_port_in(port, SCFDR) & fifo_mask;
Paul Mundt72b294c2011-06-14 17:38:19 +0900790
Paul Mundtb12bb292012-03-30 19:50:15 +0900791 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
Paul Mundte108b2c2006-09-27 16:32:13 +0900792}
793
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794/* ********************************************************************** *
795 * the interrupt related routines *
796 * ********************************************************************** */
797
798static void sci_transmit_chars(struct uart_port *port)
799{
Alan Coxebd2c8f2009-09-19 13:13:28 -0700800 struct circ_buf *xmit = &port->state->xmit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700801 unsigned int stopped = uart_tx_stopped(port);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700802 unsigned short status;
803 unsigned short ctrl;
Paul Mundte108b2c2006-09-27 16:32:13 +0900804 int count;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700805
Paul Mundtb12bb292012-03-30 19:50:15 +0900806 status = serial_port_in(port, SCxSR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807 if (!(status & SCxSR_TDxE(port))) {
Paul Mundtb12bb292012-03-30 19:50:15 +0900808 ctrl = serial_port_in(port, SCSCR);
Michael Trimarchie7c98dc2008-11-13 18:18:35 +0900809 if (uart_circ_empty(xmit))
Paul Mundt8e698612009-06-24 19:44:32 +0900810 ctrl &= ~SCSCR_TIE;
Michael Trimarchie7c98dc2008-11-13 18:18:35 +0900811 else
Paul Mundt8e698612009-06-24 19:44:32 +0900812 ctrl |= SCSCR_TIE;
Paul Mundtb12bb292012-03-30 19:50:15 +0900813 serial_port_out(port, SCSCR, ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814 return;
815 }
816
Paul Mundt72b294c2011-06-14 17:38:19 +0900817 count = sci_txroom(port);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700818
819 do {
820 unsigned char c;
821
822 if (port->x_char) {
823 c = port->x_char;
824 port->x_char = 0;
825 } else if (!uart_circ_empty(xmit) && !stopped) {
826 c = xmit->buf[xmit->tail];
827 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
828 } else {
829 break;
830 }
831
Paul Mundtb12bb292012-03-30 19:50:15 +0900832 serial_port_out(port, SCxTDR, c);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700833
834 port->icount.tx++;
835 } while (--count > 0);
836
Geert Uytterhoevena1b5b432015-08-21 20:02:25 +0200837 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700838
839 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
840 uart_write_wakeup(port);
841 if (uart_circ_empty(xmit)) {
Russell Kingb129a8c2005-08-31 10:12:14 +0100842 sci_stop_tx(port);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700843 } else {
Paul Mundtb12bb292012-03-30 19:50:15 +0900844 ctrl = serial_port_in(port, SCSCR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700845
Yoshihiro Shimoda1a22f082008-11-11 12:19:05 +0900846 if (port->type != PORT_SCI) {
Paul Mundtb12bb292012-03-30 19:50:15 +0900847 serial_port_in(port, SCxSR); /* Dummy read */
Geert Uytterhoevena1b5b432015-08-21 20:02:25 +0200848 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700850
Paul Mundt8e698612009-06-24 19:44:32 +0900851 ctrl |= SCSCR_TIE;
Paul Mundtb12bb292012-03-30 19:50:15 +0900852 serial_port_out(port, SCSCR, ctrl);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853 }
854}
855
856/* On SH3, SCIF may read end-of-break as a space->mark char */
Michael Trimarchie7c98dc2008-11-13 18:18:35 +0900857#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
Linus Torvalds1da177e2005-04-16 15:20:36 -0700858
Paul Mundt94c8b6d2011-01-20 23:26:18 +0900859static void sci_receive_chars(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860{
Jiri Slaby227434f2013-01-03 15:53:01 +0100861 struct tty_port *tport = &port->state->port;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862 int i, count, copied = 0;
863 unsigned short status;
Alan Cox33f0f882006-01-09 20:54:13 -0800864 unsigned char flag;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700865
Paul Mundtb12bb292012-03-30 19:50:15 +0900866 status = serial_port_in(port, SCxSR);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700867 if (!(status & SCxSR_RDxF(port)))
868 return;
869
870 while (1) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871 /* Don't copy more bytes than there is room for in the buffer */
Jiri Slaby227434f2013-01-03 15:53:01 +0100872 count = tty_buffer_request_room(tport, sci_rxfill(port));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700873
874 /* If for any reason we can't copy more data, we're done! */
875 if (count == 0)
876 break;
877
878 if (port->type == PORT_SCI) {
Paul Mundtb12bb292012-03-30 19:50:15 +0900879 char c = serial_port_in(port, SCxRDR);
Laurent Pinchartd5cb1312017-01-11 16:43:38 +0200880 if (uart_handle_sysrq_char(port, c))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700881 count = 0;
Michael Trimarchie7c98dc2008-11-13 18:18:35 +0900882 else
Jiri Slaby92a19f92013-01-03 15:53:03 +0100883 tty_insert_flip_char(tport, c, TTY_NORMAL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700884 } else {
Michael Trimarchie7c98dc2008-11-13 18:18:35 +0900885 for (i = 0; i < count; i++) {
Paul Mundtb12bb292012-03-30 19:50:15 +0900886 char c = serial_port_in(port, SCxRDR);
Paul Mundtd97fbbe2011-11-24 19:15:06 +0900887
Paul Mundtb12bb292012-03-30 19:50:15 +0900888 status = serial_port_in(port, SCxSR);
David Howells7d12e782006-10-05 14:55:46 +0100889 if (uart_handle_sysrq_char(port, c)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700890 count--; i--;
891 continue;
892 }
893
894 /* Store data and status */
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +0900895 if (status & SCxSR_FER(port)) {
Alan Cox33f0f882006-01-09 20:54:13 -0800896 flag = TTY_FRAME;
Paul Mundtd97fbbe2011-11-24 19:15:06 +0900897 port->icount.frame++;
Paul Mundt762c69e2008-12-16 18:55:26 +0900898 dev_notice(port->dev, "frame error\n");
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +0900899 } else if (status & SCxSR_PER(port)) {
Alan Cox33f0f882006-01-09 20:54:13 -0800900 flag = TTY_PARITY;
Paul Mundtd97fbbe2011-11-24 19:15:06 +0900901 port->icount.parity++;
Paul Mundt762c69e2008-12-16 18:55:26 +0900902 dev_notice(port->dev, "parity error\n");
Alan Cox33f0f882006-01-09 20:54:13 -0800903 } else
904 flag = TTY_NORMAL;
Paul Mundt762c69e2008-12-16 18:55:26 +0900905
Jiri Slaby92a19f92013-01-03 15:53:03 +0100906 tty_insert_flip_char(tport, c, flag);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700907 }
908 }
909
Paul Mundtb12bb292012-03-30 19:50:15 +0900910 serial_port_in(port, SCxSR); /* dummy read */
Geert Uytterhoevena1b5b432015-08-21 20:02:25 +0200911 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700912
Linus Torvalds1da177e2005-04-16 15:20:36 -0700913 copied += count;
914 port->icount.rx += count;
915 }
916
917 if (copied) {
918 /* Tell the rest of the system the news. New characters! */
Jiri Slaby2e124b42013-01-03 15:53:06 +0100919 tty_flip_buffer_push(tport);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700920 } else {
Ulrich Hecht78420552018-02-15 13:02:27 +0100921 /* TTY buffers full; read from RX reg to prevent lockup */
922 serial_port_in(port, SCxRDR);
Paul Mundtb12bb292012-03-30 19:50:15 +0900923 serial_port_in(port, SCxSR); /* dummy read */
Geert Uytterhoevena1b5b432015-08-21 20:02:25 +0200924 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700925 }
926}
927
Paul Mundt94c8b6d2011-01-20 23:26:18 +0900928static int sci_handle_errors(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700929{
930 int copied = 0;
Paul Mundtb12bb292012-03-30 19:50:15 +0900931 unsigned short status = serial_port_in(port, SCxSR);
Jiri Slaby92a19f92013-01-03 15:53:03 +0100932 struct tty_port *tport = &port->state->port;
Paul Mundtdebf9502011-06-08 18:19:37 +0900933 struct sci_port *s = to_sci_port(port);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700934
Laurent Pinchart3ae988d2013-12-06 10:59:17 +0100935 /* Handle overruns */
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200936 if (status & s->params->overrun_mask) {
Laurent Pinchart3ae988d2013-12-06 10:59:17 +0100937 port->icount.overrun++;
Paul Mundtd97fbbe2011-11-24 19:15:06 +0900938
Laurent Pinchart3ae988d2013-12-06 10:59:17 +0100939 /* overrun error */
940 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
941 copied++;
Paul Mundt762c69e2008-12-16 18:55:26 +0900942
Joe Perches9b971cd2014-03-11 10:10:46 -0700943 dev_notice(port->dev, "overrun error\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700944 }
945
Paul Mundte108b2c2006-09-27 16:32:13 +0900946 if (status & SCxSR_FER(port)) {
Laurent Pinchartd5cb1312017-01-11 16:43:38 +0200947 /* frame error */
948 port->icount.frame++;
Paul Mundte108b2c2006-09-27 16:32:13 +0900949
Laurent Pinchartd5cb1312017-01-11 16:43:38 +0200950 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
951 copied++;
Paul Mundtd97fbbe2011-11-24 19:15:06 +0900952
Laurent Pinchartd5cb1312017-01-11 16:43:38 +0200953 dev_notice(port->dev, "frame error\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700954 }
955
Paul Mundte108b2c2006-09-27 16:32:13 +0900956 if (status & SCxSR_PER(port)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700957 /* parity error */
Paul Mundtd97fbbe2011-11-24 19:15:06 +0900958 port->icount.parity++;
959
Jiri Slaby92a19f92013-01-03 15:53:03 +0100960 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
Paul Mundte108b2c2006-09-27 16:32:13 +0900961 copied++;
Paul Mundt762c69e2008-12-16 18:55:26 +0900962
Joe Perches9b971cd2014-03-11 10:10:46 -0700963 dev_notice(port->dev, "parity error\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700964 }
965
Alan Cox33f0f882006-01-09 20:54:13 -0800966 if (copied)
Jiri Slaby2e124b42013-01-03 15:53:06 +0100967 tty_flip_buffer_push(tport);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700968
969 return copied;
970}
971
Paul Mundt94c8b6d2011-01-20 23:26:18 +0900972static int sci_handle_fifo_overrun(struct uart_port *port)
Paul Mundtd830fa42008-12-16 19:29:38 +0900973{
Jiri Slaby92a19f92013-01-03 15:53:03 +0100974 struct tty_port *tport = &port->state->port;
Paul Mundtdebf9502011-06-08 18:19:37 +0900975 struct sci_port *s = to_sci_port(port);
Geert Uytterhoevend3184e62015-08-21 20:02:33 +0200976 const struct plat_sci_reg *reg;
Geert Uytterhoeven2e0842a2015-04-30 18:21:32 +0200977 int copied = 0;
Geert Uytterhoeven75c249f2015-04-30 18:21:31 +0200978 u16 status;
Paul Mundtd830fa42008-12-16 19:29:38 +0900979
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200980 reg = sci_getreg(port, s->params->overrun_reg);
Paul Mundt4b8c59a2011-06-14 17:53:34 +0900981 if (!reg->size)
Paul Mundtd830fa42008-12-16 19:29:38 +0900982 return 0;
983
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +0200984 status = serial_port_in(port, s->params->overrun_reg);
985 if (status & s->params->overrun_mask) {
986 status &= ~s->params->overrun_mask;
987 serial_port_out(port, s->params->overrun_reg, status);
Paul Mundtd830fa42008-12-16 19:29:38 +0900988
Paul Mundtd97fbbe2011-11-24 19:15:06 +0900989 port->icount.overrun++;
990
Jiri Slaby92a19f92013-01-03 15:53:03 +0100991 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
Jiri Slaby2e124b42013-01-03 15:53:06 +0100992 tty_flip_buffer_push(tport);
Paul Mundtd830fa42008-12-16 19:29:38 +0900993
Yoshihiro Kaneko51b31f12015-01-26 20:53:29 +0900994 dev_dbg(port->dev, "overrun error\n");
Paul Mundtd830fa42008-12-16 19:29:38 +0900995 copied++;
996 }
997
998 return copied;
999}
1000
Paul Mundt94c8b6d2011-01-20 23:26:18 +09001001static int sci_handle_breaks(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001002{
1003 int copied = 0;
Paul Mundtb12bb292012-03-30 19:50:15 +09001004 unsigned short status = serial_port_in(port, SCxSR);
Jiri Slaby92a19f92013-01-03 15:53:03 +01001005 struct tty_port *tport = &port->state->port;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001006
Paul Mundt0b3d4ef2007-03-14 13:22:37 +09001007 if (uart_handle_break(port))
1008 return 0;
1009
Laurent Pinchartd5cb1312017-01-11 16:43:38 +02001010 if (status & SCxSR_BRK(port)) {
Paul Mundtd97fbbe2011-11-24 19:15:06 +09001011 port->icount.brk++;
1012
Linus Torvalds1da177e2005-04-16 15:20:36 -07001013 /* Notify of BREAK */
Jiri Slaby92a19f92013-01-03 15:53:03 +01001014 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
Alan Cox33f0f882006-01-09 20:54:13 -08001015 copied++;
Paul Mundt762c69e2008-12-16 18:55:26 +09001016
1017 dev_dbg(port->dev, "BREAK detected\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001018 }
1019
Alan Cox33f0f882006-01-09 20:54:13 -08001020 if (copied)
Jiri Slaby2e124b42013-01-03 15:53:06 +01001021 tty_flip_buffer_push(tport);
Paul Mundte108b2c2006-09-27 16:32:13 +09001022
Paul Mundtd830fa42008-12-16 19:29:38 +09001023 copied += sci_handle_fifo_overrun(port);
1024
Linus Torvalds1da177e2005-04-16 15:20:36 -07001025 return copied;
1026}
1027
Ulrich Hechta380ed42017-02-02 18:10:16 +01001028static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1029{
1030 unsigned int bits;
1031
1032 if (rx_trig < 1)
1033 rx_trig = 1;
1034 if (rx_trig >= port->fifosize)
1035 rx_trig = port->fifosize;
1036
1037 /* HSCIF can be set to an arbitrary level. */
1038 if (sci_getreg(port, HSRTRGR)->size) {
1039 serial_port_out(port, HSRTRGR, rx_trig);
1040 return rx_trig;
1041 }
1042
1043 switch (port->type) {
1044 case PORT_SCIF:
1045 if (rx_trig < 4) {
1046 bits = 0;
1047 rx_trig = 1;
1048 } else if (rx_trig < 8) {
1049 bits = SCFCR_RTRG0;
1050 rx_trig = 4;
1051 } else if (rx_trig < 14) {
1052 bits = SCFCR_RTRG1;
1053 rx_trig = 8;
1054 } else {
1055 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1056 rx_trig = 14;
1057 }
1058 break;
1059 case PORT_SCIFA:
1060 case PORT_SCIFB:
1061 if (rx_trig < 16) {
1062 bits = 0;
1063 rx_trig = 1;
1064 } else if (rx_trig < 32) {
1065 bits = SCFCR_RTRG0;
1066 rx_trig = 16;
1067 } else if (rx_trig < 48) {
1068 bits = SCFCR_RTRG1;
1069 rx_trig = 32;
1070 } else {
1071 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1072 rx_trig = 48;
1073 }
1074 break;
1075 default:
1076 WARN(1, "unknown FIFO configuration");
1077 return 1;
1078 }
1079
1080 serial_port_out(port, SCFCR,
1081 (serial_port_in(port, SCFCR) &
1082 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1083
1084 return rx_trig;
1085}
1086
Ulrich Hecht03940372017-02-03 11:38:18 +01001087static int scif_rtrg_enabled(struct uart_port *port)
1088{
1089 if (sci_getreg(port, HSRTRGR)->size)
1090 return serial_port_in(port, HSRTRGR) != 0;
1091 else
1092 return (serial_port_in(port, SCFCR) &
1093 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1094}
1095
Kees Cooke99e88a2017-10-16 14:43:17 -07001096static void rx_fifo_timer_fn(struct timer_list *t)
Ulrich Hecht03940372017-02-03 11:38:18 +01001097{
Kees Cooke99e88a2017-10-16 14:43:17 -07001098 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
Ulrich Hecht03940372017-02-03 11:38:18 +01001099 struct uart_port *port = &s->port;
1100
1101 dev_dbg(port->dev, "Rx timed out\n");
1102 scif_set_rtrg(port, 1);
1103}
1104
Ulrich Hecht5d231882017-02-03 11:38:19 +01001105static ssize_t rx_trigger_show(struct device *dev,
1106 struct device_attribute *attr,
1107 char *buf)
1108{
1109 struct uart_port *port = dev_get_drvdata(dev);
1110 struct sci_port *sci = to_sci_port(port);
1111
1112 return sprintf(buf, "%d\n", sci->rx_trigger);
1113}
1114
1115static ssize_t rx_trigger_store(struct device *dev,
1116 struct device_attribute *attr,
1117 const char *buf,
1118 size_t count)
1119{
1120 struct uart_port *port = dev_get_drvdata(dev);
1121 struct sci_port *sci = to_sci_port(port);
Dan Carpenter4ab3c512017-07-17 11:34:23 +03001122 int ret;
Ulrich Hecht5d231882017-02-03 11:38:19 +01001123 long r;
1124
Dan Carpenter4ab3c512017-07-17 11:34:23 +03001125 ret = kstrtol(buf, 0, &r);
1126 if (ret)
1127 return ret;
Ulrich Hecht90afa522017-02-08 18:31:14 +01001128
Ulrich Hecht5d231882017-02-03 11:38:19 +01001129 sci->rx_trigger = scif_set_rtrg(port, r);
Ulrich Hecht90afa522017-02-08 18:31:14 +01001130 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1131 scif_set_rtrg(port, 1);
1132
Ulrich Hecht5d231882017-02-03 11:38:19 +01001133 return count;
1134}
1135
1136static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1137
1138static ssize_t rx_fifo_timeout_show(struct device *dev,
1139 struct device_attribute *attr,
1140 char *buf)
1141{
1142 struct uart_port *port = dev_get_drvdata(dev);
1143 struct sci_port *sci = to_sci_port(port);
Ulrich Hechtfa2abb02017-09-29 15:08:53 +02001144 int v;
Ulrich Hecht5d231882017-02-03 11:38:19 +01001145
Ulrich Hechtfa2abb02017-09-29 15:08:53 +02001146 if (port->type == PORT_HSCIF)
1147 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1148 else
1149 v = sci->rx_fifo_timeout;
1150
1151 return sprintf(buf, "%d\n", v);
Ulrich Hecht5d231882017-02-03 11:38:19 +01001152}
1153
1154static ssize_t rx_fifo_timeout_store(struct device *dev,
1155 struct device_attribute *attr,
1156 const char *buf,
1157 size_t count)
1158{
1159 struct uart_port *port = dev_get_drvdata(dev);
1160 struct sci_port *sci = to_sci_port(port);
Dan Carpenter4ab3c512017-07-17 11:34:23 +03001161 int ret;
Ulrich Hecht5d231882017-02-03 11:38:19 +01001162 long r;
1163
Dan Carpenter4ab3c512017-07-17 11:34:23 +03001164 ret = kstrtol(buf, 0, &r);
1165 if (ret)
1166 return ret;
Ulrich Hechtfa2abb02017-09-29 15:08:53 +02001167
1168 if (port->type == PORT_HSCIF) {
1169 if (r < 0 || r > 3)
1170 return -EINVAL;
1171 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1172 } else {
1173 sci->rx_fifo_timeout = r;
1174 scif_set_rtrg(port, 1);
1175 if (r > 0)
Kees Cooke99e88a2017-10-16 14:43:17 -07001176 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
Ulrich Hechtfa2abb02017-09-29 15:08:53 +02001177 }
1178
Ulrich Hecht5d231882017-02-03 11:38:19 +01001179 return count;
1180}
1181
Joe Perchesb6b996b2017-12-19 10:15:07 -08001182static DEVICE_ATTR_RW(rx_fifo_timeout);
Ulrich Hecht5d231882017-02-03 11:38:19 +01001183
1184
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001185#ifdef CONFIG_SERIAL_SH_SCI_DMA
1186static void sci_dma_tx_complete(void *arg)
1187{
1188 struct sci_port *s = arg;
1189 struct uart_port *port = &s->port;
1190 struct circ_buf *xmit = &port->state->xmit;
1191 unsigned long flags;
1192
1193 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1194
1195 spin_lock_irqsave(&port->lock, flags);
1196
1197 xmit->tail += s->tx_dma_len;
1198 xmit->tail &= UART_XMIT_SIZE - 1;
1199
1200 port->icount.tx += s->tx_dma_len;
1201
1202 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1203 uart_write_wakeup(port);
1204
1205 if (!uart_circ_empty(xmit)) {
1206 s->cookie_tx = 0;
1207 schedule_work(&s->work_tx);
1208 } else {
1209 s->cookie_tx = -EINVAL;
1210 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1211 u16 ctrl = serial_port_in(port, SCSCR);
1212 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1213 }
1214 }
1215
1216 spin_unlock_irqrestore(&port->lock, flags);
1217}
1218
1219/* Locking: called with port lock held */
1220static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1221{
1222 struct uart_port *port = &s->port;
1223 struct tty_port *tport = &port->state->port;
1224 int copied;
1225
1226 copied = tty_insert_flip_string(tport, buf, count);
Takatoshi Akiyama6fc5a522016-11-07 16:56:50 +01001227 if (copied < count)
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001228 port->icount.buf_overrun++;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001229
1230 port->icount.rx += copied;
1231
1232 return copied;
1233}
1234
1235static int sci_dma_rx_find_active(struct sci_port *s)
1236{
1237 unsigned int i;
1238
1239 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1240 if (s->active_rx == s->cookie_rx[i])
1241 return i;
1242
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001243 return -1;
1244}
1245
Geert Uytterhoeven11b37702019-01-07 17:23:17 +01001246static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1247{
1248 unsigned int i;
1249
1250 s->chan_rx = NULL;
1251 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1252 s->cookie_rx[i] = -EINVAL;
1253 s->active_rx = 0;
1254}
1255
Geert Uytterhoeven8fcf7a62019-01-07 17:23:20 +01001256static void sci_dma_rx_release(struct sci_port *s)
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001257{
Geert Uytterhoeven2c4ee232018-07-06 11:05:41 +02001258 struct dma_chan *chan = s->chan_rx_saved;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001259
Geert Uytterhoeven11b37702019-01-07 17:23:17 +01001260 s->chan_rx_saved = NULL;
1261 sci_dma_rx_chan_invalidate(s);
Geert Uytterhoeven6eefc682018-07-06 11:05:43 +02001262 dmaengine_terminate_sync(chan);
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001263 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1264 sg_dma_address(&s->sg_rx[0]));
1265 dma_release_channel(chan);
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001266}
1267
Ulrich Hechtb96408b2018-02-15 13:02:41 +01001268static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1269{
1270 long sec = usec / 1000000;
1271 long nsec = (usec % 1000000) * 1000;
1272 ktime_t t = ktime_set(sec, nsec);
1273
1274 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1275}
1276
Geert Uytterhoeven38766e42019-01-07 17:23:18 +01001277static void sci_dma_rx_reenable_irq(struct sci_port *s)
1278{
1279 struct uart_port *port = &s->port;
1280 u16 scr;
1281
1282 /* Direct new serial port interrupts back to CPU */
1283 scr = serial_port_in(port, SCSCR);
1284 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1285 scr &= ~SCSCR_RDRQE;
1286 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1287 }
1288 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1289}
1290
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001291static void sci_dma_rx_complete(void *arg)
1292{
1293 struct sci_port *s = arg;
Muhammad Hamza Farooq1d3db602015-09-18 13:08:30 +02001294 struct dma_chan *chan = s->chan_rx;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001295 struct uart_port *port = &s->port;
Geert Uytterhoeven67f462b02015-09-18 13:08:25 +02001296 struct dma_async_tx_descriptor *desc;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001297 unsigned long flags;
1298 int active, count = 0;
1299
1300 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1301 s->active_rx);
1302
1303 spin_lock_irqsave(&port->lock, flags);
1304
1305 active = sci_dma_rx_find_active(s);
1306 if (active >= 0)
1307 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1308
Ulrich Hechtb96408b2018-02-15 13:02:41 +01001309 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001310
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001311 if (count)
1312 tty_flip_buffer_push(&port->state->port);
1313
Geert Uytterhoeven67f462b02015-09-18 13:08:25 +02001314 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1315 DMA_DEV_TO_MEM,
1316 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1317 if (!desc)
1318 goto fail;
1319
1320 desc->callback = sci_dma_rx_complete;
1321 desc->callback_param = s;
1322 s->cookie_rx[active] = dmaengine_submit(desc);
1323 if (dma_submit_error(s->cookie_rx[active]))
1324 goto fail;
1325
1326 s->active_rx = s->cookie_rx[!active];
1327
Muhammad Hamza Farooq1d3db602015-09-18 13:08:30 +02001328 dma_async_issue_pending(chan);
1329
Takatoshi Akiyama6fc5a522016-11-07 16:56:50 +01001330 spin_unlock_irqrestore(&port->lock, flags);
Geert Uytterhoeven67f462b02015-09-18 13:08:25 +02001331 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1332 __func__, s->cookie_rx[active], active, s->active_rx);
Geert Uytterhoeven67f462b02015-09-18 13:08:25 +02001333 return;
1334
1335fail:
1336 spin_unlock_irqrestore(&port->lock, flags);
1337 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
Geert Uytterhoeven2c4ee232018-07-06 11:05:41 +02001338 /* Switch to PIO */
1339 spin_lock_irqsave(&port->lock, flags);
Geert Uytterhoeven26f07392019-01-07 17:23:19 +01001340 dmaengine_terminate_async(chan);
1341 sci_dma_rx_chan_invalidate(s);
1342 sci_dma_rx_reenable_irq(s);
Geert Uytterhoeven2c4ee232018-07-06 11:05:41 +02001343 spin_unlock_irqrestore(&port->lock, flags);
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001344}
1345
Geert Uytterhoeven8fcf7a62019-01-07 17:23:20 +01001346static void sci_dma_tx_release(struct sci_port *s)
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001347{
Geert Uytterhoeven2c4ee232018-07-06 11:05:41 +02001348 struct dma_chan *chan = s->chan_tx_saved;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001349
Geert Uytterhoevenf6611312018-07-06 11:05:42 +02001350 cancel_work_sync(&s->work_tx);
Geert Uytterhoeven2c4ee232018-07-06 11:05:41 +02001351 s->chan_tx_saved = s->chan_tx = NULL;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001352 s->cookie_tx = -EINVAL;
Geert Uytterhoeven6eefc682018-07-06 11:05:43 +02001353 dmaengine_terminate_sync(chan);
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001354 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1355 DMA_TO_DEVICE);
1356 dma_release_channel(chan);
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001357}
1358
Geert Uytterhoeven8fcf7a62019-01-07 17:23:20 +01001359static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001360{
1361 struct dma_chan *chan = s->chan_rx;
Geert Uytterhoeven2c4ee232018-07-06 11:05:41 +02001362 struct uart_port *port = &s->port;
1363 unsigned long flags;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001364 int i;
1365
1366 for (i = 0; i < 2; i++) {
1367 struct scatterlist *sg = &s->sg_rx[i];
1368 struct dma_async_tx_descriptor *desc;
1369
1370 desc = dmaengine_prep_slave_sg(chan,
1371 sg, 1, DMA_DEV_TO_MEM,
1372 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1373 if (!desc)
1374 goto fail;
1375
1376 desc->callback = sci_dma_rx_complete;
1377 desc->callback_param = s;
1378 s->cookie_rx[i] = dmaengine_submit(desc);
1379 if (dma_submit_error(s->cookie_rx[i]))
1380 goto fail;
1381
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001382 }
1383
1384 s->active_rx = s->cookie_rx[0];
1385
1386 dma_async_issue_pending(chan);
Geert Uytterhoeven71ab1c02018-12-13 19:44:43 +01001387 return 0;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001388
1389fail:
Geert Uytterhoevendd1f2252018-12-13 19:44:41 +01001390 /* Switch to PIO */
1391 if (!port_lock_held)
1392 spin_lock_irqsave(&port->lock, flags);
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001393 if (i)
Geert Uytterhoeven6eefc682018-07-06 11:05:43 +02001394 dmaengine_terminate_async(chan);
Geert Uytterhoeven11b37702019-01-07 17:23:17 +01001395 sci_dma_rx_chan_invalidate(s);
Geert Uytterhoeven2c4ee232018-07-06 11:05:41 +02001396 sci_start_rx(port);
Geert Uytterhoevendd1f2252018-12-13 19:44:41 +01001397 if (!port_lock_held)
1398 spin_unlock_irqrestore(&port->lock, flags);
Geert Uytterhoeven71ab1c02018-12-13 19:44:43 +01001399 return -EAGAIN;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001400}
1401
Geert Uytterhoeven8fcf7a62019-01-07 17:23:20 +01001402static void sci_dma_tx_work_fn(struct work_struct *work)
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001403{
1404 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1405 struct dma_async_tx_descriptor *desc;
1406 struct dma_chan *chan = s->chan_tx;
1407 struct uart_port *port = &s->port;
1408 struct circ_buf *xmit = &port->state->xmit;
Geert Uytterhoeven2c4ee232018-07-06 11:05:41 +02001409 unsigned long flags;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001410 dma_addr_t buf;
1411
1412 /*
1413 * DMA is idle now.
1414 * Port xmit buffer is already mapped, and it is one page... Just adjust
1415 * offsets and lengths. Since it is a circular buffer, we have to
1416 * transmit till the end, and then the rest. Take the port lock to get a
1417 * consistent xmit buffer state.
1418 */
1419 spin_lock_irq(&port->lock);
1420 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1421 s->tx_dma_len = min_t(unsigned int,
1422 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1423 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1424 spin_unlock_irq(&port->lock);
1425
1426 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1427 DMA_MEM_TO_DEV,
1428 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1429 if (!desc) {
1430 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
Geert Uytterhoeven2c4ee232018-07-06 11:05:41 +02001431 goto switch_to_pio;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001432 }
1433
1434 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1435 DMA_TO_DEVICE);
1436
1437 spin_lock_irq(&port->lock);
1438 desc->callback = sci_dma_tx_complete;
1439 desc->callback_param = s;
1440 spin_unlock_irq(&port->lock);
1441 s->cookie_tx = dmaengine_submit(desc);
1442 if (dma_submit_error(s->cookie_tx)) {
1443 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
Geert Uytterhoeven2c4ee232018-07-06 11:05:41 +02001444 goto switch_to_pio;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001445 }
1446
1447 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1448 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1449
1450 dma_async_issue_pending(chan);
Geert Uytterhoeven2c4ee232018-07-06 11:05:41 +02001451 return;
1452
1453switch_to_pio:
1454 spin_lock_irqsave(&port->lock, flags);
1455 s->chan_tx = NULL;
1456 sci_start_tx(port);
1457 spin_unlock_irqrestore(&port->lock, flags);
1458 return;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001459}
1460
Geert Uytterhoeven8fcf7a62019-01-07 17:23:20 +01001461static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001462{
Ulrich Hechtb96408b2018-02-15 13:02:41 +01001463 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
Muhammad Hamza Farooqe7327c02015-09-18 13:08:32 +02001464 struct dma_chan *chan = s->chan_rx;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001465 struct uart_port *port = &s->port;
Geert Uytterhoeven67f462b02015-09-18 13:08:25 +02001466 struct dma_tx_state state;
1467 enum dma_status status;
1468 unsigned long flags;
1469 unsigned int read;
1470 int active, count;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001471
Geert Uytterhoeven67f462b02015-09-18 13:08:25 +02001472 dev_dbg(port->dev, "DMA Rx timed out\n");
Geert Uytterhoeven67f462b02015-09-18 13:08:25 +02001473
Takatoshi Akiyama6fc5a522016-11-07 16:56:50 +01001474 spin_lock_irqsave(&port->lock, flags);
1475
Geert Uytterhoeven67f462b02015-09-18 13:08:25 +02001476 active = sci_dma_rx_find_active(s);
1477 if (active < 0) {
1478 spin_unlock_irqrestore(&port->lock, flags);
Ulrich Hechtb96408b2018-02-15 13:02:41 +01001479 return HRTIMER_NORESTART;
Geert Uytterhoeven67f462b02015-09-18 13:08:25 +02001480 }
1481
1482 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
Muhammad Hamza Farooq3b963042015-09-18 13:08:31 +02001483 if (status == DMA_COMPLETE) {
Takatoshi Akiyama6fc5a522016-11-07 16:56:50 +01001484 spin_unlock_irqrestore(&port->lock, flags);
Geert Uytterhoeven67f462b02015-09-18 13:08:25 +02001485 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1486 s->active_rx, active);
Muhammad Hamza Farooq3b963042015-09-18 13:08:31 +02001487
1488 /* Let packet complete handler take care of the packet */
Ulrich Hechtb96408b2018-02-15 13:02:41 +01001489 return HRTIMER_NORESTART;
Muhammad Hamza Farooq3b963042015-09-18 13:08:31 +02001490 }
Geert Uytterhoeven67f462b02015-09-18 13:08:25 +02001491
Muhammad Hamza Farooqe7327c02015-09-18 13:08:32 +02001492 dmaengine_pause(chan);
1493
1494 /*
1495 * sometimes DMA transfer doesn't stop even if it is stopped and
1496 * data keeps on coming until transaction is complete so check
1497 * for DMA_COMPLETE again
1498 * Let packet complete handler take care of the packet
1499 */
1500 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1501 if (status == DMA_COMPLETE) {
1502 spin_unlock_irqrestore(&port->lock, flags);
1503 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
Ulrich Hechtb96408b2018-02-15 13:02:41 +01001504 return HRTIMER_NORESTART;
Muhammad Hamza Farooqe7327c02015-09-18 13:08:32 +02001505 }
1506
Geert Uytterhoeven67f462b02015-09-18 13:08:25 +02001507 /* Handle incomplete DMA receive */
Geert Uytterhoeven6eefc682018-07-06 11:05:43 +02001508 dmaengine_terminate_async(s->chan_rx);
Geert Uytterhoeven67f462b02015-09-18 13:08:25 +02001509 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
Geert Uytterhoeven67f462b02015-09-18 13:08:25 +02001510
1511 if (read) {
1512 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1513 if (count)
1514 tty_flip_buffer_push(&port->state->port);
1515 }
1516
Geert Uytterhoeven756981b2015-09-18 13:08:26 +02001517 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
Geert Uytterhoeven8fcf7a62019-01-07 17:23:20 +01001518 sci_dma_rx_submit(s, true);
Muhammad Hamza Farooq371cfed2015-09-18 13:08:29 +02001519
Geert Uytterhoeven38766e42019-01-07 17:23:18 +01001520 sci_dma_rx_reenable_irq(s);
Muhammad Hamza Farooq371cfed2015-09-18 13:08:29 +02001521
1522 spin_unlock_irqrestore(&port->lock, flags);
Ulrich Hechtb96408b2018-02-15 13:02:41 +01001523
1524 return HRTIMER_NORESTART;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001525}
1526
Geert Uytterhoevenff441122015-09-18 13:08:33 +02001527static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
Laurent Pinchart219fb0c2017-01-11 16:43:37 +02001528 enum dma_transfer_direction dir)
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001529{
Geert Uytterhoevenff441122015-09-18 13:08:33 +02001530 struct dma_chan *chan;
1531 struct dma_slave_config cfg;
1532 int ret;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001533
Laurent Pinchart219fb0c2017-01-11 16:43:37 +02001534 chan = dma_request_slave_channel(port->dev,
1535 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
Geert Uytterhoevenff441122015-09-18 13:08:33 +02001536 if (!chan) {
Ulrich Hechtc58a3ae2018-10-12 15:47:49 +02001537 dev_dbg(port->dev, "dma_request_slave_channel failed\n");
Geert Uytterhoevenff441122015-09-18 13:08:33 +02001538 return NULL;
1539 }
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001540
Geert Uytterhoevenff441122015-09-18 13:08:33 +02001541 memset(&cfg, 0, sizeof(cfg));
1542 cfg.direction = dir;
1543 if (dir == DMA_MEM_TO_DEV) {
1544 cfg.dst_addr = port->mapbase +
1545 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1546 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1547 } else {
1548 cfg.src_addr = port->mapbase +
1549 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1550 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1551 }
1552
1553 ret = dmaengine_slave_config(chan, &cfg);
1554 if (ret) {
1555 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1556 dma_release_channel(chan);
1557 return NULL;
1558 }
1559
1560 return chan;
1561}
1562
1563static void sci_request_dma(struct uart_port *port)
1564{
1565 struct sci_port *s = to_sci_port(port);
1566 struct dma_chan *chan;
1567
1568 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1569
Laurent Pinchart219fb0c2017-01-11 16:43:37 +02001570 if (!port->dev->of_node)
Geert Uytterhoevenff441122015-09-18 13:08:33 +02001571 return;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001572
1573 s->cookie_tx = -EINVAL;
Andy Lowe74647792017-09-22 20:29:30 +02001574
1575 /*
1576 * Don't request a dma channel if no channel was specified
1577 * in the device tree.
1578 */
1579 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1580 return;
1581
Laurent Pinchart219fb0c2017-01-11 16:43:37 +02001582 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001583 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1584 if (chan) {
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001585 /* UART circular tx buffer is an aligned page. */
1586 s->tx_dma_addr = dma_map_single(chan->device->dev,
1587 port->state->xmit.buf,
1588 UART_XMIT_SIZE,
1589 DMA_TO_DEVICE);
1590 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1591 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1592 dma_release_channel(chan);
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001593 } else {
1594 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1595 __func__, UART_XMIT_SIZE,
1596 port->state->xmit.buf, &s->tx_dma_addr);
Geert Uytterhoeven2c4ee232018-07-06 11:05:41 +02001597
Geert Uytterhoeven8fcf7a62019-01-07 17:23:20 +01001598 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
Geert Uytterhoeven2c4ee232018-07-06 11:05:41 +02001599 s->chan_tx_saved = s->chan_tx = chan;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001600 }
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001601 }
1602
Laurent Pinchart219fb0c2017-01-11 16:43:37 +02001603 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001604 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1605 if (chan) {
1606 unsigned int i;
1607 dma_addr_t dma;
1608 void *buf;
1609
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001610 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1611 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1612 &dma, GFP_KERNEL);
1613 if (!buf) {
1614 dev_warn(port->dev,
1615 "Failed to allocate Rx dma buffer, using PIO\n");
1616 dma_release_channel(chan);
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001617 return;
1618 }
1619
1620 for (i = 0; i < 2; i++) {
1621 struct scatterlist *sg = &s->sg_rx[i];
1622
1623 sg_init_table(sg, 1);
1624 s->rx_buf[i] = buf;
1625 sg_dma_address(sg) = dma;
Yoshihiro Shimodad09959e2015-12-04 15:21:19 +01001626 sg_dma_len(sg) = s->buf_len_rx;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001627
1628 buf += s->buf_len_rx;
1629 dma += s->buf_len_rx;
1630 }
1631
Ulrich Hechtb96408b2018-02-15 13:02:41 +01001632 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
Geert Uytterhoeven8fcf7a62019-01-07 17:23:20 +01001633 s->rx_timer.function = sci_dma_rx_timer_fn;
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001634
Geert Uytterhoeven202dc3c2018-10-09 19:41:58 +02001635 s->chan_rx_saved = s->chan_rx = chan;
1636
Geert Uytterhoeven756981b2015-09-18 13:08:26 +02001637 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
Geert Uytterhoeven8fcf7a62019-01-07 17:23:20 +01001638 sci_dma_rx_submit(s, false);
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001639 }
1640}
1641
1642static void sci_free_dma(struct uart_port *port)
1643{
1644 struct sci_port *s = to_sci_port(port);
1645
Geert Uytterhoeven2c4ee232018-07-06 11:05:41 +02001646 if (s->chan_tx_saved)
Geert Uytterhoeven8fcf7a62019-01-07 17:23:20 +01001647 sci_dma_tx_release(s);
Geert Uytterhoeven2c4ee232018-07-06 11:05:41 +02001648 if (s->chan_rx_saved)
Geert Uytterhoeven8fcf7a62019-01-07 17:23:20 +01001649 sci_dma_rx_release(s);
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001650}
Geert Uytterhoeven1cf4a7e2017-04-25 20:15:35 +02001651
1652static void sci_flush_buffer(struct uart_port *port)
1653{
1654 /*
1655 * In uart_flush_buffer(), the xmit circular buffer has just been
1656 * cleared, so we have to reset tx_dma_len accordingly.
1657 */
1658 to_sci_port(port)->tx_dma_len = 0;
1659}
1660#else /* !CONFIG_SERIAL_SH_SCI_DMA */
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001661static inline void sci_request_dma(struct uart_port *port)
1662{
1663}
1664
1665static inline void sci_free_dma(struct uart_port *port)
1666{
1667}
Geert Uytterhoeven1cf4a7e2017-04-25 20:15:35 +02001668
1669#define sci_flush_buffer NULL
1670#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
Geert Uytterhoevene1910fc2015-09-18 13:08:24 +02001671
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09001672static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001673{
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09001674 struct uart_port *port = ptr;
1675 struct sci_port *s = to_sci_port(port);
1676
Ulrich Hecht03940372017-02-03 11:38:18 +01001677#ifdef CONFIG_SERIAL_SH_SCI_DMA
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09001678 if (s->chan_rx) {
Paul Mundtb12bb292012-03-30 19:50:15 +09001679 u16 scr = serial_port_in(port, SCSCR);
1680 u16 ssr = serial_port_in(port, SCxSR);
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09001681
1682 /* Disable future Rx interrupts */
Guennadi Liakhovetskid1d4b102010-05-23 16:39:09 +00001683 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
Guennadi Liakhovetski3089f382010-03-19 13:53:04 +00001684 disable_irq_nosync(irq);
Geert Uytterhoeven26de4f12014-03-11 11:11:19 +01001685 scr |= SCSCR_RDRQE;
Guennadi Liakhovetski3089f382010-03-19 13:53:04 +00001686 } else {
Geert Uytterhoeven8fcf7a62019-01-07 17:23:20 +01001687 if (sci_dma_rx_submit(s, false) < 0)
Geert Uytterhoeven71ab1c02018-12-13 19:44:43 +01001688 goto handle_pio;
1689
Paul Mundtf43dc232011-01-13 15:06:28 +09001690 scr &= ~SCSCR_RIE;
Guennadi Liakhovetski3089f382010-03-19 13:53:04 +00001691 }
Paul Mundtb12bb292012-03-30 19:50:15 +09001692 serial_port_out(port, SCSCR, scr);
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09001693 /* Clear current interrupt */
Geert Uytterhoeven54af5002015-08-21 20:02:28 +02001694 serial_port_out(port, SCxSR,
1695 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
Ulrich Hechtb96408b2018-02-15 13:02:41 +01001696 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
Guennadi Liakhovetski3089f382010-03-19 13:53:04 +00001697 jiffies, s->rx_timeout);
Ulrich Hechtb96408b2018-02-15 13:02:41 +01001698 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09001699
1700 return IRQ_HANDLED;
1701 }
Geert Uytterhoeven71ab1c02018-12-13 19:44:43 +01001702
1703handle_pio:
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09001704#endif
1705
Ulrich Hecht03940372017-02-03 11:38:18 +01001706 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1707 if (!scif_rtrg_enabled(port))
1708 scif_set_rtrg(port, s->rx_trigger);
1709
1710 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
Ulrich Hechtb96408b2018-02-15 13:02:41 +01001711 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
Ulrich Hecht03940372017-02-03 11:38:18 +01001712 }
1713
Linus Torvalds1da177e2005-04-16 15:20:36 -07001714 /* I think sci_receive_chars has to be called irrespective
1715 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1716 * to be disabled?
1717 */
Geert Uytterhoevened8c8e12018-11-07 14:37:31 +01001718 sci_receive_chars(port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001719
1720 return IRQ_HANDLED;
1721}
1722
David Howells7d12e782006-10-05 14:55:46 +01001723static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001724{
1725 struct uart_port *port = ptr;
Stuart Menefyfd78a762009-07-29 23:01:24 +09001726 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001727
Stuart Menefyfd78a762009-07-29 23:01:24 +09001728 spin_lock_irqsave(&port->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001729 sci_transmit_chars(port);
Stuart Menefyfd78a762009-07-29 23:01:24 +09001730 spin_unlock_irqrestore(&port->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001731
1732 return IRQ_HANDLED;
1733}
1734
Chris Brandt628c5342018-07-31 05:41:39 -05001735static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1736{
1737 struct uart_port *port = ptr;
1738
1739 /* Handle BREAKs */
1740 sci_handle_breaks(port);
1741 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1742
1743 return IRQ_HANDLED;
1744}
Chris Brandt8b0bbd92018-07-11 09:41:30 -05001745
David Howells7d12e782006-10-05 14:55:46 +01001746static irqreturn_t sci_er_interrupt(int irq, void *ptr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001747{
1748 struct uart_port *port = ptr;
Geert Uytterhoevene6403c12015-08-21 20:02:55 +02001749 struct sci_port *s = to_sci_port(port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001750
Chris Brandt628c5342018-07-31 05:41:39 -05001751 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
Chris Brandt8b0bbd92018-07-11 09:41:30 -05001752 /* Break and Error interrupts are muxed */
1753 unsigned short ssr_status = serial_port_in(port, SCxSR);
1754
1755 /* Break Interrupt */
1756 if (ssr_status & SCxSR_BRK(port))
1757 sci_br_interrupt(irq, ptr);
1758
1759 /* Break only? */
1760 if (!(ssr_status & SCxSR_ERRORS(port)))
1761 return IRQ_HANDLED;
1762 }
1763
Linus Torvalds1da177e2005-04-16 15:20:36 -07001764 /* Handle errors */
1765 if (port->type == PORT_SCI) {
1766 if (sci_handle_errors(port)) {
1767 /* discard character in rx buffer */
Paul Mundtb12bb292012-03-30 19:50:15 +09001768 serial_port_in(port, SCxSR);
Geert Uytterhoevena1b5b432015-08-21 20:02:25 +02001769 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001770 }
1771 } else {
Paul Mundtd830fa42008-12-16 19:29:38 +09001772 sci_handle_fifo_overrun(port);
Geert Uytterhoevene6403c12015-08-21 20:02:55 +02001773 if (!s->chan_rx)
Geert Uytterhoevened8c8e12018-11-07 14:37:31 +01001774 sci_receive_chars(port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001775 }
1776
Geert Uytterhoevena1b5b432015-08-21 20:02:25 +02001777 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001778
1779 /* Kick the transmission */
Yoshihiro Shimoda8eadb562015-08-21 20:02:56 +02001780 if (!s->chan_tx)
1781 sci_tx_interrupt(irq, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001782
1783 return IRQ_HANDLED;
1784}
1785
David Howells7d12e782006-10-05 14:55:46 +01001786static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001787{
Nobuhiro Iwamatsucb772fe2015-03-17 01:19:19 +09001788 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
Michael Trimarchia8884e32008-10-31 16:10:23 +09001789 struct uart_port *port = ptr;
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09001790 struct sci_port *s = to_sci_port(port);
Michael Trimarchia8884e32008-10-31 16:10:23 +09001791 irqreturn_t ret = IRQ_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001792
Paul Mundtb12bb292012-03-30 19:50:15 +09001793 ssr_status = serial_port_in(port, SCxSR);
1794 scr_status = serial_port_in(port, SCSCR);
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +02001795 if (s->params->overrun_reg == SCxSR)
Nobuhiro Iwamatsucb772fe2015-03-17 01:19:19 +09001796 orer_status = ssr_status;
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +02001797 else if (sci_getreg(port, s->params->overrun_reg)->size)
1798 orer_status = serial_port_in(port, s->params->overrun_reg);
Nobuhiro Iwamatsucb772fe2015-03-17 01:19:19 +09001799
Paul Mundtf43dc232011-01-13 15:06:28 +09001800 err_enabled = scr_status & port_rx_irq_mask(port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001801
1802 /* Tx Interrupt */
Paul Mundtf43dc232011-01-13 15:06:28 +09001803 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09001804 !s->chan_tx)
Michael Trimarchia8884e32008-10-31 16:10:23 +09001805 ret = sci_tx_interrupt(irq, ptr);
Paul Mundtf43dc232011-01-13 15:06:28 +09001806
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09001807 /*
1808 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1809 * DR flags
1810 */
1811 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
Geert Uytterhoevene0a12a22015-08-21 20:02:35 +02001812 (scr_status & SCSCR_RIE))
Michael Trimarchia8884e32008-10-31 16:10:23 +09001813 ret = sci_rx_interrupt(irq, ptr);
Paul Mundtf43dc232011-01-13 15:06:28 +09001814
Linus Torvalds1da177e2005-04-16 15:20:36 -07001815 /* Error Interrupt */
SUGIOKA Toshinobudd4da3a2009-07-07 05:32:07 +00001816 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
Michael Trimarchia8884e32008-10-31 16:10:23 +09001817 ret = sci_er_interrupt(irq, ptr);
Paul Mundtf43dc232011-01-13 15:06:28 +09001818
Linus Torvalds1da177e2005-04-16 15:20:36 -07001819 /* Break Interrupt */
SUGIOKA Toshinobudd4da3a2009-07-07 05:32:07 +00001820 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
Michael Trimarchia8884e32008-10-31 16:10:23 +09001821 ret = sci_br_interrupt(irq, ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001822
Hisashi Nakamura8b6ff842015-01-26 21:25:48 +09001823 /* Overrun Interrupt */
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +02001824 if (orer_status & s->params->overrun_mask) {
Nobuhiro Iwamatsucb772fe2015-03-17 01:19:19 +09001825 sci_handle_fifo_overrun(port);
Yoshihiro Shimoda90803072015-08-21 20:02:36 +02001826 ret = IRQ_HANDLED;
1827 }
Hisashi Nakamura8b6ff842015-01-26 21:25:48 +09001828
Michael Trimarchia8884e32008-10-31 16:10:23 +09001829 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001830}
1831
Geert Uytterhoevend56a91e2015-08-21 20:02:32 +02001832static const struct sci_irq_desc {
Paul Mundt9174fc82011-06-28 15:25:36 +09001833 const char *desc;
1834 irq_handler_t handler;
1835} sci_irq_desc[] = {
1836 /*
1837 * Split out handlers, the default case.
1838 */
1839 [SCIx_ERI_IRQ] = {
1840 .desc = "rx err",
1841 .handler = sci_er_interrupt,
1842 },
1843
1844 [SCIx_RXI_IRQ] = {
1845 .desc = "rx full",
1846 .handler = sci_rx_interrupt,
1847 },
1848
1849 [SCIx_TXI_IRQ] = {
1850 .desc = "tx empty",
1851 .handler = sci_tx_interrupt,
1852 },
1853
1854 [SCIx_BRI_IRQ] = {
1855 .desc = "break",
1856 .handler = sci_br_interrupt,
1857 },
1858
Chris Brandt628c5342018-07-31 05:41:39 -05001859 [SCIx_DRI_IRQ] = {
1860 .desc = "rx ready",
1861 .handler = sci_rx_interrupt,
1862 },
1863
1864 [SCIx_TEI_IRQ] = {
1865 .desc = "tx end",
1866 .handler = sci_tx_interrupt,
1867 },
1868
Paul Mundt9174fc82011-06-28 15:25:36 +09001869 /*
1870 * Special muxed handler.
1871 */
1872 [SCIx_MUX_IRQ] = {
1873 .desc = "mux",
1874 .handler = sci_mpxed_interrupt,
1875 },
1876};
1877
Linus Torvalds1da177e2005-04-16 15:20:36 -07001878static int sci_request_irq(struct sci_port *port)
1879{
Paul Mundt9174fc82011-06-28 15:25:36 +09001880 struct uart_port *up = &port->port;
Chris Brandt628c5342018-07-31 05:41:39 -05001881 int i, j, w, ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001882
Paul Mundt9174fc82011-06-28 15:25:36 +09001883 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
Geert Uytterhoevend56a91e2015-08-21 20:02:32 +02001884 const struct sci_irq_desc *desc;
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01001885 int irq;
Paul Mundte108b2c2006-09-27 16:32:13 +09001886
Chris Brandt628c5342018-07-31 05:41:39 -05001887 /* Check if already registered (muxed) */
1888 for (w = 0; w < i; w++)
1889 if (port->irqs[w] == port->irqs[i])
1890 w = i + 1;
1891 if (w > i)
1892 continue;
1893
Paul Mundt9174fc82011-06-28 15:25:36 +09001894 if (SCIx_IRQ_IS_MUXED(port)) {
1895 i = SCIx_MUX_IRQ;
1896 irq = up->irq;
Paul Mundt0e8963d2012-05-18 18:21:06 +09001897 } else {
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01001898 irq = port->irqs[i];
Paul Mundt9174fc82011-06-28 15:25:36 +09001899
Paul Mundt0e8963d2012-05-18 18:21:06 +09001900 /*
1901 * Certain port types won't support all of the
1902 * available interrupt sources.
1903 */
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01001904 if (unlikely(irq < 0))
Paul Mundt0e8963d2012-05-18 18:21:06 +09001905 continue;
1906 }
1907
Paul Mundt9174fc82011-06-28 15:25:36 +09001908 desc = sci_irq_desc + i;
Chris Brandt628c5342018-07-31 05:41:39 -05001909 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1910 dev_name(up->dev), desc->desc);
Pan Bian623ac1d2016-12-03 18:40:25 +08001911 if (!port->irqstr[j]) {
1912 ret = -ENOMEM;
Paul Mundt9174fc82011-06-28 15:25:36 +09001913 goto out_nomem;
Pan Bian623ac1d2016-12-03 18:40:25 +08001914 }
Paul Mundt762c69e2008-12-16 18:55:26 +09001915
Paul Mundt9174fc82011-06-28 15:25:36 +09001916 ret = request_irq(irq, desc->handler, up->irqflags,
1917 port->irqstr[j], port);
1918 if (unlikely(ret)) {
1919 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1920 goto out_noirq;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001921 }
1922 }
1923
1924 return 0;
Paul Mundt9174fc82011-06-28 15:25:36 +09001925
1926out_noirq:
1927 while (--i >= 0)
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01001928 free_irq(port->irqs[i], port);
Paul Mundt9174fc82011-06-28 15:25:36 +09001929
1930out_nomem:
1931 while (--j >= 0)
1932 kfree(port->irqstr[j]);
1933
1934 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001935}
1936
1937static void sci_free_irq(struct sci_port *port)
1938{
1939 int i;
1940
Paul Mundt9174fc82011-06-28 15:25:36 +09001941 /*
1942 * Intentionally in reverse order so we iterate over the muxed
1943 * IRQ first.
1944 */
1945 for (i = 0; i < SCIx_NR_IRQS; i++) {
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01001946 int irq = port->irqs[i];
Paul Mundt0e8963d2012-05-18 18:21:06 +09001947
1948 /*
1949 * Certain port types won't support all of the available
1950 * interrupt sources.
1951 */
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01001952 if (unlikely(irq < 0))
Paul Mundt0e8963d2012-05-18 18:21:06 +09001953 continue;
1954
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01001955 free_irq(port->irqs[i], port);
Paul Mundt9174fc82011-06-28 15:25:36 +09001956 kfree(port->irqstr[i]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001957
Paul Mundt9174fc82011-06-28 15:25:36 +09001958 if (SCIx_IRQ_IS_MUXED(port)) {
1959 /* If there's only one IRQ, we're done. */
1960 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001961 }
1962 }
1963}
1964
1965static unsigned int sci_tx_empty(struct uart_port *port)
1966{
Paul Mundtb12bb292012-03-30 19:50:15 +09001967 unsigned short status = serial_port_in(port, SCxSR);
Paul Mundt72b294c2011-06-14 17:38:19 +09001968 unsigned short in_tx_fifo = sci_txfill(port);
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09001969
1970 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001971}
1972
Geert Uytterhoeven33f50ff2016-06-03 12:00:10 +02001973static void sci_set_rts(struct uart_port *port, bool state)
1974{
1975 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1976 u16 data = serial_port_in(port, SCPDR);
1977
1978 /* Active low */
1979 if (state)
1980 data &= ~SCPDR_RTSD;
1981 else
1982 data |= SCPDR_RTSD;
1983 serial_port_out(port, SCPDR, data);
1984
1985 /* RTS# is output */
1986 serial_port_out(port, SCPCR,
1987 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1988 } else if (sci_getreg(port, SCSPTR)->size) {
1989 u16 ctrl = serial_port_in(port, SCSPTR);
1990
1991 /* Active low */
1992 if (state)
1993 ctrl &= ~SCSPTR_RTSDT;
1994 else
1995 ctrl |= SCSPTR_RTSDT;
1996 serial_port_out(port, SCSPTR, ctrl);
1997 }
1998}
1999
2000static bool sci_get_cts(struct uart_port *port)
2001{
2002 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2003 /* Active low */
2004 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2005 } else if (sci_getreg(port, SCSPTR)->size) {
2006 /* Active low */
2007 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2008 }
2009
2010 return true;
2011}
2012
Paul Mundtcdf7c422011-11-24 20:18:32 +09002013/*
2014 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2015 * CTS/RTS is supported in hardware by at least one port and controlled
2016 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2017 * handled via the ->init_pins() op, which is a bit of a one-way street,
2018 * lacking any ability to defer pin control -- this will later be
2019 * converted over to the GPIO framework).
Paul Mundtdc7e3ef2011-11-24 20:20:53 +09002020 *
2021 * Other modes (such as loopback) are supported generically on certain
2022 * port types, but not others. For these it's sufficient to test for the
2023 * existence of the support register and simply ignore the port type.
Paul Mundtcdf7c422011-11-24 20:18:32 +09002024 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002025static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2026{
Geert Uytterhoevenf907c9e2016-06-03 12:00:04 +02002027 struct sci_port *s = to_sci_port(port);
2028
Paul Mundtdc7e3ef2011-11-24 20:20:53 +09002029 if (mctrl & TIOCM_LOOP) {
Geert Uytterhoevend3184e62015-08-21 20:02:33 +02002030 const struct plat_sci_reg *reg;
Paul Mundtdc7e3ef2011-11-24 20:20:53 +09002031
2032 /*
2033 * Standard loopback mode for SCFCR ports.
2034 */
2035 reg = sci_getreg(port, SCFCR);
2036 if (reg->size)
Geert Uytterhoeven26de4f12014-03-11 11:11:19 +01002037 serial_port_out(port, SCFCR,
2038 serial_port_in(port, SCFCR) |
2039 SCFCR_LOOP);
Paul Mundtdc7e3ef2011-11-24 20:20:53 +09002040 }
Geert Uytterhoevenf907c9e2016-06-03 12:00:04 +02002041
2042 mctrl_gpio_set(s->gpios, mctrl);
Geert Uytterhoeven33f50ff2016-06-03 12:00:10 +02002043
Laurent Pinchart97ed9792017-01-11 16:43:39 +02002044 if (!s->has_rtscts)
Geert Uytterhoeven33f50ff2016-06-03 12:00:10 +02002045 return;
2046
2047 if (!(mctrl & TIOCM_RTS)) {
2048 /* Disable Auto RTS */
2049 serial_port_out(port, SCFCR,
2050 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2051
2052 /* Clear RTS */
2053 sci_set_rts(port, 0);
2054 } else if (s->autorts) {
2055 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2056 /* Enable RTS# pin function */
2057 serial_port_out(port, SCPCR,
2058 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2059 }
2060
2061 /* Enable Auto RTS */
2062 serial_port_out(port, SCFCR,
2063 serial_port_in(port, SCFCR) | SCFCR_MCE);
2064 } else {
2065 /* Set RTS */
2066 sci_set_rts(port, 1);
2067 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002068}
2069
2070static unsigned int sci_get_mctrl(struct uart_port *port)
2071{
Geert Uytterhoevenf907c9e2016-06-03 12:00:04 +02002072 struct sci_port *s = to_sci_port(port);
2073 struct mctrl_gpios *gpios = s->gpios;
2074 unsigned int mctrl = 0;
2075
2076 mctrl_gpio_get(gpios, &mctrl);
2077
Paul Mundtcdf7c422011-11-24 20:18:32 +09002078 /*
2079 * CTS/RTS is handled in hardware when supported, while nothing
Geert Uytterhoeven33f50ff2016-06-03 12:00:10 +02002080 * else is wired up.
Paul Mundtcdf7c422011-11-24 20:18:32 +09002081 */
Geert Uytterhoeven33f50ff2016-06-03 12:00:10 +02002082 if (s->autorts) {
2083 if (sci_get_cts(port))
2084 mctrl |= TIOCM_CTS;
2085 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
Geert Uytterhoevenf907c9e2016-06-03 12:00:04 +02002086 mctrl |= TIOCM_CTS;
Geert Uytterhoeven33f50ff2016-06-03 12:00:10 +02002087 }
Geert Uytterhoevenf907c9e2016-06-03 12:00:04 +02002088 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
2089 mctrl |= TIOCM_DSR;
2090 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
2091 mctrl |= TIOCM_CAR;
2092
2093 return mctrl;
2094}
2095
2096static void sci_enable_ms(struct uart_port *port)
2097{
2098 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002099}
2100
Linus Torvalds1da177e2005-04-16 15:20:36 -07002101static void sci_break_ctl(struct uart_port *port, int break_state)
2102{
Shimoda, Yoshihirobbb4ce52012-04-06 09:59:14 +09002103 unsigned short scscr, scsptr;
Takatoshi Akiyama1be22662017-11-02 11:14:55 +01002104 unsigned long flags;
Shimoda, Yoshihirobbb4ce52012-04-06 09:59:14 +09002105
Shimoda, Yoshihiroa4e02f62012-04-12 19:19:21 +09002106 /* check wheter the port has SCSPTR */
Geert Uytterhoevenabbf1212016-06-03 12:00:05 +02002107 if (!sci_getreg(port, SCSPTR)->size) {
Shimoda, Yoshihirobbb4ce52012-04-06 09:59:14 +09002108 /*
2109 * Not supported by hardware. Most parts couple break and rx
2110 * interrupts together, with break detection always enabled.
2111 */
Shimoda, Yoshihiroa4e02f62012-04-12 19:19:21 +09002112 return;
Shimoda, Yoshihirobbb4ce52012-04-06 09:59:14 +09002113 }
Shimoda, Yoshihiroa4e02f62012-04-12 19:19:21 +09002114
Takatoshi Akiyama1be22662017-11-02 11:14:55 +01002115 spin_lock_irqsave(&port->lock, flags);
Shimoda, Yoshihiroa4e02f62012-04-12 19:19:21 +09002116 scsptr = serial_port_in(port, SCSPTR);
2117 scscr = serial_port_in(port, SCSCR);
2118
2119 if (break_state == -1) {
2120 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2121 scscr &= ~SCSCR_TE;
2122 } else {
2123 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2124 scscr |= SCSCR_TE;
2125 }
2126
2127 serial_port_out(port, SCSPTR, scsptr);
2128 serial_port_out(port, SCSCR, scscr);
Takatoshi Akiyama1be22662017-11-02 11:14:55 +01002129 spin_unlock_irqrestore(&port->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002130}
2131
2132static int sci_startup(struct uart_port *port)
2133{
Magnus Damma5660ad2009-01-21 15:14:38 +00002134 struct sci_port *s = to_sci_port(port);
Paul Mundt073e84c2011-01-19 17:30:53 +09002135 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002136
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09002137 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2138
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09002139 sci_request_dma(port);
Paul Mundt073e84c2011-01-19 17:30:53 +09002140
Takatoshi Akiyama3c910172017-02-27 15:56:31 +09002141 ret = sci_request_irq(s);
2142 if (unlikely(ret < 0)) {
2143 sci_free_dma(port);
2144 return ret;
2145 }
2146
Linus Torvalds1da177e2005-04-16 15:20:36 -07002147 return 0;
2148}
2149
2150static void sci_shutdown(struct uart_port *port)
2151{
Magnus Damma5660ad2009-01-21 15:14:38 +00002152 struct sci_port *s = to_sci_port(port);
Shinya Kuribayashi33b48e12012-11-16 10:54:49 +09002153 unsigned long flags;
Geert Uytterhoeven5fd2b6e2016-06-26 11:20:21 +02002154 u16 scr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002155
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09002156 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2157
Geert Uytterhoeven33f50ff2016-06-03 12:00:10 +02002158 s->autorts = false;
Geert Uytterhoevenf907c9e2016-06-03 12:00:04 +02002159 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2160
Shinya Kuribayashi33b48e12012-11-16 10:54:49 +09002161 spin_lock_irqsave(&port->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002162 sci_stop_rx(port);
Russell Kingb129a8c2005-08-31 10:12:14 +01002163 sci_stop_tx(port);
Ulrich Hechtfa2abb02017-09-29 15:08:53 +02002164 /*
2165 * Stop RX and TX, disable related interrupts, keep clock source
2166 * and HSCIF TOT bits
2167 */
Geert Uytterhoeven5fd2b6e2016-06-26 11:20:21 +02002168 scr = serial_port_in(port, SCSCR);
Ulrich Hechtfa2abb02017-09-29 15:08:53 +02002169 serial_port_out(port, SCSCR, scr &
2170 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
Shinya Kuribayashi33b48e12012-11-16 10:54:49 +09002171 spin_unlock_irqrestore(&port->lock, flags);
Paul Mundt073e84c2011-01-19 17:30:53 +09002172
Aleksandar Mitev9ab76552015-09-18 13:08:28 +02002173#ifdef CONFIG_SERIAL_SH_SCI_DMA
Geert Uytterhoeven2c4ee232018-07-06 11:05:41 +02002174 if (s->chan_rx_saved) {
Aleksandar Mitev9ab76552015-09-18 13:08:28 +02002175 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2176 port->line);
Ulrich Hechtb96408b2018-02-15 13:02:41 +01002177 hrtimer_cancel(&s->rx_timer);
Aleksandar Mitev9ab76552015-09-18 13:08:28 +02002178 }
2179#endif
2180
Geert Uytterhoevenc5a92622018-07-06 11:08:36 +02002181 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2182 del_timer_sync(&s->rx_fifo_timer);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002183 sci_free_irq(s);
Takatoshi Akiyama3c910172017-02-27 15:56:31 +09002184 sci_free_dma(port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002185}
2186
Geert Uytterhoeven6af27bf2015-11-18 11:12:26 +01002187static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2188 unsigned int *srr)
Paul Mundt26c92f32009-06-24 18:23:52 +09002189{
Geert Uytterhoeven6af27bf2015-11-18 11:12:26 +01002190 unsigned long freq = s->clk_rates[SCI_SCK];
Geert Uytterhoeven6af27bf2015-11-18 11:12:26 +01002191 int err, min_err = INT_MAX;
Geert Uytterhoeven69eee8e2016-01-04 14:45:21 +01002192 unsigned int sr;
Laurent Pinchartec09c5e2013-12-06 10:59:20 +01002193
Geert Uytterhoeven7b5c0c02016-01-04 14:45:20 +01002194 if (s->port.type != PORT_HSCIF)
2195 freq *= 2;
Paul Mundte8183a62011-01-19 17:51:37 +09002196
Geert Uytterhoeven69eee8e2016-01-04 14:45:21 +01002197 for_each_sr(sr, s) {
Geert Uytterhoeven6af27bf2015-11-18 11:12:26 +01002198 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2199 if (abs(err) >= abs(min_err))
2200 continue;
2201
2202 min_err = err;
2203 *srr = sr - 1;
2204
2205 if (!err)
2206 break;
2207 }
2208
2209 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2210 *srr + 1);
2211 return min_err;
Paul Mundt26c92f32009-06-24 18:23:52 +09002212}
2213
Geert Uytterhoeven1270f862015-11-18 11:25:53 +01002214static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2215 unsigned long freq, unsigned int *dlr,
2216 unsigned int *srr)
Nobuhiro Iwamatsu730c4e72014-07-14 16:10:00 +09002217{
Geert Uytterhoeven1270f862015-11-18 11:25:53 +01002218 int err, min_err = INT_MAX;
Geert Uytterhoeven69eee8e2016-01-04 14:45:21 +01002219 unsigned int sr, dl;
Nobuhiro Iwamatsu730c4e72014-07-14 16:10:00 +09002220
Geert Uytterhoeven7b5c0c02016-01-04 14:45:20 +01002221 if (s->port.type != PORT_HSCIF)
2222 freq *= 2;
Nobuhiro Iwamatsu730c4e72014-07-14 16:10:00 +09002223
Geert Uytterhoeven69eee8e2016-01-04 14:45:21 +01002224 for_each_sr(sr, s) {
Geert Uytterhoeven1270f862015-11-18 11:25:53 +01002225 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2226 dl = clamp(dl, 1U, 65535U);
2227
2228 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2229 if (abs(err) >= abs(min_err))
2230 continue;
2231
2232 min_err = err;
2233 *dlr = dl;
2234 *srr = sr - 1;
2235
2236 if (!err)
2237 break;
2238 }
2239
2240 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2241 min_err, *dlr, *srr + 1);
2242 return min_err;
Nobuhiro Iwamatsu730c4e72014-07-14 16:10:00 +09002243}
2244
Geert Uytterhoevenb4a5c452015-11-16 17:22:16 +01002245/* calculate sample rate, BRR, and clock select */
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002246static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2247 unsigned int *brr, unsigned int *srr,
2248 unsigned int *cks)
Ulrich Hechtf303b362013-05-31 17:57:01 +02002249{
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002250 unsigned long freq = s->clk_rates[SCI_FCK];
Geert Uytterhoeven69eee8e2016-01-04 14:45:21 +01002251 unsigned int sr, br, prediv, scrate, c;
Geert Uytterhoeven6c513322015-11-16 16:33:22 +01002252 int err, min_err = INT_MAX;
Ulrich Hechtf303b362013-05-31 17:57:01 +02002253
Geert Uytterhoeven7b5c0c02016-01-04 14:45:20 +01002254 if (s->port.type != PORT_HSCIF)
2255 freq *= 2;
Geert Uytterhoevenb4a5c452015-11-16 17:22:16 +01002256
Geert Uytterhoeven6c513322015-11-16 16:33:22 +01002257 /*
2258 * Find the combination of sample rate and clock select with the
2259 * smallest deviation from the desired baud rate.
2260 * Prefer high sample rates to maximise the receive margin.
2261 *
2262 * M: Receive margin (%)
2263 * N: Ratio of bit rate to clock (N = sampling rate)
2264 * D: Clock duty (D = 0 to 1.0)
2265 * L: Frame length (L = 9 to 12)
2266 * F: Absolute value of clock frequency deviation
2267 *
2268 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2269 * (|D - 0.5| / N * (1 + F))|
2270 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2271 */
Geert Uytterhoeven69eee8e2016-01-04 14:45:21 +01002272 for_each_sr(sr, s) {
Ulrich Hechtf303b362013-05-31 17:57:01 +02002273 for (c = 0; c <= 3; c++) {
2274 /* integerized formulas from HSCIF documentation */
Geert Uytterhoeven7b5c0c02016-01-04 14:45:20 +01002275 prediv = sr * (1 << (2 * c + 1));
Geert Uytterhoevende01e6c2015-11-13 17:04:56 +01002276
2277 /*
2278 * We need to calculate:
Nobuhiro Iwamatsu730c4e72014-07-14 16:10:00 +09002279 *
Geert Uytterhoevende01e6c2015-11-13 17:04:56 +01002280 * br = freq / (prediv * bps) clamped to [1..256]
Geert Uytterhoeven881a7482015-11-16 15:54:47 +01002281 * err = freq / (br * prediv) - bps
Geert Uytterhoevende01e6c2015-11-13 17:04:56 +01002282 *
2283 * Watch out for overflow when calculating the desired
2284 * sampling clock rate!
Nobuhiro Iwamatsu730c4e72014-07-14 16:10:00 +09002285 */
Geert Uytterhoevende01e6c2015-11-13 17:04:56 +01002286 if (bps > UINT_MAX / prediv)
2287 break;
2288
2289 scrate = prediv * bps;
2290 br = DIV_ROUND_CLOSEST(freq, scrate);
Geert Uytterhoeven95a27032015-11-13 16:56:08 +01002291 br = clamp(br, 1U, 256U);
Geert Uytterhoeven6c513322015-11-16 16:33:22 +01002292
Geert Uytterhoeven881a7482015-11-16 15:54:47 +01002293 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
Geert Uytterhoeven6c513322015-11-16 16:33:22 +01002294 if (abs(err) >= abs(min_err))
Nobuhiro Iwamatsu730c4e72014-07-14 16:10:00 +09002295 continue;
2296
Geert Uytterhoeven6c513322015-11-16 16:33:22 +01002297 min_err = err;
Geert Uytterhoeven95a27032015-11-13 16:56:08 +01002298 *brr = br - 1;
Nobuhiro Iwamatsu730c4e72014-07-14 16:10:00 +09002299 *srr = sr - 1;
2300 *cks = c;
Geert Uytterhoeven6c513322015-11-16 16:33:22 +01002301
2302 if (!err)
2303 goto found;
Ulrich Hechtf303b362013-05-31 17:57:01 +02002304 }
2305 }
2306
Geert Uytterhoeven6c513322015-11-16 16:33:22 +01002307found:
Geert Uytterhoeven881a7482015-11-16 15:54:47 +01002308 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2309 min_err, *brr, *srr + 1, *cks);
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002310 return min_err;
Ulrich Hechtf303b362013-05-31 17:57:01 +02002311}
2312
Magnus Damm1ba76222011-08-03 03:47:36 +00002313static void sci_reset(struct uart_port *port)
2314{
Geert Uytterhoevend3184e62015-08-21 20:02:33 +02002315 const struct plat_sci_reg *reg;
Magnus Damm1ba76222011-08-03 03:47:36 +00002316 unsigned int status;
Ulrich Hecht18e8cf12017-02-03 11:38:17 +01002317 struct sci_port *s = to_sci_port(port);
Magnus Damm1ba76222011-08-03 03:47:36 +00002318
Ulrich Hechtfa2abb02017-09-29 15:08:53 +02002319 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
Magnus Damm1ba76222011-08-03 03:47:36 +00002320
Paul Mundt0979e0e2011-11-24 18:35:49 +09002321 reg = sci_getreg(port, SCFCR);
2322 if (reg->size)
Paul Mundtb12bb292012-03-30 19:50:15 +09002323 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
Geert Uytterhoeven2768cf42016-06-24 16:59:15 +02002324
2325 sci_clear_SCxSR(port,
2326 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2327 SCxSR_BREAK_CLEAR(port));
Geert Uytterhoevenfc2af332016-06-24 16:59:16 +02002328 if (sci_getreg(port, SCLSR)->size) {
2329 status = serial_port_in(port, SCLSR);
2330 status &= ~(SCLSR_TO | SCLSR_ORER);
2331 serial_port_out(port, SCLSR, status);
2332 }
Ulrich Hecht18e8cf12017-02-03 11:38:17 +01002333
Ulrich Hecht03940372017-02-03 11:38:18 +01002334 if (s->rx_trigger > 1) {
2335 if (s->rx_fifo_timeout) {
2336 scif_set_rtrg(port, 1);
Kees Cooke99e88a2017-10-16 14:43:17 -07002337 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
Ulrich Hecht03940372017-02-03 11:38:18 +01002338 } else {
Ulrich Hecht90afa522017-02-08 18:31:14 +01002339 if (port->type == PORT_SCIFA ||
2340 port->type == PORT_SCIFB)
2341 scif_set_rtrg(port, 1);
2342 else
2343 scif_set_rtrg(port, s->rx_trigger);
Ulrich Hecht03940372017-02-03 11:38:18 +01002344 }
2345 }
Magnus Damm1ba76222011-08-03 03:47:36 +00002346}
2347
Alan Cox606d0992006-12-08 02:38:45 -08002348static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2349 struct ktermios *old)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002350{
Ulrich Hecht03940372017-02-03 11:38:18 +01002351 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
Geert Uytterhoeven1270f862015-11-18 11:25:53 +01002352 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2353 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
Paul Mundt00b9de92009-06-24 17:53:33 +09002354 struct sci_port *s = to_sci_port(port);
Geert Uytterhoevend3184e62015-08-21 20:02:33 +02002355 const struct plat_sci_reg *reg;
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002356 int min_err = INT_MAX, err;
2357 unsigned long max_freq = 0;
2358 int best_clk = -1;
Takatoshi Akiyama1be22662017-11-02 11:14:55 +01002359 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002360
Nobuhiro Iwamatsu730c4e72014-07-14 16:10:00 +09002361 if ((termios->c_cflag & CSIZE) == CS7)
2362 smr_val |= SCSMR_CHR;
2363 if (termios->c_cflag & PARENB)
2364 smr_val |= SCSMR_PE;
2365 if (termios->c_cflag & PARODD)
2366 smr_val |= SCSMR_PE | SCSMR_ODD;
2367 if (termios->c_cflag & CSTOPB)
2368 smr_val |= SCSMR_STOP;
2369
Magnus Damm154280f2009-12-22 03:37:28 +00002370 /*
2371 * earlyprintk comes here early on with port->uartclk set to zero.
2372 * the clock framework is not up and running at this point so here
2373 * we assume that 115200 is the maximum baud rate. please note that
2374 * the baud rate is not programmed during earlyprintk - it is assumed
2375 * that the previous boot loader has enabled required clocks and
2376 * setup the baud rate generator hardware for us already.
2377 */
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002378 if (!port->uartclk) {
2379 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2380 goto done;
2381 }
Magnus Damm154280f2009-12-22 03:37:28 +00002382
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002383 for (i = 0; i < SCI_NUM_CLKS; i++)
2384 max_freq = max(max_freq, s->clk_rates[i]);
2385
Geert Uytterhoeven69eee8e2016-01-04 14:45:21 +01002386 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002387 if (!baud)
2388 goto done;
2389
2390 /*
2391 * There can be multiple sources for the sampling clock. Find the one
2392 * that gives us the smallest deviation from the desired baud rate.
2393 */
2394
Geert Uytterhoeven6af27bf2015-11-18 11:12:26 +01002395 /* Optional Undivided External Clock */
2396 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2397 port->type != PORT_SCIFB) {
2398 err = sci_sck_calc(s, baud, &srr1);
2399 if (abs(err) < abs(min_err)) {
2400 best_clk = SCI_SCK;
2401 scr_val = SCSCR_CKE1;
2402 sccks = SCCKS_CKS;
2403 min_err = err;
2404 srr = srr1;
2405 if (!err)
2406 goto done;
Ulrich Hechtf303b362013-05-31 17:57:01 +02002407 }
2408 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002409
Geert Uytterhoeven1270f862015-11-18 11:25:53 +01002410 /* Optional BRG Frequency Divided External Clock */
2411 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2412 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2413 &srr1);
2414 if (abs(err) < abs(min_err)) {
2415 best_clk = SCI_SCIF_CLK;
2416 scr_val = SCSCR_CKE1;
2417 sccks = 0;
2418 min_err = err;
2419 dl = dl1;
2420 srr = srr1;
2421 if (!err)
2422 goto done;
2423 }
2424 }
2425
2426 /* Optional BRG Frequency Divided Internal Clock */
2427 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2428 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2429 &srr1);
2430 if (abs(err) < abs(min_err)) {
2431 best_clk = SCI_BRG_INT;
2432 scr_val = SCSCR_CKE1;
2433 sccks = SCCKS_XIN;
2434 min_err = err;
2435 dl = dl1;
2436 srr = srr1;
2437 if (!min_err)
2438 goto done;
2439 }
2440 }
2441
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002442 /* Divided Functional Clock using standard Bit Rate Register */
2443 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2444 if (abs(err) < abs(min_err)) {
2445 best_clk = SCI_FCK;
Geert Uytterhoeven6af27bf2015-11-18 11:12:26 +01002446 scr_val = 0;
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002447 min_err = err;
2448 brr = brr1;
2449 srr = srr1;
2450 cks = cks1;
2451 }
2452
2453done:
2454 if (best_clk >= 0)
2455 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2456 s->clks[best_clk], baud, min_err);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002457
Paul Mundt23241d42011-06-28 13:55:31 +09002458 sci_port_enable(s);
Alexandre Courbot36003382011-03-03 08:04:42 +00002459
Geert Uytterhoeven6af27bf2015-11-18 11:12:26 +01002460 /*
2461 * Program the optional External Baud Rate Generator (BRG) first.
2462 * It controls the mux to select (H)SCK or frequency divided clock.
2463 */
Geert Uytterhoeven1270f862015-11-18 11:25:53 +01002464 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2465 serial_port_out(port, SCDL, dl);
Geert Uytterhoeven6af27bf2015-11-18 11:12:26 +01002466 serial_port_out(port, SCCKS, sccks);
Geert Uytterhoeven1270f862015-11-18 11:25:53 +01002467 }
Geert Uytterhoeven6af27bf2015-11-18 11:12:26 +01002468
Takatoshi Akiyama1be22662017-11-02 11:14:55 +01002469 spin_lock_irqsave(&port->lock, flags);
2470
Magnus Damm1ba76222011-08-03 03:47:36 +00002471 sci_reset(port);
Paul Mundte108b2c2006-09-27 16:32:13 +09002472
Paul Mundte108b2c2006-09-27 16:32:13 +09002473 uart_update_timeout(port, termios->c_cflag, baud);
2474
Ulrich Hecht63ba1e02018-04-04 17:48:51 +02002475 /* byte size and parity */
2476 switch (termios->c_cflag & CSIZE) {
2477 case CS5:
2478 bits = 7;
2479 break;
2480 case CS6:
2481 bits = 8;
2482 break;
2483 case CS7:
2484 bits = 9;
2485 break;
2486 default:
2487 bits = 10;
2488 break;
2489 }
2490
2491 if (termios->c_cflag & CSTOPB)
2492 bits++;
2493 if (termios->c_cflag & PARENB)
2494 bits++;
2495
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002496 if (best_clk >= 0) {
Geert Uytterhoeven92a05742016-01-04 14:45:22 +01002497 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2498 switch (srr + 1) {
2499 case 5: smr_val |= SCSMR_SRC_5; break;
2500 case 7: smr_val |= SCSMR_SRC_7; break;
2501 case 11: smr_val |= SCSMR_SRC_11; break;
2502 case 13: smr_val |= SCSMR_SRC_13; break;
2503 case 16: smr_val |= SCSMR_SRC_16; break;
2504 case 17: smr_val |= SCSMR_SRC_17; break;
2505 case 19: smr_val |= SCSMR_SRC_19; break;
2506 case 27: smr_val |= SCSMR_SRC_27; break;
2507 }
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002508 smr_val |= cks;
Ulrich Hechtfa2abb02017-09-29 15:08:53 +02002509 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
Takashi Yoshii9d482cc2012-11-16 10:52:49 +09002510 serial_port_out(port, SCSMR, smr_val);
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002511 serial_port_out(port, SCBRR, brr);
Ulrich Hecht63ba1e02018-04-04 17:48:51 +02002512 if (sci_getreg(port, HSSRR)->size) {
2513 unsigned int hssrr = srr | HSCIF_SRE;
2514 /* Calculate deviation from intended rate at the
2515 * center of the last stop bit in sampling clocks.
2516 */
2517 int last_stop = bits * 2 - 1;
2518 int deviation = min_err * srr * last_stop / 2 / baud;
2519
2520 if (abs(deviation) >= 2) {
2521 /* At least two sampling clocks off at the
2522 * last stop bit; we can increase the error
2523 * margin by shifting the sampling point.
2524 */
2525 int shift = min(-8, max(7, deviation / 2));
2526
2527 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2528 HSCIF_SRHP_MASK;
2529 hssrr |= HSCIF_SRDE;
2530 }
2531 serial_port_out(port, HSSRR, hssrr);
2532 }
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002533
2534 /* Wait one bit interval */
2535 udelay((1000000 + (baud - 1)) / baud);
2536 } else {
2537 /* Don't touch the bit rate configuration */
2538 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
Geert Uytterhoeven3a964ab2016-01-04 14:45:19 +01002539 smr_val |= serial_port_in(port, SCSMR) &
2540 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
Ulrich Hechtfa2abb02017-09-29 15:08:53 +02002541 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002542 serial_port_out(port, SCSMR, smr_val);
2543 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002544
Paul Mundtd5701642008-12-16 20:07:27 +09002545 sci_init_pins(port, termios->c_cflag);
Paul Mundt0979e0e2011-11-24 18:35:49 +09002546
Geert Uytterhoeven33f50ff2016-06-03 12:00:10 +02002547 port->status &= ~UPSTAT_AUTOCTS;
2548 s->autorts = false;
Paul Mundt73c3d532011-12-02 19:02:06 +09002549 reg = sci_getreg(port, SCFCR);
2550 if (reg->size) {
Paul Mundtb12bb292012-03-30 19:50:15 +09002551 unsigned short ctrl = serial_port_in(port, SCFCR);
Paul Mundt0979e0e2011-11-24 18:35:49 +09002552
Geert Uytterhoeven33f50ff2016-06-03 12:00:10 +02002553 if ((port->flags & UPF_HARD_FLOW) &&
2554 (termios->c_cflag & CRTSCTS)) {
2555 /* There is no CTS interrupt to restart the hardware */
2556 port->status |= UPSTAT_AUTOCTS;
2557 /* MCE is enabled when RTS is raised */
2558 s->autorts = true;
Paul Mundtfaf02f82011-12-02 17:44:50 +09002559 }
Paul Mundt73c3d532011-12-02 19:02:06 +09002560
2561 /*
2562 * As we've done a sci_reset() above, ensure we don't
2563 * interfere with the FIFOs while toggling MCE. As the
2564 * reset values could still be set, simply mask them out.
2565 */
2566 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2567
Paul Mundtb12bb292012-03-30 19:50:15 +09002568 serial_port_out(port, SCFCR, ctrl);
Paul Mundt0979e0e2011-11-24 18:35:49 +09002569 }
Geert Uytterhoeven5f768952017-03-28 11:13:45 +02002570 if (port->flags & UPF_HARD_FLOW) {
2571 /* Refresh (Auto) RTS */
2572 sci_set_mctrl(port, port->mctrl);
2573 }
Paul Mundtb7a76e42006-02-01 03:06:06 -08002574
Laurent Pinchart9f8325b2017-01-11 16:43:23 +02002575 scr_val |= SCSCR_RE | SCSCR_TE |
2576 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
Ulrich Hechtfa2abb02017-09-29 15:08:53 +02002577 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
Geert Uytterhoeven92a05742016-01-04 14:45:22 +01002578 if ((srr + 1 == 5) &&
2579 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2580 /*
2581 * In asynchronous mode, when the sampling rate is 1/5, first
2582 * received data may become invalid on some SCIFA and SCIFB.
2583 * To avoid this problem wait more than 1 serial data time (1
2584 * bit time x serial data number) after setting SCSCR.RE = 1.
2585 */
2586 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2587 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002588
Guennadi Liakhovetski3089f382010-03-19 13:53:04 +00002589 /*
Nobuhiro Iwamatsu5f6d8512015-03-17 01:19:54 +09002590 * Calculate delay for 2 DMA buffers (4 FIFO).
Geert Uytterhoevenf5835c12015-08-21 20:02:38 +02002591 * See serial_core.c::uart_update_timeout().
2592 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2593 * function calculates 1 jiffie for the data plus 5 jiffies for the
2594 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2595 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2596 * value obtained by this formula is too small. Therefore, if the value
2597 * is smaller than 20ms, use 20ms as the timeout value for DMA.
Guennadi Liakhovetski3089f382010-03-19 13:53:04 +00002598 */
Ulrich Hechtb96408b2018-02-15 13:02:41 +01002599 s->rx_frame = (10000 * bits) / (baud / 100);
Ulrich Hecht03940372017-02-03 11:38:18 +01002600#ifdef CONFIG_SERIAL_SH_SCI_DMA
Ulrich Hechtb96408b2018-02-15 13:02:41 +01002601 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2602 if (s->rx_timeout < 20)
2603 s->rx_timeout = 20;
Guennadi Liakhovetski3089f382010-03-19 13:53:04 +00002604#endif
2605
Linus Torvalds1da177e2005-04-16 15:20:36 -07002606 if ((termios->c_cflag & CREAD) != 0)
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09002607 sci_start_rx(port);
Alexandre Courbot36003382011-03-03 08:04:42 +00002608
Takatoshi Akiyama1be22662017-11-02 11:14:55 +01002609 spin_unlock_irqrestore(&port->lock, flags);
2610
Paul Mundt23241d42011-06-28 13:55:31 +09002611 sci_port_disable(s);
Geert Uytterhoevenf907c9e2016-06-03 12:00:04 +02002612
2613 if (UART_ENABLE_MS(port, termios->c_cflag))
2614 sci_enable_ms(port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002615}
2616
Teppei Kamijou0174e5c2012-11-16 10:51:55 +09002617static void sci_pm(struct uart_port *port, unsigned int state,
2618 unsigned int oldstate)
2619{
2620 struct sci_port *sci_port = to_sci_port(port);
2621
2622 switch (state) {
Geert Uytterhoevend3dfe5d2014-03-11 11:11:20 +01002623 case UART_PM_STATE_OFF:
Teppei Kamijou0174e5c2012-11-16 10:51:55 +09002624 sci_port_disable(sci_port);
2625 break;
2626 default:
2627 sci_port_enable(sci_port);
2628 break;
2629 }
2630}
2631
Linus Torvalds1da177e2005-04-16 15:20:36 -07002632static const char *sci_type(struct uart_port *port)
2633{
2634 switch (port->type) {
Michael Trimarchie7c98dc2008-11-13 18:18:35 +09002635 case PORT_IRDA:
2636 return "irda";
2637 case PORT_SCI:
2638 return "sci";
2639 case PORT_SCIF:
2640 return "scif";
2641 case PORT_SCIFA:
2642 return "scifa";
Guennadi Liakhovetskid1d4b102010-05-23 16:39:09 +00002643 case PORT_SCIFB:
2644 return "scifb";
Ulrich Hechtf303b362013-05-31 17:57:01 +02002645 case PORT_HSCIF:
2646 return "hscif";
Linus Torvalds1da177e2005-04-16 15:20:36 -07002647 }
2648
Paul Mundtfa439722008-09-04 18:53:58 +09002649 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002650}
2651
Paul Mundtf6e94952011-01-21 15:25:36 +09002652static int sci_remap_port(struct uart_port *port)
2653{
Yoshinori Satoe4d6f912015-05-16 23:57:31 +09002654 struct sci_port *sport = to_sci_port(port);
Paul Mundtf6e94952011-01-21 15:25:36 +09002655
2656 /*
2657 * Nothing to do if there's already an established membase.
2658 */
2659 if (port->membase)
2660 return 0;
2661
Laurent Pinchart3d73f322017-01-11 16:43:24 +02002662 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
Yoshinori Satoe4d6f912015-05-16 23:57:31 +09002663 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
Paul Mundtf6e94952011-01-21 15:25:36 +09002664 if (unlikely(!port->membase)) {
2665 dev_err(port->dev, "can't remap port#%d\n", port->line);
2666 return -ENXIO;
2667 }
2668 } else {
2669 /*
2670 * For the simple (and majority of) cases where we don't
2671 * need to do any remapping, just cast the cookie
2672 * directly.
2673 */
Jingoo Han3af4e962014-02-05 09:56:37 +09002674 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
Paul Mundtf6e94952011-01-21 15:25:36 +09002675 }
2676
2677 return 0;
2678}
2679
Linus Torvalds1da177e2005-04-16 15:20:36 -07002680static void sci_release_port(struct uart_port *port)
2681{
Yoshinori Satoe4d6f912015-05-16 23:57:31 +09002682 struct sci_port *sport = to_sci_port(port);
2683
Laurent Pinchart3d73f322017-01-11 16:43:24 +02002684 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
Paul Mundte2651642011-01-20 21:24:03 +09002685 iounmap(port->membase);
2686 port->membase = NULL;
2687 }
2688
Yoshinori Satoe4d6f912015-05-16 23:57:31 +09002689 release_mem_region(port->mapbase, sport->reg_size);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002690}
2691
2692static int sci_request_port(struct uart_port *port)
2693{
Paul Mundte2651642011-01-20 21:24:03 +09002694 struct resource *res;
Yoshinori Satoe4d6f912015-05-16 23:57:31 +09002695 struct sci_port *sport = to_sci_port(port);
Paul Mundtf6e94952011-01-21 15:25:36 +09002696 int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002697
Yoshinori Satoe4d6f912015-05-16 23:57:31 +09002698 res = request_mem_region(port->mapbase, sport->reg_size,
2699 dev_name(port->dev));
2700 if (unlikely(res == NULL)) {
2701 dev_err(port->dev, "request_mem_region failed.");
Paul Mundte2651642011-01-20 21:24:03 +09002702 return -EBUSY;
Yoshinori Satoe4d6f912015-05-16 23:57:31 +09002703 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002704
Paul Mundtf6e94952011-01-21 15:25:36 +09002705 ret = sci_remap_port(port);
2706 if (unlikely(ret != 0)) {
2707 release_resource(res);
2708 return ret;
Paul Mundt7ff731a2008-10-01 15:46:58 +09002709 }
Paul Mundte2651642011-01-20 21:24:03 +09002710
2711 return 0;
2712}
2713
2714static void sci_config_port(struct uart_port *port, int flags)
2715{
2716 if (flags & UART_CONFIG_TYPE) {
2717 struct sci_port *sport = to_sci_port(port);
2718
2719 port->type = sport->cfg->type;
2720 sci_request_port(port);
2721 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002722}
2723
2724static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2725{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002726 if (ser->baud_base < 2400)
2727 /* No paper tape reader for Mitch.. */
2728 return -EINVAL;
2729
2730 return 0;
2731}
2732
Julia Lawall069a47e2016-09-01 19:51:35 +02002733static const struct uart_ops sci_uart_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002734 .tx_empty = sci_tx_empty,
2735 .set_mctrl = sci_set_mctrl,
2736 .get_mctrl = sci_get_mctrl,
2737 .start_tx = sci_start_tx,
2738 .stop_tx = sci_stop_tx,
2739 .stop_rx = sci_stop_rx,
Geert Uytterhoevenf907c9e2016-06-03 12:00:04 +02002740 .enable_ms = sci_enable_ms,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002741 .break_ctl = sci_break_ctl,
2742 .startup = sci_startup,
2743 .shutdown = sci_shutdown,
Geert Uytterhoeven1cf4a7e2017-04-25 20:15:35 +02002744 .flush_buffer = sci_flush_buffer,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002745 .set_termios = sci_set_termios,
Teppei Kamijou0174e5c2012-11-16 10:51:55 +09002746 .pm = sci_pm,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002747 .type = sci_type,
2748 .release_port = sci_release_port,
2749 .request_port = sci_request_port,
2750 .config_port = sci_config_port,
2751 .verify_port = sci_verify_port,
Paul Mundt07d2a1a2008-12-11 19:06:43 +09002752#ifdef CONFIG_CONSOLE_POLL
2753 .poll_get_char = sci_poll_get_char,
2754 .poll_put_char = sci_poll_put_char,
2755#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002756};
2757
Laurent Pincharta9ec81f2015-09-14 15:14:23 +03002758static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2759{
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002760 const char *clk_names[] = {
2761 [SCI_FCK] = "fck",
Geert Uytterhoeven6af27bf2015-11-18 11:12:26 +01002762 [SCI_SCK] = "sck",
Geert Uytterhoeven1270f862015-11-18 11:25:53 +01002763 [SCI_BRG_INT] = "brg_int",
2764 [SCI_SCIF_CLK] = "scif_clk",
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002765 };
2766 struct clk *clk;
2767 unsigned int i;
Laurent Pincharta9ec81f2015-09-14 15:14:23 +03002768
Geert Uytterhoeven6af27bf2015-11-18 11:12:26 +01002769 if (sci_port->cfg->type == PORT_HSCIF)
2770 clk_names[SCI_SCK] = "hsck";
2771
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002772 for (i = 0; i < SCI_NUM_CLKS; i++) {
2773 clk = devm_clk_get(dev, clk_names[i]);
2774 if (PTR_ERR(clk) == -EPROBE_DEFER)
2775 return -EPROBE_DEFER;
Laurent Pincharta9ec81f2015-09-14 15:14:23 +03002776
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002777 if (IS_ERR(clk) && i == SCI_FCK) {
2778 /*
2779 * "fck" used to be called "sci_ick", and we need to
2780 * maintain DT backward compatibility.
2781 */
2782 clk = devm_clk_get(dev, "sci_ick");
2783 if (PTR_ERR(clk) == -EPROBE_DEFER)
2784 return -EPROBE_DEFER;
Laurent Pincharta9ec81f2015-09-14 15:14:23 +03002785
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002786 if (!IS_ERR(clk))
2787 goto found;
Laurent Pincharta9ec81f2015-09-14 15:14:23 +03002788
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002789 /*
2790 * Not all SH platforms declare a clock lookup entry
2791 * for SCI devices, in which case we need to get the
2792 * global "peripheral_clk" clock.
2793 */
2794 clk = devm_clk_get(dev, "peripheral_clk");
2795 if (!IS_ERR(clk))
2796 goto found;
2797
2798 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2799 PTR_ERR(clk));
2800 return PTR_ERR(clk);
2801 }
2802
2803found:
2804 if (IS_ERR(clk))
2805 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2806 PTR_ERR(clk));
2807 else
Geert Uytterhoevend63c16f2018-06-01 11:28:21 +02002808 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2809 clk, clk_get_rate(clk));
Geert Uytterhoevenf4998e52015-10-26 09:58:16 +01002810 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2811 }
2812 return 0;
Laurent Pincharta9ec81f2015-09-14 15:14:23 +03002813}
2814
Laurent Pinchartdaf5a892017-01-11 16:43:35 +02002815static const struct sci_port_params *
2816sci_probe_regmap(const struct plat_sci_port *cfg)
2817{
2818 unsigned int regtype;
2819
2820 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2821 return &sci_port_params[cfg->regtype];
2822
2823 switch (cfg->type) {
2824 case PORT_SCI:
2825 regtype = SCIx_SCI_REGTYPE;
2826 break;
2827 case PORT_IRDA:
2828 regtype = SCIx_IRDA_REGTYPE;
2829 break;
2830 case PORT_SCIFA:
2831 regtype = SCIx_SCIFA_REGTYPE;
2832 break;
2833 case PORT_SCIFB:
2834 regtype = SCIx_SCIFB_REGTYPE;
2835 break;
2836 case PORT_SCIF:
2837 /*
2838 * The SH-4 is a bit of a misnomer here, although that's
2839 * where this particular port layout originated. This
2840 * configuration (or some slight variation thereof)
2841 * remains the dominant model for all SCIFs.
2842 */
2843 regtype = SCIx_SH4_SCIF_REGTYPE;
2844 break;
2845 case PORT_HSCIF:
2846 regtype = SCIx_HSCIF_REGTYPE;
2847 break;
2848 default:
2849 pr_err("Can't probe register map for given port\n");
2850 return NULL;
2851 }
2852
2853 return &sci_port_params[regtype];
2854}
2855
Bill Pemberton9671f092012-11-19 13:21:50 -05002856static int sci_init_single(struct platform_device *dev,
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01002857 struct sci_port *sci_port, unsigned int index,
Laurent Pinchartdaf5a892017-01-11 16:43:35 +02002858 const struct plat_sci_port *p, bool early)
Paul Mundte108b2c2006-09-27 16:32:13 +09002859{
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09002860 struct uart_port *port = &sci_port->port;
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01002861 const struct resource *res;
Geert Uytterhoevena1c2fd72018-08-30 14:54:04 +02002862 unsigned int i;
Paul Mundt3127c6b2011-06-28 13:44:37 +09002863 int ret;
Paul Mundte108b2c2006-09-27 16:32:13 +09002864
Paul Mundt50f09592011-12-02 20:09:48 +09002865 sci_port->cfg = p;
2866
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09002867 port->ops = &sci_uart_ops;
2868 port->iotype = UPIO_MEM;
2869 port->line = index;
Markus Pietrek75136d42010-01-15 08:33:20 +09002870
Laurent Pinchart89b5c1a2013-12-06 10:59:52 +01002871 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2872 if (res == NULL)
2873 return -ENOMEM;
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01002874
Laurent Pinchart89b5c1a2013-12-06 10:59:52 +01002875 port->mapbase = res->start;
Yoshinori Satoe4d6f912015-05-16 23:57:31 +09002876 sci_port->reg_size = resource_size(res);
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01002877
Laurent Pinchart89b5c1a2013-12-06 10:59:52 +01002878 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2879 sci_port->irqs[i] = platform_get_irq(dev, i);
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01002880
Laurent Pinchart89b5c1a2013-12-06 10:59:52 +01002881 /* The SCI generates several interrupts. They can be muxed together or
2882 * connected to different interrupt lines. In the muxed case only one
Chris Brandt628c5342018-07-31 05:41:39 -05002883 * interrupt resource is specified as there is only one interrupt ID.
2884 * In the non-muxed case, up to 6 interrupt signals might be generated
2885 * from the SCI, however those signals might have their own individual
2886 * interrupt ID numbers, or muxed together with another interrupt.
Laurent Pinchart89b5c1a2013-12-06 10:59:52 +01002887 */
2888 if (sci_port->irqs[0] < 0)
2889 return -ENXIO;
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01002890
Chris Brandt628c5342018-07-31 05:41:39 -05002891 if (sci_port->irqs[1] < 0)
2892 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2893 sci_port->irqs[i] = sci_port->irqs[0];
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01002894
Laurent Pinchartdaf5a892017-01-11 16:43:35 +02002895 sci_port->params = sci_probe_regmap(p);
2896 if (unlikely(sci_port->params == NULL))
2897 return -EINVAL;
Laurent Pincharte095ee62017-01-11 16:43:34 +02002898
Ulrich Hecht18e8cf12017-02-03 11:38:17 +01002899 switch (p->type) {
2900 case PORT_SCIFB:
2901 sci_port->rx_trigger = 48;
2902 break;
2903 case PORT_HSCIF:
2904 sci_port->rx_trigger = 64;
2905 break;
2906 case PORT_SCIFA:
2907 sci_port->rx_trigger = 32;
2908 break;
2909 case PORT_SCIF:
2910 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2911 /* RX triggering not implemented for this IP */
2912 sci_port->rx_trigger = 1;
2913 else
2914 sci_port->rx_trigger = 8;
2915 break;
2916 default:
2917 sci_port->rx_trigger = 1;
2918 break;
2919 }
2920
Ulrich Hecht03940372017-02-03 11:38:18 +01002921 sci_port->rx_fifo_timeout = 0;
Ulrich Hechtfa2abb02017-09-29 15:08:53 +02002922 sci_port->hscif_tot = 0;
Ulrich Hecht03940372017-02-03 11:38:18 +01002923
Laurent Pinchart878fbb912013-12-06 10:59:51 +01002924 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2925 * match the SoC datasheet, this should be investigated. Let platform
2926 * data override the sampling rate for now.
Laurent Pinchartec09c5e2013-12-06 10:59:20 +01002927 */
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +02002928 sci_port->sampling_rate_mask = p->sampling_rate
2929 ? SCI_SR(p->sampling_rate)
2930 : sci_port->params->sampling_rate_mask;
Laurent Pinchartec09c5e2013-12-06 10:59:20 +01002931
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01002932 if (!early) {
Laurent Pincharta9ec81f2015-09-14 15:14:23 +03002933 ret = sci_init_clocks(sci_port, &dev->dev);
2934 if (ret < 0)
2935 return ret;
Paul Mundtc7ed1ab2010-03-10 18:35:14 +09002936
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09002937 port->dev = &dev->dev;
Magnus Damm5e50d2d2011-04-19 10:38:25 +00002938
2939 pm_runtime_enable(&dev->dev);
Magnus Damm7b6fd3b2009-12-14 10:24:42 +00002940 }
Paul Mundte108b2c2006-09-27 16:32:13 +09002941
Paul Mundtce6738b2011-01-19 15:24:40 +09002942 port->type = p->type;
Laurent Pinchart3d73f322017-01-11 16:43:24 +02002943 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
Laurent Pinchartb2f20ed2017-01-11 16:43:36 +02002944 port->fifosize = sci_port->params->fifosize;
Paul Mundtce6738b2011-01-19 15:24:40 +09002945
Laurent Pinchartdfc80382017-01-11 16:43:40 +02002946 if (port->type == PORT_SCI) {
2947 if (sci_port->reg_size >= 0x20)
2948 port->regshift = 2;
2949 else
2950 port->regshift = 1;
2951 }
2952
Paul Mundtce6738b2011-01-19 15:24:40 +09002953 /*
Paul Mundt61a69762011-06-14 12:40:19 +09002954 * The UART port needs an IRQ value, so we peg this to the RX IRQ
Paul Mundtce6738b2011-01-19 15:24:40 +09002955 * for the multi-IRQ ports, which is where we are primarily
2956 * concerned with the shutdown path synchronization.
2957 *
2958 * For the muxed case there's nothing more to do.
2959 */
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01002960 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
Yong Zhang9cfb5c02011-09-22 16:59:15 +08002961 port->irqflags = 0;
Guennadi Liakhovetski73a19e4c2010-03-02 11:39:15 +09002962
Paul Mundt61a69762011-06-14 12:40:19 +09002963 port->serial_in = sci_serial_in;
2964 port->serial_out = sci_serial_out;
2965
Paul Mundtc7ed1ab2010-03-10 18:35:14 +09002966 return 0;
Paul Mundte108b2c2006-09-27 16:32:13 +09002967}
2968
Laurent Pinchart6dae1422012-06-13 00:28:23 +02002969static void sci_cleanup_single(struct sci_port *port)
2970{
Laurent Pinchart6dae1422012-06-13 00:28:23 +02002971 pm_runtime_disable(port->port.dev);
2972}
2973
Yoshinori Sato0b0cced2015-12-24 11:24:48 +01002974#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2975 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
Magnus Dammdc8e6f52009-01-21 15:14:06 +00002976static void serial_console_putchar(struct uart_port *port, int ch)
2977{
2978 sci_poll_put_char(port, ch);
2979}
2980
Linus Torvalds1da177e2005-04-16 15:20:36 -07002981/*
2982 * Print a string to the serial port trying not to disturb
2983 * any possible real use of the port...
2984 */
2985static void serial_console_write(struct console *co, const char *s,
2986 unsigned count)
2987{
Paul Mundt906b17d2011-01-21 16:19:53 +09002988 struct sci_port *sci_port = &sci_ports[co->index];
2989 struct uart_port *port = &sci_port->port;
Geert Uytterhoevena67969b2015-11-18 16:20:44 +01002990 unsigned short bits, ctrl, ctrl_temp;
Shinya Kuribayashi40f70c02012-11-16 10:54:15 +09002991 unsigned long flags;
2992 int locked = 1;
2993
Yoshinori Sato0b0cced2015-12-24 11:24:48 +01002994#if defined(SUPPORT_SYSRQ)
Shinya Kuribayashi40f70c02012-11-16 10:54:15 +09002995 if (port->sysrq)
2996 locked = 0;
Yoshinori Sato0b0cced2015-12-24 11:24:48 +01002997 else
2998#endif
2999 if (oops_in_progress)
Daniel Wagner8afb1d22018-05-08 10:55:09 +02003000 locked = spin_trylock_irqsave(&port->lock, flags);
Shinya Kuribayashi40f70c02012-11-16 10:54:15 +09003001 else
Daniel Wagner8afb1d22018-05-08 10:55:09 +02003002 spin_lock_irqsave(&port->lock, flags);
Shinya Kuribayashi40f70c02012-11-16 10:54:15 +09003003
Geert Uytterhoevena67969b2015-11-18 16:20:44 +01003004 /* first save SCSCR then disable interrupts, keep clock source */
Shinya Kuribayashi40f70c02012-11-16 10:54:15 +09003005 ctrl = serial_port_in(port, SCSCR);
Laurent Pinchart9f8325b2017-01-11 16:43:23 +02003006 ctrl_temp = SCSCR_RE | SCSCR_TE |
3007 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
Geert Uytterhoevena67969b2015-11-18 16:20:44 +01003008 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
Ulrich Hechtfa2abb02017-09-29 15:08:53 +02003009 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
Paul Mundt07d2a1a2008-12-11 19:06:43 +09003010
Magnus Damm501b8252009-01-21 15:14:30 +00003011 uart_console_write(port, s, count, serial_console_putchar);
Magnus Damm973e5d52009-02-24 15:57:12 +09003012
3013 /* wait until fifo is empty and last bit has been transmitted */
3014 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
Paul Mundtb12bb292012-03-30 19:50:15 +09003015 while ((serial_port_in(port, SCxSR) & bits) != bits)
Magnus Damm973e5d52009-02-24 15:57:12 +09003016 cpu_relax();
Shinya Kuribayashi40f70c02012-11-16 10:54:15 +09003017
3018 /* restore the SCSCR */
3019 serial_port_out(port, SCSCR, ctrl);
3020
3021 if (locked)
Daniel Wagner8afb1d22018-05-08 10:55:09 +02003022 spin_unlock_irqrestore(&port->lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003023}
3024
Bill Pemberton9671f092012-11-19 13:21:50 -05003025static int serial_console_setup(struct console *co, char *options)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003026{
Magnus Dammdc8e6f52009-01-21 15:14:06 +00003027 struct sci_port *sci_port;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003028 struct uart_port *port;
3029 int baud = 115200;
3030 int bits = 8;
3031 int parity = 'n';
3032 int flow = 'n';
3033 int ret;
3034
Paul Mundte108b2c2006-09-27 16:32:13 +09003035 /*
Paul Mundt906b17d2011-01-21 16:19:53 +09003036 * Refuse to handle any bogus ports.
Paul Mundte108b2c2006-09-27 16:32:13 +09003037 */
Paul Mundt906b17d2011-01-21 16:19:53 +09003038 if (co->index < 0 || co->index >= SCI_NPORTS)
Paul Mundte108b2c2006-09-27 16:32:13 +09003039 return -ENODEV;
Paul Mundte108b2c2006-09-27 16:32:13 +09003040
Paul Mundt906b17d2011-01-21 16:19:53 +09003041 sci_port = &sci_ports[co->index];
3042 port = &sci_port->port;
3043
Alexandre Courbotb2267a62011-02-09 03:18:46 +00003044 /*
3045 * Refuse to handle uninitialized ports.
3046 */
3047 if (!port->ops)
3048 return -ENODEV;
3049
Paul Mundtf6e94952011-01-21 15:25:36 +09003050 ret = sci_remap_port(port);
3051 if (unlikely(ret != 0))
3052 return ret;
Paul Mundte108b2c2006-09-27 16:32:13 +09003053
Linus Torvalds1da177e2005-04-16 15:20:36 -07003054 if (options)
3055 uart_parse_options(options, &baud, &parity, &bits, &flow);
3056
Paul Mundtab7cfb52011-06-01 14:47:42 +09003057 return uart_set_options(port, co, baud, parity, bits, flow);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003058}
3059
3060static struct console serial_console = {
3061 .name = "ttySC",
Paul Mundt906b17d2011-01-21 16:19:53 +09003062 .device = uart_console_device,
Linus Torvalds1da177e2005-04-16 15:20:36 -07003063 .write = serial_console_write,
3064 .setup = serial_console_setup,
Paul Mundtfa5da2f2007-03-08 17:27:37 +09003065 .flags = CON_PRINTBUFFER,
Linus Torvalds1da177e2005-04-16 15:20:36 -07003066 .index = -1,
Paul Mundt906b17d2011-01-21 16:19:53 +09003067 .data = &sci_uart_driver,
Linus Torvalds1da177e2005-04-16 15:20:36 -07003068};
3069
Magnus Damm7b6fd3b2009-12-14 10:24:42 +00003070static struct console early_serial_console = {
3071 .name = "early_ttySC",
3072 .write = serial_console_write,
3073 .flags = CON_PRINTBUFFER,
Paul Mundt906b17d2011-01-21 16:19:53 +09003074 .index = -1,
Magnus Damm7b6fd3b2009-12-14 10:24:42 +00003075};
Paul Mundtecdf8a42011-01-21 00:05:48 +09003076
Magnus Damm7b6fd3b2009-12-14 10:24:42 +00003077static char early_serial_buf[32];
3078
Bill Pemberton9671f092012-11-19 13:21:50 -05003079static int sci_probe_earlyprintk(struct platform_device *pdev)
Paul Mundtecdf8a42011-01-21 00:05:48 +09003080{
Laurent Pinchartdaf5a892017-01-11 16:43:35 +02003081 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
Paul Mundtecdf8a42011-01-21 00:05:48 +09003082
3083 if (early_serial_console.data)
3084 return -EEXIST;
3085
3086 early_serial_console.index = pdev->id;
Paul Mundtecdf8a42011-01-21 00:05:48 +09003087
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01003088 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
Paul Mundtecdf8a42011-01-21 00:05:48 +09003089
3090 serial_console_setup(&early_serial_console, early_serial_buf);
3091
3092 if (!strstr(early_serial_buf, "keep"))
3093 early_serial_console.flags |= CON_BOOT;
3094
3095 register_console(&early_serial_console);
3096 return 0;
3097}
Nobuhiro Iwamatsu6a8c9792011-03-24 02:20:56 +00003098
3099#define SCI_CONSOLE (&serial_console)
3100
Paul Mundtecdf8a42011-01-21 00:05:48 +09003101#else
Bill Pemberton9671f092012-11-19 13:21:50 -05003102static inline int sci_probe_earlyprintk(struct platform_device *pdev)
Paul Mundtecdf8a42011-01-21 00:05:48 +09003103{
3104 return -EINVAL;
3105}
Linus Torvalds1da177e2005-04-16 15:20:36 -07003106
Nobuhiro Iwamatsu6a8c9792011-03-24 02:20:56 +00003107#define SCI_CONSOLE NULL
3108
Yoshinori Sato0b0cced2015-12-24 11:24:48 +01003109#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003110
Geert Uytterhoeven6c13d5d2014-03-11 11:11:17 +01003111static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
Linus Torvalds1da177e2005-04-16 15:20:36 -07003112
Sjoerd Simons352b9262017-04-20 14:13:01 +02003113static DEFINE_MUTEX(sci_uart_registration_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003114static struct uart_driver sci_uart_driver = {
3115 .owner = THIS_MODULE,
3116 .driver_name = "sci",
Linus Torvalds1da177e2005-04-16 15:20:36 -07003117 .dev_name = "ttySC",
3118 .major = SCI_MAJOR,
3119 .minor = SCI_MINOR_START,
Paul Mundte108b2c2006-09-27 16:32:13 +09003120 .nr = SCI_NPORTS,
Linus Torvalds1da177e2005-04-16 15:20:36 -07003121 .cons = SCI_CONSOLE,
3122};
3123
Paul Mundt54507f62009-05-08 23:48:33 +09003124static int sci_remove(struct platform_device *dev)
Magnus Damme552de22009-01-21 15:13:42 +00003125{
Paul Mundtd535a232011-01-19 17:19:35 +09003126 struct sci_port *port = platform_get_drvdata(dev);
Yoshihiro Shimoda641a41d2018-10-30 15:13:35 +09003127 unsigned int type = port->port.type; /* uart_remove_... clears it */
Magnus Damme552de22009-01-21 15:13:42 +00003128
Geert Uytterhoeven7678f4c2018-03-05 18:17:40 +01003129 sci_ports_in_use &= ~BIT(port->port.line);
Paul Mundtd535a232011-01-19 17:19:35 +09003130 uart_remove_one_port(&sci_uart_driver, &port->port);
Magnus Damme552de22009-01-21 15:13:42 +00003131
Laurent Pinchart6dae1422012-06-13 00:28:23 +02003132 sci_cleanup_single(port);
Paul Mundtd535a232011-01-19 17:19:35 +09003133
Ulrich Hecht5d231882017-02-03 11:38:19 +01003134 if (port->port.fifosize > 1) {
3135 sysfs_remove_file(&dev->dev.kobj,
3136 &dev_attr_rx_fifo_trigger.attr);
3137 }
Yoshihiro Shimoda641a41d2018-10-30 15:13:35 +09003138 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) {
Ulrich Hecht5d231882017-02-03 11:38:19 +01003139 sysfs_remove_file(&dev->dev.kobj,
3140 &dev_attr_rx_fifo_timeout.attr);
3141 }
3142
Magnus Damme552de22009-01-21 15:13:42 +00003143 return 0;
3144}
3145
Geert Uytterhoevenbd2238f2015-11-10 16:09:23 +01003146
3147#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3148#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3149#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003150
3151static const struct of_device_id of_sci_match[] = {
Geert Uytterhoevenf443ff82015-11-10 16:16:54 +01003152 /* SoC-specific types */
3153 {
3154 .compatible = "renesas,scif-r7s72100",
3155 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3156 },
Geert Uytterhoeven10c63442018-08-30 14:54:03 +02003157 {
3158 .compatible = "renesas,scif-r7s9210",
3159 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3160 },
Geert Uytterhoeven9ed44bb2015-11-10 18:57:23 +01003161 /* Family-specific types */
3162 {
3163 .compatible = "renesas,rcar-gen1-scif",
3164 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3165 }, {
3166 .compatible = "renesas,rcar-gen2-scif",
3167 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3168 }, {
3169 .compatible = "renesas,rcar-gen3-scif",
3170 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3171 },
Geert Uytterhoevenf443ff82015-11-10 16:16:54 +01003172 /* Generic types */
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003173 {
3174 .compatible = "renesas,scif",
Geert Uytterhoevenbd2238f2015-11-10 16:09:23 +01003175 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003176 }, {
3177 .compatible = "renesas,scifa",
Geert Uytterhoevenbd2238f2015-11-10 16:09:23 +01003178 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003179 }, {
3180 .compatible = "renesas,scifb",
Geert Uytterhoevenbd2238f2015-11-10 16:09:23 +01003181 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003182 }, {
3183 .compatible = "renesas,hscif",
Geert Uytterhoevenbd2238f2015-11-10 16:09:23 +01003184 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003185 }, {
Yoshinori Satoe1d0be62015-01-28 02:53:55 +09003186 .compatible = "renesas,sci",
Geert Uytterhoevenbd2238f2015-11-10 16:09:23 +01003187 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
Yoshinori Satoe1d0be62015-01-28 02:53:55 +09003188 }, {
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003189 /* Terminator */
3190 },
3191};
3192MODULE_DEVICE_TABLE(of, of_sci_match);
3193
Geert Uytterhoeven54b12c42017-01-25 15:55:49 +01003194static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3195 unsigned int *dev_id)
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003196{
3197 struct device_node *np = pdev->dev.of_node;
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003198 struct plat_sci_port *p;
Laurent Pinchart97ed9792017-01-11 16:43:39 +02003199 struct sci_port *sp;
Geert Uytterhoeven6e605a02017-10-04 14:21:56 +02003200 const void *data;
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003201 int id;
3202
3203 if (!IS_ENABLED(CONFIG_OF) || !np)
3204 return NULL;
3205
Geert Uytterhoeven6e605a02017-10-04 14:21:56 +02003206 data = of_device_get_match_data(&pdev->dev);
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003207
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003208 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
Geert Uytterhoeven42054632015-08-21 20:02:34 +02003209 if (!p)
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003210 return NULL;
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003211
Geert Uytterhoeven2095fc72015-11-12 13:39:49 +01003212 /* Get the line number from the aliases node. */
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003213 id = of_alias_get_id(np, "serial");
Geert Uytterhoeven7678f4c2018-03-05 18:17:40 +01003214 if (id < 0 && ~sci_ports_in_use)
3215 id = ffz(sci_ports_in_use);
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003216 if (id < 0) {
3217 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3218 return NULL;
3219 }
Geert Uytterhoeven090fa4b2018-02-23 14:38:35 +01003220 if (id >= ARRAY_SIZE(sci_ports)) {
3221 dev_err(&pdev->dev, "serial%d out of range\n", id);
3222 return NULL;
3223 }
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003224
Laurent Pinchart97ed9792017-01-11 16:43:39 +02003225 sp = &sci_ports[id];
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003226 *dev_id = id;
3227
Geert Uytterhoeven6e605a02017-10-04 14:21:56 +02003228 p->type = SCI_OF_TYPE(data);
3229 p->regtype = SCI_OF_REGTYPE(data);
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003230
Sergei Shtylyov43c61282017-08-13 22:11:24 +03003231 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
Geert Uytterhoeven861a70a2016-06-03 12:00:11 +02003232
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003233 return p;
3234}
3235
Bill Pemberton9671f092012-11-19 13:21:50 -05003236static int sci_probe_single(struct platform_device *dev,
Magnus Damm0ee70712009-01-21 15:13:50 +00003237 unsigned int index,
3238 struct plat_sci_port *p,
3239 struct sci_port *sciport)
3240{
Magnus Damm0ee70712009-01-21 15:13:50 +00003241 int ret;
3242
3243 /* Sanity check */
3244 if (unlikely(index >= SCI_NPORTS)) {
Joe Perches9b971cd2014-03-11 10:10:46 -07003245 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
Magnus Damm0ee70712009-01-21 15:13:50 +00003246 index+1, SCI_NPORTS);
Joe Perches9b971cd2014-03-11 10:10:46 -07003247 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
Laurent Pinchartb6c5ef62012-06-13 00:28:24 +02003248 return -EINVAL;
Magnus Damm0ee70712009-01-21 15:13:50 +00003249 }
Geert Uytterhoeven7678f4c2018-03-05 18:17:40 +01003250 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3251 if (sci_ports_in_use & BIT(index))
3252 return -EBUSY;
Magnus Damm0ee70712009-01-21 15:13:50 +00003253
Sjoerd Simons352b9262017-04-20 14:13:01 +02003254 mutex_lock(&sci_uart_registration_lock);
3255 if (!sci_uart_driver.state) {
3256 ret = uart_register_driver(&sci_uart_driver);
3257 if (ret) {
3258 mutex_unlock(&sci_uart_registration_lock);
3259 return ret;
3260 }
3261 }
3262 mutex_unlock(&sci_uart_registration_lock);
3263
Laurent Pinchart1fcc91a2013-12-06 10:59:16 +01003264 ret = sci_init_single(dev, sciport, index, p, false);
Paul Mundtc7ed1ab2010-03-10 18:35:14 +09003265 if (ret)
3266 return ret;
Magnus Damm0ee70712009-01-21 15:13:50 +00003267
Geert Uytterhoevenf907c9e2016-06-03 12:00:04 +02003268 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3269 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3270 return PTR_ERR(sciport->gpios);
3271
Laurent Pinchart97ed9792017-01-11 16:43:39 +02003272 if (sciport->has_rtscts) {
Geert Uytterhoevenf907c9e2016-06-03 12:00:04 +02003273 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3274 UART_GPIO_CTS)) ||
3275 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3276 UART_GPIO_RTS))) {
3277 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3278 return -EINVAL;
3279 }
Geert Uytterhoeven33f50ff2016-06-03 12:00:10 +02003280 sciport->port.flags |= UPF_HARD_FLOW;
Geert Uytterhoevenf907c9e2016-06-03 12:00:04 +02003281 }
3282
Laurent Pinchart6dae1422012-06-13 00:28:23 +02003283 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3284 if (ret) {
3285 sci_cleanup_single(sciport);
3286 return ret;
3287 }
3288
3289 return 0;
Magnus Damm0ee70712009-01-21 15:13:50 +00003290}
3291
Bill Pemberton9671f092012-11-19 13:21:50 -05003292static int sci_probe(struct platform_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003293{
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003294 struct plat_sci_port *p;
3295 struct sci_port *sp;
3296 unsigned int dev_id;
Paul Mundtecdf8a42011-01-21 00:05:48 +09003297 int ret;
Magnus Damme552de22009-01-21 15:13:42 +00003298
Paul Mundtecdf8a42011-01-21 00:05:48 +09003299 /*
3300 * If we've come here via earlyprintk initialization, head off to
3301 * the special early probe. We don't have sufficient device state
3302 * to make it beyond this yet.
3303 */
3304 if (is_early_platform_device(dev))
3305 return sci_probe_earlyprintk(dev);
Magnus Damm7b6fd3b2009-12-14 10:24:42 +00003306
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003307 if (dev->dev.of_node) {
3308 p = sci_parse_dt(dev, &dev_id);
3309 if (p == NULL)
3310 return -EINVAL;
3311 } else {
3312 p = dev->dev.platform_data;
3313 if (p == NULL) {
3314 dev_err(&dev->dev, "no platform data supplied\n");
3315 return -EINVAL;
3316 }
3317
3318 dev_id = dev->id;
3319 }
3320
3321 sp = &sci_ports[dev_id];
Paul Mundtd535a232011-01-19 17:19:35 +09003322 platform_set_drvdata(dev, sp);
Magnus Damme552de22009-01-21 15:13:42 +00003323
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003324 ret = sci_probe_single(dev, dev_id, p, sp);
Paul Mundtd535a232011-01-19 17:19:35 +09003325 if (ret)
Laurent Pinchart6dae1422012-06-13 00:28:23 +02003326 return ret;
Magnus Damme552de22009-01-21 15:13:42 +00003327
Ulrich Hecht5d231882017-02-03 11:38:19 +01003328 if (sp->port.fifosize > 1) {
3329 ret = sysfs_create_file(&dev->dev.kobj,
3330 &dev_attr_rx_fifo_trigger.attr);
3331 if (ret)
3332 return ret;
3333 }
Ulrich Hechtfa2abb02017-09-29 15:08:53 +02003334 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3335 sp->port.type == PORT_HSCIF) {
Ulrich Hecht5d231882017-02-03 11:38:19 +01003336 ret = sysfs_create_file(&dev->dev.kobj,
3337 &dev_attr_rx_fifo_timeout.attr);
3338 if (ret) {
3339 if (sp->port.fifosize > 1) {
3340 sysfs_remove_file(&dev->dev.kobj,
3341 &dev_attr_rx_fifo_trigger.attr);
3342 }
3343 return ret;
3344 }
3345 }
3346
Linus Torvalds1da177e2005-04-16 15:20:36 -07003347#ifdef CONFIG_SH_STANDARD_BIOS
3348 sh_bios_gdb_detach();
3349#endif
3350
Geert Uytterhoeven7678f4c2018-03-05 18:17:40 +01003351 sci_ports_in_use |= BIT(dev_id);
Paul Mundte108b2c2006-09-27 16:32:13 +09003352 return 0;
3353}
3354
Sergei Shtylyovcb876342015-01-16 13:56:02 -08003355static __maybe_unused int sci_suspend(struct device *dev)
Paul Mundte108b2c2006-09-27 16:32:13 +09003356{
Paul Mundtd535a232011-01-19 17:19:35 +09003357 struct sci_port *sport = dev_get_drvdata(dev);
Paul Mundte108b2c2006-09-27 16:32:13 +09003358
Paul Mundtd535a232011-01-19 17:19:35 +09003359 if (sport)
3360 uart_suspend_port(&sci_uart_driver, &sport->port);
Paul Mundte108b2c2006-09-27 16:32:13 +09003361
3362 return 0;
3363}
3364
Sergei Shtylyovcb876342015-01-16 13:56:02 -08003365static __maybe_unused int sci_resume(struct device *dev)
Paul Mundte108b2c2006-09-27 16:32:13 +09003366{
Paul Mundtd535a232011-01-19 17:19:35 +09003367 struct sci_port *sport = dev_get_drvdata(dev);
Paul Mundte108b2c2006-09-27 16:32:13 +09003368
Paul Mundtd535a232011-01-19 17:19:35 +09003369 if (sport)
3370 uart_resume_port(&sci_uart_driver, &sport->port);
Paul Mundte108b2c2006-09-27 16:32:13 +09003371
3372 return 0;
3373}
3374
Sergei Shtylyovcb876342015-01-16 13:56:02 -08003375static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
Paul Mundt6daa79b2009-06-15 07:07:38 +09003376
Paul Mundte108b2c2006-09-27 16:32:13 +09003377static struct platform_driver sci_driver = {
3378 .probe = sci_probe,
Uwe Kleine-Königb9e39c82009-11-24 22:07:32 +01003379 .remove = sci_remove,
Paul Mundte108b2c2006-09-27 16:32:13 +09003380 .driver = {
3381 .name = "sh-sci",
Paul Mundt6daa79b2009-06-15 07:07:38 +09003382 .pm = &sci_dev_pm_ops,
Bastian Hecht20bdcab2013-12-06 10:59:54 +01003383 .of_match_table = of_match_ptr(of_sci_match),
Paul Mundte108b2c2006-09-27 16:32:13 +09003384 },
3385};
3386
3387static int __init sci_init(void)
3388{
Geert Uytterhoeven6c13d5d2014-03-11 11:11:17 +01003389 pr_info("%s\n", banner);
Paul Mundte108b2c2006-09-27 16:32:13 +09003390
Sjoerd Simons352b9262017-04-20 14:13:01 +02003391 return platform_driver_register(&sci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003392}
3393
3394static void __exit sci_exit(void)
3395{
Paul Mundte108b2c2006-09-27 16:32:13 +09003396 platform_driver_unregister(&sci_driver);
Sjoerd Simons352b9262017-04-20 14:13:01 +02003397
3398 if (sci_uart_driver.state)
3399 uart_unregister_driver(&sci_uart_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003400}
3401
Magnus Damm7b6fd3b2009-12-14 10:24:42 +00003402#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3403early_platform_init_buffer("earlyprintk", &sci_driver,
3404 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3405#endif
Yoshinori Sato0b0cced2015-12-24 11:24:48 +01003406#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
Matthias Kaehlckedd076cf2017-10-09 18:26:22 -07003407static struct plat_sci_port port_cfg __initdata;
Yoshinori Sato0b0cced2015-12-24 11:24:48 +01003408
3409static int __init early_console_setup(struct earlycon_device *device,
3410 int type)
3411{
3412 if (!device->port.membase)
3413 return -ENODEV;
3414
3415 device->port.serial_in = sci_serial_in;
3416 device->port.serial_out = sci_serial_out;
3417 device->port.type = type;
3418 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
Laurent Pinchartdaf5a892017-01-11 16:43:35 +02003419 port_cfg.type = type;
Yoshinori Sato0b0cced2015-12-24 11:24:48 +01003420 sci_ports[0].cfg = &port_cfg;
Laurent Pinchartdaf5a892017-01-11 16:43:35 +02003421 sci_ports[0].params = sci_probe_regmap(&port_cfg);
Laurent Pinchart9f8325b2017-01-11 16:43:23 +02003422 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3423 sci_serial_out(&sci_ports[0].port, SCSCR,
3424 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
Yoshinori Sato0b0cced2015-12-24 11:24:48 +01003425
3426 device->con->write = serial_console_write;
3427 return 0;
3428}
3429static int __init sci_early_console_setup(struct earlycon_device *device,
3430 const char *opt)
3431{
3432 return early_console_setup(device, PORT_SCI);
3433}
3434static int __init scif_early_console_setup(struct earlycon_device *device,
3435 const char *opt)
3436{
3437 return early_console_setup(device, PORT_SCIF);
3438}
Chris Brandt3d8b43a2018-09-17 13:26:23 -05003439static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3440 const char *opt)
3441{
3442 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3443 return early_console_setup(device, PORT_SCIF);
3444}
Yoshinori Sato0b0cced2015-12-24 11:24:48 +01003445static int __init scifa_early_console_setup(struct earlycon_device *device,
3446 const char *opt)
3447{
3448 return early_console_setup(device, PORT_SCIFA);
3449}
3450static int __init scifb_early_console_setup(struct earlycon_device *device,
3451 const char *opt)
3452{
3453 return early_console_setup(device, PORT_SCIFB);
3454}
3455static int __init hscif_early_console_setup(struct earlycon_device *device,
3456 const char *opt)
3457{
3458 return early_console_setup(device, PORT_HSCIF);
3459}
3460
Yoshinori Sato0b0cced2015-12-24 11:24:48 +01003461OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
Yoshinori Sato0b0cced2015-12-24 11:24:48 +01003462OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
Chris Brandt3d8b43a2018-09-17 13:26:23 -05003463OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
Yoshinori Sato0b0cced2015-12-24 11:24:48 +01003464OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
Yoshinori Sato0b0cced2015-12-24 11:24:48 +01003465OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
Yoshinori Sato0b0cced2015-12-24 11:24:48 +01003466OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3467#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3468
Linus Torvalds1da177e2005-04-16 15:20:36 -07003469module_init(sci_init);
3470module_exit(sci_exit);
3471
Paul Mundte108b2c2006-09-27 16:32:13 +09003472MODULE_LICENSE("GPL");
Kay Sieverse169c132008-04-15 14:34:35 -07003473MODULE_ALIAS("platform:sh-sci");
Paul Mundt7f405f92011-06-28 13:47:40 +09003474MODULE_AUTHOR("Paul Mundt");
Ulrich Hechtf303b362013-05-31 17:57:01 +02003475MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");