blob: 730bb18c3f45d2bdf4e1aedc4018b060866d0154 [file] [log] [blame]
Kalle Valo5e3dd152013-06-12 20:52:10 +03001/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#include <linux/pci.h>
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/spinlock.h>
Kalle Valo650b91f2013-11-20 10:00:49 +020022#include <linux/bitops.h>
Kalle Valo5e3dd152013-06-12 20:52:10 +030023
24#include "core.h"
25#include "debug.h"
26
27#include "targaddrs.h"
28#include "bmi.h"
29
30#include "hif.h"
31#include "htc.h"
32
33#include "ce.h"
34#include "pci.h"
35
Michal Kaziorcfe9c452013-11-25 14:06:27 +010036enum ath10k_pci_irq_mode {
37 ATH10K_PCI_IRQ_AUTO = 0,
38 ATH10K_PCI_IRQ_LEGACY = 1,
39 ATH10K_PCI_IRQ_MSI = 2,
40};
41
Kalle Valo35098462014-03-28 09:32:27 +020042enum ath10k_pci_reset_mode {
43 ATH10K_PCI_RESET_AUTO = 0,
44 ATH10K_PCI_RESET_WARM_ONLY = 1,
45};
46
Michal Kaziorcfe9c452013-11-25 14:06:27 +010047static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO;
Kalle Valo35098462014-03-28 09:32:27 +020048static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO;
Michal Kaziorcfe9c452013-11-25 14:06:27 +010049
Michal Kaziorcfe9c452013-11-25 14:06:27 +010050module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
51MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
52
Kalle Valo35098462014-03-28 09:32:27 +020053module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644);
54MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)");
55
Kalle Valo0399eca2014-03-28 09:32:21 +020056/* how long wait to wait for target to initialise, in ms */
57#define ATH10K_PCI_TARGET_WAIT 3000
Michal Kazior61c95ce2014-05-14 16:56:16 +030058#define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3
Kalle Valo0399eca2014-03-28 09:32:21 +020059
Kalle Valo5e3dd152013-06-12 20:52:10 +030060#define QCA988X_2_0_DEVICE_ID (0x003c)
61
Benoit Taine9baa3c32014-08-08 15:56:03 +020062static const struct pci_device_id ath10k_pci_id_table[] = {
Kalle Valo5e3dd152013-06-12 20:52:10 +030063 { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */
64 {0}
65};
66
Michal Kazior728f95e2014-08-22 14:33:14 +020067static void ath10k_pci_buffer_cleanup(struct ath10k *ar);
Michal Kaziorfc36e3f2014-02-10 17:14:22 +010068static int ath10k_pci_cold_reset(struct ath10k *ar);
69static int ath10k_pci_warm_reset(struct ath10k *ar);
Michal Kaziord7fb47f2013-11-08 08:01:26 +010070static int ath10k_pci_wait_for_target_init(struct ath10k *ar);
Michal Kaziorfc15ca12013-11-25 14:06:21 +010071static int ath10k_pci_init_irq(struct ath10k *ar);
72static int ath10k_pci_deinit_irq(struct ath10k *ar);
73static int ath10k_pci_request_irq(struct ath10k *ar);
74static void ath10k_pci_free_irq(struct ath10k *ar);
Michal Kazior85622cd2013-11-25 14:06:22 +010075static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
76 struct ath10k_ce_pipe *rx_pipe,
77 struct bmi_xfer *xfer);
Kalle Valo5e3dd152013-06-12 20:52:10 +030078
79static const struct ce_attr host_ce_config_wlan[] = {
Kalle Valo48e9c222013-09-01 10:01:32 +030080 /* CE0: host->target HTC control and raw streams */
81 {
82 .flags = CE_ATTR_FLAGS,
83 .src_nentries = 16,
84 .src_sz_max = 256,
85 .dest_nentries = 0,
86 },
87
88 /* CE1: target->host HTT + HTC control */
89 {
90 .flags = CE_ATTR_FLAGS,
91 .src_nentries = 0,
92 .src_sz_max = 512,
93 .dest_nentries = 512,
94 },
95
96 /* CE2: target->host WMI */
97 {
98 .flags = CE_ATTR_FLAGS,
99 .src_nentries = 0,
100 .src_sz_max = 2048,
101 .dest_nentries = 32,
102 },
103
104 /* CE3: host->target WMI */
105 {
106 .flags = CE_ATTR_FLAGS,
107 .src_nentries = 32,
108 .src_sz_max = 2048,
109 .dest_nentries = 0,
110 },
111
112 /* CE4: host->target HTT */
113 {
114 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
115 .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES,
116 .src_sz_max = 256,
117 .dest_nentries = 0,
118 },
119
120 /* CE5: unused */
121 {
122 .flags = CE_ATTR_FLAGS,
123 .src_nentries = 0,
124 .src_sz_max = 0,
125 .dest_nentries = 0,
126 },
127
128 /* CE6: target autonomous hif_memcpy */
129 {
130 .flags = CE_ATTR_FLAGS,
131 .src_nentries = 0,
132 .src_sz_max = 0,
133 .dest_nentries = 0,
134 },
135
136 /* CE7: ce_diag, the Diagnostic Window */
137 {
138 .flags = CE_ATTR_FLAGS,
139 .src_nentries = 2,
140 .src_sz_max = DIAG_TRANSFER_LIMIT,
141 .dest_nentries = 2,
142 },
Kalle Valo5e3dd152013-06-12 20:52:10 +0300143};
144
145/* Target firmware's Copy Engine configuration. */
146static const struct ce_pipe_config target_ce_config_wlan[] = {
Kalle Valod88effb2013-09-01 10:01:39 +0300147 /* CE0: host->target HTC control and raw streams */
148 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300149 .pipenum = __cpu_to_le32(0),
150 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
151 .nentries = __cpu_to_le32(32),
152 .nbytes_max = __cpu_to_le32(256),
153 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
154 .reserved = __cpu_to_le32(0),
Kalle Valod88effb2013-09-01 10:01:39 +0300155 },
156
157 /* CE1: target->host HTT + HTC control */
158 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300159 .pipenum = __cpu_to_le32(1),
160 .pipedir = __cpu_to_le32(PIPEDIR_IN),
161 .nentries = __cpu_to_le32(32),
162 .nbytes_max = __cpu_to_le32(512),
163 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
164 .reserved = __cpu_to_le32(0),
Kalle Valod88effb2013-09-01 10:01:39 +0300165 },
166
167 /* CE2: target->host WMI */
168 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300169 .pipenum = __cpu_to_le32(2),
170 .pipedir = __cpu_to_le32(PIPEDIR_IN),
171 .nentries = __cpu_to_le32(32),
172 .nbytes_max = __cpu_to_le32(2048),
173 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
174 .reserved = __cpu_to_le32(0),
Kalle Valod88effb2013-09-01 10:01:39 +0300175 },
176
177 /* CE3: host->target WMI */
178 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300179 .pipenum = __cpu_to_le32(3),
180 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
181 .nentries = __cpu_to_le32(32),
182 .nbytes_max = __cpu_to_le32(2048),
183 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
184 .reserved = __cpu_to_le32(0),
Kalle Valod88effb2013-09-01 10:01:39 +0300185 },
186
187 /* CE4: host->target HTT */
188 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300189 .pipenum = __cpu_to_le32(4),
190 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
191 .nentries = __cpu_to_le32(256),
192 .nbytes_max = __cpu_to_le32(256),
193 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
194 .reserved = __cpu_to_le32(0),
Kalle Valod88effb2013-09-01 10:01:39 +0300195 },
196
Kalle Valo5e3dd152013-06-12 20:52:10 +0300197 /* NB: 50% of src nentries, since tx has 2 frags */
Kalle Valod88effb2013-09-01 10:01:39 +0300198
199 /* CE5: unused */
200 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300201 .pipenum = __cpu_to_le32(5),
202 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
203 .nentries = __cpu_to_le32(32),
204 .nbytes_max = __cpu_to_le32(2048),
205 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
206 .reserved = __cpu_to_le32(0),
Kalle Valod88effb2013-09-01 10:01:39 +0300207 },
208
209 /* CE6: Reserved for target autonomous hif_memcpy */
210 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300211 .pipenum = __cpu_to_le32(6),
212 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
213 .nentries = __cpu_to_le32(32),
214 .nbytes_max = __cpu_to_le32(4096),
215 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
216 .reserved = __cpu_to_le32(0),
Kalle Valod88effb2013-09-01 10:01:39 +0300217 },
218
Kalle Valo5e3dd152013-06-12 20:52:10 +0300219 /* CE7 used only by Host */
220};
221
Michal Kaziord7bfb7a2014-08-26 19:14:02 +0300222/*
223 * Map from service/endpoint to Copy Engine.
224 * This table is derived from the CE_PCI TABLE, above.
225 * It is passed to the Target at startup for use by firmware.
226 */
227static const struct service_to_pipe target_service_to_ce_map_wlan[] = {
228 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300229 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
230 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
231 __cpu_to_le32(3),
Michal Kaziord7bfb7a2014-08-26 19:14:02 +0300232 },
233 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300234 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
235 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
236 __cpu_to_le32(2),
Michal Kaziord7bfb7a2014-08-26 19:14:02 +0300237 },
238 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300239 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
240 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
241 __cpu_to_le32(3),
Michal Kaziord7bfb7a2014-08-26 19:14:02 +0300242 },
243 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300244 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
245 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
246 __cpu_to_le32(2),
Michal Kaziord7bfb7a2014-08-26 19:14:02 +0300247 },
248 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300249 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
250 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
251 __cpu_to_le32(3),
Michal Kaziord7bfb7a2014-08-26 19:14:02 +0300252 },
253 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300254 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
255 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
256 __cpu_to_le32(2),
Michal Kaziord7bfb7a2014-08-26 19:14:02 +0300257 },
258 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300259 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
260 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
261 __cpu_to_le32(3),
Michal Kaziord7bfb7a2014-08-26 19:14:02 +0300262 },
263 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300264 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
265 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
266 __cpu_to_le32(2),
Michal Kaziord7bfb7a2014-08-26 19:14:02 +0300267 },
268 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300269 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
270 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
271 __cpu_to_le32(3),
Michal Kaziord7bfb7a2014-08-26 19:14:02 +0300272 },
273 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300274 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
275 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
276 __cpu_to_le32(2),
Michal Kaziord7bfb7a2014-08-26 19:14:02 +0300277 },
278 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300279 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
280 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
281 __cpu_to_le32(0),
Michal Kaziord7bfb7a2014-08-26 19:14:02 +0300282 },
283 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300284 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
285 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
286 __cpu_to_le32(1),
287 },
288 { /* not used */
289 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
290 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
291 __cpu_to_le32(0),
292 },
293 { /* not used */
294 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
295 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
296 __cpu_to_le32(1),
Michal Kaziord7bfb7a2014-08-26 19:14:02 +0300297 },
298 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300299 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
300 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
301 __cpu_to_le32(4),
Michal Kaziord7bfb7a2014-08-26 19:14:02 +0300302 },
303 {
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300304 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
305 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
306 __cpu_to_le32(1),
Michal Kaziord7bfb7a2014-08-26 19:14:02 +0300307 },
308
309 /* (Additions here) */
310
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300311 { /* must be last */
312 __cpu_to_le32(0),
313 __cpu_to_le32(0),
314 __cpu_to_le32(0),
Michal Kaziord7bfb7a2014-08-26 19:14:02 +0300315 },
316};
317
Michal Kaziore5398872013-11-25 14:06:20 +0100318static bool ath10k_pci_irq_pending(struct ath10k *ar)
319{
320 u32 cause;
321
322 /* Check if the shared legacy irq is for us */
323 cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
324 PCIE_INTR_CAUSE_ADDRESS);
325 if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL))
326 return true;
327
328 return false;
329}
330
Michal Kazior26852182013-11-25 14:06:25 +0100331static void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar)
332{
333 /* IMPORTANT: INTR_CLR register has to be set after
334 * INTR_ENABLE is set to 0, otherwise interrupt can not be
335 * really cleared. */
336 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
337 0);
338 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS,
339 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
340
341 /* IMPORTANT: this extra read transaction is required to
342 * flush the posted write buffer. */
Kalle Valocfbc06a2014-09-14 12:50:23 +0300343 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
344 PCIE_INTR_ENABLE_ADDRESS);
Michal Kazior26852182013-11-25 14:06:25 +0100345}
346
347static void ath10k_pci_enable_legacy_irq(struct ath10k *ar)
348{
349 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
350 PCIE_INTR_ENABLE_ADDRESS,
351 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
352
353 /* IMPORTANT: this extra read transaction is required to
354 * flush the posted write buffer. */
Kalle Valocfbc06a2014-09-14 12:50:23 +0300355 (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
356 PCIE_INTR_ENABLE_ADDRESS);
Michal Kazior26852182013-11-25 14:06:25 +0100357}
358
Michal Kazior403d6272014-08-22 14:23:31 +0200359static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar)
Michal Kaziorab977bd2013-11-25 14:06:26 +0100360{
Michal Kaziorab977bd2013-11-25 14:06:26 +0100361 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
362
Michal Kazior403d6272014-08-22 14:23:31 +0200363 if (ar_pci->num_msi_intrs > 1)
364 return "msi-x";
Kalle Valod8bb26b2014-09-14 12:50:33 +0300365
366 if (ar_pci->num_msi_intrs == 1)
Michal Kazior403d6272014-08-22 14:23:31 +0200367 return "msi";
Kalle Valod8bb26b2014-09-14 12:50:33 +0300368
369 return "legacy";
Michal Kaziorab977bd2013-11-25 14:06:26 +0100370}
371
Michal Kazior728f95e2014-08-22 14:33:14 +0200372static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe)
Michal Kaziorab977bd2013-11-25 14:06:26 +0100373{
Michal Kazior728f95e2014-08-22 14:33:14 +0200374 struct ath10k *ar = pipe->hif_ce_state;
Michal Kaziorab977bd2013-11-25 14:06:26 +0100375 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
Michal Kazior728f95e2014-08-22 14:33:14 +0200376 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
377 struct sk_buff *skb;
378 dma_addr_t paddr;
Michal Kaziorab977bd2013-11-25 14:06:26 +0100379 int ret;
380
Michal Kazior728f95e2014-08-22 14:33:14 +0200381 lockdep_assert_held(&ar_pci->ce_lock);
382
383 skb = dev_alloc_skb(pipe->buf_sz);
384 if (!skb)
385 return -ENOMEM;
386
387 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
388
389 paddr = dma_map_single(ar->dev, skb->data,
390 skb->len + skb_tailroom(skb),
391 DMA_FROM_DEVICE);
392 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
Michal Kazior7aa7a722014-08-25 12:09:38 +0200393 ath10k_warn(ar, "failed to dma map pci rx buf\n");
Michal Kazior728f95e2014-08-22 14:33:14 +0200394 dev_kfree_skb_any(skb);
395 return -EIO;
396 }
397
398 ATH10K_SKB_CB(skb)->paddr = paddr;
399
400 ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr);
Michal Kaziorab977bd2013-11-25 14:06:26 +0100401 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +0200402 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
Michal Kazior728f95e2014-08-22 14:33:14 +0200403 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
404 DMA_FROM_DEVICE);
405 dev_kfree_skb_any(skb);
Michal Kaziorab977bd2013-11-25 14:06:26 +0100406 return ret;
407 }
408
409 return 0;
410}
411
Michal Kazior728f95e2014-08-22 14:33:14 +0200412static void __ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
Michal Kaziorab977bd2013-11-25 14:06:26 +0100413{
Michal Kazior728f95e2014-08-22 14:33:14 +0200414 struct ath10k *ar = pipe->hif_ce_state;
415 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
416 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
417 int ret, num;
418
419 lockdep_assert_held(&ar_pci->ce_lock);
420
421 if (pipe->buf_sz == 0)
422 return;
423
424 if (!ce_pipe->dest_ring)
425 return;
426
427 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
428 while (num--) {
429 ret = __ath10k_pci_rx_post_buf(pipe);
430 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +0200431 ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret);
Michal Kazior728f95e2014-08-22 14:33:14 +0200432 mod_timer(&ar_pci->rx_post_retry, jiffies +
433 ATH10K_PCI_RX_POST_RETRY_MS);
434 break;
435 }
436 }
437}
438
439static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe)
440{
441 struct ath10k *ar = pipe->hif_ce_state;
442 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
443
444 spin_lock_bh(&ar_pci->ce_lock);
445 __ath10k_pci_rx_post_pipe(pipe);
446 spin_unlock_bh(&ar_pci->ce_lock);
447}
448
449static void ath10k_pci_rx_post(struct ath10k *ar)
450{
451 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
452 int i;
453
454 spin_lock_bh(&ar_pci->ce_lock);
455 for (i = 0; i < CE_COUNT; i++)
456 __ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]);
457 spin_unlock_bh(&ar_pci->ce_lock);
458}
459
460static void ath10k_pci_rx_replenish_retry(unsigned long ptr)
461{
462 struct ath10k *ar = (void *)ptr;
463
464 ath10k_pci_rx_post(ar);
Michal Kaziorab977bd2013-11-25 14:06:26 +0100465}
466
Kalle Valo5e3dd152013-06-12 20:52:10 +0300467/*
468 * Diagnostic read/write access is provided for startup/config/debug usage.
469 * Caller must guarantee proper alignment, when applicable, and single user
470 * at any moment.
471 */
472static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data,
473 int nbytes)
474{
475 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
476 int ret = 0;
477 u32 buf;
478 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
479 unsigned int id;
480 unsigned int flags;
Michal Kazior2aa39112013-08-27 13:08:02 +0200481 struct ath10k_ce_pipe *ce_diag;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300482 /* Host buffer address in CE space */
483 u32 ce_data;
484 dma_addr_t ce_data_base = 0;
485 void *data_buf = NULL;
486 int i;
487
Kalle Valoeef25402014-09-24 14:16:52 +0300488 spin_lock_bh(&ar_pci->ce_lock);
489
Kalle Valo5e3dd152013-06-12 20:52:10 +0300490 ce_diag = ar_pci->ce_diag;
491
492 /*
493 * Allocate a temporary bounce buffer to hold caller's data
494 * to be DMA'ed from Target. This guarantees
495 * 1) 4-byte alignment
496 * 2) Buffer in DMA-able space
497 */
498 orig_nbytes = nbytes;
Michal Kazior68c03242014-03-28 10:02:35 +0200499 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
500 orig_nbytes,
501 &ce_data_base,
502 GFP_ATOMIC);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300503
504 if (!data_buf) {
505 ret = -ENOMEM;
506 goto done;
507 }
508 memset(data_buf, 0, orig_nbytes);
509
510 remaining_bytes = orig_nbytes;
511 ce_data = ce_data_base;
512 while (remaining_bytes) {
513 nbytes = min_t(unsigned int, remaining_bytes,
514 DIAG_TRANSFER_LIMIT);
515
Kalle Valoeef25402014-09-24 14:16:52 +0300516 ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, ce_data);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300517 if (ret != 0)
518 goto done;
519
520 /* Request CE to send from Target(!) address to Host buffer */
521 /*
522 * The address supplied by the caller is in the
523 * Target CPU virtual address space.
524 *
525 * In order to use this address with the diagnostic CE,
526 * convert it from Target CPU virtual address space
527 * to CE address space
528 */
Kalle Valo5e3dd152013-06-12 20:52:10 +0300529 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem,
530 address);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300531
Kalle Valoeef25402014-09-24 14:16:52 +0300532 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0,
533 0);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300534 if (ret)
535 goto done;
536
537 i = 0;
Kalle Valoeef25402014-09-24 14:16:52 +0300538 while (ath10k_ce_completed_send_next_nolock(ce_diag, NULL, &buf,
539 &completed_nbytes,
540 &id) != 0) {
Kalle Valo5e3dd152013-06-12 20:52:10 +0300541 mdelay(1);
542 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
543 ret = -EBUSY;
544 goto done;
545 }
546 }
547
548 if (nbytes != completed_nbytes) {
549 ret = -EIO;
550 goto done;
551 }
552
Kalle Valocfbc06a2014-09-14 12:50:23 +0300553 if (buf != (u32)address) {
Kalle Valo5e3dd152013-06-12 20:52:10 +0300554 ret = -EIO;
555 goto done;
556 }
557
558 i = 0;
Kalle Valoeef25402014-09-24 14:16:52 +0300559 while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf,
560 &completed_nbytes,
561 &id, &flags) != 0) {
Kalle Valo5e3dd152013-06-12 20:52:10 +0300562 mdelay(1);
563
564 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
565 ret = -EBUSY;
566 goto done;
567 }
568 }
569
570 if (nbytes != completed_nbytes) {
571 ret = -EIO;
572 goto done;
573 }
574
575 if (buf != ce_data) {
576 ret = -EIO;
577 goto done;
578 }
579
580 remaining_bytes -= nbytes;
581 address += nbytes;
582 ce_data += nbytes;
583 }
584
585done:
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300586 if (ret == 0)
587 memcpy(data, data_buf, orig_nbytes);
588 else
Michal Kazior7aa7a722014-08-25 12:09:38 +0200589 ath10k_warn(ar, "failed to read diag value at 0x%x: %d\n",
Kalle Valo50f87a62014-03-28 09:32:52 +0200590 address, ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300591
592 if (data_buf)
Michal Kazior68c03242014-03-28 10:02:35 +0200593 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
594 ce_data_base);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300595
Kalle Valoeef25402014-09-24 14:16:52 +0300596 spin_unlock_bh(&ar_pci->ce_lock);
597
Kalle Valo5e3dd152013-06-12 20:52:10 +0300598 return ret;
599}
600
Kalle Valo3d29a3e2014-08-25 08:37:26 +0300601static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value)
602{
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300603 __le32 val = 0;
604 int ret;
605
606 ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val));
607 *value = __le32_to_cpu(val);
608
609 return ret;
Kalle Valo3d29a3e2014-08-25 08:37:26 +0300610}
611
612static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest,
613 u32 src, u32 len)
614{
615 u32 host_addr, addr;
616 int ret;
617
618 host_addr = host_interest_item_address(src);
619
620 ret = ath10k_pci_diag_read32(ar, host_addr, &addr);
621 if (ret != 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +0200622 ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n",
Kalle Valo3d29a3e2014-08-25 08:37:26 +0300623 src, ret);
624 return ret;
625 }
626
627 ret = ath10k_pci_diag_read_mem(ar, addr, dest, len);
628 if (ret != 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +0200629 ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n",
Kalle Valo3d29a3e2014-08-25 08:37:26 +0300630 addr, len, ret);
631 return ret;
632 }
633
634 return 0;
635}
636
637#define ath10k_pci_diag_read_hi(ar, dest, src, len) \
Kalle Valo8cc7f262014-09-14 12:50:39 +0300638 __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len)
Kalle Valo3d29a3e2014-08-25 08:37:26 +0300639
Kalle Valo5e3dd152013-06-12 20:52:10 +0300640static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
641 const void *data, int nbytes)
642{
643 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
644 int ret = 0;
645 u32 buf;
646 unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
647 unsigned int id;
648 unsigned int flags;
Michal Kazior2aa39112013-08-27 13:08:02 +0200649 struct ath10k_ce_pipe *ce_diag;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300650 void *data_buf = NULL;
651 u32 ce_data; /* Host buffer address in CE space */
652 dma_addr_t ce_data_base = 0;
653 int i;
654
Kalle Valoeef25402014-09-24 14:16:52 +0300655 spin_lock_bh(&ar_pci->ce_lock);
656
Kalle Valo5e3dd152013-06-12 20:52:10 +0300657 ce_diag = ar_pci->ce_diag;
658
659 /*
660 * Allocate a temporary bounce buffer to hold caller's data
661 * to be DMA'ed to Target. This guarantees
662 * 1) 4-byte alignment
663 * 2) Buffer in DMA-able space
664 */
665 orig_nbytes = nbytes;
Michal Kazior68c03242014-03-28 10:02:35 +0200666 data_buf = (unsigned char *)dma_alloc_coherent(ar->dev,
667 orig_nbytes,
668 &ce_data_base,
669 GFP_ATOMIC);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300670 if (!data_buf) {
671 ret = -ENOMEM;
672 goto done;
673 }
674
675 /* Copy caller's data to allocated DMA buf */
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300676 memcpy(data_buf, data, orig_nbytes);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300677
678 /*
679 * The address supplied by the caller is in the
680 * Target CPU virtual address space.
681 *
682 * In order to use this address with the diagnostic CE,
683 * convert it from
684 * Target CPU virtual address space
685 * to
686 * CE address space
687 */
Kalle Valo5e3dd152013-06-12 20:52:10 +0300688 address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300689
690 remaining_bytes = orig_nbytes;
691 ce_data = ce_data_base;
692 while (remaining_bytes) {
693 /* FIXME: check cast */
694 nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT);
695
696 /* Set up to receive directly into Target(!) address */
Kalle Valoeef25402014-09-24 14:16:52 +0300697 ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, address);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300698 if (ret != 0)
699 goto done;
700
701 /*
702 * Request CE to send caller-supplied data that
703 * was copied to bounce buffer to Target(!) address.
704 */
Kalle Valoeef25402014-09-24 14:16:52 +0300705 ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)ce_data,
706 nbytes, 0, 0);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300707 if (ret != 0)
708 goto done;
709
710 i = 0;
Kalle Valoeef25402014-09-24 14:16:52 +0300711 while (ath10k_ce_completed_send_next_nolock(ce_diag, NULL, &buf,
712 &completed_nbytes,
713 &id) != 0) {
Kalle Valo5e3dd152013-06-12 20:52:10 +0300714 mdelay(1);
715
716 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
717 ret = -EBUSY;
718 goto done;
719 }
720 }
721
722 if (nbytes != completed_nbytes) {
723 ret = -EIO;
724 goto done;
725 }
726
727 if (buf != ce_data) {
728 ret = -EIO;
729 goto done;
730 }
731
732 i = 0;
Kalle Valoeef25402014-09-24 14:16:52 +0300733 while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf,
734 &completed_nbytes,
735 &id, &flags) != 0) {
Kalle Valo5e3dd152013-06-12 20:52:10 +0300736 mdelay(1);
737
738 if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) {
739 ret = -EBUSY;
740 goto done;
741 }
742 }
743
744 if (nbytes != completed_nbytes) {
745 ret = -EIO;
746 goto done;
747 }
748
749 if (buf != address) {
750 ret = -EIO;
751 goto done;
752 }
753
754 remaining_bytes -= nbytes;
755 address += nbytes;
756 ce_data += nbytes;
757 }
758
759done:
760 if (data_buf) {
Michal Kazior68c03242014-03-28 10:02:35 +0200761 dma_free_coherent(ar->dev, orig_nbytes, data_buf,
762 ce_data_base);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300763 }
764
765 if (ret != 0)
Michal Kazior7aa7a722014-08-25 12:09:38 +0200766 ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n",
Kalle Valo50f87a62014-03-28 09:32:52 +0200767 address, ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300768
Kalle Valoeef25402014-09-24 14:16:52 +0300769 spin_unlock_bh(&ar_pci->ce_lock);
770
Kalle Valo5e3dd152013-06-12 20:52:10 +0300771 return ret;
772}
773
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300774static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value)
775{
776 __le32 val = __cpu_to_le32(value);
777
778 return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val));
779}
780
Michal Kaziorc0c378f2014-08-07 11:03:28 +0200781static bool ath10k_pci_is_awake(struct ath10k *ar)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300782{
Michal Kaziorc0c378f2014-08-07 11:03:28 +0200783 u32 val = ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS);
784
785 return RTC_STATE_V_GET(val) == RTC_STATE_V_ON;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300786}
787
Michal Kaziorc0c378f2014-08-07 11:03:28 +0200788static int ath10k_pci_wake_wait(struct ath10k *ar)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300789{
Kalle Valo5e3dd152013-06-12 20:52:10 +0300790 int tot_delay = 0;
791 int curr_delay = 5;
792
Michal Kaziorc0c378f2014-08-07 11:03:28 +0200793 while (tot_delay < PCIE_WAKE_TIMEOUT) {
794 if (ath10k_pci_is_awake(ar))
Kalle Valo3aebe542013-09-01 10:02:07 +0300795 return 0;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300796
797 udelay(curr_delay);
798 tot_delay += curr_delay;
799
800 if (curr_delay < 50)
801 curr_delay += 5;
802 }
Michal Kaziorc0c378f2014-08-07 11:03:28 +0200803
804 return -ETIMEDOUT;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300805}
806
Michal Kaziorc0c378f2014-08-07 11:03:28 +0200807static int ath10k_pci_wake(struct ath10k *ar)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300808{
Michal Kaziorc0c378f2014-08-07 11:03:28 +0200809 ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS,
810 PCIE_SOC_WAKE_V_MASK);
811 return ath10k_pci_wake_wait(ar);
812}
Kalle Valo5e3dd152013-06-12 20:52:10 +0300813
Michal Kaziorc0c378f2014-08-07 11:03:28 +0200814static void ath10k_pci_sleep(struct ath10k *ar)
815{
816 ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS,
817 PCIE_SOC_WAKE_RESET);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300818}
819
Kalle Valo5e3dd152013-06-12 20:52:10 +0300820/* Called by lower (CE) layer when a send to Target completes. */
Michal Kazior5440ce22013-09-03 15:09:58 +0200821static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300822{
823 struct ath10k *ar = ce_state->ar;
824 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
Michal Kazior2f5280d2014-02-27 18:50:05 +0200825 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
Michal Kazior5440ce22013-09-03 15:09:58 +0200826 void *transfer_context;
827 u32 ce_data;
828 unsigned int nbytes;
829 unsigned int transfer_id;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300830
Michal Kazior5440ce22013-09-03 15:09:58 +0200831 while (ath10k_ce_completed_send_next(ce_state, &transfer_context,
832 &ce_data, &nbytes,
833 &transfer_id) == 0) {
Michal Kaziora16942e2014-02-27 18:50:04 +0200834 /* no need to call tx completion for NULL pointers */
Michal Kazior726346f2014-02-27 18:50:04 +0200835 if (transfer_context == NULL)
836 continue;
837
Michal Kazior2f5280d2014-02-27 18:50:05 +0200838 cb->tx_completion(ar, transfer_context, transfer_id);
Michal Kazior5440ce22013-09-03 15:09:58 +0200839 }
Kalle Valo5e3dd152013-06-12 20:52:10 +0300840}
841
842/* Called by lower (CE) layer when data is received from the Target. */
Michal Kazior5440ce22013-09-03 15:09:58 +0200843static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300844{
845 struct ath10k *ar = ce_state->ar;
846 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
Michal Kazior87263e52013-08-27 13:08:01 +0200847 struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id];
Michal Kazior2f5280d2014-02-27 18:50:05 +0200848 struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300849 struct sk_buff *skb;
Michal Kazior5440ce22013-09-03 15:09:58 +0200850 void *transfer_context;
851 u32 ce_data;
Michal Kazior2f5280d2014-02-27 18:50:05 +0200852 unsigned int nbytes, max_nbytes;
Michal Kazior5440ce22013-09-03 15:09:58 +0200853 unsigned int transfer_id;
854 unsigned int flags;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300855
Michal Kazior5440ce22013-09-03 15:09:58 +0200856 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
857 &ce_data, &nbytes, &transfer_id,
858 &flags) == 0) {
Kalle Valo5e3dd152013-06-12 20:52:10 +0300859 skb = transfer_context;
Michal Kazior2f5280d2014-02-27 18:50:05 +0200860 max_nbytes = skb->len + skb_tailroom(skb);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300861 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
Michal Kazior2f5280d2014-02-27 18:50:05 +0200862 max_nbytes, DMA_FROM_DEVICE);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300863
Michal Kazior2f5280d2014-02-27 18:50:05 +0200864 if (unlikely(max_nbytes < nbytes)) {
Michal Kazior7aa7a722014-08-25 12:09:38 +0200865 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)",
Michal Kazior2f5280d2014-02-27 18:50:05 +0200866 nbytes, max_nbytes);
867 dev_kfree_skb_any(skb);
868 continue;
869 }
870
871 skb_put(skb, nbytes);
Michal Kaziora360e542014-09-23 10:22:54 +0200872
873 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n",
874 ce_state->id, skb->len);
875 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ",
876 skb->data, skb->len);
877
Michal Kazior2f5280d2014-02-27 18:50:05 +0200878 cb->rx_completion(ar, skb, pipe_info->pipe_num);
879 }
Michal Kaziorc29a3802014-07-21 21:03:10 +0300880
Michal Kazior728f95e2014-08-22 14:33:14 +0200881 ath10k_pci_rx_post_pipe(pipe_info);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300882}
883
Michal Kazior726346f2014-02-27 18:50:04 +0200884static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
885 struct ath10k_hif_sg_item *items, int n_items)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300886{
Kalle Valo5e3dd152013-06-12 20:52:10 +0300887 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
Michal Kazior726346f2014-02-27 18:50:04 +0200888 struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id];
889 struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl;
890 struct ath10k_ce_ring *src_ring = ce_pipe->src_ring;
Michal Kazior7147a132014-05-26 12:02:58 +0200891 unsigned int nentries_mask;
892 unsigned int sw_index;
893 unsigned int write_index;
Michal Kazior08b8aa02014-05-26 12:02:59 +0200894 int err, i = 0;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300895
Michal Kazior726346f2014-02-27 18:50:04 +0200896 spin_lock_bh(&ar_pci->ce_lock);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300897
Michal Kazior7147a132014-05-26 12:02:58 +0200898 nentries_mask = src_ring->nentries_mask;
899 sw_index = src_ring->sw_index;
900 write_index = src_ring->write_index;
901
Michal Kazior726346f2014-02-27 18:50:04 +0200902 if (unlikely(CE_RING_DELTA(nentries_mask,
903 write_index, sw_index - 1) < n_items)) {
904 err = -ENOBUFS;
Michal Kazior08b8aa02014-05-26 12:02:59 +0200905 goto err;
Michal Kazior726346f2014-02-27 18:50:04 +0200906 }
907
908 for (i = 0; i < n_items - 1; i++) {
Michal Kazior7aa7a722014-08-25 12:09:38 +0200909 ath10k_dbg(ar, ATH10K_DBG_PCI,
Michal Kazior726346f2014-02-27 18:50:04 +0200910 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
911 i, items[i].paddr, items[i].len, n_items);
Michal Kazior7aa7a722014-08-25 12:09:38 +0200912 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
Michal Kazior726346f2014-02-27 18:50:04 +0200913 items[i].vaddr, items[i].len);
914
915 err = ath10k_ce_send_nolock(ce_pipe,
916 items[i].transfer_context,
917 items[i].paddr,
918 items[i].len,
919 items[i].transfer_id,
920 CE_SEND_FLAG_GATHER);
921 if (err)
Michal Kazior08b8aa02014-05-26 12:02:59 +0200922 goto err;
Michal Kazior726346f2014-02-27 18:50:04 +0200923 }
924
925 /* `i` is equal to `n_items -1` after for() */
Kalle Valo5e3dd152013-06-12 20:52:10 +0300926
Michal Kazior7aa7a722014-08-25 12:09:38 +0200927 ath10k_dbg(ar, ATH10K_DBG_PCI,
Michal Kazior726346f2014-02-27 18:50:04 +0200928 "pci tx item %d paddr 0x%08x len %d n_items %d\n",
929 i, items[i].paddr, items[i].len, n_items);
Michal Kazior7aa7a722014-08-25 12:09:38 +0200930 ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ",
Michal Kazior726346f2014-02-27 18:50:04 +0200931 items[i].vaddr, items[i].len);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300932
Michal Kazior726346f2014-02-27 18:50:04 +0200933 err = ath10k_ce_send_nolock(ce_pipe,
934 items[i].transfer_context,
935 items[i].paddr,
936 items[i].len,
937 items[i].transfer_id,
938 0);
939 if (err)
Michal Kazior08b8aa02014-05-26 12:02:59 +0200940 goto err;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300941
Michal Kazior08b8aa02014-05-26 12:02:59 +0200942 spin_unlock_bh(&ar_pci->ce_lock);
943 return 0;
944
945err:
946 for (; i > 0; i--)
947 __ath10k_ce_send_revert(ce_pipe);
948
Michal Kazior726346f2014-02-27 18:50:04 +0200949 spin_unlock_bh(&ar_pci->ce_lock);
950 return err;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300951}
952
Kalle Valoeef25402014-09-24 14:16:52 +0300953static int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
954 size_t buf_len)
955{
956 return ath10k_pci_diag_read_mem(ar, address, buf, buf_len);
957}
958
Kalle Valo5e3dd152013-06-12 20:52:10 +0300959static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
960{
961 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
Kalle Valo50f87a62014-03-28 09:32:52 +0200962
Michal Kazior7aa7a722014-08-25 12:09:38 +0200963 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n");
Kalle Valo50f87a62014-03-28 09:32:52 +0200964
Michal Kazior3efcb3b2013-10-02 11:03:41 +0200965 return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300966}
967
Ben Greear384914b2014-08-25 08:37:32 +0300968static void ath10k_pci_dump_registers(struct ath10k *ar,
969 struct ath10k_fw_crash_data *crash_data)
Kalle Valo5e3dd152013-06-12 20:52:10 +0300970{
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300971 __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {};
972 int i, ret;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300973
Ben Greear384914b2014-08-25 08:37:32 +0300974 lockdep_assert_held(&ar->data_lock);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300975
Kalle Valo3d29a3e2014-08-25 08:37:26 +0300976 ret = ath10k_pci_diag_read_hi(ar, &reg_dump_values[0],
977 hi_failure_state,
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300978 REG_DUMP_COUNT_QCA988X * sizeof(__le32));
Michal Kazior1d2b48d2013-11-08 08:01:34 +0100979 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +0200980 ath10k_err(ar, "failed to read firmware dump area: %d\n", ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300981 return;
982 }
983
984 BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4);
985
Michal Kazior7aa7a722014-08-25 12:09:38 +0200986 ath10k_err(ar, "firmware register dump:\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +0300987 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4)
Michal Kazior7aa7a722014-08-25 12:09:38 +0200988 ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n",
Kalle Valo5e3dd152013-06-12 20:52:10 +0300989 i,
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300990 __le32_to_cpu(reg_dump_values[i]),
991 __le32_to_cpu(reg_dump_values[i + 1]),
992 __le32_to_cpu(reg_dump_values[i + 2]),
993 __le32_to_cpu(reg_dump_values[i + 3]));
Michal Kazioraffd3212013-07-16 09:54:35 +0200994
Michal Kazior1bbb1192014-08-25 12:13:14 +0200995 if (!crash_data)
996 return;
997
Ben Greear384914b2014-08-25 08:37:32 +0300998 for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++)
Michal Kazior0fdc14e42014-08-26 19:14:03 +0300999 crash_data->registers[i] = reg_dump_values[i];
Ben Greear384914b2014-08-25 08:37:32 +03001000}
1001
Kalle Valo0e9848c2014-08-25 08:37:37 +03001002static void ath10k_pci_fw_crashed_dump(struct ath10k *ar)
Ben Greear384914b2014-08-25 08:37:32 +03001003{
1004 struct ath10k_fw_crash_data *crash_data;
1005 char uuid[50];
1006
1007 spin_lock_bh(&ar->data_lock);
1008
Ben Greearf51dbe72014-09-29 14:41:46 +03001009 ar->stats.fw_crash_counter++;
1010
Ben Greear384914b2014-08-25 08:37:32 +03001011 crash_data = ath10k_debug_get_new_fw_crash_data(ar);
1012
1013 if (crash_data)
1014 scnprintf(uuid, sizeof(uuid), "%pUl", &crash_data->uuid);
1015 else
1016 scnprintf(uuid, sizeof(uuid), "n/a");
1017
Michal Kazior7aa7a722014-08-25 12:09:38 +02001018 ath10k_err(ar, "firmware crashed! (uuid %s)\n", uuid);
Kalle Valo8a0c7972014-08-25 08:37:45 +03001019 ath10k_print_driver_info(ar);
Ben Greear384914b2014-08-25 08:37:32 +03001020 ath10k_pci_dump_registers(ar, crash_data);
1021
Ben Greear384914b2014-08-25 08:37:32 +03001022 spin_unlock_bh(&ar->data_lock);
Michal Kazioraffd3212013-07-16 09:54:35 +02001023
Michal Kazior5e90de82013-10-16 16:46:05 +03001024 queue_work(ar->workqueue, &ar->restart_work);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001025}
1026
1027static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
1028 int force)
1029{
Michal Kazior7aa7a722014-08-25 12:09:38 +02001030 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n");
Kalle Valo50f87a62014-03-28 09:32:52 +02001031
Kalle Valo5e3dd152013-06-12 20:52:10 +03001032 if (!force) {
1033 int resources;
1034 /*
1035 * Decide whether to actually poll for completions, or just
1036 * wait for a later chance.
1037 * If there seem to be plenty of resources left, then just wait
1038 * since checking involves reading a CE register, which is a
1039 * relatively expensive operation.
1040 */
1041 resources = ath10k_pci_hif_get_free_queue_number(ar, pipe);
1042
1043 /*
1044 * If at least 50% of the total resources are still available,
1045 * don't bother checking again yet.
1046 */
1047 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
1048 return;
1049 }
1050 ath10k_ce_per_engine_service(ar, pipe);
1051}
1052
Michal Kaziore799bbf2013-07-05 16:15:12 +03001053static void ath10k_pci_hif_set_callbacks(struct ath10k *ar,
1054 struct ath10k_hif_cb *callbacks)
Kalle Valo5e3dd152013-06-12 20:52:10 +03001055{
1056 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1057
Michal Kazior7aa7a722014-08-25 12:09:38 +02001058 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif set callbacks\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03001059
1060 memcpy(&ar_pci->msg_callbacks_current, callbacks,
1061 sizeof(ar_pci->msg_callbacks_current));
1062}
1063
Michal Kazior96a9d0d2013-11-08 08:01:25 +01001064static void ath10k_pci_kill_tasklet(struct ath10k *ar)
Kalle Valo5e3dd152013-06-12 20:52:10 +03001065{
1066 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001067 int i;
1068
Kalle Valo5e3dd152013-06-12 20:52:10 +03001069 tasklet_kill(&ar_pci->intr_tq);
Michal Kazior103d4f52013-11-08 08:01:24 +01001070 tasklet_kill(&ar_pci->msi_fw_err);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001071
1072 for (i = 0; i < CE_COUNT; i++)
1073 tasklet_kill(&ar_pci->pipe_info[i].intr);
Michal Kazior728f95e2014-08-22 14:33:14 +02001074
1075 del_timer_sync(&ar_pci->rx_post_retry);
Michal Kazior96a9d0d2013-11-08 08:01:25 +01001076}
1077
Kalle Valo5e3dd152013-06-12 20:52:10 +03001078static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar,
1079 u16 service_id, u8 *ul_pipe,
1080 u8 *dl_pipe, int *ul_is_polled,
1081 int *dl_is_polled)
1082{
Michal Kazior7c6aa252014-08-26 19:14:03 +03001083 const struct service_to_pipe *entry;
1084 bool ul_set = false, dl_set = false;
1085 int i;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001086
Michal Kazior7aa7a722014-08-25 12:09:38 +02001087 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n");
Kalle Valo50f87a62014-03-28 09:32:52 +02001088
Kalle Valo5e3dd152013-06-12 20:52:10 +03001089 /* polling for received messages not supported */
1090 *dl_is_polled = 0;
1091
Michal Kazior7c6aa252014-08-26 19:14:03 +03001092 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
1093 entry = &target_service_to_ce_map_wlan[i];
Kalle Valo5e3dd152013-06-12 20:52:10 +03001094
Michal Kazior0fdc14e42014-08-26 19:14:03 +03001095 if (__le32_to_cpu(entry->service_id) != service_id)
Michal Kazior7c6aa252014-08-26 19:14:03 +03001096 continue;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001097
Michal Kazior0fdc14e42014-08-26 19:14:03 +03001098 switch (__le32_to_cpu(entry->pipedir)) {
Michal Kazior7c6aa252014-08-26 19:14:03 +03001099 case PIPEDIR_NONE:
1100 break;
1101 case PIPEDIR_IN:
1102 WARN_ON(dl_set);
Michal Kazior0fdc14e42014-08-26 19:14:03 +03001103 *dl_pipe = __le32_to_cpu(entry->pipenum);
Michal Kazior7c6aa252014-08-26 19:14:03 +03001104 dl_set = true;
1105 break;
1106 case PIPEDIR_OUT:
1107 WARN_ON(ul_set);
Michal Kazior0fdc14e42014-08-26 19:14:03 +03001108 *ul_pipe = __le32_to_cpu(entry->pipenum);
Michal Kazior7c6aa252014-08-26 19:14:03 +03001109 ul_set = true;
1110 break;
1111 case PIPEDIR_INOUT:
1112 WARN_ON(dl_set);
1113 WARN_ON(ul_set);
Michal Kazior0fdc14e42014-08-26 19:14:03 +03001114 *dl_pipe = __le32_to_cpu(entry->pipenum);
1115 *ul_pipe = __le32_to_cpu(entry->pipenum);
Michal Kazior7c6aa252014-08-26 19:14:03 +03001116 dl_set = true;
1117 ul_set = true;
1118 break;
1119 }
Kalle Valo5e3dd152013-06-12 20:52:10 +03001120 }
Michal Kazior7c6aa252014-08-26 19:14:03 +03001121
1122 if (WARN_ON(!ul_set || !dl_set))
1123 return -ENOENT;
1124
Kalle Valo5e3dd152013-06-12 20:52:10 +03001125 *ul_is_polled =
1126 (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0;
1127
Michal Kazior7c6aa252014-08-26 19:14:03 +03001128 return 0;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001129}
1130
1131static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar,
Kalle Valo5b07e072014-09-14 12:50:06 +03001132 u8 *ul_pipe, u8 *dl_pipe)
Kalle Valo5e3dd152013-06-12 20:52:10 +03001133{
1134 int ul_is_polled, dl_is_polled;
1135
Michal Kazior7aa7a722014-08-25 12:09:38 +02001136 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n");
Kalle Valo50f87a62014-03-28 09:32:52 +02001137
Kalle Valo5e3dd152013-06-12 20:52:10 +03001138 (void)ath10k_pci_hif_map_service_to_pipe(ar,
1139 ATH10K_HTC_SVC_ID_RSVD_CTRL,
1140 ul_pipe,
1141 dl_pipe,
1142 &ul_is_polled,
1143 &dl_is_polled);
1144}
1145
Michal Kaziorec5ba4d2014-08-22 14:23:33 +02001146static void ath10k_pci_irq_disable(struct ath10k *ar)
Kalle Valo5e3dd152013-06-12 20:52:10 +03001147{
Kalle Valo5e3dd152013-06-12 20:52:10 +03001148 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
Michal Kaziorec5ba4d2014-08-22 14:23:33 +02001149 int i;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001150
Michal Kaziorec5ba4d2014-08-22 14:23:33 +02001151 ath10k_ce_disable_interrupts(ar);
Michal Kaziore75db4e2014-08-28 22:14:16 +03001152 ath10k_pci_disable_and_clear_legacy_irq(ar);
1153 /* FIXME: How to mask all MSI interrupts? */
Kalle Valo5e3dd152013-06-12 20:52:10 +03001154
Michal Kaziorec5ba4d2014-08-22 14:23:33 +02001155 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
1156 synchronize_irq(ar_pci->pdev->irq + i);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001157}
1158
Michal Kaziorec5ba4d2014-08-22 14:23:33 +02001159static void ath10k_pci_irq_enable(struct ath10k *ar)
Kalle Valo5e3dd152013-06-12 20:52:10 +03001160{
Michal Kaziorec5ba4d2014-08-22 14:23:33 +02001161 ath10k_ce_enable_interrupts(ar);
Michal Kaziore75db4e2014-08-28 22:14:16 +03001162 ath10k_pci_enable_legacy_irq(ar);
1163 /* FIXME: How to unmask all MSI interrupts? */
Kalle Valo5e3dd152013-06-12 20:52:10 +03001164}
1165
1166static int ath10k_pci_hif_start(struct ath10k *ar)
1167{
Michal Kazior7aa7a722014-08-25 12:09:38 +02001168 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03001169
Michal Kaziorec5ba4d2014-08-22 14:23:33 +02001170 ath10k_pci_irq_enable(ar);
Michal Kazior728f95e2014-08-22 14:33:14 +02001171 ath10k_pci_rx_post(ar);
Kalle Valo50f87a62014-03-28 09:32:52 +02001172
Kalle Valo5e3dd152013-06-12 20:52:10 +03001173 return 0;
1174}
1175
Michal Kazior87263e52013-08-27 13:08:01 +02001176static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
Kalle Valo5e3dd152013-06-12 20:52:10 +03001177{
1178 struct ath10k *ar;
1179 struct ath10k_pci *ar_pci;
Michal Kazior2aa39112013-08-27 13:08:02 +02001180 struct ath10k_ce_pipe *ce_hdl;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001181 u32 buf_sz;
1182 struct sk_buff *netbuf;
1183 u32 ce_data;
1184
1185 buf_sz = pipe_info->buf_sz;
1186
1187 /* Unused Copy Engine */
1188 if (buf_sz == 0)
1189 return;
1190
1191 ar = pipe_info->hif_ce_state;
1192 ar_pci = ath10k_pci_priv(ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001193 ce_hdl = pipe_info->ce_hdl;
1194
1195 while (ath10k_ce_revoke_recv_next(ce_hdl, (void **)&netbuf,
1196 &ce_data) == 0) {
1197 dma_unmap_single(ar->dev, ATH10K_SKB_CB(netbuf)->paddr,
1198 netbuf->len + skb_tailroom(netbuf),
1199 DMA_FROM_DEVICE);
1200 dev_kfree_skb_any(netbuf);
1201 }
1202}
1203
Michal Kazior87263e52013-08-27 13:08:01 +02001204static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pipe_info)
Kalle Valo5e3dd152013-06-12 20:52:10 +03001205{
1206 struct ath10k *ar;
1207 struct ath10k_pci *ar_pci;
Michal Kazior2aa39112013-08-27 13:08:02 +02001208 struct ath10k_ce_pipe *ce_hdl;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001209 struct sk_buff *netbuf;
1210 u32 ce_data;
1211 unsigned int nbytes;
1212 unsigned int id;
1213 u32 buf_sz;
1214
1215 buf_sz = pipe_info->buf_sz;
1216
1217 /* Unused Copy Engine */
1218 if (buf_sz == 0)
1219 return;
1220
1221 ar = pipe_info->hif_ce_state;
1222 ar_pci = ath10k_pci_priv(ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001223 ce_hdl = pipe_info->ce_hdl;
1224
1225 while (ath10k_ce_cancel_send_next(ce_hdl, (void **)&netbuf,
1226 &ce_data, &nbytes, &id) == 0) {
Michal Kaziora16942e2014-02-27 18:50:04 +02001227 /* no need to call tx completion for NULL pointers */
1228 if (!netbuf)
Michal Kazior2415fc12013-11-08 08:01:32 +01001229 continue;
Michal Kazior2415fc12013-11-08 08:01:32 +01001230
Kalle Valoe9bb0aa2013-09-08 18:36:11 +03001231 ar_pci->msg_callbacks_current.tx_completion(ar,
1232 netbuf,
1233 id);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001234 }
1235}
1236
1237/*
1238 * Cleanup residual buffers for device shutdown:
1239 * buffers that were enqueued for receive
1240 * buffers that were to be sent
1241 * Note: Buffers that had completed but which were
1242 * not yet processed are on a completion queue. They
1243 * are handled when the completion thread shuts down.
1244 */
1245static void ath10k_pci_buffer_cleanup(struct ath10k *ar)
1246{
1247 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1248 int pipe_num;
1249
Michal Kaziorfad6ed72013-11-08 08:01:23 +01001250 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
Michal Kazior87263e52013-08-27 13:08:01 +02001251 struct ath10k_pci_pipe *pipe_info;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001252
1253 pipe_info = &ar_pci->pipe_info[pipe_num];
1254 ath10k_pci_rx_pipe_cleanup(pipe_info);
1255 ath10k_pci_tx_pipe_cleanup(pipe_info);
1256 }
1257}
1258
1259static void ath10k_pci_ce_deinit(struct ath10k *ar)
1260{
Michal Kazior25d0dbc2014-03-28 10:02:38 +02001261 int i;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001262
Michal Kazior25d0dbc2014-03-28 10:02:38 +02001263 for (i = 0; i < CE_COUNT; i++)
1264 ath10k_ce_deinit_pipe(ar, i);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001265}
1266
Michal Kazior728f95e2014-08-22 14:33:14 +02001267static void ath10k_pci_flush(struct ath10k *ar)
1268{
1269 ath10k_pci_kill_tasklet(ar);
1270 ath10k_pci_buffer_cleanup(ar);
1271}
1272
Kalle Valo5e3dd152013-06-12 20:52:10 +03001273static void ath10k_pci_hif_stop(struct ath10k *ar)
1274{
Michal Kazior7aa7a722014-08-25 12:09:38 +02001275 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
Michal Kazior32270b62013-08-02 09:15:47 +02001276
Michal Kazior10d23db2014-08-22 14:33:15 +02001277 /* Most likely the device has HTT Rx ring configured. The only way to
1278 * prevent the device from accessing (and possible corrupting) host
1279 * memory is to reset the chip now.
Michal Kaziore75db4e2014-08-28 22:14:16 +03001280 *
1281 * There's also no known way of masking MSI interrupts on the device.
1282 * For ranged MSI the CE-related interrupts can be masked. However
1283 * regardless how many MSI interrupts are assigned the first one
1284 * is always used for firmware indications (crashes) and cannot be
1285 * masked. To prevent the device from asserting the interrupt reset it
1286 * before proceeding with cleanup.
Michal Kazior10d23db2014-08-22 14:33:15 +02001287 */
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001288 ath10k_pci_warm_reset(ar);
Michal Kaziore75db4e2014-08-28 22:14:16 +03001289
1290 ath10k_pci_irq_disable(ar);
1291 ath10k_pci_flush(ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001292}
1293
1294static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar,
1295 void *req, u32 req_len,
1296 void *resp, u32 *resp_len)
1297{
1298 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
Michal Kazior2aa39112013-08-27 13:08:02 +02001299 struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG];
1300 struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST];
1301 struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl;
1302 struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001303 dma_addr_t req_paddr = 0;
1304 dma_addr_t resp_paddr = 0;
1305 struct bmi_xfer xfer = {};
1306 void *treq, *tresp = NULL;
1307 int ret = 0;
1308
Michal Kazior85622cd2013-11-25 14:06:22 +01001309 might_sleep();
1310
Kalle Valo5e3dd152013-06-12 20:52:10 +03001311 if (resp && !resp_len)
1312 return -EINVAL;
1313
1314 if (resp && resp_len && *resp_len == 0)
1315 return -EINVAL;
1316
1317 treq = kmemdup(req, req_len, GFP_KERNEL);
1318 if (!treq)
1319 return -ENOMEM;
1320
1321 req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE);
1322 ret = dma_mapping_error(ar->dev, req_paddr);
1323 if (ret)
1324 goto err_dma;
1325
1326 if (resp && resp_len) {
1327 tresp = kzalloc(*resp_len, GFP_KERNEL);
1328 if (!tresp) {
1329 ret = -ENOMEM;
1330 goto err_req;
1331 }
1332
1333 resp_paddr = dma_map_single(ar->dev, tresp, *resp_len,
1334 DMA_FROM_DEVICE);
1335 ret = dma_mapping_error(ar->dev, resp_paddr);
1336 if (ret)
1337 goto err_req;
1338
1339 xfer.wait_for_resp = true;
1340 xfer.resp_len = 0;
1341
Michal Kazior728f95e2014-08-22 14:33:14 +02001342 ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001343 }
1344
Kalle Valo5e3dd152013-06-12 20:52:10 +03001345 ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0);
1346 if (ret)
1347 goto err_resp;
1348
Michal Kazior85622cd2013-11-25 14:06:22 +01001349 ret = ath10k_pci_bmi_wait(ce_tx, ce_rx, &xfer);
1350 if (ret) {
Kalle Valo5e3dd152013-06-12 20:52:10 +03001351 u32 unused_buffer;
1352 unsigned int unused_nbytes;
1353 unsigned int unused_id;
1354
Kalle Valo5e3dd152013-06-12 20:52:10 +03001355 ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer,
1356 &unused_nbytes, &unused_id);
1357 } else {
1358 /* non-zero means we did not time out */
1359 ret = 0;
1360 }
1361
1362err_resp:
1363 if (resp) {
1364 u32 unused_buffer;
1365
1366 ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer);
1367 dma_unmap_single(ar->dev, resp_paddr,
1368 *resp_len, DMA_FROM_DEVICE);
1369 }
1370err_req:
1371 dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE);
1372
1373 if (ret == 0 && resp_len) {
1374 *resp_len = min(*resp_len, xfer.resp_len);
1375 memcpy(resp, tresp, xfer.resp_len);
1376 }
1377err_dma:
1378 kfree(treq);
1379 kfree(tresp);
1380
1381 return ret;
1382}
1383
Michal Kazior5440ce22013-09-03 15:09:58 +02001384static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state)
Kalle Valo5e3dd152013-06-12 20:52:10 +03001385{
Michal Kazior5440ce22013-09-03 15:09:58 +02001386 struct bmi_xfer *xfer;
1387 u32 ce_data;
1388 unsigned int nbytes;
1389 unsigned int transfer_id;
1390
1391 if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer, &ce_data,
1392 &nbytes, &transfer_id))
1393 return;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001394
Michal Kazior2374b182014-07-14 16:25:25 +03001395 xfer->tx_done = true;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001396}
1397
Michal Kazior5440ce22013-09-03 15:09:58 +02001398static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state)
Kalle Valo5e3dd152013-06-12 20:52:10 +03001399{
Michal Kazior7aa7a722014-08-25 12:09:38 +02001400 struct ath10k *ar = ce_state->ar;
Michal Kazior5440ce22013-09-03 15:09:58 +02001401 struct bmi_xfer *xfer;
1402 u32 ce_data;
1403 unsigned int nbytes;
1404 unsigned int transfer_id;
1405 unsigned int flags;
1406
1407 if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data,
1408 &nbytes, &transfer_id, &flags))
1409 return;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001410
1411 if (!xfer->wait_for_resp) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001412 ath10k_warn(ar, "unexpected: BMI data received; ignoring\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03001413 return;
1414 }
1415
1416 xfer->resp_len = nbytes;
Michal Kazior2374b182014-07-14 16:25:25 +03001417 xfer->rx_done = true;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001418}
1419
Michal Kazior85622cd2013-11-25 14:06:22 +01001420static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe,
1421 struct ath10k_ce_pipe *rx_pipe,
1422 struct bmi_xfer *xfer)
1423{
1424 unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ;
1425
1426 while (time_before_eq(jiffies, timeout)) {
1427 ath10k_pci_bmi_send_done(tx_pipe);
1428 ath10k_pci_bmi_recv_data(rx_pipe);
1429
Michal Kazior2374b182014-07-14 16:25:25 +03001430 if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp))
Michal Kazior85622cd2013-11-25 14:06:22 +01001431 return 0;
1432
1433 schedule();
1434 }
1435
1436 return -ETIMEDOUT;
1437}
1438
Kalle Valo5e3dd152013-06-12 20:52:10 +03001439/*
Kalle Valo5e3dd152013-06-12 20:52:10 +03001440 * Send an interrupt to the device to wake up the Target CPU
1441 * so it has an opportunity to notice any changed state.
1442 */
1443static int ath10k_pci_wake_target_cpu(struct ath10k *ar)
1444{
Michal Kazior9e264942014-09-02 11:00:21 +03001445 u32 addr, val;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001446
Michal Kazior9e264942014-09-02 11:00:21 +03001447 addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS;
1448 val = ath10k_pci_read32(ar, addr);
1449 val |= CORE_CTRL_CPU_INTR_MASK;
1450 ath10k_pci_write32(ar, addr, val);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001451
Michal Kazior1d2b48d2013-11-08 08:01:34 +01001452 return 0;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001453}
1454
1455static int ath10k_pci_init_config(struct ath10k *ar)
1456{
1457 u32 interconnect_targ_addr;
1458 u32 pcie_state_targ_addr = 0;
1459 u32 pipe_cfg_targ_addr = 0;
1460 u32 svc_to_pipe_map = 0;
1461 u32 pcie_config_flags = 0;
1462 u32 ealloc_value;
1463 u32 ealloc_targ_addr;
1464 u32 flag2_value;
1465 u32 flag2_targ_addr;
1466 int ret = 0;
1467
1468 /* Download to Target the CE Config and the service-to-CE map */
1469 interconnect_targ_addr =
1470 host_interest_item_address(HI_ITEM(hi_interconnect_state));
1471
1472 /* Supply Target-side CE configuration */
Michal Kazior9e264942014-09-02 11:00:21 +03001473 ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr,
1474 &pcie_state_targ_addr);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001475 if (ret != 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001476 ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001477 return ret;
1478 }
1479
1480 if (pcie_state_targ_addr == 0) {
1481 ret = -EIO;
Michal Kazior7aa7a722014-08-25 12:09:38 +02001482 ath10k_err(ar, "Invalid pcie state addr\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03001483 return ret;
1484 }
1485
Michal Kazior9e264942014-09-02 11:00:21 +03001486 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
Kalle Valo5e3dd152013-06-12 20:52:10 +03001487 offsetof(struct pcie_state,
Michal Kazior9e264942014-09-02 11:00:21 +03001488 pipe_cfg_addr)),
1489 &pipe_cfg_targ_addr);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001490 if (ret != 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001491 ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001492 return ret;
1493 }
1494
1495 if (pipe_cfg_targ_addr == 0) {
1496 ret = -EIO;
Michal Kazior7aa7a722014-08-25 12:09:38 +02001497 ath10k_err(ar, "Invalid pipe cfg addr\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03001498 return ret;
1499 }
1500
1501 ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr,
Kalle Valo5b07e072014-09-14 12:50:06 +03001502 target_ce_config_wlan,
1503 sizeof(target_ce_config_wlan));
Kalle Valo5e3dd152013-06-12 20:52:10 +03001504
1505 if (ret != 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001506 ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001507 return ret;
1508 }
1509
Michal Kazior9e264942014-09-02 11:00:21 +03001510 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
Kalle Valo5e3dd152013-06-12 20:52:10 +03001511 offsetof(struct pcie_state,
Michal Kazior9e264942014-09-02 11:00:21 +03001512 svc_to_pipe_map)),
1513 &svc_to_pipe_map);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001514 if (ret != 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001515 ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001516 return ret;
1517 }
1518
1519 if (svc_to_pipe_map == 0) {
1520 ret = -EIO;
Michal Kazior7aa7a722014-08-25 12:09:38 +02001521 ath10k_err(ar, "Invalid svc_to_pipe map\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03001522 return ret;
1523 }
1524
1525 ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map,
Kalle Valo5b07e072014-09-14 12:50:06 +03001526 target_service_to_ce_map_wlan,
1527 sizeof(target_service_to_ce_map_wlan));
Kalle Valo5e3dd152013-06-12 20:52:10 +03001528 if (ret != 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001529 ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001530 return ret;
1531 }
1532
Michal Kazior9e264942014-09-02 11:00:21 +03001533 ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr +
Kalle Valo5e3dd152013-06-12 20:52:10 +03001534 offsetof(struct pcie_state,
Michal Kazior9e264942014-09-02 11:00:21 +03001535 config_flags)),
1536 &pcie_config_flags);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001537 if (ret != 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001538 ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001539 return ret;
1540 }
1541
1542 pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1;
1543
Michal Kazior9e264942014-09-02 11:00:21 +03001544 ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr +
1545 offsetof(struct pcie_state,
1546 config_flags)),
1547 pcie_config_flags);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001548 if (ret != 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001549 ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001550 return ret;
1551 }
1552
1553 /* configure early allocation */
1554 ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc));
1555
Michal Kazior9e264942014-09-02 11:00:21 +03001556 ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001557 if (ret != 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001558 ath10k_err(ar, "Faile to get early alloc val: %d\n", ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001559 return ret;
1560 }
1561
1562 /* first bank is switched to IRAM */
1563 ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) &
1564 HI_EARLY_ALLOC_MAGIC_MASK);
1565 ealloc_value |= ((1 << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) &
1566 HI_EARLY_ALLOC_IRAM_BANKS_MASK);
1567
Michal Kazior9e264942014-09-02 11:00:21 +03001568 ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001569 if (ret != 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001570 ath10k_err(ar, "Failed to set early alloc val: %d\n", ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001571 return ret;
1572 }
1573
1574 /* Tell Target to proceed with initialization */
1575 flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2));
1576
Michal Kazior9e264942014-09-02 11:00:21 +03001577 ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001578 if (ret != 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001579 ath10k_err(ar, "Failed to get option val: %d\n", ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001580 return ret;
1581 }
1582
1583 flag2_value |= HI_OPTION_EARLY_CFG_DONE;
1584
Michal Kazior9e264942014-09-02 11:00:21 +03001585 ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001586 if (ret != 0) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001587 ath10k_err(ar, "Failed to set option val: %d\n", ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001588 return ret;
1589 }
1590
1591 return 0;
1592}
1593
Michal Kazior25d0dbc2014-03-28 10:02:38 +02001594static int ath10k_pci_alloc_ce(struct ath10k *ar)
1595{
1596 int i, ret;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001597
Michal Kazior25d0dbc2014-03-28 10:02:38 +02001598 for (i = 0; i < CE_COUNT; i++) {
1599 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
1600 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001601 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
Michal Kazior25d0dbc2014-03-28 10:02:38 +02001602 i, ret);
1603 return ret;
1604 }
1605 }
1606
1607 return 0;
1608}
1609
1610static void ath10k_pci_free_ce(struct ath10k *ar)
1611{
1612 int i;
1613
1614 for (i = 0; i < CE_COUNT; i++)
1615 ath10k_ce_free_pipe(ar, i);
1616}
Kalle Valo5e3dd152013-06-12 20:52:10 +03001617
1618static int ath10k_pci_ce_init(struct ath10k *ar)
1619{
1620 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
Michal Kazior87263e52013-08-27 13:08:01 +02001621 struct ath10k_pci_pipe *pipe_info;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001622 const struct ce_attr *attr;
Michal Kazior25d0dbc2014-03-28 10:02:38 +02001623 int pipe_num, ret;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001624
Michal Kaziorfad6ed72013-11-08 08:01:23 +01001625 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
Kalle Valo5e3dd152013-06-12 20:52:10 +03001626 pipe_info = &ar_pci->pipe_info[pipe_num];
Michal Kazior25d0dbc2014-03-28 10:02:38 +02001627 pipe_info->ce_hdl = &ar_pci->ce_states[pipe_num];
Kalle Valo5e3dd152013-06-12 20:52:10 +03001628 pipe_info->pipe_num = pipe_num;
1629 pipe_info->hif_ce_state = ar;
1630 attr = &host_ce_config_wlan[pipe_num];
1631
Michal Kazior145cc122014-08-22 14:23:32 +02001632 ret = ath10k_ce_init_pipe(ar, pipe_num, attr,
1633 ath10k_pci_ce_send_done,
1634 ath10k_pci_ce_recv_data);
Michal Kazior25d0dbc2014-03-28 10:02:38 +02001635 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001636 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
Michal Kazior25d0dbc2014-03-28 10:02:38 +02001637 pipe_num, ret);
1638 return ret;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001639 }
1640
Michal Kaziorfad6ed72013-11-08 08:01:23 +01001641 if (pipe_num == CE_COUNT - 1) {
Kalle Valo5e3dd152013-06-12 20:52:10 +03001642 /*
1643 * Reserve the ultimate CE for
1644 * diagnostic Window support
1645 */
Michal Kaziorfad6ed72013-11-08 08:01:23 +01001646 ar_pci->ce_diag = pipe_info->ce_hdl;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001647 continue;
1648 }
1649
Kalle Valocfbc06a2014-09-14 12:50:23 +03001650 pipe_info->buf_sz = (size_t)(attr->src_sz_max);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001651 }
1652
Kalle Valo5e3dd152013-06-12 20:52:10 +03001653 return 0;
1654}
1655
Michal Kazior5c771e72014-08-22 14:23:34 +02001656static bool ath10k_pci_has_fw_crashed(struct ath10k *ar)
Kalle Valo5e3dd152013-06-12 20:52:10 +03001657{
Michal Kazior5c771e72014-08-22 14:23:34 +02001658 return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) &
1659 FW_IND_EVENT_PENDING;
1660}
Kalle Valo5e3dd152013-06-12 20:52:10 +03001661
Michal Kazior5c771e72014-08-22 14:23:34 +02001662static void ath10k_pci_fw_crashed_clear(struct ath10k *ar)
1663{
1664 u32 val;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001665
Michal Kazior5c771e72014-08-22 14:23:34 +02001666 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
1667 val &= ~FW_IND_EVENT_PENDING;
1668 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001669}
1670
Michal Kaziorde013572014-05-14 16:56:16 +03001671/* this function effectively clears target memory controller assert line */
1672static void ath10k_pci_warm_reset_si0(struct ath10k *ar)
1673{
1674 u32 val;
1675
1676 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1677 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
1678 val | SOC_RESET_CONTROL_SI0_RST_MASK);
1679 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1680
1681 msleep(10);
1682
1683 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1684 ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS,
1685 val & ~SOC_RESET_CONTROL_SI0_RST_MASK);
1686 val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS);
1687
1688 msleep(10);
1689}
1690
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001691static int ath10k_pci_warm_reset(struct ath10k *ar)
1692{
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001693 u32 val;
1694
Michal Kazior7aa7a722014-08-25 12:09:38 +02001695 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n");
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001696
Ben Greearf51dbe72014-09-29 14:41:46 +03001697 spin_lock_bh(&ar->data_lock);
1698
1699 ar->stats.fw_warm_reset_counter++;
1700
1701 spin_unlock_bh(&ar->data_lock);
1702
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001703 /* debug */
1704 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1705 PCIE_INTR_CAUSE_ADDRESS);
Michal Kazior7aa7a722014-08-25 12:09:38 +02001706 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n",
1707 val);
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001708
1709 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1710 CPU_INTR_ADDRESS);
Michal Kazior7aa7a722014-08-25 12:09:38 +02001711 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n",
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001712 val);
1713
1714 /* disable pending irqs */
1715 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1716 PCIE_INTR_ENABLE_ADDRESS, 0);
1717
1718 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
1719 PCIE_INTR_CLR_ADDRESS, ~0);
1720
1721 msleep(100);
1722
1723 /* clear fw indicator */
Kalle Valob39712c2014-03-28 09:32:46 +02001724 ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0);
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001725
1726 /* clear target LF timer interrupts */
1727 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1728 SOC_LF_TIMER_CONTROL0_ADDRESS);
1729 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS +
1730 SOC_LF_TIMER_CONTROL0_ADDRESS,
1731 val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK);
1732
1733 /* reset CE */
1734 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1735 SOC_RESET_CONTROL_ADDRESS);
1736 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1737 val | SOC_RESET_CONTROL_CE_RST_MASK);
1738 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1739 SOC_RESET_CONTROL_ADDRESS);
1740 msleep(10);
1741
1742 /* unreset CE */
1743 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1744 val & ~SOC_RESET_CONTROL_CE_RST_MASK);
1745 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1746 SOC_RESET_CONTROL_ADDRESS);
1747 msleep(10);
1748
Michal Kaziorde013572014-05-14 16:56:16 +03001749 ath10k_pci_warm_reset_si0(ar);
1750
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001751 /* debug */
1752 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1753 PCIE_INTR_CAUSE_ADDRESS);
Michal Kazior7aa7a722014-08-25 12:09:38 +02001754 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot host cpu intr cause: 0x%08x\n",
1755 val);
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001756
1757 val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS +
1758 CPU_INTR_ADDRESS);
Michal Kazior7aa7a722014-08-25 12:09:38 +02001759 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target cpu intr cause: 0x%08x\n",
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001760 val);
1761
1762 /* CPU warm reset */
1763 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1764 SOC_RESET_CONTROL_ADDRESS);
1765 ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS,
1766 val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK);
1767
1768 val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS +
1769 SOC_RESET_CONTROL_ADDRESS);
Michal Kazior7aa7a722014-08-25 12:09:38 +02001770 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target reset state: 0x%08x\n",
1771 val);
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001772
1773 msleep(100);
1774
Michal Kazior7aa7a722014-08-25 12:09:38 +02001775 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n");
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001776
Michal Kaziorc0c378f2014-08-07 11:03:28 +02001777 return 0;
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001778}
1779
1780static int __ath10k_pci_hif_power_up(struct ath10k *ar, bool cold_reset)
Michal Kazior8c5c5362013-07-16 09:38:50 +02001781{
1782 int ret;
1783
1784 /*
1785 * Bring the target up cleanly.
1786 *
1787 * The target may be in an undefined state with an AUX-powered Target
1788 * and a Host in WoW mode. If the Host crashes, loses power, or is
1789 * restarted (without unloading the driver) then the Target is left
1790 * (aux) powered and running. On a subsequent driver load, the Target
1791 * is in an unexpected state. We try to catch that here in order to
1792 * reset the Target and retry the probe.
1793 */
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001794 if (cold_reset)
1795 ret = ath10k_pci_cold_reset(ar);
1796 else
1797 ret = ath10k_pci_warm_reset(ar);
1798
Michal Kazior5b2589f2013-11-08 08:01:30 +01001799 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001800 ath10k_err(ar, "failed to reset target: %d\n", ret);
Michal Kazior98563d52013-11-08 08:01:33 +01001801 goto err;
Michal Kazior5b2589f2013-11-08 08:01:30 +01001802 }
Michal Kazior8c5c5362013-07-16 09:38:50 +02001803
Michal Kazior8c5c5362013-07-16 09:38:50 +02001804 ret = ath10k_pci_ce_init(ar);
Michal Kazior8c5c5362013-07-16 09:38:50 +02001805 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001806 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
Michal Kaziorc0c378f2014-08-07 11:03:28 +02001807 goto err;
Michal Kaziorab977bd2013-11-25 14:06:26 +01001808 }
1809
Michal Kazior98563d52013-11-08 08:01:33 +01001810 ret = ath10k_pci_wait_for_target_init(ar);
1811 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001812 ath10k_err(ar, "failed to wait for target to init: %d\n", ret);
Michal Kazior5c771e72014-08-22 14:23:34 +02001813 goto err_ce;
Michal Kazior98563d52013-11-08 08:01:33 +01001814 }
1815
1816 ret = ath10k_pci_init_config(ar);
1817 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001818 ath10k_err(ar, "failed to setup init config: %d\n", ret);
Michal Kazior5c771e72014-08-22 14:23:34 +02001819 goto err_ce;
Michal Kazior98563d52013-11-08 08:01:33 +01001820 }
Michal Kazior8c5c5362013-07-16 09:38:50 +02001821
1822 ret = ath10k_pci_wake_target_cpu(ar);
1823 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001824 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
Michal Kazior5c771e72014-08-22 14:23:34 +02001825 goto err_ce;
Michal Kazior8c5c5362013-07-16 09:38:50 +02001826 }
1827
1828 return 0;
1829
1830err_ce:
1831 ath10k_pci_ce_deinit(ar);
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001832 ath10k_pci_warm_reset(ar);
Michal Kazior8c5c5362013-07-16 09:38:50 +02001833err:
1834 return ret;
1835}
1836
Michal Kazior61c95ce2014-05-14 16:56:16 +03001837static int ath10k_pci_hif_power_up_warm(struct ath10k *ar)
1838{
1839 int i, ret;
1840
1841 /*
1842 * Sometime warm reset succeeds after retries.
1843 *
1844 * FIXME: It might be possible to tune ath10k_pci_warm_reset() to work
1845 * at first try.
1846 */
1847 for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) {
1848 ret = __ath10k_pci_hif_power_up(ar, false);
1849 if (ret == 0)
1850 break;
1851
Michal Kazior7aa7a722014-08-25 12:09:38 +02001852 ath10k_warn(ar, "failed to warm reset (attempt %d out of %d): %d\n",
Michal Kazior61c95ce2014-05-14 16:56:16 +03001853 i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, ret);
1854 }
1855
1856 return ret;
1857}
1858
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001859static int ath10k_pci_hif_power_up(struct ath10k *ar)
1860{
1861 int ret;
1862
Michal Kazior7aa7a722014-08-25 12:09:38 +02001863 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n");
Kalle Valo50f87a62014-03-28 09:32:52 +02001864
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001865 /*
1866 * Hardware CUS232 version 2 has some issues with cold reset and the
1867 * preferred (and safer) way to perform a device reset is through a
1868 * warm reset.
1869 *
Michal Kazior61c95ce2014-05-14 16:56:16 +03001870 * Warm reset doesn't always work though so fall back to cold reset may
1871 * be necessary.
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001872 */
Michal Kazior61c95ce2014-05-14 16:56:16 +03001873 ret = ath10k_pci_hif_power_up_warm(ar);
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001874 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001875 ath10k_warn(ar, "failed to power up target using warm reset: %d\n",
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001876 ret);
1877
Kalle Valo35098462014-03-28 09:32:27 +02001878 if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY)
1879 return ret;
1880
Michal Kazior7aa7a722014-08-25 12:09:38 +02001881 ath10k_warn(ar, "trying cold reset\n");
Kalle Valo35098462014-03-28 09:32:27 +02001882
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001883 ret = __ath10k_pci_hif_power_up(ar, true);
1884 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001885 ath10k_err(ar, "failed to power up target using cold reset too (%d)\n",
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001886 ret);
1887 return ret;
1888 }
1889 }
1890
1891 return 0;
1892}
1893
Michal Kazior8c5c5362013-07-16 09:38:50 +02001894static void ath10k_pci_hif_power_down(struct ath10k *ar)
1895{
Michal Kazior7aa7a722014-08-25 12:09:38 +02001896 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
Bartosz Markowski8cc8df92013-08-02 09:58:49 +02001897
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01001898 ath10k_pci_warm_reset(ar);
Michal Kazior8c5c5362013-07-16 09:38:50 +02001899}
1900
Michal Kazior8cd13ca2013-07-16 09:38:54 +02001901#ifdef CONFIG_PM
1902
1903#define ATH10K_PCI_PM_CONTROL 0x44
1904
1905static int ath10k_pci_hif_suspend(struct ath10k *ar)
1906{
1907 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1908 struct pci_dev *pdev = ar_pci->pdev;
1909 u32 val;
1910
1911 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1912
1913 if ((val & 0x000000ff) != 0x3) {
1914 pci_save_state(pdev);
1915 pci_disable_device(pdev);
1916 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1917 (val & 0xffffff00) | 0x03);
1918 }
1919
1920 return 0;
1921}
1922
1923static int ath10k_pci_hif_resume(struct ath10k *ar)
1924{
1925 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1926 struct pci_dev *pdev = ar_pci->pdev;
1927 u32 val;
1928
1929 pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val);
1930
1931 if ((val & 0x000000ff) != 0) {
1932 pci_restore_state(pdev);
1933 pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL,
1934 val & 0xffffff00);
1935 /*
1936 * Suspend/Resume resets the PCI configuration space,
1937 * so we have to re-disable the RETRY_TIMEOUT register (0x41)
1938 * to keep PCI Tx retries from interfering with C3 CPU state
1939 */
1940 pci_read_config_dword(pdev, 0x40, &val);
1941
1942 if ((val & 0x0000ff00) != 0)
1943 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
1944 }
1945
1946 return 0;
1947}
1948#endif
1949
Kalle Valo5e3dd152013-06-12 20:52:10 +03001950static const struct ath10k_hif_ops ath10k_pci_hif_ops = {
Michal Kazior726346f2014-02-27 18:50:04 +02001951 .tx_sg = ath10k_pci_hif_tx_sg,
Kalle Valoeef25402014-09-24 14:16:52 +03001952 .diag_read = ath10k_pci_hif_diag_read,
Kalle Valo5e3dd152013-06-12 20:52:10 +03001953 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
1954 .start = ath10k_pci_hif_start,
1955 .stop = ath10k_pci_hif_stop,
1956 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
1957 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
1958 .send_complete_check = ath10k_pci_hif_send_complete_check,
Michal Kaziore799bbf2013-07-05 16:15:12 +03001959 .set_callbacks = ath10k_pci_hif_set_callbacks,
Kalle Valo5e3dd152013-06-12 20:52:10 +03001960 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
Michal Kazior8c5c5362013-07-16 09:38:50 +02001961 .power_up = ath10k_pci_hif_power_up,
1962 .power_down = ath10k_pci_hif_power_down,
Michal Kazior8cd13ca2013-07-16 09:38:54 +02001963#ifdef CONFIG_PM
1964 .suspend = ath10k_pci_hif_suspend,
1965 .resume = ath10k_pci_hif_resume,
1966#endif
Kalle Valo5e3dd152013-06-12 20:52:10 +03001967};
1968
1969static void ath10k_pci_ce_tasklet(unsigned long ptr)
1970{
Michal Kazior87263e52013-08-27 13:08:01 +02001971 struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr;
Kalle Valo5e3dd152013-06-12 20:52:10 +03001972 struct ath10k_pci *ar_pci = pipe->ar_pci;
1973
1974 ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num);
1975}
1976
1977static void ath10k_msi_err_tasklet(unsigned long data)
1978{
1979 struct ath10k *ar = (struct ath10k *)data;
1980
Michal Kazior5c771e72014-08-22 14:23:34 +02001981 if (!ath10k_pci_has_fw_crashed(ar)) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02001982 ath10k_warn(ar, "received unsolicited fw crash interrupt\n");
Michal Kazior5c771e72014-08-22 14:23:34 +02001983 return;
1984 }
1985
1986 ath10k_pci_fw_crashed_clear(ar);
1987 ath10k_pci_fw_crashed_dump(ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03001988}
1989
1990/*
1991 * Handler for a per-engine interrupt on a PARTICULAR CE.
1992 * This is used in cases where each CE has a private MSI interrupt.
1993 */
1994static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg)
1995{
1996 struct ath10k *ar = arg;
1997 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
1998 int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL;
1999
Dan Carpentere5742672013-06-18 10:28:46 +03002000 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002001 ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq,
2002 ce_id);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002003 return IRQ_HANDLED;
2004 }
2005
2006 /*
2007 * NOTE: We are able to derive ce_id from irq because we
2008 * use a one-to-one mapping for CE's 0..5.
2009 * CE's 6 & 7 do not use interrupts at all.
2010 *
2011 * This mapping must be kept in sync with the mapping
2012 * used by firmware.
2013 */
2014 tasklet_schedule(&ar_pci->pipe_info[ce_id].intr);
2015 return IRQ_HANDLED;
2016}
2017
2018static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg)
2019{
2020 struct ath10k *ar = arg;
2021 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2022
2023 tasklet_schedule(&ar_pci->msi_fw_err);
2024 return IRQ_HANDLED;
2025}
2026
2027/*
2028 * Top-level interrupt handler for all PCI interrupts from a Target.
2029 * When a block of MSI interrupts is allocated, this top-level handler
2030 * is not used; instead, we directly call the correct sub-handler.
2031 */
2032static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg)
2033{
2034 struct ath10k *ar = arg;
2035 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2036
2037 if (ar_pci->num_msi_intrs == 0) {
Michal Kaziore5398872013-11-25 14:06:20 +01002038 if (!ath10k_pci_irq_pending(ar))
2039 return IRQ_NONE;
2040
Michal Kazior26852182013-11-25 14:06:25 +01002041 ath10k_pci_disable_and_clear_legacy_irq(ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002042 }
2043
2044 tasklet_schedule(&ar_pci->intr_tq);
2045
2046 return IRQ_HANDLED;
2047}
2048
2049static void ath10k_pci_tasklet(unsigned long data)
2050{
2051 struct ath10k *ar = (struct ath10k *)data;
2052 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2053
Michal Kazior5c771e72014-08-22 14:23:34 +02002054 if (ath10k_pci_has_fw_crashed(ar)) {
2055 ath10k_pci_fw_crashed_clear(ar);
2056 ath10k_pci_fw_crashed_dump(ar);
2057 return;
2058 }
2059
Kalle Valo5e3dd152013-06-12 20:52:10 +03002060 ath10k_ce_per_engine_service_any(ar);
2061
Michal Kazior26852182013-11-25 14:06:25 +01002062 /* Re-enable legacy irq that was disabled in the irq handler */
2063 if (ar_pci->num_msi_intrs == 0)
2064 ath10k_pci_enable_legacy_irq(ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002065}
2066
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002067static int ath10k_pci_request_irq_msix(struct ath10k *ar)
Kalle Valo5e3dd152013-06-12 20:52:10 +03002068{
2069 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002070 int ret, i;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002071
2072 ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW,
2073 ath10k_pci_msi_fw_handler,
2074 IRQF_SHARED, "ath10k_pci", ar);
Michal Kazior591ecdb2013-07-31 10:55:15 +02002075 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002076 ath10k_warn(ar, "failed to request MSI-X fw irq %d: %d\n",
Michal Kazior591ecdb2013-07-31 10:55:15 +02002077 ar_pci->pdev->irq + MSI_ASSIGN_FW, ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002078 return ret;
Michal Kazior591ecdb2013-07-31 10:55:15 +02002079 }
Kalle Valo5e3dd152013-06-12 20:52:10 +03002080
2081 for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) {
2082 ret = request_irq(ar_pci->pdev->irq + i,
2083 ath10k_pci_per_engine_handler,
2084 IRQF_SHARED, "ath10k_pci", ar);
2085 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002086 ath10k_warn(ar, "failed to request MSI-X ce irq %d: %d\n",
Kalle Valo5e3dd152013-06-12 20:52:10 +03002087 ar_pci->pdev->irq + i, ret);
2088
Michal Kazior87b14232013-06-26 08:50:50 +02002089 for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--)
2090 free_irq(ar_pci->pdev->irq + i, ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002091
Michal Kazior87b14232013-06-26 08:50:50 +02002092 free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002093 return ret;
2094 }
2095 }
2096
Kalle Valo5e3dd152013-06-12 20:52:10 +03002097 return 0;
2098}
2099
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002100static int ath10k_pci_request_irq_msi(struct ath10k *ar)
Kalle Valo5e3dd152013-06-12 20:52:10 +03002101{
2102 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2103 int ret;
2104
2105 ret = request_irq(ar_pci->pdev->irq,
2106 ath10k_pci_interrupt_handler,
2107 IRQF_SHARED, "ath10k_pci", ar);
Kalle Valof3782742013-10-17 11:36:15 +03002108 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002109 ath10k_warn(ar, "failed to request MSI irq %d: %d\n",
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002110 ar_pci->pdev->irq, ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002111 return ret;
Kalle Valof3782742013-10-17 11:36:15 +03002112 }
Kalle Valo5e3dd152013-06-12 20:52:10 +03002113
Kalle Valo5e3dd152013-06-12 20:52:10 +03002114 return 0;
2115}
2116
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002117static int ath10k_pci_request_irq_legacy(struct ath10k *ar)
Kalle Valo5e3dd152013-06-12 20:52:10 +03002118{
2119 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002120 int ret;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002121
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002122 ret = request_irq(ar_pci->pdev->irq,
2123 ath10k_pci_interrupt_handler,
2124 IRQF_SHARED, "ath10k_pci", ar);
Kalle Valof3782742013-10-17 11:36:15 +03002125 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002126 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002127 ar_pci->pdev->irq, ret);
Kalle Valof3782742013-10-17 11:36:15 +03002128 return ret;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002129 }
2130
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002131 return 0;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002132}
2133
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002134static int ath10k_pci_request_irq(struct ath10k *ar)
2135{
2136 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2137
2138 switch (ar_pci->num_msi_intrs) {
2139 case 0:
2140 return ath10k_pci_request_irq_legacy(ar);
2141 case 1:
2142 return ath10k_pci_request_irq_msi(ar);
2143 case MSI_NUM_REQUEST:
2144 return ath10k_pci_request_irq_msix(ar);
2145 }
2146
Michal Kazior7aa7a722014-08-25 12:09:38 +02002147 ath10k_warn(ar, "unknown irq configuration upon request\n");
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002148 return -EINVAL;
2149}
2150
2151static void ath10k_pci_free_irq(struct ath10k *ar)
Kalle Valo5e3dd152013-06-12 20:52:10 +03002152{
2153 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2154 int i;
2155
2156 /* There's at least one interrupt irregardless whether its legacy INTR
2157 * or MSI or MSI-X */
2158 for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++)
2159 free_irq(ar_pci->pdev->irq + i, ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002160}
2161
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002162static void ath10k_pci_init_irq_tasklets(struct ath10k *ar)
2163{
2164 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2165 int i;
2166
2167 tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar);
2168 tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet,
2169 (unsigned long)ar);
2170
2171 for (i = 0; i < CE_COUNT; i++) {
2172 ar_pci->pipe_info[i].ar_pci = ar_pci;
2173 tasklet_init(&ar_pci->pipe_info[i].intr, ath10k_pci_ce_tasklet,
2174 (unsigned long)&ar_pci->pipe_info[i]);
2175 }
2176}
2177
2178static int ath10k_pci_init_irq(struct ath10k *ar)
2179{
2180 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2181 int ret;
2182
2183 ath10k_pci_init_irq_tasklets(ar);
2184
Michal Kazior403d6272014-08-22 14:23:31 +02002185 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO)
Michal Kazior7aa7a722014-08-25 12:09:38 +02002186 ath10k_info(ar, "limiting irq mode to: %d\n",
2187 ath10k_pci_irq_mode);
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002188
2189 /* Try MSI-X */
Michal Kazior0edf2572014-08-07 11:03:29 +02002190 if (ath10k_pci_irq_mode == ATH10K_PCI_IRQ_AUTO) {
Michal Kaziorcfe9c452013-11-25 14:06:27 +01002191 ar_pci->num_msi_intrs = MSI_NUM_REQUEST;
Alexander Gordeev5ad68672014-02-13 17:50:02 +02002192 ret = pci_enable_msi_range(ar_pci->pdev, ar_pci->num_msi_intrs,
Kalle Valo5b07e072014-09-14 12:50:06 +03002193 ar_pci->num_msi_intrs);
Alexander Gordeev5ad68672014-02-13 17:50:02 +02002194 if (ret > 0)
Michal Kaziorcfe9c452013-11-25 14:06:27 +01002195 return 0;
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002196
Michal Kaziorcfe9c452013-11-25 14:06:27 +01002197 /* fall-through */
2198 }
2199
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002200 /* Try MSI */
Michal Kaziorcfe9c452013-11-25 14:06:27 +01002201 if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) {
2202 ar_pci->num_msi_intrs = 1;
2203 ret = pci_enable_msi(ar_pci->pdev);
2204 if (ret == 0)
2205 return 0;
2206
2207 /* fall-through */
2208 }
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002209
2210 /* Try legacy irq
2211 *
2212 * A potential race occurs here: The CORE_BASE write
2213 * depends on target correctly decoding AXI address but
2214 * host won't know when target writes BAR to CORE_CTRL.
2215 * This write might get lost if target has NOT written BAR.
2216 * For now, fix the race by repeating the write in below
2217 * synchronization checking. */
2218 ar_pci->num_msi_intrs = 0;
2219
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002220 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2221 PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL);
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002222
2223 return 0;
2224}
2225
Michal Kaziorc0c378f2014-08-07 11:03:28 +02002226static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar)
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002227{
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002228 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS,
2229 0);
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002230}
2231
2232static int ath10k_pci_deinit_irq(struct ath10k *ar)
2233{
2234 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2235
2236 switch (ar_pci->num_msi_intrs) {
2237 case 0:
Michal Kaziorc0c378f2014-08-07 11:03:28 +02002238 ath10k_pci_deinit_irq_legacy(ar);
2239 return 0;
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002240 case 1:
2241 /* fall-through */
2242 case MSI_NUM_REQUEST:
2243 pci_disable_msi(ar_pci->pdev);
2244 return 0;
Alexander Gordeevbb8b6212014-02-13 17:50:01 +02002245 default:
2246 pci_disable_msi(ar_pci->pdev);
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002247 }
2248
Michal Kazior7aa7a722014-08-25 12:09:38 +02002249 ath10k_warn(ar, "unknown irq configuration upon deinit\n");
Michal Kaziorfc15ca12013-11-25 14:06:21 +01002250 return -EINVAL;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002251}
2252
Michal Kaziord7fb47f2013-11-08 08:01:26 +01002253static int ath10k_pci_wait_for_target_init(struct ath10k *ar)
Kalle Valo5e3dd152013-06-12 20:52:10 +03002254{
2255 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
Kalle Valo0399eca2014-03-28 09:32:21 +02002256 unsigned long timeout;
Kalle Valo0399eca2014-03-28 09:32:21 +02002257 u32 val;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002258
Michal Kazior7aa7a722014-08-25 12:09:38 +02002259 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03002260
Kalle Valo0399eca2014-03-28 09:32:21 +02002261 timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
2262
2263 do {
2264 val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
2265
Michal Kazior7aa7a722014-08-25 12:09:38 +02002266 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n",
2267 val);
Kalle Valo50f87a62014-03-28 09:32:52 +02002268
Kalle Valo0399eca2014-03-28 09:32:21 +02002269 /* target should never return this */
2270 if (val == 0xffffffff)
2271 continue;
2272
Michal Kazior7710cd22014-04-23 19:30:04 +03002273 /* the device has crashed so don't bother trying anymore */
2274 if (val & FW_IND_EVENT_PENDING)
2275 break;
2276
Kalle Valo0399eca2014-03-28 09:32:21 +02002277 if (val & FW_IND_INITIALIZED)
2278 break;
2279
Kalle Valo5e3dd152013-06-12 20:52:10 +03002280 if (ar_pci->num_msi_intrs == 0)
2281 /* Fix potential race by repeating CORE_BASE writes */
Michal Kaziorc947a9e2014-08-22 14:23:30 +02002282 ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS +
2283 PCIE_INTR_ENABLE_ADDRESS,
2284 PCIE_INTR_FIRMWARE_MASK |
2285 PCIE_INTR_CE_MASK_ALL);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002286
Kalle Valo0399eca2014-03-28 09:32:21 +02002287 mdelay(10);
2288 } while (time_before(jiffies, timeout));
2289
Michal Kazior6a4f6e12014-04-23 19:30:03 +03002290 if (val == 0xffffffff) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002291 ath10k_err(ar, "failed to read device register, device is gone\n");
Michal Kaziorc0c378f2014-08-07 11:03:28 +02002292 return -EIO;
Michal Kazior6a4f6e12014-04-23 19:30:03 +03002293 }
2294
Michal Kazior7710cd22014-04-23 19:30:04 +03002295 if (val & FW_IND_EVENT_PENDING) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002296 ath10k_warn(ar, "device has crashed during init\n");
Michal Kazior5c771e72014-08-22 14:23:34 +02002297 ath10k_pci_fw_crashed_clear(ar);
Kalle Valo0e9848c2014-08-25 08:37:37 +03002298 ath10k_pci_fw_crashed_dump(ar);
Michal Kaziorc0c378f2014-08-07 11:03:28 +02002299 return -ECOMM;
Michal Kazior7710cd22014-04-23 19:30:04 +03002300 }
2301
Michal Kazior6a4f6e12014-04-23 19:30:03 +03002302 if (!(val & FW_IND_INITIALIZED)) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002303 ath10k_err(ar, "failed to receive initialized event from target: %08x\n",
Kalle Valo0399eca2014-03-28 09:32:21 +02002304 val);
Michal Kaziorc0c378f2014-08-07 11:03:28 +02002305 return -ETIMEDOUT;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002306 }
2307
Michal Kazior7aa7a722014-08-25 12:09:38 +02002308 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n");
Michal Kaziorc0c378f2014-08-07 11:03:28 +02002309 return 0;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002310}
2311
Michal Kaziorfc36e3f2014-02-10 17:14:22 +01002312static int ath10k_pci_cold_reset(struct ath10k *ar)
Kalle Valo5e3dd152013-06-12 20:52:10 +03002313{
Michal Kaziorc0c378f2014-08-07 11:03:28 +02002314 int i;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002315 u32 val;
2316
Michal Kazior7aa7a722014-08-25 12:09:38 +02002317 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03002318
Ben Greearf51dbe72014-09-29 14:41:46 +03002319 spin_lock_bh(&ar->data_lock);
2320
2321 ar->stats.fw_cold_reset_counter++;
2322
2323 spin_unlock_bh(&ar->data_lock);
2324
Kalle Valo5e3dd152013-06-12 20:52:10 +03002325 /* Put Target, including PCIe, into RESET. */
Kalle Valoe479ed42013-09-01 10:01:53 +03002326 val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002327 val |= 1;
Kalle Valoe479ed42013-09-01 10:01:53 +03002328 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002329
2330 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
Kalle Valoe479ed42013-09-01 10:01:53 +03002331 if (ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
Kalle Valo5e3dd152013-06-12 20:52:10 +03002332 RTC_STATE_COLD_RESET_MASK)
2333 break;
2334 msleep(1);
2335 }
2336
2337 /* Pull Target, including PCIe, out of RESET. */
2338 val &= ~1;
Kalle Valoe479ed42013-09-01 10:01:53 +03002339 ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002340
2341 for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
Kalle Valoe479ed42013-09-01 10:01:53 +03002342 if (!(ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
Kalle Valo5e3dd152013-06-12 20:52:10 +03002343 RTC_STATE_COLD_RESET_MASK))
2344 break;
2345 msleep(1);
2346 }
2347
Michal Kazior7aa7a722014-08-25 12:09:38 +02002348 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
Kalle Valo50f87a62014-03-28 09:32:52 +02002349
Michal Kazior5b2589f2013-11-08 08:01:30 +01002350 return 0;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002351}
2352
Michal Kazior2986e3e2014-08-07 11:03:30 +02002353static int ath10k_pci_claim(struct ath10k *ar)
Kalle Valo5e3dd152013-06-12 20:52:10 +03002354{
Michal Kazior2986e3e2014-08-07 11:03:30 +02002355 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2356 struct pci_dev *pdev = ar_pci->pdev;
2357 u32 lcr_val;
2358 int ret;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002359
2360 pci_set_drvdata(pdev, ar);
2361
Kalle Valo5e3dd152013-06-12 20:52:10 +03002362 ret = pci_enable_device(pdev);
2363 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002364 ath10k_err(ar, "failed to enable pci device: %d\n", ret);
Michal Kazior2986e3e2014-08-07 11:03:30 +02002365 return ret;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002366 }
2367
Kalle Valo5e3dd152013-06-12 20:52:10 +03002368 ret = pci_request_region(pdev, BAR_NUM, "ath");
2369 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002370 ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM,
Michal Kazior2986e3e2014-08-07 11:03:30 +02002371 ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002372 goto err_device;
2373 }
2374
Michal Kazior2986e3e2014-08-07 11:03:30 +02002375 /* Target expects 32 bit DMA. Enforce it. */
Kalle Valo5e3dd152013-06-12 20:52:10 +03002376 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2377 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002378 ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002379 goto err_region;
2380 }
2381
2382 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2383 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002384 ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n",
Michal Kazior2986e3e2014-08-07 11:03:30 +02002385 ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002386 goto err_region;
2387 }
2388
Kalle Valo5e3dd152013-06-12 20:52:10 +03002389 pci_set_master(pdev);
2390
Michal Kazior2986e3e2014-08-07 11:03:30 +02002391 /* Workaround: Disable ASPM */
Kalle Valo5e3dd152013-06-12 20:52:10 +03002392 pci_read_config_dword(pdev, 0x80, &lcr_val);
2393 pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00));
2394
2395 /* Arrange for access to Target SoC registers. */
Michal Kazior2986e3e2014-08-07 11:03:30 +02002396 ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0);
2397 if (!ar_pci->mem) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002398 ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002399 ret = -EIO;
2400 goto err_master;
2401 }
2402
Michal Kazior7aa7a722014-08-25 12:09:38 +02002403 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem);
Michal Kazior2986e3e2014-08-07 11:03:30 +02002404 return 0;
2405
2406err_master:
2407 pci_clear_master(pdev);
2408
2409err_region:
2410 pci_release_region(pdev, BAR_NUM);
2411
2412err_device:
2413 pci_disable_device(pdev);
2414
2415 return ret;
2416}
2417
2418static void ath10k_pci_release(struct ath10k *ar)
2419{
2420 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
2421 struct pci_dev *pdev = ar_pci->pdev;
2422
2423 pci_iounmap(pdev, ar_pci->mem);
2424 pci_release_region(pdev, BAR_NUM);
2425 pci_clear_master(pdev);
2426 pci_disable_device(pdev);
2427}
2428
Kalle Valo5e3dd152013-06-12 20:52:10 +03002429static int ath10k_pci_probe(struct pci_dev *pdev,
2430 const struct pci_device_id *pci_dev)
2431{
Kalle Valo5e3dd152013-06-12 20:52:10 +03002432 int ret = 0;
2433 struct ath10k *ar;
2434 struct ath10k_pci *ar_pci;
Michal Kazior2986e3e2014-08-07 11:03:30 +02002435 u32 chip_id;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002436
Michal Kaziore7b54192014-08-07 11:03:27 +02002437 ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev,
2438 &ath10k_pci_hif_ops);
2439 if (!ar) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002440 dev_err(&pdev->dev, "failed to allocate core\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03002441 return -ENOMEM;
Michal Kaziore7b54192014-08-07 11:03:27 +02002442 }
Kalle Valo5e3dd152013-06-12 20:52:10 +03002443
Michal Kazior7aa7a722014-08-25 12:09:38 +02002444 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci probe\n");
2445
Michal Kaziore7b54192014-08-07 11:03:27 +02002446 ar_pci = ath10k_pci_priv(ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002447 ar_pci->pdev = pdev;
2448 ar_pci->dev = &pdev->dev;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002449 ar_pci->ar = ar;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002450
2451 spin_lock_init(&ar_pci->ce_lock);
Michal Kazior728f95e2014-08-22 14:33:14 +02002452 setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry,
2453 (unsigned long)ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002454
Michal Kazior2986e3e2014-08-07 11:03:30 +02002455 ret = ath10k_pci_claim(ar);
Kalle Valoe01ae682013-09-01 11:22:14 +03002456 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002457 ath10k_err(ar, "failed to claim device: %d\n", ret);
Michal Kaziore7b54192014-08-07 11:03:27 +02002458 goto err_core_destroy;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002459 }
2460
Michal Kaziorc0c378f2014-08-07 11:03:28 +02002461 ret = ath10k_pci_wake(ar);
Kalle Valoe01ae682013-09-01 11:22:14 +03002462 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002463 ath10k_err(ar, "failed to wake up: %d\n", ret);
Michal Kazior2986e3e2014-08-07 11:03:30 +02002464 goto err_release;
Kalle Valoe01ae682013-09-01 11:22:14 +03002465 }
2466
Kalle Valo233eb972013-10-16 16:46:11 +03002467 chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
Michal Kaziorc0c378f2014-08-07 11:03:28 +02002468 if (chip_id == 0xffffffff) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002469 ath10k_err(ar, "failed to get chip id\n");
Michal Kaziorc0c378f2014-08-07 11:03:28 +02002470 goto err_sleep;
2471 }
Kalle Valoe01ae682013-09-01 11:22:14 +03002472
Michal Kazior25d0dbc2014-03-28 10:02:38 +02002473 ret = ath10k_pci_alloc_ce(ar);
2474 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002475 ath10k_err(ar, "failed to allocate copy engine pipes: %d\n",
2476 ret);
Michal Kaziorc0c378f2014-08-07 11:03:28 +02002477 goto err_sleep;
Michal Kazior25d0dbc2014-03-28 10:02:38 +02002478 }
2479
Michal Kazior403d6272014-08-22 14:23:31 +02002480 ath10k_pci_ce_deinit(ar);
2481
2482 ret = ath10k_ce_disable_interrupts(ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002483 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002484 ath10k_err(ar, "failed to disable copy engine interrupts: %d\n",
Michal Kazior403d6272014-08-22 14:23:31 +02002485 ret);
Michal Kazior25d0dbc2014-03-28 10:02:38 +02002486 goto err_free_ce;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002487 }
2488
Michal Kazior5c771e72014-08-22 14:23:34 +02002489 /* Workaround: There's no known way to mask all possible interrupts via
2490 * device CSR. The only way to make sure device doesn't assert
2491 * interrupts is to reset it. Interrupts are then disabled on host
2492 * after handlers are registered.
2493 */
2494 ath10k_pci_warm_reset(ar);
2495
Michal Kazior403d6272014-08-22 14:23:31 +02002496 ret = ath10k_pci_init_irq(ar);
2497 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002498 ath10k_err(ar, "failed to init irqs: %d\n", ret);
Michal Kazior403d6272014-08-22 14:23:31 +02002499 goto err_free_ce;
2500 }
2501
Michal Kazior7aa7a722014-08-25 12:09:38 +02002502 ath10k_info(ar, "pci irq %s interrupts %d irq_mode %d reset_mode %d\n",
Michal Kazior403d6272014-08-22 14:23:31 +02002503 ath10k_pci_get_irq_method(ar), ar_pci->num_msi_intrs,
2504 ath10k_pci_irq_mode, ath10k_pci_reset_mode);
2505
Michal Kazior5c771e72014-08-22 14:23:34 +02002506 ret = ath10k_pci_request_irq(ar);
Michal Kazior403d6272014-08-22 14:23:31 +02002507 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002508 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
Michal Kazior403d6272014-08-22 14:23:31 +02002509 goto err_deinit_irq;
2510 }
2511
Michal Kazior5c771e72014-08-22 14:23:34 +02002512 /* This shouldn't race as the device has been reset above. */
2513 ath10k_pci_irq_disable(ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002514
2515 ret = ath10k_core_register(ar, chip_id);
2516 if (ret) {
Michal Kazior7aa7a722014-08-25 12:09:38 +02002517 ath10k_err(ar, "failed to register driver core: %d\n", ret);
Michal Kazior5c771e72014-08-22 14:23:34 +02002518 goto err_free_irq;
Kalle Valo5e3dd152013-06-12 20:52:10 +03002519 }
2520
2521 return 0;
2522
Michal Kazior5c771e72014-08-22 14:23:34 +02002523err_free_irq:
2524 ath10k_pci_free_irq(ar);
Michal Kazior21396272014-08-28 10:24:40 +02002525 ath10k_pci_kill_tasklet(ar);
Michal Kazior5c771e72014-08-22 14:23:34 +02002526
Michal Kazior403d6272014-08-22 14:23:31 +02002527err_deinit_irq:
2528 ath10k_pci_deinit_irq(ar);
2529
Michal Kazior25d0dbc2014-03-28 10:02:38 +02002530err_free_ce:
2531 ath10k_pci_free_ce(ar);
Michal Kazior2986e3e2014-08-07 11:03:30 +02002532
Michal Kaziorc0c378f2014-08-07 11:03:28 +02002533err_sleep:
2534 ath10k_pci_sleep(ar);
Michal Kazior2986e3e2014-08-07 11:03:30 +02002535
2536err_release:
2537 ath10k_pci_release(ar);
2538
Michal Kaziore7b54192014-08-07 11:03:27 +02002539err_core_destroy:
Kalle Valo5e3dd152013-06-12 20:52:10 +03002540 ath10k_core_destroy(ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002541
2542 return ret;
2543}
2544
2545static void ath10k_pci_remove(struct pci_dev *pdev)
2546{
2547 struct ath10k *ar = pci_get_drvdata(pdev);
2548 struct ath10k_pci *ar_pci;
2549
Michal Kazior7aa7a722014-08-25 12:09:38 +02002550 ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n");
Kalle Valo5e3dd152013-06-12 20:52:10 +03002551
2552 if (!ar)
2553 return;
2554
2555 ar_pci = ath10k_pci_priv(ar);
2556
2557 if (!ar_pci)
2558 return;
2559
Kalle Valo5e3dd152013-06-12 20:52:10 +03002560 ath10k_core_unregister(ar);
Michal Kazior5c771e72014-08-22 14:23:34 +02002561 ath10k_pci_free_irq(ar);
Michal Kazior21396272014-08-28 10:24:40 +02002562 ath10k_pci_kill_tasklet(ar);
Michal Kazior403d6272014-08-22 14:23:31 +02002563 ath10k_pci_deinit_irq(ar);
2564 ath10k_pci_ce_deinit(ar);
Michal Kazior25d0dbc2014-03-28 10:02:38 +02002565 ath10k_pci_free_ce(ar);
Michal Kaziorc0c378f2014-08-07 11:03:28 +02002566 ath10k_pci_sleep(ar);
Michal Kazior2986e3e2014-08-07 11:03:30 +02002567 ath10k_pci_release(ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002568 ath10k_core_destroy(ar);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002569}
2570
Kalle Valo5e3dd152013-06-12 20:52:10 +03002571MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table);
2572
2573static struct pci_driver ath10k_pci_driver = {
2574 .name = "ath10k_pci",
2575 .id_table = ath10k_pci_id_table,
2576 .probe = ath10k_pci_probe,
2577 .remove = ath10k_pci_remove,
Kalle Valo5e3dd152013-06-12 20:52:10 +03002578};
2579
2580static int __init ath10k_pci_init(void)
2581{
2582 int ret;
2583
2584 ret = pci_register_driver(&ath10k_pci_driver);
2585 if (ret)
Michal Kazior7aa7a722014-08-25 12:09:38 +02002586 printk(KERN_ERR "failed to register ath10k pci driver: %d\n",
2587 ret);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002588
2589 return ret;
2590}
2591module_init(ath10k_pci_init);
2592
2593static void __exit ath10k_pci_exit(void)
2594{
2595 pci_unregister_driver(&ath10k_pci_driver);
2596}
2597
2598module_exit(ath10k_pci_exit);
2599
2600MODULE_AUTHOR("Qualcomm Atheros");
2601MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices");
2602MODULE_LICENSE("Dual BSD/GPL");
Bartosz Markowski8026cae2014-10-06 14:16:41 +02002603MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_FILE);
2604MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE);
2605MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE);
Kalle Valo5e3dd152013-06-12 20:52:10 +03002606MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE);