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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 46f0537b1ecf672052007c97f102a7e6bf0791e4 / . / drivers / irqchip / Kconfig
blob: 595d0c95563b08c14983d38d117422c4b7b50ba6 [file] [log] [blame]
Thomas Petazzonif6e916b2012-11-20 23:00:52 +0100[diff] [blame]1config IRQCHIP
2 def_bool y
3 depends on OF_IRQ
4
Rob Herring81243e42012-11-20 21:21:40 -0600[diff] [blame]5config ARM_GIC
6 bool
7 select IRQ_DOMAIN
Yingjoe Chen9a1091e2014-11-25 16:04:19 +0800[diff] [blame]8 select IRQ_DOMAIN_HIERARCHY
Rob Herring81243e42012-11-20 21:21:40 -0600[diff] [blame]9 select MULTI_IRQ_HANDLER
10
Jon Hunter9c8eddd2016-06-07 16:12:34 +0100[diff] [blame]11config ARM_GIC_PM
12 bool
13 depends on PM
14 select ARM_GIC
15 select PM_CLK
16
Linus Walleija27d21e2015-12-18 10:44:53 +0100[diff] [blame]17config ARM_GIC_MAX_NR
18 int
19 default 2 if ARCH_REALVIEW
20 default 1
21
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +0000[diff] [blame]22config ARM_GIC_V2M
23 bool
Arnd Bergmann3ee803642016-06-15 15:47:33 -0500[diff] [blame]24 depends on PCI
25 select ARM_GIC
26 select PCI_MSI
Suravee Suthikulpanit853a33c2014-11-25 18:47:22 +0000[diff] [blame]27
Rob Herring81243e42012-11-20 21:21:40 -0600[diff] [blame]28config GIC_NON_BANKED
29 bool
30
Marc Zyngier021f6532014-06-30 16:01:31 +0100[diff] [blame]31config ARM_GIC_V3
32 bool
33 select IRQ_DOMAIN
34 select MULTI_IRQ_HANDLER
Marc Zyngier443acc42014-11-24 14:35:09 +0000[diff] [blame]35 select IRQ_DOMAIN_HIERARCHY
Marc Zyngiere3825ba2016-04-11 09:57:54 +0100[diff] [blame]36 select PARTITION_PERCPU
Marc Zyngier021f6532014-06-30 16:01:31 +0100[diff] [blame]37
Marc Zyngier19812722014-11-24 14:35:19 +0000[diff] [blame]38config ARM_GIC_V3_ITS
39 bool
Arnd Bergmann3ee803642016-06-15 15:47:33 -0500[diff] [blame]40 depends on PCI
41 depends on PCI_MSI
Tomasz Nowicki3f010cf2016-09-12 20:32:25 +0200[diff] [blame]42 select ACPI_IORT if ACPI
Uwe Kleine-König292ec082013-06-26 09:18:48 +0200[diff] [blame]43
Rob Herring44430ec2012-10-27 17:25:26 -0500[diff] [blame]44config ARM_NVIC
45 bool
46 select IRQ_DOMAIN
Stefan Agner2d9f59f2015-05-16 11:44:16 +0200[diff] [blame]47 select IRQ_DOMAIN_HIERARCHY
Rob Herring44430ec2012-10-27 17:25:26 -0500[diff] [blame]48 select GENERIC_IRQ_CHIP
49
50config ARM_VIC
51 bool
52 select IRQ_DOMAIN
53 select MULTI_IRQ_HANDLER
54
55config ARM_VIC_NR
56 int
57 default 4 if ARCH_S5PV210
Rob Herring44430ec2012-10-27 17:25:26 -0500[diff] [blame]58 default 2
59 depends on ARM_VIC
60 help
61 The maximum number of VICs available in the system, for
62 power management.
63
Thomas Petazzonifed6d332016-02-10 15:46:56 +0100[diff] [blame]64config ARMADA_370_XP_IRQ
65 bool
Thomas Petazzonifed6d332016-02-10 15:46:56 +0100[diff] [blame]66 select GENERIC_IRQ_CHIP
Arnd Bergmann3ee803642016-06-15 15:47:33 -0500[diff] [blame]67 select PCI_MSI if PCI
Thomas Petazzonifed6d332016-02-10 15:46:56 +0100[diff] [blame]68
Antoine Tenarte6b78f22016-02-19 16:22:44 +0100[diff] [blame]69config ALPINE_MSI
70 bool
Arnd Bergmann3ee803642016-06-15 15:47:33 -0500[diff] [blame]71 depends on PCI
72 select PCI_MSI
Antoine Tenarte6b78f22016-02-19 16:22:44 +0100[diff] [blame]73 select GENERIC_IRQ_CHIP
Antoine Tenarte6b78f22016-02-19 16:22:44 +0100[diff] [blame]74
Boris BREZILLONb1479eb2014-07-10 19:14:18 +0200[diff] [blame]75config ATMEL_AIC_IRQ
76 bool
77 select GENERIC_IRQ_CHIP
78 select IRQ_DOMAIN
79 select MULTI_IRQ_HANDLER
80 select SPARSE_IRQ
81
82config ATMEL_AIC5_IRQ
83 bool
84 select GENERIC_IRQ_CHIP
85 select IRQ_DOMAIN
86 select MULTI_IRQ_HANDLER
87 select SPARSE_IRQ
88
Ralf Baechle0509cfd2015-07-08 14:46:08 +0200[diff] [blame]89config I8259
90 bool
91 select IRQ_DOMAIN
92
Simon Arlottc7c42ec2015-11-22 14:30:14 +0000[diff] [blame]93config BCM6345_L1_IRQ
94 bool
95 select GENERIC_IRQ_CHIP
96 select IRQ_DOMAIN
97
Kevin Cernekee5f7f0312014-12-25 09:49:06 -0800[diff] [blame]98config BCM7038_L1_IRQ
99 bool
100 select GENERIC_IRQ_CHIP
101 select IRQ_DOMAIN
102
Kevin Cernekeea4fcbb82014-11-06 22:44:27 -0800[diff] [blame]103config BCM7120_L2_IRQ
104 bool
105 select GENERIC_IRQ_CHIP
106 select IRQ_DOMAIN
107
Florian Fainelli7f646e92014-05-23 17:40:53 -0700[diff] [blame]108config BRCMSTB_L2_IRQ
109 bool
Florian Fainelli7f646e92014-05-23 17:40:53 -0700[diff] [blame]110 select GENERIC_IRQ_CHIP
111 select IRQ_DOMAIN
112
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200[diff] [blame]113config DW_APB_ICTL
114 bool
Jisheng Zhange1588492014-10-22 20:59:10 +0800[diff] [blame]115 select GENERIC_IRQ_CHIP
Sebastian Hesselbarth350d71b92013-09-09 14:01:20 +0200[diff] [blame]116 select IRQ_DOMAIN
117
Linus Walleij6ee532e2017-03-18 17:53:24 +0100[diff] [blame]118config FARADAY_FTINTC010
119 bool
120 select IRQ_DOMAIN
121 select MULTI_IRQ_HANDLER
122 select SPARSE_IRQ
123
MaJun9a7c4ab2016-03-23 17:06:33 +0800[diff] [blame]124config HISILICON_IRQ_MBIGEN
125 bool
126 select ARM_GIC_V3
127 select ARM_GIC_V3_ITS
MaJun9a7c4ab2016-03-23 17:06:33 +0800[diff] [blame]128
James Hoganb6ef9162013-04-22 15:43:50 +0100[diff] [blame]129config IMGPDC_IRQ
130 bool
131 select GENERIC_IRQ_CHIP
132 select IRQ_DOMAIN
133
Ralf Baechle67e38cf2015-05-26 18:20:06 +0200[diff] [blame]134config IRQ_MIPS_CPU
135 bool
136 select GENERIC_IRQ_CHIP
137 select IRQ_DOMAIN
138
Alexander Shiyanafc98d92014-02-02 12:07:46 +0400[diff] [blame]139config CLPS711X_IRQCHIP
140 bool
141 depends on ARCH_CLPS711X
142 select IRQ_DOMAIN
143 select MULTI_IRQ_HANDLER
144 select SPARSE_IRQ
145 default y
146
Stefan Kristiansson4db8e6d2014-05-26 23:31:42 +0300[diff] [blame]147config OR1K_PIC
148 bool
149 select IRQ_DOMAIN
150
Felipe Balbi85980662014-09-15 16:15:02 -0500[diff] [blame]151config OMAP_IRQCHIP
152 bool
153 select GENERIC_IRQ_CHIP
154 select IRQ_DOMAIN
155
Sebastian Hesselbarth9dbd90f2013-06-06 18:27:09 +0200[diff] [blame]156config ORION_IRQCHIP
157 bool
158 select IRQ_DOMAIN
159 select MULTI_IRQ_HANDLER
160
Cristian Birsanaaa86662016-01-13 18:15:35 -0700[diff] [blame]161config PIC32_EVIC
162 bool
163 select GENERIC_IRQ_CHIP
164 select IRQ_DOMAIN
165
Rich Felker981b58f2016-08-04 04:30:37 +0000[diff] [blame]166config JCORE_AIC
Rich Felker3602ffd2016-10-19 17:53:52 +0000[diff] [blame]167 bool "J-Core integrated AIC" if COMPILE_TEST
168 depends on OF
Rich Felker981b58f2016-08-04 04:30:37 +0000[diff] [blame]169 select IRQ_DOMAIN
170 help
171 Support for the J-Core integrated AIC.
172
Magnus Damm44358042013-02-18 23:28:34 +0900[diff] [blame]173config RENESAS_INTC_IRQPIN
174 bool
175 select IRQ_DOMAIN
176
Magnus Dammfbc83b72013-02-27 17:15:01 +0900[diff] [blame]177config RENESAS_IRQC
178 bool
Magnus Damm99c221d2015-09-28 18:42:37 +0900[diff] [blame]179 select GENERIC_IRQ_CHIP
Magnus Dammfbc83b72013-02-27 17:15:01 +0900[diff] [blame]180 select IRQ_DOMAIN
181
Lee Jones07088482015-02-18 15:13:58 +0000[diff] [blame]182config ST_IRQCHIP
183 bool
184 select REGMAP
185 select MFD_SYSCON
186 help
187 Enables SysCfg Controlled IRQs on STi based platforms.
188
Mans Rullgard4bba6682016-01-20 18:07:17 +0000[diff] [blame]189config TANGO_IRQ
190 bool
191 select IRQ_DOMAIN
192 select GENERIC_IRQ_CHIP
193
Christian Ruppertb06eb012013-06-25 18:29:57 +0200[diff] [blame]194config TB10X_IRQC
195 bool
196 select IRQ_DOMAIN
197 select GENERIC_IRQ_CHIP
198
Damien Riegeld01f8632015-12-21 15:11:23 -0500[diff] [blame]199config TS4800_IRQ
200 tristate "TS-4800 IRQ controller"
201 select IRQ_DOMAIN
Richard Weinberger0df337c2016-01-25 23:24:17 +0100[diff] [blame]202 depends on HAS_IOMEM
Jean Delvared2b383d2016-02-09 11:19:20 +0100[diff] [blame]203 depends on SOC_IMX51 || COMPILE_TEST
Damien Riegeld01f8632015-12-21 15:11:23 -0500[diff] [blame]204 help
205 Support for the TS-4800 FPGA IRQ controller
206
Linus Walleij2389d502012-10-31 22:04:31 +0100[diff] [blame]207config VERSATILE_FPGA_IRQ
208 bool
209 select IRQ_DOMAIN
210
211config VERSATILE_FPGA_IRQ_NR
212 int
213 default 4
214 depends on VERSATILE_FPGA_IRQ
Max Filippov26a8e962013-12-01 12:04:57 +0400[diff] [blame]215
216config XTENSA_MX
217 bool
218 select IRQ_DOMAIN
Sricharan R96ca8482013-12-03 15:57:23 +0530[diff] [blame]219
Zubair Lutfullah Kakakhel0547dc72016-11-14 12:13:45 +0000[diff] [blame]220config XILINX_INTC
221 bool
222 select IRQ_DOMAIN
223
Sricharan R96ca8482013-12-03 15:57:23 +0530[diff] [blame]224config IRQ_CROSSBAR
225 bool
226 help
Masanari Iidaf54619f2014-09-18 12:09:42 +0900[diff] [blame]227 Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R96ca8482013-12-03 15:57:23 +0530[diff] [blame]228 The primary irqchip invokes the crossbar's callback which inturn allocates
229 a free irq and configures the IP. Thus the peripheral interrupts are
230 routed to one of the free irqchip interrupt lines.
Grygorii Strashko89323f82014-07-23 17:40:30 +0300[diff] [blame]231
232config KEYSTONE_IRQ
233 tristate "Keystone 2 IRQ controller IP"
234 depends on ARCH_KEYSTONE
235 help
236 Support for Texas Instruments Keystone 2 IRQ controller IP which
237 is part of the Keystone 2 IPC mechanism
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700[diff] [blame]238
239config MIPS_GIC
240 bool
Qais Yousefbb11cff2015-12-08 13:20:28 +0000[diff] [blame]241 select GENERIC_IRQ_IPI
Qais Yousef2af70a92015-12-08 13:20:23 +0000[diff] [blame]242 select IRQ_DOMAIN_HIERARCHY
Andrew Bresticker8a19b8f2014-09-18 14:47:19 -0700[diff] [blame]243 select MIPS_CM
Yoshinori Sato8a764482015-05-10 02:30:47 +0900[diff] [blame]244
Paul Burton44e08e72015-05-24 16:11:31 +0100[diff] [blame]245config INGENIC_IRQ
246 bool
247 depends on MACH_INGENIC
248 default y
Linus Torvalds78c10e52015-06-27 12:44:34 -0700[diff] [blame]249
Yoshinori Sato8a764482015-05-10 02:30:47 +0900[diff] [blame]250config RENESAS_H8300H_INTC
251 bool
252 select IRQ_DOMAIN
253
254config RENESAS_H8S_INTC
255 bool
Linus Torvalds78c10e52015-06-27 12:44:34 -0700[diff] [blame]256 select IRQ_DOMAIN
Shenwei Wange324c4d2015-08-24 14:04:15 -0500[diff] [blame]257
258config IMX_GPCV2
259 bool
260 select IRQ_DOMAIN
261 help
262 Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel7e4ac672015-10-12 21:15:34 +0200[diff] [blame]263
264config IRQ_MXS
265 def_bool y if MACH_ASM9260 || ARCH_MXS
266 select IRQ_DOMAIN
267 select STMP_DEVICE
Thomas Petazzonic27f29b2016-02-19 14:34:43 +0100[diff] [blame]268
269config MVEBU_ODMI
270 bool
Arnd Bergmannfa23b9d2017-03-14 13:54:12 +0100[diff] [blame]271 select GENERIC_MSI_IRQ_DOMAIN
Marc Zyngier9e2c9862016-04-11 09:57:53 +0100[diff] [blame]272
Thomas Petazzonia1098932016-08-05 16:55:19 +0200[diff] [blame]273config MVEBU_PIC
274 bool
275
Minghuan Lianb8f3ebe2016-03-23 19:08:20 +0800[diff] [blame]276config LS_SCFG_MSI
277 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
278 depends on PCI && PCI_MSI
Minghuan Lianb8f3ebe2016-03-23 19:08:20 +0800[diff] [blame]279
Marc Zyngier9e2c9862016-04-11 09:57:53 +0100[diff] [blame]280config PARTITION_PERCPU
281 bool
Linus Torvalds0efacbb2016-05-19 09:46:18 -0700[diff] [blame]282
Noam Camus44df427c2015-10-29 00:26:22 +0200[diff] [blame]283config EZNPS_GIC
284 bool "NPS400 Global Interrupt Manager (GIM)"
Arnd Bergmannffd565e2016-05-12 23:03:35 +0200[diff] [blame]285 depends on ARC || (COMPILE_TEST && !64BIT)
Noam Camus44df427c2015-10-29 00:26:22 +0200[diff] [blame]286 select IRQ_DOMAIN
287 help
288 Support the EZchip NPS400 global interrupt controller
Alexandre TORGUEe07204162016-09-20 18:00:57 +0200[diff] [blame]289
290config STM32_EXTI
291 bool
292 select IRQ_DOMAIN
Agustin Vega-Friasf20cc9b2017-02-02 18:23:59 -0500[diff] [blame]293
294config QCOM_IRQ_COMBINER
295 bool "QCOM IRQ combiner support"
296 depends on ARCH_QCOM && ACPI
297 select IRQ_DOMAIN
298 select IRQ_DOMAIN_HIERARCHY
299 help
300 Say yes here to add support for the IRQ combiner devices embedded
301 in Qualcomm Technologies chips.