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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 26dc638ae6e32bddfb8d3da0fc93946955c28c78 / . / arch / powerpc / platforms / powernv / pci.h
blob: 7dee25e304db2cbe1faedfe3329754605e678beb [file] [log] [blame]
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]1#ifndef __POWERNV_PCI_H
2#define __POWERNV_PCI_H
3
4struct pci_dn;
5
6enum pnv_phb_type {
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]7 PNV_PHB_IODA1 = 0,
8 PNV_PHB_IODA2 = 1,
9 PNV_PHB_NPU = 2,
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]10};
11
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]12/* Precise PHB model for error management */
13enum pnv_phb_model {
14 PNV_PHB_MODEL_UNKNOWN,
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]15 PNV_PHB_MODEL_P7IOC,
Gavin Shanaa0c0332013-04-25 19:20:57 +0000[diff] [blame]16 PNV_PHB_MODEL_PHB3,
Alistair Popple5d2aa712015-12-17 13:43:13 +1100[diff] [blame]17 PNV_PHB_MODEL_NPU,
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]18};
19
Gavin Shan5c9d6d72013-09-06 09:00:03 +0800[diff] [blame]20#define PNV_PCI_DIAG_BUF_SIZE 8192
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]21#define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
22#define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
23#define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]24#define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
25#define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
Wei Yang781a8682015-03-25 16:23:57 +0800[diff] [blame]26#define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]27
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]28/* Data associated with a PE, including IOMMU tracking etc.. */
Gavin Shan4cce9552013-04-25 19:21:00 +0000[diff] [blame]29struct pnv_phb;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]30struct pnv_ioda_pe {
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]31 unsigned long flags;
Gavin Shan4cce9552013-04-25 19:21:00 +0000[diff] [blame]32 struct pnv_phb *phb;
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]33
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]34 /* A PE can be associated with a single device or an
35 * entire bus (& children). In the former case, pdev
36 * is populated, in the later case, pbus is.
37 */
Wei Yang781a8682015-03-25 16:23:57 +0800[diff] [blame]38#ifdef CONFIG_PCI_IOV
39 struct pci_dev *parent_dev;
40#endif
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]41 struct pci_dev *pdev;
42 struct pci_bus *pbus;
43
44 /* Effective RID (device RID for a device PE and base bus
45 * RID with devfn 0 for a bus PE)
46 */
47 unsigned int rid;
48
49 /* PE number */
50 unsigned int pe_number;
51
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]52 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
Alexey Kardashevskiyb348aa62015-06-05 16:35:08 +1000[diff] [blame]53 struct iommu_table_group table_group;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]54
Benjamin Herrenschmidtcd15b042014-02-11 11:32:38 +1100[diff] [blame]55 /* 64-bit TCE bypass region */
56 bool tce_bypass_enabled;
57 uint64_t tce_bypass_base;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]58
59 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
60 * and -1 if not supported. (It's actually identical to the
61 * PE number)
62 */
63 int mve_number;
64
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]65 /* PEs in compound case */
66 struct pnv_ioda_pe *master;
67 struct list_head slaves;
68
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]69 /* Link in list of PE#s */
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]70 struct list_head list;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]71};
72
Gavin Shanf5bc6b72014-04-24 18:00:09 +1000[diff] [blame]73#define PNV_PHB_FLAG_EEH (1 << 0)
74
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]75struct pnv_phb {
76 struct pci_controller *hose;
77 enum pnv_phb_type type;
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]78 enum pnv_phb_model model;
Gavin Shan8747f362013-06-20 13:21:06 +0800[diff] [blame]79 u64 hub_id;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]80 u64 opal_id;
Gavin Shanf5bc6b72014-04-24 18:00:09 +1000[diff] [blame]81 int flags;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]82 void __iomem *regs;
Gavin Shandb1266c2012-08-20 03:49:18 +0000[diff] [blame]83 int initialized;
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]84 spinlock_t lock;
85
Gavin Shan37c367f2013-06-20 18:13:25 +0800[diff] [blame]86#ifdef CONFIG_DEBUG_FS
Gavin Shan7f52a5262014-04-24 18:00:18 +1000[diff] [blame]87 int has_dbgfs;
Gavin Shan37c367f2013-06-20 18:13:25 +0800[diff] [blame]88 struct dentry *dbgfs;
89#endif
90
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000[diff] [blame]91#ifdef CONFIG_PCI_MSI
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000[diff] [blame]92 unsigned int msi_base;
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000[diff] [blame]93 unsigned int msi32_support;
Gavin Shanfb1b55d2013-03-05 21:12:37 +0000[diff] [blame]94 struct msi_bitmap msi_bmp;
Benjamin Herrenschmidtc1a25622011-09-19 17:45:06 +0000[diff] [blame]95#endif
96 int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
Gavin Shan137436c2013-04-25 19:20:59 +0000[diff] [blame]97 unsigned int hwirq, unsigned int virq,
98 unsigned int is_64, struct msi_msg *msg);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]99 void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
100 void (*fixup_phb)(struct pci_controller *hose);
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]101 int (*init_m64)(struct pnv_phb *phb);
Gavin Shan96a2f922015-06-19 12:26:17 +1000[diff] [blame]102 void (*reserve_m64_pe)(struct pci_bus *bus,
103 unsigned long *pe_bitmap, bool all);
Gavin Shan1e916772016-05-03 15:41:36 +1000[diff] [blame]104 struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all);
Gavin Shan49dec922014-07-21 14:42:33 +1000[diff] [blame]105 int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
106 void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
107 int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]108
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]109 struct {
110 /* Global bridge info */
Gavin Shan92b8f132016-05-03 15:41:24 +1000[diff] [blame]111 unsigned int total_pe_num;
112 unsigned int reserved_pe_idx;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]113
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]114 /* 32-bit MMIO window */
115 unsigned int m32_size;
116 unsigned int m32_segsize;
117 unsigned int m32_pci_base;
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]118
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]119 /* 64-bit MMIO window */
120 unsigned int m64_bar_idx;
121 unsigned long m64_size;
122 unsigned long m64_segsize;
123 unsigned long m64_base;
124 unsigned long m64_bar_alloc;
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]125
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]126 /* IO ports */
127 unsigned int io_size;
128 unsigned int io_segsize;
129 unsigned int io_pci_base;
Guo Chao262af552014-07-21 14:42:30 +1000[diff] [blame]130
Gavin Shan13ce7592016-05-03 15:41:23 +1000[diff] [blame]131 /* PE allocation */
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]132 struct mutex pe_alloc_mutex;
Gavin Shan13ce7592016-05-03 15:41:23 +1000[diff] [blame]133 unsigned long *pe_alloc;
134 struct pnv_ioda_pe *pe_array;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]135
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]136 /* M32 & IO segment maps */
Gavin Shan93289d82016-05-03 15:41:29 +1000[diff] [blame]137 unsigned int *m64_segmap;
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]138 unsigned int *m32_segmap;
139 unsigned int *io_segmap;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]140
Gavin Shan2b923ed2016-05-05 12:04:16 +1000[diff] [blame]141 /* DMA32 segment maps - IODA1 only */
142 unsigned int dma32_count;
143 unsigned int *dma32_segmap;
144
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]145 /* IRQ chip */
146 int irq_chip_init;
147 struct irq_chip irq_chip;
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]148
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]149 /* Sorted list of used PE's based
150 * on the sequence of creation
151 */
152 struct list_head pe_list;
153 struct mutex pe_list_mutex;
Gavin Shan137436c2013-04-25 19:20:59 +0000[diff] [blame]154
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]155 /* Reverse map of PEs, will have to extend if
156 * we are to support more than 256 PEs, indexed
157 * bus { bus, devfn }
158 */
159 unsigned char pe_rmap[0x10000];
Gavin Shan7ebdf952012-08-20 03:49:15 +0000[diff] [blame]160
Russell Currey2de50e92016-02-08 15:08:20 +1100[diff] [blame]161 /* TCE cache invalidate registers (physical and
162 * remapped)
163 */
164 phys_addr_t tce_inval_reg_phys;
165 __be64 __iomem *tce_inval_reg;
166 } ioda;
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]167
Brian W Hartca1de5d2013-12-20 13:06:01 -0600[diff] [blame]168 /* PHB and hub status structure */
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]169 union {
170 unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
171 struct OpalIoP7IOCPhbErrorData p7ioc;
Gavin Shan93aef2a2013-11-22 16:28:45 +0800[diff] [blame]172 struct OpalIoPhb3ErrorData phb3;
Brian W Hartca1de5d2013-12-20 13:06:01 -0600[diff] [blame]173 struct OpalIoP7IOCErrorData hub_diag;
Benjamin Herrenschmidtcee72d52011-11-29 18:22:53 +0000[diff] [blame]174 } diag;
Brian W Hartca1de5d2013-12-20 13:06:01 -0600[diff] [blame]175
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]176};
177
178extern struct pci_ops pnv_pci_ops;
Alexey Kardashevskiyda004c32015-06-05 16:35:06 +1000[diff] [blame]179extern int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
180 unsigned long uaddr, enum dma_data_direction direction,
181 struct dma_attrs *attrs);
182extern void pnv_tce_free(struct iommu_table *tbl, long index, long npages);
Alexey Kardashevskiy05c6cfb2015-06-05 16:35:15 +1000[diff] [blame]183extern int pnv_tce_xchg(struct iommu_table *tbl, long index,
184 unsigned long *hpa, enum dma_data_direction *direction);
Alexey Kardashevskiyda004c32015-06-05 16:35:06 +1000[diff] [blame]185extern unsigned long pnv_tce_get(struct iommu_table *tbl, long index);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]186
Gavin Shan93aef2a2013-11-22 16:28:45 +0800[diff] [blame]187void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
188 unsigned char *log_buff);
Gavin Shan3532a7412015-03-17 16:15:03 +1100[diff] [blame]189int pnv_pci_cfg_read(struct pci_dn *pdn,
Gavin Shan9bf41be2013-06-27 13:46:48 +0800[diff] [blame]190 int where, int size, u32 *val);
Gavin Shan3532a7412015-03-17 16:15:03 +1100[diff] [blame]191int pnv_pci_cfg_write(struct pci_dn *pdn,
Gavin Shan9bf41be2013-06-27 13:46:48 +0800[diff] [blame]192 int where, int size, u32 val);
Alexey Kardashevskiy0eaf4de2015-06-05 16:35:09 +1000[diff] [blame]193extern struct iommu_table *pnv_pci_table_alloc(int nid);
194
195extern long pnv_pci_link_table_and_group(int node, int num,
196 struct iommu_table *tbl,
197 struct iommu_table_group *table_group);
198extern void pnv_pci_unlink_table_and_group(struct iommu_table *tbl,
199 struct iommu_table_group *table_group);
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]200extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
201 void *tce_mem, u64 tce_size,
Alexey Kardashevskiy8fa5d452014-06-06 18:44:03 +1000[diff] [blame]202 u64 dma_offset, unsigned page_shift);
Benjamin Herrenschmidt184cd4a2011-11-15 17:29:08 +0000[diff] [blame]203extern void pnv_pci_init_ioda_hub(struct device_node *np);
Gavin Shanaa0c0332013-04-25 19:20:57 +0000[diff] [blame]204extern void pnv_pci_init_ioda2_phb(struct device_node *np);
Alistair Popple5d2aa712015-12-17 13:43:13 +1100[diff] [blame]205extern void pnv_pci_init_npu_phb(struct device_node *np);
Gavin Shan4cce9552013-04-25 19:21:00 +0000[diff] [blame]206extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
Benjamin Herrenschmidt3ad26e52013-10-11 18:23:53 +1100[diff] [blame]207 __be64 *startp, __be64 *endp, bool rm);
Gavin Shand92a2082014-04-24 18:00:24 +1000[diff] [blame]208extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
Gavin Shancadf3642015-02-16 14:45:47 +1100[diff] [blame]209extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
Benjamin Herrenschmidt73ed1482013-05-10 16:59:18 +1000[diff] [blame]210
Daniel Axtens92ae0352015-04-28 15:12:05 +1000[diff] [blame]211extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
Gavin Shan1bc74f12016-02-09 15:50:22 +1100[diff] [blame]212extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
Daniel Axtens92ae0352015-04-28 15:12:05 +1000[diff] [blame]213extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
214extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
215
Alexey Kardashevskiy7d623e42016-04-29 18:55:21 +1000[diff] [blame]216extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
217 const char *fmt, ...);
218#define pe_err(pe, fmt, ...) \
219 pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
220#define pe_warn(pe, fmt, ...) \
221 pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
222#define pe_info(pe, fmt, ...) \
223 pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
224
Alistair Popple5d2aa712015-12-17 13:43:13 +1100[diff] [blame]225/* Nvlink functions */
Alexey Kardashevskiyf9f83452016-04-29 18:55:20 +1000[diff] [blame]226extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
Alexey Kardashevskiy0bbcdb42016-04-29 18:55:18 +1000[diff] [blame]227extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
Alexey Kardashevskiyb5cb9ab2016-04-29 18:55:24 +1000[diff] [blame]228extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
229extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
230 struct iommu_table *tbl);
231extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
232extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
233extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
Alistair Popple5d2aa712015-12-17 13:43:13 +1100[diff] [blame]234
Benjamin Herrenschmidt61305a92011-09-19 17:45:05 +0000[diff] [blame]235#endif /* __POWERNV_PCI_H */