Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <drm/drmP.h> |
| 29 | #include <drm/radeon_drm.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 30 | #include "radeon.h" |
| 31 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 32 | void radeon_gem_object_free(struct drm_gem_object *gobj) |
| 33 | { |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 34 | struct radeon_bo *robj = gem_to_radeon_bo(gobj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 35 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 36 | if (robj) { |
Alex Deucher | 40f5cf9 | 2012-05-10 18:33:13 -0400 | [diff] [blame] | 37 | if (robj->gem_base.import_attach) |
| 38 | drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 39 | radeon_bo_unref(&robj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 40 | } |
| 41 | } |
| 42 | |
Alex Deucher | 391bfec | 2014-07-17 12:26:29 -0400 | [diff] [blame] | 43 | int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 44 | int alignment, int initial_domain, |
Christian König | ed5cb43 | 2014-07-21 13:27:27 +0200 | [diff] [blame] | 45 | u32 flags, bool kernel, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 46 | struct drm_gem_object **obj) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 47 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 48 | struct radeon_bo *robj; |
Christian König | 6c0d112 | 2012-10-23 15:53:18 +0200 | [diff] [blame] | 49 | unsigned long max_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 50 | int r; |
| 51 | |
| 52 | *obj = NULL; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 53 | /* At least align on page size */ |
| 54 | if (alignment < PAGE_SIZE) { |
| 55 | alignment = PAGE_SIZE; |
| 56 | } |
Christian König | 6c0d112 | 2012-10-23 15:53:18 +0200 | [diff] [blame] | 57 | |
Alex Deucher | 391bfec | 2014-07-17 12:26:29 -0400 | [diff] [blame] | 58 | /* Maximum bo size is the unpinned gtt size since we use the gtt to |
| 59 | * handle vram to system pool migrations. |
| 60 | */ |
| 61 | max_size = rdev->mc.gtt_size - rdev->gart_pin_size; |
Christian König | 6c0d112 | 2012-10-23 15:53:18 +0200 | [diff] [blame] | 62 | if (size > max_size) { |
Alex Deucher | 391bfec | 2014-07-17 12:26:29 -0400 | [diff] [blame] | 63 | DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n", |
Michel Dänzer | 380670a | 2014-07-16 18:40:32 +0900 | [diff] [blame] | 64 | size >> 20, max_size >> 20); |
Christian König | 6c0d112 | 2012-10-23 15:53:18 +0200 | [diff] [blame] | 65 | return -ENOMEM; |
| 66 | } |
| 67 | |
Christian König | 0fe7158 | 2012-10-23 15:53:19 +0200 | [diff] [blame] | 68 | retry: |
Michel Dänzer | 02376d8 | 2014-07-17 19:01:08 +0900 | [diff] [blame] | 69 | r = radeon_bo_create(rdev, size, alignment, kernel, initial_domain, |
| 70 | flags, NULL, &robj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 71 | if (r) { |
Christian König | 0fe7158 | 2012-10-23 15:53:19 +0200 | [diff] [blame] | 72 | if (r != -ERESTARTSYS) { |
| 73 | if (initial_domain == RADEON_GEM_DOMAIN_VRAM) { |
| 74 | initial_domain |= RADEON_GEM_DOMAIN_GTT; |
| 75 | goto retry; |
| 76 | } |
Alex Deucher | 391bfec | 2014-07-17 12:26:29 -0400 | [diff] [blame] | 77 | DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n", |
Dave Airlie | ecabd32 | 2009-12-15 10:39:48 +1000 | [diff] [blame] | 78 | size, initial_domain, alignment, r); |
Christian König | 0fe7158 | 2012-10-23 15:53:19 +0200 | [diff] [blame] | 79 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 80 | return r; |
| 81 | } |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 82 | *obj = &robj->gem_base; |
Jerome Glisse | 409851f | 2013-04-25 22:29:27 -0400 | [diff] [blame] | 83 | robj->pid = task_pid_nr(current); |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 84 | |
| 85 | mutex_lock(&rdev->gem.mutex); |
| 86 | list_add_tail(&robj->list, &rdev->gem.objects); |
| 87 | mutex_unlock(&rdev->gem.mutex); |
| 88 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 89 | return 0; |
| 90 | } |
| 91 | |
Rashika Kheria | 248a6c4 | 2014-01-06 20:58:45 +0530 | [diff] [blame] | 92 | static int radeon_gem_set_domain(struct drm_gem_object *gobj, |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 93 | uint32_t rdomain, uint32_t wdomain) |
| 94 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 95 | struct radeon_bo *robj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 96 | uint32_t domain; |
| 97 | int r; |
| 98 | |
| 99 | /* FIXME: reeimplement */ |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 100 | robj = gem_to_radeon_bo(gobj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 101 | /* work out where to validate the buffer to */ |
| 102 | domain = wdomain; |
| 103 | if (!domain) { |
| 104 | domain = rdomain; |
| 105 | } |
| 106 | if (!domain) { |
| 107 | /* Do nothings */ |
Masanari Iida | b6cafa2 | 2012-02-27 23:28:38 +0900 | [diff] [blame] | 108 | printk(KERN_WARNING "Set domain without domain !\n"); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 109 | return 0; |
| 110 | } |
| 111 | if (domain == RADEON_GEM_DOMAIN_CPU) { |
| 112 | /* Asking for cpu access wait for object idle */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 113 | r = radeon_bo_wait(robj, NULL, false); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 114 | if (r) { |
| 115 | printk(KERN_ERR "Failed to wait for object !\n"); |
| 116 | return r; |
| 117 | } |
| 118 | } |
| 119 | return 0; |
| 120 | } |
| 121 | |
| 122 | int radeon_gem_init(struct radeon_device *rdev) |
| 123 | { |
| 124 | INIT_LIST_HEAD(&rdev->gem.objects); |
| 125 | return 0; |
| 126 | } |
| 127 | |
| 128 | void radeon_gem_fini(struct radeon_device *rdev) |
| 129 | { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 130 | radeon_bo_force_delete(rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 131 | } |
| 132 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 133 | /* |
| 134 | * Call from drm_gem_handle_create which appear in both new and open ioctl |
| 135 | * case. |
| 136 | */ |
| 137 | int radeon_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) |
| 138 | { |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 139 | struct radeon_bo *rbo = gem_to_radeon_bo(obj); |
| 140 | struct radeon_device *rdev = rbo->rdev; |
| 141 | struct radeon_fpriv *fpriv = file_priv->driver_priv; |
| 142 | struct radeon_vm *vm = &fpriv->vm; |
| 143 | struct radeon_bo_va *bo_va; |
| 144 | int r; |
| 145 | |
| 146 | if (rdev->family < CHIP_CAYMAN) { |
| 147 | return 0; |
| 148 | } |
| 149 | |
| 150 | r = radeon_bo_reserve(rbo, false); |
| 151 | if (r) { |
| 152 | return r; |
| 153 | } |
| 154 | |
| 155 | bo_va = radeon_vm_bo_find(vm, rbo); |
| 156 | if (!bo_va) { |
| 157 | bo_va = radeon_vm_bo_add(rdev, vm, rbo); |
| 158 | } else { |
| 159 | ++bo_va->ref_count; |
| 160 | } |
| 161 | radeon_bo_unreserve(rbo); |
| 162 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 163 | return 0; |
| 164 | } |
| 165 | |
| 166 | void radeon_gem_object_close(struct drm_gem_object *obj, |
| 167 | struct drm_file *file_priv) |
| 168 | { |
| 169 | struct radeon_bo *rbo = gem_to_radeon_bo(obj); |
| 170 | struct radeon_device *rdev = rbo->rdev; |
| 171 | struct radeon_fpriv *fpriv = file_priv->driver_priv; |
| 172 | struct radeon_vm *vm = &fpriv->vm; |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 173 | struct radeon_bo_va *bo_va; |
Christian König | d59f702 | 2012-09-11 16:10:02 +0200 | [diff] [blame] | 174 | int r; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 175 | |
| 176 | if (rdev->family < CHIP_CAYMAN) { |
| 177 | return; |
| 178 | } |
| 179 | |
Christian König | d59f702 | 2012-09-11 16:10:02 +0200 | [diff] [blame] | 180 | r = radeon_bo_reserve(rbo, true); |
| 181 | if (r) { |
| 182 | dev_err(rdev->dev, "leaking bo va because " |
| 183 | "we fail to reserve bo (%d)\n", r); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 184 | return; |
| 185 | } |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 186 | bo_va = radeon_vm_bo_find(vm, rbo); |
| 187 | if (bo_va) { |
| 188 | if (--bo_va->ref_count == 0) { |
| 189 | radeon_vm_bo_rmv(rdev, bo_va); |
| 190 | } |
| 191 | } |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 192 | radeon_bo_unreserve(rbo); |
| 193 | } |
| 194 | |
Christian König | 6c6f478 | 2012-05-02 15:11:19 +0200 | [diff] [blame] | 195 | static int radeon_gem_handle_lockup(struct radeon_device *rdev, int r) |
| 196 | { |
| 197 | if (r == -EDEADLK) { |
Christian König | 6c6f478 | 2012-05-02 15:11:19 +0200 | [diff] [blame] | 198 | r = radeon_gpu_reset(rdev); |
| 199 | if (!r) |
| 200 | r = -EAGAIN; |
Christian König | 6c6f478 | 2012-05-02 15:11:19 +0200 | [diff] [blame] | 201 | } |
| 202 | return r; |
| 203 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 204 | |
| 205 | /* |
| 206 | * GEM ioctls. |
| 207 | */ |
| 208 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, |
| 209 | struct drm_file *filp) |
| 210 | { |
| 211 | struct radeon_device *rdev = dev->dev_private; |
| 212 | struct drm_radeon_gem_info *args = data; |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 213 | struct ttm_mem_type_manager *man; |
| 214 | |
| 215 | man = &rdev->mman.bdev.man[TTM_PL_VRAM]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 216 | |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 217 | args->vram_size = rdev->mc.real_vram_size; |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 218 | args->vram_visible = (u64)man->size << PAGE_SHIFT; |
Alex Deucher | ccbe006 | 2014-07-17 12:16:20 -0400 | [diff] [blame] | 219 | args->vram_visible -= rdev->vram_pin_size; |
| 220 | args->gart_size = rdev->mc.gtt_size; |
| 221 | args->gart_size -= rdev->gart_pin_size; |
| 222 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 227 | struct drm_file *filp) |
| 228 | { |
| 229 | /* TODO: implement */ |
| 230 | DRM_ERROR("unimplemented %s\n", __func__); |
| 231 | return -ENOSYS; |
| 232 | } |
| 233 | |
| 234 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 235 | struct drm_file *filp) |
| 236 | { |
| 237 | /* TODO: implement */ |
| 238 | DRM_ERROR("unimplemented %s\n", __func__); |
| 239 | return -ENOSYS; |
| 240 | } |
| 241 | |
| 242 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, |
| 243 | struct drm_file *filp) |
| 244 | { |
| 245 | struct radeon_device *rdev = dev->dev_private; |
| 246 | struct drm_radeon_gem_create *args = data; |
| 247 | struct drm_gem_object *gobj; |
| 248 | uint32_t handle; |
| 249 | int r; |
| 250 | |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 251 | down_read(&rdev->exclusive_lock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 252 | /* create a gem object to contain this object in */ |
| 253 | args->size = roundup(args->size, PAGE_SIZE); |
| 254 | r = radeon_gem_object_create(rdev, args->size, args->alignment, |
Michel Dänzer | 02376d8 | 2014-07-17 19:01:08 +0900 | [diff] [blame] | 255 | args->initial_domain, args->flags, |
Christian König | ed5cb43 | 2014-07-21 13:27:27 +0200 | [diff] [blame] | 256 | false, &gobj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 257 | if (r) { |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 258 | up_read(&rdev->exclusive_lock); |
Christian König | 6c6f478 | 2012-05-02 15:11:19 +0200 | [diff] [blame] | 259 | r = radeon_gem_handle_lockup(rdev, r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 260 | return r; |
| 261 | } |
| 262 | r = drm_gem_handle_create(filp, gobj, &handle); |
Dave Airlie | 29d08b3 | 2010-09-27 16:17:17 +1000 | [diff] [blame] | 263 | /* drop reference from allocate - handle holds it now */ |
| 264 | drm_gem_object_unreference_unlocked(gobj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 265 | if (r) { |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 266 | up_read(&rdev->exclusive_lock); |
Christian König | 6c6f478 | 2012-05-02 15:11:19 +0200 | [diff] [blame] | 267 | r = radeon_gem_handle_lockup(rdev, r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 268 | return r; |
| 269 | } |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 270 | args->handle = handle; |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 271 | up_read(&rdev->exclusive_lock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 272 | return 0; |
| 273 | } |
| 274 | |
| 275 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 276 | struct drm_file *filp) |
| 277 | { |
| 278 | /* transition the BO to a domain - |
| 279 | * just validate the BO into a certain domain */ |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 280 | struct radeon_device *rdev = dev->dev_private; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 281 | struct drm_radeon_gem_set_domain *args = data; |
| 282 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 283 | struct radeon_bo *robj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 284 | int r; |
| 285 | |
| 286 | /* for now if someone requests domain CPU - |
| 287 | * just make sure the buffer is finished with */ |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 288 | down_read(&rdev->exclusive_lock); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 289 | |
| 290 | /* just do a BO wait for now */ |
| 291 | gobj = drm_gem_object_lookup(dev, filp, args->handle); |
| 292 | if (gobj == NULL) { |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 293 | up_read(&rdev->exclusive_lock); |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 294 | return -ENOENT; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 295 | } |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 296 | robj = gem_to_radeon_bo(gobj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 297 | |
| 298 | r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain); |
| 299 | |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 300 | drm_gem_object_unreference_unlocked(gobj); |
Jerome Glisse | dee53e7 | 2012-07-02 12:45:19 -0400 | [diff] [blame] | 301 | up_read(&rdev->exclusive_lock); |
Christian König | 6c6f478 | 2012-05-02 15:11:19 +0200 | [diff] [blame] | 302 | r = radeon_gem_handle_lockup(robj->rdev, r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 303 | return r; |
| 304 | } |
| 305 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 306 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
| 307 | struct drm_device *dev, |
| 308 | uint32_t handle, uint64_t *offset_p) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 309 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 310 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 311 | struct radeon_bo *robj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 312 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 313 | gobj = drm_gem_object_lookup(dev, filp, handle); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 314 | if (gobj == NULL) { |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 315 | return -ENOENT; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 316 | } |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 317 | robj = gem_to_radeon_bo(gobj); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 318 | *offset_p = radeon_bo_mmap_offset(robj); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 319 | drm_gem_object_unreference_unlocked(gobj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 320 | return 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 321 | } |
| 322 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 323 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 324 | struct drm_file *filp) |
| 325 | { |
| 326 | struct drm_radeon_gem_mmap *args = data; |
| 327 | |
| 328 | return radeon_mode_dumb_mmap(filp, dev, args->handle, &args->addr_ptr); |
| 329 | } |
| 330 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 331 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 332 | struct drm_file *filp) |
| 333 | { |
Jerome Glisse | 1ef5325 | 2012-07-02 12:40:54 -0400 | [diff] [blame] | 334 | struct radeon_device *rdev = dev->dev_private; |
Dave Airlie | cefb87e | 2009-08-16 21:05:45 +1000 | [diff] [blame] | 335 | struct drm_radeon_gem_busy *args = data; |
| 336 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 337 | struct radeon_bo *robj; |
Dave Airlie | cefb87e | 2009-08-16 21:05:45 +1000 | [diff] [blame] | 338 | int r; |
Dave Airlie | 4361e52 | 2009-12-10 15:59:32 +1000 | [diff] [blame] | 339 | uint32_t cur_placement = 0; |
Dave Airlie | cefb87e | 2009-08-16 21:05:45 +1000 | [diff] [blame] | 340 | |
| 341 | gobj = drm_gem_object_lookup(dev, filp, args->handle); |
| 342 | if (gobj == NULL) { |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 343 | return -ENOENT; |
Dave Airlie | cefb87e | 2009-08-16 21:05:45 +1000 | [diff] [blame] | 344 | } |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 345 | robj = gem_to_radeon_bo(gobj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 346 | r = radeon_bo_wait(robj, &cur_placement, true); |
Marek Olšák | 0bc490a | 2014-03-02 00:56:19 +0100 | [diff] [blame] | 347 | args->domain = radeon_mem_type_to_domain(cur_placement); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 348 | drm_gem_object_unreference_unlocked(gobj); |
Jerome Glisse | 1ef5325 | 2012-07-02 12:40:54 -0400 | [diff] [blame] | 349 | r = radeon_gem_handle_lockup(rdev, r); |
Dave Airlie | e3b2415 | 2009-08-21 09:47:45 +1000 | [diff] [blame] | 350 | return r; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 351 | } |
| 352 | |
| 353 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, |
| 354 | struct drm_file *filp) |
| 355 | { |
Jerome Glisse | 1ef5325 | 2012-07-02 12:40:54 -0400 | [diff] [blame] | 356 | struct radeon_device *rdev = dev->dev_private; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 357 | struct drm_radeon_gem_wait_idle *args = data; |
| 358 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 359 | struct radeon_bo *robj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 360 | int r; |
Michel Dänzer | 404a6a5 | 2014-08-01 17:22:09 +0900 | [diff] [blame] | 361 | uint32_t cur_placement = 0; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 362 | |
| 363 | gobj = drm_gem_object_lookup(dev, filp, args->handle); |
| 364 | if (gobj == NULL) { |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 365 | return -ENOENT; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 366 | } |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 367 | robj = gem_to_radeon_bo(gobj); |
Michel Dänzer | 404a6a5 | 2014-08-01 17:22:09 +0900 | [diff] [blame] | 368 | r = radeon_bo_wait(robj, &cur_placement, false); |
Michel Dänzer | 124764f | 2014-07-31 18:43:48 +0900 | [diff] [blame] | 369 | /* Flush HDP cache via MMIO if necessary */ |
Michel Dänzer | 404a6a5 | 2014-08-01 17:22:09 +0900 | [diff] [blame] | 370 | if (rdev->asic->mmio_hdp_flush && |
| 371 | radeon_mem_type_to_domain(cur_placement) == RADEON_GEM_DOMAIN_VRAM) |
Michel Dänzer | 124764f | 2014-07-31 18:43:48 +0900 | [diff] [blame] | 372 | robj->rdev->asic->mmio_hdp_flush(rdev); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 373 | drm_gem_object_unreference_unlocked(gobj); |
Jerome Glisse | 1ef5325 | 2012-07-02 12:40:54 -0400 | [diff] [blame] | 374 | r = radeon_gem_handle_lockup(rdev, r); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 375 | return r; |
| 376 | } |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 377 | |
| 378 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
| 379 | struct drm_file *filp) |
| 380 | { |
| 381 | struct drm_radeon_gem_set_tiling *args = data; |
| 382 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 383 | struct radeon_bo *robj; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 384 | int r = 0; |
| 385 | |
| 386 | DRM_DEBUG("%d \n", args->handle); |
| 387 | gobj = drm_gem_object_lookup(dev, filp, args->handle); |
| 388 | if (gobj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 389 | return -ENOENT; |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 390 | robj = gem_to_radeon_bo(gobj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 391 | r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 392 | drm_gem_object_unreference_unlocked(gobj); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 393 | return r; |
| 394 | } |
| 395 | |
| 396 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, |
| 397 | struct drm_file *filp) |
| 398 | { |
| 399 | struct drm_radeon_gem_get_tiling *args = data; |
| 400 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 401 | struct radeon_bo *rbo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 402 | int r = 0; |
| 403 | |
| 404 | DRM_DEBUG("\n"); |
| 405 | gobj = drm_gem_object_lookup(dev, filp, args->handle); |
| 406 | if (gobj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 407 | return -ENOENT; |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 408 | rbo = gem_to_radeon_bo(gobj); |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 409 | r = radeon_bo_reserve(rbo, false); |
| 410 | if (unlikely(r != 0)) |
Dave Airlie | 51f07b7 | 2009-12-16 13:10:43 +1000 | [diff] [blame] | 411 | goto out; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 412 | radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); |
| 413 | radeon_bo_unreserve(rbo); |
Dave Airlie | 51f07b7 | 2009-12-16 13:10:43 +1000 | [diff] [blame] | 414 | out: |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 415 | drm_gem_object_unreference_unlocked(gobj); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 416 | return r; |
| 417 | } |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 418 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 419 | int radeon_gem_va_ioctl(struct drm_device *dev, void *data, |
| 420 | struct drm_file *filp) |
| 421 | { |
| 422 | struct drm_radeon_gem_va *args = data; |
| 423 | struct drm_gem_object *gobj; |
| 424 | struct radeon_device *rdev = dev->dev_private; |
| 425 | struct radeon_fpriv *fpriv = filp->driver_priv; |
| 426 | struct radeon_bo *rbo; |
| 427 | struct radeon_bo_va *bo_va; |
| 428 | u32 invalid_flags; |
| 429 | int r = 0; |
| 430 | |
Alex Deucher | 67e915e | 2012-01-06 09:38:15 -0500 | [diff] [blame] | 431 | if (!rdev->vm_manager.enabled) { |
| 432 | args->operation = RADEON_VA_RESULT_ERROR; |
| 433 | return -ENOTTY; |
| 434 | } |
| 435 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 436 | /* !! DONT REMOVE !! |
| 437 | * We don't support vm_id yet, to be sure we don't have have broken |
| 438 | * userspace, reject anyone trying to use non 0 value thus moving |
| 439 | * forward we can use those fields without breaking existant userspace |
| 440 | */ |
| 441 | if (args->vm_id) { |
| 442 | args->operation = RADEON_VA_RESULT_ERROR; |
| 443 | return -EINVAL; |
| 444 | } |
| 445 | |
| 446 | if (args->offset < RADEON_VA_RESERVED_SIZE) { |
| 447 | dev_err(&dev->pdev->dev, |
| 448 | "offset 0x%lX is in reserved area 0x%X\n", |
| 449 | (unsigned long)args->offset, |
| 450 | RADEON_VA_RESERVED_SIZE); |
| 451 | args->operation = RADEON_VA_RESULT_ERROR; |
| 452 | return -EINVAL; |
| 453 | } |
| 454 | |
| 455 | /* don't remove, we need to enforce userspace to set the snooped flag |
| 456 | * otherwise we will endup with broken userspace and we won't be able |
| 457 | * to enable this feature without adding new interface |
| 458 | */ |
| 459 | invalid_flags = RADEON_VM_PAGE_VALID | RADEON_VM_PAGE_SYSTEM; |
| 460 | if ((args->flags & invalid_flags)) { |
| 461 | dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n", |
| 462 | args->flags, invalid_flags); |
| 463 | args->operation = RADEON_VA_RESULT_ERROR; |
| 464 | return -EINVAL; |
| 465 | } |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 466 | |
| 467 | switch (args->operation) { |
| 468 | case RADEON_VA_MAP: |
| 469 | case RADEON_VA_UNMAP: |
| 470 | break; |
| 471 | default: |
| 472 | dev_err(&dev->pdev->dev, "unsupported operation %d\n", |
| 473 | args->operation); |
| 474 | args->operation = RADEON_VA_RESULT_ERROR; |
| 475 | return -EINVAL; |
| 476 | } |
| 477 | |
| 478 | gobj = drm_gem_object_lookup(dev, filp, args->handle); |
| 479 | if (gobj == NULL) { |
| 480 | args->operation = RADEON_VA_RESULT_ERROR; |
| 481 | return -ENOENT; |
| 482 | } |
| 483 | rbo = gem_to_radeon_bo(gobj); |
| 484 | r = radeon_bo_reserve(rbo, false); |
| 485 | if (r) { |
| 486 | args->operation = RADEON_VA_RESULT_ERROR; |
| 487 | drm_gem_object_unreference_unlocked(gobj); |
| 488 | return r; |
| 489 | } |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 490 | bo_va = radeon_vm_bo_find(&fpriv->vm, rbo); |
| 491 | if (!bo_va) { |
| 492 | args->operation = RADEON_VA_RESULT_ERROR; |
| 493 | drm_gem_object_unreference_unlocked(gobj); |
| 494 | return -ENOENT; |
| 495 | } |
| 496 | |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 497 | switch (args->operation) { |
| 498 | case RADEON_VA_MAP: |
Alex Deucher | 0aea5e4 | 2014-07-30 11:49:56 -0400 | [diff] [blame^] | 499 | if (bo_va->it.start) { |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 500 | args->operation = RADEON_VA_RESULT_VA_EXIST; |
Alex Deucher | 0aea5e4 | 2014-07-30 11:49:56 -0400 | [diff] [blame^] | 501 | args->offset = bo_va->it.start * RADEON_GPU_PAGE_SIZE; |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 502 | goto out; |
| 503 | } |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 504 | r = radeon_vm_bo_set_addr(rdev, bo_va, args->offset, args->flags); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 505 | break; |
| 506 | case RADEON_VA_UNMAP: |
Christian König | e971bd5 | 2012-09-11 16:10:04 +0200 | [diff] [blame] | 507 | r = radeon_vm_bo_set_addr(rdev, bo_va, 0, 0); |
Jerome Glisse | 721604a | 2012-01-05 22:11:05 -0500 | [diff] [blame] | 508 | break; |
| 509 | default: |
| 510 | break; |
| 511 | } |
| 512 | args->operation = RADEON_VA_RESULT_OK; |
| 513 | if (r) { |
| 514 | args->operation = RADEON_VA_RESULT_ERROR; |
| 515 | } |
| 516 | out: |
| 517 | radeon_bo_unreserve(rbo); |
| 518 | drm_gem_object_unreference_unlocked(gobj); |
| 519 | return r; |
| 520 | } |
| 521 | |
Marek Olšák | bda72d5 | 2014-03-02 00:56:17 +0100 | [diff] [blame] | 522 | int radeon_gem_op_ioctl(struct drm_device *dev, void *data, |
| 523 | struct drm_file *filp) |
| 524 | { |
| 525 | struct drm_radeon_gem_op *args = data; |
| 526 | struct drm_gem_object *gobj; |
| 527 | struct radeon_bo *robj; |
| 528 | int r; |
| 529 | |
| 530 | gobj = drm_gem_object_lookup(dev, filp, args->handle); |
| 531 | if (gobj == NULL) { |
| 532 | return -ENOENT; |
| 533 | } |
| 534 | robj = gem_to_radeon_bo(gobj); |
| 535 | r = radeon_bo_reserve(robj, false); |
| 536 | if (unlikely(r)) |
| 537 | goto out; |
| 538 | |
| 539 | switch (args->op) { |
| 540 | case RADEON_GEM_OP_GET_INITIAL_DOMAIN: |
| 541 | args->value = robj->initial_domain; |
| 542 | break; |
| 543 | case RADEON_GEM_OP_SET_INITIAL_DOMAIN: |
| 544 | robj->initial_domain = args->value & (RADEON_GEM_DOMAIN_VRAM | |
| 545 | RADEON_GEM_DOMAIN_GTT | |
| 546 | RADEON_GEM_DOMAIN_CPU); |
| 547 | break; |
| 548 | default: |
| 549 | r = -EINVAL; |
| 550 | } |
| 551 | |
| 552 | radeon_bo_unreserve(robj); |
| 553 | out: |
| 554 | drm_gem_object_unreference_unlocked(gobj); |
| 555 | return r; |
| 556 | } |
| 557 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 558 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
| 559 | struct drm_device *dev, |
| 560 | struct drm_mode_create_dumb *args) |
| 561 | { |
| 562 | struct radeon_device *rdev = dev->dev_private; |
| 563 | struct drm_gem_object *gobj; |
Dave Airlie | c87a8d8 | 2011-03-17 13:58:34 +1000 | [diff] [blame] | 564 | uint32_t handle; |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 565 | int r; |
| 566 | |
| 567 | args->pitch = radeon_align_pitch(rdev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8); |
| 568 | args->size = args->pitch * args->height; |
| 569 | args->size = ALIGN(args->size, PAGE_SIZE); |
| 570 | |
| 571 | r = radeon_gem_object_create(rdev, args->size, 0, |
Michel Dänzer | 02376d8 | 2014-07-17 19:01:08 +0900 | [diff] [blame] | 572 | RADEON_GEM_DOMAIN_VRAM, 0, |
Christian König | ed5cb43 | 2014-07-21 13:27:27 +0200 | [diff] [blame] | 573 | false, &gobj); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 574 | if (r) |
| 575 | return -ENOMEM; |
| 576 | |
Dave Airlie | c87a8d8 | 2011-03-17 13:58:34 +1000 | [diff] [blame] | 577 | r = drm_gem_handle_create(file_priv, gobj, &handle); |
| 578 | /* drop reference from allocate - handle holds it now */ |
| 579 | drm_gem_object_unreference_unlocked(gobj); |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 580 | if (r) { |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 581 | return r; |
| 582 | } |
Dave Airlie | c87a8d8 | 2011-03-17 13:58:34 +1000 | [diff] [blame] | 583 | args->handle = handle; |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 584 | return 0; |
| 585 | } |
| 586 | |
Jerome Glisse | 409851f | 2013-04-25 22:29:27 -0400 | [diff] [blame] | 587 | #if defined(CONFIG_DEBUG_FS) |
| 588 | static int radeon_debugfs_gem_info(struct seq_file *m, void *data) |
| 589 | { |
| 590 | struct drm_info_node *node = (struct drm_info_node *)m->private; |
| 591 | struct drm_device *dev = node->minor->dev; |
| 592 | struct radeon_device *rdev = dev->dev_private; |
| 593 | struct radeon_bo *rbo; |
| 594 | unsigned i = 0; |
| 595 | |
| 596 | mutex_lock(&rdev->gem.mutex); |
| 597 | list_for_each_entry(rbo, &rdev->gem.objects, list) { |
| 598 | unsigned domain; |
| 599 | const char *placement; |
| 600 | |
| 601 | domain = radeon_mem_type_to_domain(rbo->tbo.mem.mem_type); |
| 602 | switch (domain) { |
| 603 | case RADEON_GEM_DOMAIN_VRAM: |
| 604 | placement = "VRAM"; |
| 605 | break; |
| 606 | case RADEON_GEM_DOMAIN_GTT: |
| 607 | placement = " GTT"; |
| 608 | break; |
| 609 | case RADEON_GEM_DOMAIN_CPU: |
| 610 | default: |
| 611 | placement = " CPU"; |
| 612 | break; |
| 613 | } |
| 614 | seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n", |
| 615 | i, radeon_bo_size(rbo) >> 10, radeon_bo_size(rbo) >> 20, |
| 616 | placement, (unsigned long)rbo->pid); |
| 617 | i++; |
| 618 | } |
| 619 | mutex_unlock(&rdev->gem.mutex); |
| 620 | return 0; |
| 621 | } |
| 622 | |
| 623 | static struct drm_info_list radeon_debugfs_gem_list[] = { |
| 624 | {"radeon_gem_info", &radeon_debugfs_gem_info, 0, NULL}, |
| 625 | }; |
| 626 | #endif |
| 627 | |
| 628 | int radeon_gem_debugfs_init(struct radeon_device *rdev) |
| 629 | { |
| 630 | #if defined(CONFIG_DEBUG_FS) |
| 631 | return radeon_debugfs_add_files(rdev, radeon_debugfs_gem_list, 1); |
| 632 | #endif |
| 633 | return 0; |
| 634 | } |