Amelie Delaunay | 7c60930 | 2017-01-05 14:43:23 +0100 | [diff] [blame] | 1 | STM32 Real Time Clock |
| 2 | |
| 3 | Required properties: |
Amelie Delaunay | 5c4554d | 2018-05-17 14:04:25 +0200 | [diff] [blame] | 4 | - compatible: can be one of the following: |
| 5 | - "st,stm32-rtc" for devices compatible with stm32(f4/f7). |
| 6 | - "st,stm32h7-rtc" for devices compatible with stm32h7. |
| 7 | - "st,stm32mp1-rtc" for devices compatible with stm32mp1. |
Amelie Delaunay | 7c60930 | 2017-01-05 14:43:23 +0100 | [diff] [blame] | 8 | - reg: address range of rtc register set. |
Amelie Delaunay | d2be279 | 2017-07-06 10:47:44 +0200 | [diff] [blame] | 9 | - clocks: can use up to two clocks, depending on part used: |
| 10 | - "rtc_ck": RTC clock source. |
Amelie Delaunay | d2be279 | 2017-07-06 10:47:44 +0200 | [diff] [blame] | 11 | - "pclk": RTC APB interface clock. |
| 12 | It is not present on stm32(f4/f7). |
Amelie Delaunay | 5c4554d | 2018-05-17 14:04:25 +0200 | [diff] [blame] | 13 | It is required on stm32(h7/mp1). |
Amelie Delaunay | d2be279 | 2017-07-06 10:47:44 +0200 | [diff] [blame] | 14 | - clock-names: must be "rtc_ck" and "pclk". |
Amelie Delaunay | 5c4554d | 2018-05-17 14:04:25 +0200 | [diff] [blame] | 15 | It is required on stm32(h7/mp1). |
Amelie Delaunay | 5c4554d | 2018-05-17 14:04:25 +0200 | [diff] [blame] | 16 | - interrupts: rtc alarm interrupt. On stm32mp1, a second interrupt is required |
| 17 | for rtc alarm wakeup interrupt. |
Amelie Delaunay | deb7dcf | 2018-04-19 15:21:42 +0200 | [diff] [blame] | 18 | - st,syscfg: phandle/offset/mask triplet. The phandle to pwrcfg used to |
| 19 | access control register at offset, and change the dbp (Disable Backup |
| 20 | Protection) bit represented by the mask, mandatory to disable/enable backup |
| 21 | domain (RTC registers) write protection. |
Amelie Delaunay | 5c4554d | 2018-05-17 14:04:25 +0200 | [diff] [blame] | 22 | It is required on stm32(f4/f7/h7). |
Amelie Delaunay | 7c60930 | 2017-01-05 14:43:23 +0100 | [diff] [blame] | 23 | |
Amelie Delaunay | 5c4554d | 2018-05-17 14:04:25 +0200 | [diff] [blame] | 24 | Optional properties (to override default rtc_ck parent clock on stm32(f4/f7/h7): |
Amelie Delaunay | d2be279 | 2017-07-06 10:47:44 +0200 | [diff] [blame] | 25 | - assigned-clocks: reference to the rtc_ck clock entry. |
| 26 | - assigned-clock-parents: phandle of the new parent clock of rtc_ck. |
Amelie Delaunay | 7c60930 | 2017-01-05 14:43:23 +0100 | [diff] [blame] | 27 | |
| 28 | Example: |
| 29 | |
| 30 | rtc: rtc@40002800 { |
| 31 | compatible = "st,stm32-rtc"; |
| 32 | reg = <0x40002800 0x400>; |
| 33 | clocks = <&rcc 1 CLK_RTC>; |
| 34 | assigned-clocks = <&rcc 1 CLK_RTC>; |
| 35 | assigned-clock-parents = <&rcc 1 CLK_LSE>; |
| 36 | interrupt-parent = <&exti>; |
| 37 | interrupts = <17 1>; |
Amelie Delaunay | deb7dcf | 2018-04-19 15:21:42 +0200 | [diff] [blame] | 38 | st,syscfg = <&pwrcfg 0x00 0x100>; |
Amelie Delaunay | 7c60930 | 2017-01-05 14:43:23 +0100 | [diff] [blame] | 39 | }; |
Amelie Delaunay | d2be279 | 2017-07-06 10:47:44 +0200 | [diff] [blame] | 40 | |
| 41 | rtc: rtc@58004000 { |
| 42 | compatible = "st,stm32h7-rtc"; |
| 43 | reg = <0x58004000 0x400>; |
| 44 | clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>; |
| 45 | clock-names = "pclk", "rtc_ck"; |
| 46 | assigned-clocks = <&rcc RTC_CK>; |
| 47 | assigned-clock-parents = <&rcc LSE_CK>; |
| 48 | interrupt-parent = <&exti>; |
| 49 | interrupts = <17 1>; |
| 50 | interrupt-names = "alarm"; |
Amelie Delaunay | deb7dcf | 2018-04-19 15:21:42 +0200 | [diff] [blame] | 51 | st,syscfg = <&pwrcfg 0x00 0x100>; |
Amelie Delaunay | d2be279 | 2017-07-06 10:47:44 +0200 | [diff] [blame] | 52 | }; |
Amelie Delaunay | 5c4554d | 2018-05-17 14:04:25 +0200 | [diff] [blame] | 53 | |
| 54 | rtc: rtc@5c004000 { |
| 55 | compatible = "st,stm32mp1-rtc"; |
| 56 | reg = <0x5c004000 0x400>; |
| 57 | clocks = <&rcc RTCAPB>, <&rcc RTC>; |
| 58 | clock-names = "pclk", "rtc_ck"; |
| 59 | interrupts-extended = <&intc GIC_SPI 3 IRQ_TYPE_NONE>, |
| 60 | <&exti 19 1>; |
| 61 | }; |