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Amelie Delaunay7c609302017-01-05 14:43:23 +01001STM32 Real Time Clock
2
3Required properties:
Amelie Delaunay5c4554d2018-05-17 14:04:25 +02004- compatible: can be one of the following:
5 - "st,stm32-rtc" for devices compatible with stm32(f4/f7).
6 - "st,stm32h7-rtc" for devices compatible with stm32h7.
7 - "st,stm32mp1-rtc" for devices compatible with stm32mp1.
Amelie Delaunay7c609302017-01-05 14:43:23 +01008- reg: address range of rtc register set.
Amelie Delaunayd2be2792017-07-06 10:47:44 +02009- clocks: can use up to two clocks, depending on part used:
10 - "rtc_ck": RTC clock source.
Amelie Delaunayd2be2792017-07-06 10:47:44 +020011 - "pclk": RTC APB interface clock.
12 It is not present on stm32(f4/f7).
Amelie Delaunay5c4554d2018-05-17 14:04:25 +020013 It is required on stm32(h7/mp1).
Amelie Delaunayd2be2792017-07-06 10:47:44 +020014- clock-names: must be "rtc_ck" and "pclk".
Amelie Delaunay5c4554d2018-05-17 14:04:25 +020015 It is required on stm32(h7/mp1).
Amelie Delaunay7c609302017-01-05 14:43:23 +010016- interrupt-parent: phandle for the interrupt controller.
Amelie Delaunay5c4554d2018-05-17 14:04:25 +020017 It is required on stm32(f4/f7/h7).
18- interrupts: rtc alarm interrupt. On stm32mp1, a second interrupt is required
19 for rtc alarm wakeup interrupt.
Amelie Delaunaydeb7dcf2018-04-19 15:21:42 +020020- st,syscfg: phandle/offset/mask triplet. The phandle to pwrcfg used to
21 access control register at offset, and change the dbp (Disable Backup
22 Protection) bit represented by the mask, mandatory to disable/enable backup
23 domain (RTC registers) write protection.
Amelie Delaunay5c4554d2018-05-17 14:04:25 +020024 It is required on stm32(f4/f7/h7).
Amelie Delaunay7c609302017-01-05 14:43:23 +010025
Amelie Delaunay5c4554d2018-05-17 14:04:25 +020026Optional properties (to override default rtc_ck parent clock on stm32(f4/f7/h7):
Amelie Delaunayd2be2792017-07-06 10:47:44 +020027- assigned-clocks: reference to the rtc_ck clock entry.
28- assigned-clock-parents: phandle of the new parent clock of rtc_ck.
Amelie Delaunay7c609302017-01-05 14:43:23 +010029
30Example:
31
32 rtc: rtc@40002800 {
33 compatible = "st,stm32-rtc";
34 reg = <0x40002800 0x400>;
35 clocks = <&rcc 1 CLK_RTC>;
36 assigned-clocks = <&rcc 1 CLK_RTC>;
37 assigned-clock-parents = <&rcc 1 CLK_LSE>;
38 interrupt-parent = <&exti>;
39 interrupts = <17 1>;
Amelie Delaunaydeb7dcf2018-04-19 15:21:42 +020040 st,syscfg = <&pwrcfg 0x00 0x100>;
Amelie Delaunay7c609302017-01-05 14:43:23 +010041 };
Amelie Delaunayd2be2792017-07-06 10:47:44 +020042
43 rtc: rtc@58004000 {
44 compatible = "st,stm32h7-rtc";
45 reg = <0x58004000 0x400>;
46 clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
47 clock-names = "pclk", "rtc_ck";
48 assigned-clocks = <&rcc RTC_CK>;
49 assigned-clock-parents = <&rcc LSE_CK>;
50 interrupt-parent = <&exti>;
51 interrupts = <17 1>;
52 interrupt-names = "alarm";
Amelie Delaunaydeb7dcf2018-04-19 15:21:42 +020053 st,syscfg = <&pwrcfg 0x00 0x100>;
Amelie Delaunayd2be2792017-07-06 10:47:44 +020054 };
Amelie Delaunay5c4554d2018-05-17 14:04:25 +020055
56 rtc: rtc@5c004000 {
57 compatible = "st,stm32mp1-rtc";
58 reg = <0x5c004000 0x400>;
59 clocks = <&rcc RTCAPB>, <&rcc RTC>;
60 clock-names = "pclk", "rtc_ck";
61 interrupts-extended = <&intc GIC_SPI 3 IRQ_TYPE_NONE>,
62 <&exti 19 1>;
63 };