blob: 64786cb89a93bdba111181082e8aef600525d8da [file] [log] [blame]
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001/*
2 * net/dsa/mv88e6xxx.h - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10
11#ifndef __MV88E6XXX_H
12#define __MV88E6XXX_H
13
Andrew Lunn80c46272015-06-20 18:42:30 +020014#ifndef UINT64_MAX
15#define UINT64_MAX (u64)(~((u64)0))
16#endif
17
Andrew Lunncca8b132015-04-02 04:06:39 +020018#define SMI_CMD 0x00
19#define SMI_CMD_BUSY BIT(15)
20#define SMI_CMD_CLAUSE_22 BIT(12)
21#define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
22#define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
23#define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY)
24#define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY)
25#define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY)
26#define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY)
27#define SMI_DATA 0x01
Guenter Roeckb2eb0662015-04-02 04:06:30 +020028
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000029#define REG_PORT(p) (0x10 + (p))
Andrew Lunncca8b132015-04-02 04:06:39 +020030#define PORT_STATUS 0x00
31#define PORT_STATUS_PAUSE_EN BIT(15)
32#define PORT_STATUS_MY_PAUSE BIT(14)
33#define PORT_STATUS_HD_FLOW BIT(13)
34#define PORT_STATUS_PHY_DETECT BIT(12)
35#define PORT_STATUS_LINK BIT(11)
36#define PORT_STATUS_DUPLEX BIT(10)
37#define PORT_STATUS_SPEED_MASK 0x0300
38#define PORT_STATUS_SPEED_10 0x0000
39#define PORT_STATUS_SPEED_100 0x0100
40#define PORT_STATUS_SPEED_1000 0x0200
41#define PORT_STATUS_EEE BIT(6) /* 6352 */
42#define PORT_STATUS_AM_DIS BIT(6) /* 6165 */
43#define PORT_STATUS_MGMII BIT(6) /* 6185 */
44#define PORT_STATUS_TX_PAUSED BIT(5)
45#define PORT_STATUS_FLOW_CTRL BIT(4)
46#define PORT_PCS_CTRL 0x01
Andrew Lunn54d792f2015-05-06 01:09:47 +020047#define PORT_PCS_CTRL_FC BIT(7)
48#define PORT_PCS_CTRL_FORCE_FC BIT(6)
49#define PORT_PCS_CTRL_LINK_UP BIT(5)
50#define PORT_PCS_CTRL_FORCE_LINK BIT(4)
51#define PORT_PCS_CTRL_DUPLEX_FULL BIT(3)
52#define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2)
53#define PORT_PCS_CTRL_10 0x00
54#define PORT_PCS_CTRL_100 0x01
55#define PORT_PCS_CTRL_1000 0x02
56#define PORT_PCS_CTRL_UNFORCED 0x03
57#define PORT_PAUSE_CTRL 0x02
Andrew Lunncca8b132015-04-02 04:06:39 +020058#define PORT_SWITCH_ID 0x03
Andrew Lunn54d792f2015-05-06 01:09:47 +020059#define PORT_SWITCH_ID_6031 0x0310
60#define PORT_SWITCH_ID_6035 0x0350
61#define PORT_SWITCH_ID_6046 0x0480
62#define PORT_SWITCH_ID_6061 0x0610
63#define PORT_SWITCH_ID_6065 0x0650
Andrew Lunncca8b132015-04-02 04:06:39 +020064#define PORT_SWITCH_ID_6085 0x04a0
Andrew Lunn54d792f2015-05-06 01:09:47 +020065#define PORT_SWITCH_ID_6092 0x0970
Andrew Lunncca8b132015-04-02 04:06:39 +020066#define PORT_SWITCH_ID_6095 0x0950
Andrew Lunn54d792f2015-05-06 01:09:47 +020067#define PORT_SWITCH_ID_6096 0x0980
68#define PORT_SWITCH_ID_6097 0x0990
69#define PORT_SWITCH_ID_6108 0x1070
70#define PORT_SWITCH_ID_6121 0x1040
71#define PORT_SWITCH_ID_6122 0x1050
Andrew Lunncca8b132015-04-02 04:06:39 +020072#define PORT_SWITCH_ID_6123 0x1210
73#define PORT_SWITCH_ID_6123_A1 0x1212
74#define PORT_SWITCH_ID_6123_A2 0x1213
75#define PORT_SWITCH_ID_6131 0x1060
76#define PORT_SWITCH_ID_6131_B2 0x1066
77#define PORT_SWITCH_ID_6152 0x1a40
78#define PORT_SWITCH_ID_6155 0x1a50
79#define PORT_SWITCH_ID_6161 0x1610
80#define PORT_SWITCH_ID_6161_A1 0x1612
81#define PORT_SWITCH_ID_6161_A2 0x1613
82#define PORT_SWITCH_ID_6165 0x1650
83#define PORT_SWITCH_ID_6165_A1 0x1652
84#define PORT_SWITCH_ID_6165_A2 0x1653
85#define PORT_SWITCH_ID_6171 0x1710
86#define PORT_SWITCH_ID_6172 0x1720
Andrew Lunn54d792f2015-05-06 01:09:47 +020087#define PORT_SWITCH_ID_6175 0x1750
Andrew Lunncca8b132015-04-02 04:06:39 +020088#define PORT_SWITCH_ID_6176 0x1760
89#define PORT_SWITCH_ID_6182 0x1a60
90#define PORT_SWITCH_ID_6185 0x1a70
Andrew Lunn54d792f2015-05-06 01:09:47 +020091#define PORT_SWITCH_ID_6240 0x2400
Aleksey S. Kazantsev7c3d0d62015-07-07 20:38:15 -070092#define PORT_SWITCH_ID_6320 0x1150
93#define PORT_SWITCH_ID_6320_A1 0x1151
94#define PORT_SWITCH_ID_6320_A2 0x1152
95#define PORT_SWITCH_ID_6321 0x3100
96#define PORT_SWITCH_ID_6321_A1 0x3101
97#define PORT_SWITCH_ID_6321_A2 0x3102
Andrew Lunn54d792f2015-05-06 01:09:47 +020098#define PORT_SWITCH_ID_6350 0x3710
99#define PORT_SWITCH_ID_6351 0x3750
Andrew Lunncca8b132015-04-02 04:06:39 +0200100#define PORT_SWITCH_ID_6352 0x3520
101#define PORT_SWITCH_ID_6352_A0 0x3521
102#define PORT_SWITCH_ID_6352_A1 0x3522
103#define PORT_CONTROL 0x04
Andrew Lunn54d792f2015-05-06 01:09:47 +0200104#define PORT_CONTROL_USE_CORE_TAG BIT(15)
105#define PORT_CONTROL_DROP_ON_LOCK BIT(14)
106#define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12)
107#define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12)
108#define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12)
109#define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12)
110#define PORT_CONTROL_HEADER BIT(11)
111#define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10)
112#define PORT_CONTROL_DOUBLE_TAG BIT(9)
113#define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8)
114#define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8)
115#define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8)
116#define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8)
117#define PORT_CONTROL_DSA_TAG BIT(8)
118#define PORT_CONTROL_VLAN_TUNNEL BIT(7)
119#define PORT_CONTROL_TAG_IF_BOTH BIT(6)
120#define PORT_CONTROL_USE_IP BIT(5)
121#define PORT_CONTROL_USE_TAG BIT(4)
122#define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3)
123#define PORT_CONTROL_FORWARD_UNKNOWN BIT(2)
Andrew Lunncca8b132015-04-02 04:06:39 +0200124#define PORT_CONTROL_STATE_MASK 0x03
125#define PORT_CONTROL_STATE_DISABLED 0x00
126#define PORT_CONTROL_STATE_BLOCKING 0x01
127#define PORT_CONTROL_STATE_LEARNING 0x02
128#define PORT_CONTROL_STATE_FORWARDING 0x03
129#define PORT_CONTROL_1 0x05
130#define PORT_BASE_VLAN 0x06
131#define PORT_DEFAULT_VLAN 0x07
132#define PORT_CONTROL_2 0x08
Andrew Lunn54d792f2015-05-06 01:09:47 +0200133#define PORT_CONTROL_2_IGNORE_FCS BIT(15)
134#define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14)
135#define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13)
136#define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12)
137#define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12)
138#define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12)
139#define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12)
140#define PORT_CONTROL_2_DISCARD_TAGGED BIT(9)
141#define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8)
142#define PORT_CONTROL_2_MAP_DA BIT(7)
143#define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6)
144#define PORT_CONTROL_2_FORWARD_UNKNOWN BIT(6)
145#define PORT_CONTROL_2_EGRESS_MONITOR BIT(5)
146#define PORT_CONTROL_2_INGRESS_MONITOR BIT(4)
Andrew Lunncca8b132015-04-02 04:06:39 +0200147#define PORT_RATE_CONTROL 0x09
148#define PORT_RATE_CONTROL_2 0x0a
149#define PORT_ASSOC_VECTOR 0x0b
Andrew Lunn54d792f2015-05-06 01:09:47 +0200150#define PORT_ATU_CONTROL 0x0c
151#define PORT_PRI_OVERRIDE 0x0d
152#define PORT_ETH_TYPE 0x0f
Andrew Lunncca8b132015-04-02 04:06:39 +0200153#define PORT_IN_DISCARD_LO 0x10
154#define PORT_IN_DISCARD_HI 0x11
155#define PORT_IN_FILTERED 0x12
156#define PORT_OUT_FILTERED 0x13
Andrew Lunn54d792f2015-05-06 01:09:47 +0200157#define PORT_TAG_REGMAP_0123 0x18
158#define PORT_TAG_REGMAP_4567 0x19
Andrew Lunncca8b132015-04-02 04:06:39 +0200159
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000160#define REG_GLOBAL 0x1b
Andrew Lunncca8b132015-04-02 04:06:39 +0200161#define GLOBAL_STATUS 0x00
162#define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */
163/* Two bits for 6165, 6185 etc */
164#define GLOBAL_STATUS_PPU_MASK (0x3 << 14)
165#define GLOBAL_STATUS_PPU_DISABLED_RST (0x0 << 14)
166#define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14)
167#define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14)
168#define GLOBAL_STATUS_PPU_POLLING (0x3 << 14)
169#define GLOBAL_MAC_01 0x01
170#define GLOBAL_MAC_23 0x02
171#define GLOBAL_MAC_45 0x03
172#define GLOBAL_CONTROL 0x04
173#define GLOBAL_CONTROL_SW_RESET BIT(15)
174#define GLOBAL_CONTROL_PPU_ENABLE BIT(14)
175#define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */
176#define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */
177#define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */
Andrew Lunn54d792f2015-05-06 01:09:47 +0200178#define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */
Andrew Lunncca8b132015-04-02 04:06:39 +0200179#define GLOBAL_CONTROL_DEVICE_EN BIT(7)
180#define GLOBAL_CONTROL_STATS_DONE_EN BIT(6)
181#define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5)
182#define GLOBAL_CONTROL_VTU_DONE_EN BIT(4)
183#define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3)
184#define GLOBAL_CONTROL_ATU_DONE_EN BIT(2)
185#define GLOBAL_CONTROL_TCAM_EN BIT(1)
186#define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0)
187#define GLOBAL_VTU_OP 0x05
188#define GLOBAL_VTU_VID 0x06
189#define GLOBAL_VTU_DATA_0_3 0x07
190#define GLOBAL_VTU_DATA_4_7 0x08
191#define GLOBAL_VTU_DATA_8_11 0x09
192#define GLOBAL_ATU_CONTROL 0x0a
Andrew Lunn54d792f2015-05-06 01:09:47 +0200193#define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3)
Andrew Lunncca8b132015-04-02 04:06:39 +0200194#define GLOBAL_ATU_OP 0x0b
195#define GLOBAL_ATU_OP_BUSY BIT(15)
196#define GLOBAL_ATU_OP_NOP (0 << 12)
197#define GLOBAL_ATU_OP_FLUSH_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY)
198#define GLOBAL_ATU_OP_FLUSH_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY)
199#define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY)
200#define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY)
201#define GLOBAL_ATU_OP_FLUSH_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY)
202#define GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
203#define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY)
204#define GLOBAL_ATU_DATA 0x0c
Andrew Lunn8a0a2652015-06-20 18:42:29 +0200205#define GLOBAL_ATU_DATA_TRUNK BIT(15)
206#define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0
207#define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4
Andrew Lunncca8b132015-04-02 04:06:39 +0200208#define GLOBAL_ATU_DATA_STATE_MASK 0x0f
209#define GLOBAL_ATU_DATA_STATE_UNUSED 0x00
210#define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d
211#define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e
212#define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f
213#define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05
214#define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07
215#define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e
216#define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f
217#define GLOBAL_ATU_MAC_01 0x0d
218#define GLOBAL_ATU_MAC_23 0x0e
219#define GLOBAL_ATU_MAC_45 0x0f
220#define GLOBAL_IP_PRI_0 0x10
221#define GLOBAL_IP_PRI_1 0x11
222#define GLOBAL_IP_PRI_2 0x12
223#define GLOBAL_IP_PRI_3 0x13
224#define GLOBAL_IP_PRI_4 0x14
225#define GLOBAL_IP_PRI_5 0x15
226#define GLOBAL_IP_PRI_6 0x16
227#define GLOBAL_IP_PRI_7 0x17
228#define GLOBAL_IEEE_PRI 0x18
229#define GLOBAL_CORE_TAG_TYPE 0x19
230#define GLOBAL_MONITOR_CONTROL 0x1a
Andrew Lunn15966a22015-05-06 01:09:49 +0200231#define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12
232#define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8
233#define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4
234#define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0
235#define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0)
Andrew Lunncca8b132015-04-02 04:06:39 +0200236#define GLOBAL_CONTROL_2 0x1c
Andrew Lunn15966a22015-05-06 01:09:49 +0200237#define GLOBAL_CONTROL_2_NO_CASCADE 0xe000
238#define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000
239
Andrew Lunncca8b132015-04-02 04:06:39 +0200240#define GLOBAL_STATS_OP 0x1d
241#define GLOBAL_STATS_OP_BUSY BIT(15)
242#define GLOBAL_STATS_OP_NOP (0 << 12)
243#define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY)
244#define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY)
245#define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY)
246#define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY)
247#define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY)
248#define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY)
249#define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY)
250#define GLOBAL_STATS_COUNTER_32 0x1e
251#define GLOBAL_STATS_COUNTER_01 0x1f
252
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000253#define REG_GLOBAL2 0x1c
Andrew Lunncca8b132015-04-02 04:06:39 +0200254#define GLOBAL2_INT_SOURCE 0x00
255#define GLOBAL2_INT_MASK 0x01
256#define GLOBAL2_MGMT_EN_2X 0x02
257#define GLOBAL2_MGMT_EN_0X 0x03
258#define GLOBAL2_FLOW_CONTROL 0x04
259#define GLOBAL2_SWITCH_MGMT 0x05
Andrew Lunn54d792f2015-05-06 01:09:47 +0200260#define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15)
261#define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS BIT(14)
262#define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG BIT(13)
263#define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7)
264#define GLOBAL2_SWITCH_MGMT_RSVD2CPU BIT(3)
Andrew Lunncca8b132015-04-02 04:06:39 +0200265#define GLOBAL2_DEVICE_MAPPING 0x06
Andrew Lunn54d792f2015-05-06 01:09:47 +0200266#define GLOBAL2_DEVICE_MAPPING_UPDATE BIT(15)
267#define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT 8
Andrew Lunnd35bd872015-06-20 18:42:32 +0200268#define GLOBAL2_DEVICE_MAPPING_PORT_MASK 0x0f
Andrew Lunncca8b132015-04-02 04:06:39 +0200269#define GLOBAL2_TRUNK_MASK 0x07
Andrew Lunn54d792f2015-05-06 01:09:47 +0200270#define GLOBAL2_TRUNK_MASK_UPDATE BIT(15)
271#define GLOBAL2_TRUNK_MASK_NUM_SHIFT 12
Andrew Lunncca8b132015-04-02 04:06:39 +0200272#define GLOBAL2_TRUNK_MAPPING 0x08
Andrew Lunn54d792f2015-05-06 01:09:47 +0200273#define GLOBAL2_TRUNK_MAPPING_UPDATE BIT(15)
274#define GLOBAL2_TRUNK_MAPPING_ID_SHIFT 11
Andrew Lunncca8b132015-04-02 04:06:39 +0200275#define GLOBAL2_INGRESS_OP 0x09
276#define GLOBAL2_INGRESS_DATA 0x0a
277#define GLOBAL2_PVT_ADDR 0x0b
278#define GLOBAL2_PVT_DATA 0x0c
279#define GLOBAL2_SWITCH_MAC 0x0d
280#define GLOBAL2_SWITCH_MAC_BUSY BIT(15)
281#define GLOBAL2_ATU_STATS 0x0e
282#define GLOBAL2_PRIO_OVERRIDE 0x0f
Andrew Lunn15966a22015-05-06 01:09:49 +0200283#define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7)
284#define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT 4
285#define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP BIT(3)
286#define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT 0
Andrew Lunncca8b132015-04-02 04:06:39 +0200287#define GLOBAL2_EEPROM_OP 0x14
288#define GLOBAL2_EEPROM_OP_BUSY BIT(15)
289#define GLOBAL2_EEPROM_OP_LOAD BIT(11)
290#define GLOBAL2_EEPROM_DATA 0x15
291#define GLOBAL2_PTP_AVB_OP 0x16
292#define GLOBAL2_PTP_AVB_DATA 0x17
293#define GLOBAL2_SMI_OP 0x18
294#define GLOBAL2_SMI_OP_BUSY BIT(15)
295#define GLOBAL2_SMI_OP_CLAUSE_22 BIT(12)
296#define GLOBAL2_SMI_OP_22_WRITE ((1 << 10) | GLOBAL2_SMI_OP_BUSY | \
297 GLOBAL2_SMI_OP_CLAUSE_22)
298#define GLOBAL2_SMI_OP_22_READ ((2 << 10) | GLOBAL2_SMI_OP_BUSY | \
299 GLOBAL2_SMI_OP_CLAUSE_22)
300#define GLOBAL2_SMI_OP_45_WRITE_ADDR ((0 << 10) | GLOBAL2_SMI_OP_BUSY)
301#define GLOBAL2_SMI_OP_45_WRITE_DATA ((1 << 10) | GLOBAL2_SMI_OP_BUSY)
302#define GLOBAL2_SMI_OP_45_READ_DATA ((2 << 10) | GLOBAL2_SMI_OP_BUSY)
303#define GLOBAL2_SMI_DATA 0x19
304#define GLOBAL2_SCRATCH_MISC 0x1a
Andrew Lunn56d95e22015-06-20 18:42:33 +0200305#define GLOBAL2_SCRATCH_BUSY BIT(15)
306#define GLOBAL2_SCRATCH_REGISTER_SHIFT 8
307#define GLOBAL2_SCRATCH_VALUE_MASK 0xff
Andrew Lunncca8b132015-04-02 04:06:39 +0200308#define GLOBAL2_WDOG_CONTROL 0x1b
309#define GLOBAL2_QOS_WEIGHT 0x1c
310#define GLOBAL2_MISC 0x1d
Guenter Roeckdefb05b2015-03-26 18:36:38 -0700311
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000312struct mv88e6xxx_priv_state {
Barry Grussling3675c8d2013-01-08 16:05:53 +0000313 /* When using multi-chip addressing, this mutex protects
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000314 * access to the indirect access registers. (In single-chip
315 * mode, this mutex is effectively useless.)
316 */
317 struct mutex smi_mutex;
318
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000319#ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
Barry Grussling3675c8d2013-01-08 16:05:53 +0000320 /* Handles automatic disabling and re-enabling of the PHY
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000321 * polling unit.
322 */
323 struct mutex ppu_mutex;
324 int ppu_disabled;
325 struct work_struct ppu_work;
326 struct timer_list ppu_timer;
327#endif
328
Barry Grussling3675c8d2013-01-08 16:05:53 +0000329 /* This mutex serialises access to the statistics unit.
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000330 * Hold this mutex over snapshot + dump sequences.
331 */
332 struct mutex stats_mutex;
Peter Korsgaardec80bfc2011-04-05 03:03:56 +0000333
Guenter Roeck3ad50cc2014-10-29 10:44:56 -0700334 /* This mutex serializes phy access for chips with
335 * indirect phy addressing. It is unused for chips
336 * with direct phy access.
337 */
338 struct mutex phy_mutex;
339
Guenter Roeck33b43df2014-10-29 10:45:03 -0700340 /* This mutex serializes eeprom access for chips with
341 * eeprom support.
342 */
343 struct mutex eeprom_mutex;
344
Peter Korsgaardec80bfc2011-04-05 03:03:56 +0000345 int id; /* switch product id */
Guenter Roeckd1988932015-04-02 04:06:31 +0200346 int num_ports; /* number of switch ports */
Guenter Roeckfacd95b2015-03-26 18:36:35 -0700347
348 /* hw bridging */
349
350 u32 fid_mask;
351 u8 fid[DSA_MAX_PORTS];
352 u16 bridge_mask[DSA_MAX_PORTS];
353
354 unsigned long port_state_update_mask;
355 u8 port_state[DSA_MAX_PORTS];
356
357 struct work_struct bridge_work;
Andrew Lunn87c8cef2015-06-20 18:42:28 +0200358
359 struct dentry *dbgfs;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000360};
361
362struct mv88e6xxx_hw_stat {
363 char string[ETH_GSTRING_LEN];
364 int sizeof_stat;
365 int reg;
366};
367
Andrew Lunn143a8302015-04-02 04:06:34 +0200368int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active);
Andrew Lunndbde9e62015-05-06 01:09:48 +0200369int mv88e6xxx_setup_ports(struct dsa_switch *ds);
Guenter Roeckacdaffc2015-03-26 18:36:28 -0700370int mv88e6xxx_setup_common(struct dsa_switch *ds);
Andrew Lunn54d792f2015-05-06 01:09:47 +0200371int mv88e6xxx_setup_global(struct dsa_switch *ds);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000372int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg);
373int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg);
374int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
Barry Grussling85686582013-01-08 16:05:56 +0000375 int reg, u16 val);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000376int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000377int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000378int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr);
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +0200379int mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum);
380int mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val);
381int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum);
382int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
383 u16 val);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000384void mv88e6xxx_ppu_state_init(struct dsa_switch *ds);
385int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum);
386int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
387 int regnum, u16 val);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000388void mv88e6xxx_poll_link(struct dsa_switch *ds);
Andrew Lunne413e7e2015-04-02 04:06:38 +0200389void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data);
390void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
391 uint64_t *data);
392int mv88e6xxx_get_sset_count(struct dsa_switch *ds);
393int mv88e6xxx_get_sset_count_basic(struct dsa_switch *ds);
Guenter Roecka1ab91f2014-10-29 10:45:05 -0700394int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port);
395void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
396 struct ethtool_regs *regs, void *_p);
Andrew Lunneaa23762014-11-15 22:24:51 +0100397int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp);
Andrew Lunnf3044682015-02-14 19:17:50 +0100398int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds);
399int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds);
400int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum);
401int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum,
402 u16 val);
Guenter Roeck11b3b452015-03-06 22:23:51 -0800403int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e);
404int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
405 struct phy_device *phydev, struct ethtool_eee *e);
Guenter Roeckfacd95b2015-03-26 18:36:35 -0700406int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask);
407int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask);
408int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state);
Guenter Roeckdefb05b2015-03-26 18:36:38 -0700409int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
410 const unsigned char *addr, u16 vid);
411int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
412 const unsigned char *addr, u16 vid);
413int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
414 unsigned char *addr, bool *is_static);
Andrew Lunn491435852015-04-02 04:06:35 +0200415int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg);
416int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
417 int reg, int val);
Aleksey S. Kazantsev7c3d0d62015-07-07 20:38:15 -0700418bool mv88e6xxx_6320_family(struct dsa_switch *ds);
Ben Hutchings98e67302011-11-25 14:36:19 +0000419extern struct dsa_switch_driver mv88e6131_switch_driver;
420extern struct dsa_switch_driver mv88e6123_61_65_switch_driver;
Guenter Roeck3ad50cc2014-10-29 10:44:56 -0700421extern struct dsa_switch_driver mv88e6352_switch_driver;
Andrew Lunn42f27252014-09-12 23:58:44 +0200422extern struct dsa_switch_driver mv88e6171_switch_driver;
Ben Hutchings98e67302011-11-25 14:36:19 +0000423
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000424#define REG_READ(addr, reg) \
425 ({ \
426 int __ret; \
427 \
428 __ret = mv88e6xxx_reg_read(ds, addr, reg); \
429 if (__ret < 0) \
430 return __ret; \
431 __ret; \
432 })
433
434#define REG_WRITE(addr, reg, val) \
435 ({ \
436 int __ret; \
437 \
438 __ret = mv88e6xxx_reg_write(ds, addr, reg, val); \
439 if (__ret < 0) \
440 return __ret; \
441 })
442
443
444
445#endif