- f1a0a37 sched/core: Initialize the idle task with preemption disabled by Valentin Schneider · 3 years, 8 months ago
- 6f4eea9 riscv: Introduce alternative mechanism to apply errata solution by Vincent Chen · 3 years, 10 months ago
- 4f0e8ee riscv: Add numa support for riscv64 platform by Atish Patra · 4 years, 2 months ago
- 2bc3fc8 RISC-V: Remove CLINT related code from timer and arch by Anup Patel · 4 years, 5 months ago
- cc7f3f7 RISC-V: Add mechanism to provide custom IPI operations by Anup Patel · 4 years, 5 months ago
- 635093e RISC-V: Fix build warning for smpboot.c by Atish Patra · 4 years, 6 months ago
- 79b1feb RISC-V: Setup exception vector early by Atish Patra · 4 years, 6 months ago
- c159599 riscv: Fixup lockdep_assert_held with wrong param cpu_running by Zong Li · 4 years, 7 months ago
- a2693fe RISC-V: Use a local variable instead of smp_processor_id() by Greentime Hu · 4 years, 7 months ago
- cfafe26 RISC-V: Add supported for ordered booting method using HSM by Atish Patra · 4 years, 10 months ago
- 2875fe0 RISC-V: Add cpu_ops and modify default booting method by Atish Patra · 4 years, 10 months ago
- fcdc653 riscv: provide native clint access for M-mode by Christoph Hellwig · 5 years ago
- f307307 riscv: for C functions called only from assembly, mark with __visible by Paul Walmsley · 5 years ago
- 5ed881b riscv: add missing header file includes by Paul Walmsley · 5 years ago
- ffaee27 riscv: add prototypes for assembly language functions from head.S by Paul Walmsley · 5 years ago
- 03f11f0 RISC-V: Parse cpu topology during boot. by Atish Patra · 6 years ago
- 1802d0b treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 by Thomas Gleixner · 6 years ago
- 8b4302a RISC-V: Support nr_cpus command line option. by Atish Patra · 6 years ago
- ab3d265 RISC-V: Implement nosmp commandline option. by Atish Patra · 6 years ago
- 291debb RISC-V: Compare cpuid with NR_CPUS before mapping. by Atish Patra · 6 years ago
- e15c6e3 RISC-V: Do not wait indefinitely in __cpu_up by Atish Patra · 6 years ago
- dd81c8a riscv: use for_each_of_cpu_node iterator by Johan Hovold · 6 years ago
- 2bb1063 RISC-V: fix bad use of of_node_put by Andreas Schwab · 6 years ago
- 94f9bf1 RISC-V: Fix of_node_* refcount by Atish Patra · 6 years ago
- f99fb60 RISC-V: Use Linux logical CPU number instead of hartid by Atish Patra · 6 years ago
- a37d56f RISC-V: Use WRITE_ONCE instead of direct access by Atish Patra · 6 years ago
- 46373cb RISC-V: Use mmgrab() by Palmer Dabbelt · 6 years ago
- 177fae45 RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu by Palmer Dabbelt · 6 years ago
- b2f8cfa7 RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid by Palmer Dabbelt · 6 years ago
- 6db170f RISC-V: Disable preemption before enabling interrupts by Atish Patra · 6 years ago
- b18d6f0 RISC-V: Comment on the TLB flush in smp_callin() by Palmer Dabbelt · 6 years ago
- 62b0194 clocksource: new RISC-V SBI timer driver by Palmer Dabbelt · 6 years ago
- 76d2a04 RISC-V: Init and Halt Code by Palmer Dabbelt · 8 years ago