| commit | a37d56fc401108f39dec9ba83ed923a453937a26 | [log] [tgz] |
|---|---|---|
| author | Atish Patra <atish.patra@wdc.com> | Tue Oct 02 12:15:03 2018 -0700 |
| committer | Palmer Dabbelt <palmer@sifive.com> | Mon Oct 22 17:03:37 2018 -0700 |
| tree | b050e592dc352a44bddc333ead5602abbab2e7a4 | |
| parent | 46373cb442c56d2f8a4c8b3f777c89d20546c9d5 [diff] |
RISC-V: Use WRITE_ONCE instead of direct access The secondary harts spin on couple of per cpu variables until both of these are non-zero so it's not necessary to have any ordering here. However, WRITE_ONCE should be used to avoid tearing. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>