| Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Jonathan Cameron | 0b5e92c5 | 2009-04-27 13:49:44 +0000 | [diff] [blame] | 2 | /* |
| 3 | * wm8940.h -- WM8940 Soc Audio driver |
| Jonathan Cameron | 0b5e92c5 | 2009-04-27 13:49:44 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _WM8940_H |
| 7 | #define _WM8940_H |
| 8 | |
| 9 | struct wm8940_setup_data { |
| 10 | /* Vref to analogue output resistance */ |
| 11 | #define WM8940_VROI_1K 0 |
| 12 | #define WM8940_VROI_30K 1 |
| 13 | unsigned int vroi:1; |
| 14 | }; |
| Jonathan Cameron | 0b5e92c5 | 2009-04-27 13:49:44 +0000 | [diff] [blame] | 15 | |
| 16 | /* WM8940 register space */ |
| 17 | #define WM8940_SOFTRESET 0x00 |
| 18 | #define WM8940_POWER1 0x01 |
| 19 | #define WM8940_POWER2 0x02 |
| 20 | #define WM8940_POWER3 0x03 |
| 21 | #define WM8940_IFACE 0x04 |
| 22 | #define WM8940_COMPANDINGCTL 0x05 |
| 23 | #define WM8940_CLOCK 0x06 |
| 24 | #define WM8940_ADDCNTRL 0x07 |
| 25 | #define WM8940_GPIO 0x08 |
| 26 | #define WM8940_CTLINT 0x09 |
| 27 | #define WM8940_DAC 0x0A |
| 28 | #define WM8940_DACVOL 0x0B |
| 29 | |
| 30 | #define WM8940_ADC 0x0E |
| 31 | #define WM8940_ADCVOL 0x0F |
| 32 | #define WM8940_NOTCH1 0x10 |
| 33 | #define WM8940_NOTCH2 0x11 |
| 34 | #define WM8940_NOTCH3 0x12 |
| 35 | #define WM8940_NOTCH4 0x13 |
| 36 | #define WM8940_NOTCH5 0x14 |
| 37 | #define WM8940_NOTCH6 0x15 |
| 38 | #define WM8940_NOTCH7 0x16 |
| 39 | #define WM8940_NOTCH8 0x17 |
| 40 | #define WM8940_DACLIM1 0x18 |
| 41 | #define WM8940_DACLIM2 0x19 |
| 42 | |
| 43 | #define WM8940_ALC1 0x20 |
| 44 | #define WM8940_ALC2 0x21 |
| 45 | #define WM8940_ALC3 0x22 |
| 46 | #define WM8940_NOISEGATE 0x23 |
| 47 | #define WM8940_PLLN 0x24 |
| 48 | #define WM8940_PLLK1 0x25 |
| 49 | #define WM8940_PLLK2 0x26 |
| 50 | #define WM8940_PLLK3 0x27 |
| 51 | |
| 52 | #define WM8940_ALC4 0x2A |
| 53 | |
| 54 | #define WM8940_INPUTCTL 0x2C |
| 55 | #define WM8940_PGAGAIN 0x2D |
| 56 | |
| 57 | #define WM8940_ADCBOOST 0x2F |
| 58 | |
| 59 | #define WM8940_OUTPUTCTL 0x31 |
| 60 | #define WM8940_SPKMIX 0x32 |
| 61 | |
| 62 | #define WM8940_SPKVOL 0x36 |
| 63 | |
| 64 | #define WM8940_MONOMIX 0x38 |
| 65 | |
| 66 | #define WM8940_CACHEREGNUM 0x57 |
| 67 | |
| 68 | |
| 69 | /* Clock divider Id's */ |
| 70 | #define WM8940_BCLKDIV 0 |
| 71 | #define WM8940_MCLKDIV 1 |
| 72 | #define WM8940_OPCLKDIV 2 |
| 73 | |
| 74 | /* MCLK clock dividers */ |
| 75 | #define WM8940_MCLKDIV_1 0 |
| 76 | #define WM8940_MCLKDIV_1_5 1 |
| 77 | #define WM8940_MCLKDIV_2 2 |
| 78 | #define WM8940_MCLKDIV_3 3 |
| 79 | #define WM8940_MCLKDIV_4 4 |
| 80 | #define WM8940_MCLKDIV_6 5 |
| 81 | #define WM8940_MCLKDIV_8 6 |
| 82 | #define WM8940_MCLKDIV_12 7 |
| 83 | |
| 84 | /* BCLK clock dividers */ |
| 85 | #define WM8940_BCLKDIV_1 0 |
| 86 | #define WM8940_BCLKDIV_2 1 |
| 87 | #define WM8940_BCLKDIV_4 2 |
| 88 | #define WM8940_BCLKDIV_8 3 |
| 89 | #define WM8940_BCLKDIV_16 4 |
| 90 | #define WM8940_BCLKDIV_32 5 |
| 91 | |
| 92 | /* PLL Out Dividers */ |
| 93 | #define WM8940_OPCLKDIV_1 0 |
| 94 | #define WM8940_OPCLKDIV_2 1 |
| 95 | #define WM8940_OPCLKDIV_3 2 |
| 96 | #define WM8940_OPCLKDIV_4 3 |
| 97 | |
| 98 | #endif /* _WM8940_H */ |
| 99 | |