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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / ffc58bc4af9365d4eea72526bb3cf6a83615c673 / . / drivers / pinctrl / pinctrl-thunderbay.c
blob: b5b47f4dd77497370cecae0768f94e17b0f32e89 [file] [log] [blame]
Lakshmi Sowjanya D12422af2021-12-01 12:56:26 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel Thunder Bay SOC pinctrl/GPIO driver
4 *
5 * Copyright (C) 2021 Intel Corporation
6 */
7
8#include <linux/device.h>
9#include <linux/err.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_irq.h>
18
19#include <linux/pinctrl/pinconf.h>
20#include <linux/pinctrl/pinconf-generic.h>
21#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinmux.h>
23
24#include <linux/platform_device.h>
25#include <linux/slab.h>
26#include <linux/spinlock.h>
27
28#include "core.h"
29#include "pinconf.h"
30#include "pinctrl-utils.h"
31#include "pinmux.h"
32
33/* Bit 0:2 and 4:6 should be used for mode selection */
34#define THB_GPIO_PINMUX_MODE_0 0x00
35#define THB_GPIO_PINMUX_MODE_1 0x11
36#define THB_GPIO_PINMUX_MODE_2 0x22
37#define THB_GPIO_PINMUX_MODE_3 0x33
38#define THB_GPIO_PINMUX_MODE_4 0x44
39
40#define THB_GPIO_PORT_SELECT_MASK BIT(8)
41#define THB_GPIO_PAD_DIRECTION_MASK BIT(10)
42#define THB_GPIO_SPU_MASK BIT(11)
43#define THB_GPIO_PULL_ENABLE_MASK BIT(12)
44#define THB_GPIO_PULL_UP_MASK BIT(13)
45#define THB_GPIO_PULL_DOWN_MASK BIT(14)
46#define THB_GPIO_ENAQ_MASK BIT(15)
47/* bit 16-19: Drive Strength for the Pad */
48#define THB_GPIO_DRIVE_STRENGTH_MASK (0xF0000)
49#define THB_GPIO_SLEW_RATE_MASK BIT(20)
50#define THB_GPIO_SCHMITT_TRIGGER_MASK BIT(21)
51
52#define THB_GPIO_REG_OFFSET(pin_num) ((pin_num) * (0x4))
53#define THB_MAX_MODE_SUPPORTED (5u)
54#define THB_MAX_NPINS_SUPPORTED (67u)
55
56/* store Pin status */
57static u32 thb_pinx_status[THB_MAX_NPINS_SUPPORTED];
58
59struct thunderbay_mux_desc {
60 u8 mode;
61 const char *name;
62};
63
64#define THUNDERBAY_PIN_DESC(pin_number, pin_name, ...) { \
65 .number = pin_number, \
66 .name = pin_name, \
67 .drv_data = &(struct thunderbay_mux_desc[]) { \
68 __VA_ARGS__, { } }, \
69}
70
71#define THUNDERBAY_MUX(pin_mode, pin_function) { \
72 .mode = pin_mode, \
73 .name = pin_function, \
74}
75
76struct thunderbay_pin_soc {
77 const struct pinctrl_pin_desc *pins;
78 unsigned int npins;
79};
80
81/**
82 * struct thunderbay_pinctrl - Intel Thunderbay pinctrl structure
83 * @pctrl: Pointer to the pin controller device
84 * @base0: First register base address
85 * @dev: Pointer to the device structure
86 * @chip: GPIO chip used by this pin controller
87 * @soc: Pin control configuration data based on SoC
88 * @ngroups: Number of pin groups available
89 * @nfuncs: Number of pin functions available
90 */
91struct thunderbay_pinctrl {
92 struct pinctrl_dev *pctrl;
93 void __iomem *base0;
94 struct device *dev;
95 struct gpio_chip chip;
96 const struct thunderbay_pin_soc *soc;
97 unsigned int ngroups;
98 unsigned int nfuncs;
99};
100
101static const struct pinctrl_pin_desc thunderbay_pins[] = {
102 THUNDERBAY_PIN_DESC(0, "GPIO0",
103 THUNDERBAY_MUX(0X0, "I2C0_M0"),
104 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
105 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
106 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
107 THUNDERBAY_MUX(0X4, "GPIO_M4")),
108 THUNDERBAY_PIN_DESC(1, "GPIO1",
109 THUNDERBAY_MUX(0X0, "I2C0_M0"),
110 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
111 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
112 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
113 THUNDERBAY_MUX(0X4, "GPIO_M4")),
114 THUNDERBAY_PIN_DESC(2, "GPIO2",
115 THUNDERBAY_MUX(0X0, "I2C1_M0"),
116 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
117 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
118 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
119 THUNDERBAY_MUX(0X4, "GPIO_M4")),
120 THUNDERBAY_PIN_DESC(3, "GPIO3",
121 THUNDERBAY_MUX(0X0, "I2C1_M0"),
122 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
123 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
124 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
125 THUNDERBAY_MUX(0X4, "GPIO_M4")),
126 THUNDERBAY_PIN_DESC(4, "GPIO4",
127 THUNDERBAY_MUX(0X0, "I2C2_M0"),
128 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
129 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
130 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
131 THUNDERBAY_MUX(0X4, "GPIO_M4")),
132 THUNDERBAY_PIN_DESC(5, "GPIO5",
133 THUNDERBAY_MUX(0X0, "I2C2_M0"),
134 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
135 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
136 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
137 THUNDERBAY_MUX(0X4, "GPIO_M4")),
138 THUNDERBAY_PIN_DESC(6, "GPIO6",
139 THUNDERBAY_MUX(0X0, "I2C3_M0"),
140 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
141 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
142 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
143 THUNDERBAY_MUX(0X4, "GPIO_M4")),
144 THUNDERBAY_PIN_DESC(7, "GPIO7",
145 THUNDERBAY_MUX(0X0, "I2C3_M0"),
146 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
147 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
148 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
149 THUNDERBAY_MUX(0X4, "GPIO_M4")),
150 THUNDERBAY_PIN_DESC(8, "GPIO8",
151 THUNDERBAY_MUX(0X0, "I2C4_M0"),
152 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
153 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
154 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
155 THUNDERBAY_MUX(0X4, "GPIO_M4")),
156 THUNDERBAY_PIN_DESC(9, "GPIO9",
157 THUNDERBAY_MUX(0X0, "I2C4_M0"),
158 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
159 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
160 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
161 THUNDERBAY_MUX(0X4, "GPIO_M4")),
162 THUNDERBAY_PIN_DESC(10, "GPIO10",
163 THUNDERBAY_MUX(0X0, "UART0_M0"),
164 THUNDERBAY_MUX(0X1, "RT0_DSU_M1"),
165 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
166 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
167 THUNDERBAY_MUX(0X4, "GPIO_M4")),
168 THUNDERBAY_PIN_DESC(11, "GPIO11",
169 THUNDERBAY_MUX(0X0, "UART0_M0"),
170 THUNDERBAY_MUX(0X1, "RT0_DSU_M1"),
171 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
172 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
173 THUNDERBAY_MUX(0X4, "GPIO_M4")),
174 THUNDERBAY_PIN_DESC(12, "GPIO12",
175 THUNDERBAY_MUX(0X0, "UART0_M0"),
176 THUNDERBAY_MUX(0X1, "RT1_DSU_M1"),
177 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
178 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
179 THUNDERBAY_MUX(0X4, "GPIO_M4")),
180 THUNDERBAY_PIN_DESC(13, "GPIO13",
181 THUNDERBAY_MUX(0X0, "UART0_M0"),
182 THUNDERBAY_MUX(0X1, "RT1_DSU_M1"),
183 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
184 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
185 THUNDERBAY_MUX(0X4, "GPIO_M4")),
186 THUNDERBAY_PIN_DESC(14, "GPIO14",
187 THUNDERBAY_MUX(0X0, "UART1_M0"),
188 THUNDERBAY_MUX(0X1, "RT2_DSU_M1"),
189 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
190 THUNDERBAY_MUX(0X3, "TRIGGER_M3"),
191 THUNDERBAY_MUX(0X4, "GPIO_M4")),
192 THUNDERBAY_PIN_DESC(15, "GPIO15",
193 THUNDERBAY_MUX(0X0, "UART1_M0"),
194 THUNDERBAY_MUX(0X1, "RT2_DSU_M1"),
195 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
196 THUNDERBAY_MUX(0X3, "TRIGGER_M3"),
197 THUNDERBAY_MUX(0X4, "GPIO_M4")),
198 THUNDERBAY_PIN_DESC(16, "GPIO16",
199 THUNDERBAY_MUX(0X0, "UART1_M0"),
200 THUNDERBAY_MUX(0X1, "RT3_DSU_M1"),
201 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
202 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
203 THUNDERBAY_MUX(0X4, "GPIO_M4")),
204 THUNDERBAY_PIN_DESC(17, "GPIO17",
205 THUNDERBAY_MUX(0X0, "UART1_M0"),
206 THUNDERBAY_MUX(0X1, "RT3_DSU_M1"),
207 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
208 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
209 THUNDERBAY_MUX(0X4, "GPIO_M4")),
210 THUNDERBAY_PIN_DESC(18, "GPIO18",
211 THUNDERBAY_MUX(0X0, "SPI0_M0"),
212 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
213 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
214 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
215 THUNDERBAY_MUX(0X4, "GPIO_M4")),
216 THUNDERBAY_PIN_DESC(19, "GPIO19",
217 THUNDERBAY_MUX(0X0, "SPI0_M0"),
218 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
219 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
220 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
221 THUNDERBAY_MUX(0X4, "GPIO_M4")),
222 THUNDERBAY_PIN_DESC(20, "GPIO20",
223 THUNDERBAY_MUX(0X0, "SPI0_M0"),
224 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
225 THUNDERBAY_MUX(0X2, "TPIU_TRACE_M2"),
226 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
227 THUNDERBAY_MUX(0X4, "GPIO_M4")),
228 THUNDERBAY_PIN_DESC(21, "GPIO21",
229 THUNDERBAY_MUX(0X0, "SPI0_M0"),
230 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
231 THUNDERBAY_MUX(0X2, "TPIU_TRACE_M2"),
232 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
233 THUNDERBAY_MUX(0X4, "GPIO_M4")),
234 THUNDERBAY_PIN_DESC(22, "GPIO22",
235 THUNDERBAY_MUX(0X0, "SPI1_M0"),
236 THUNDERBAY_MUX(0X1, "EMPTY_M0"),
237 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
238 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
239 THUNDERBAY_MUX(0X4, "GPIO_M4")),
240 THUNDERBAY_PIN_DESC(23, "GPIO23",
241 THUNDERBAY_MUX(0X0, "SPI1_M0"),
242 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
243 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
244 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
245 THUNDERBAY_MUX(0X4, "GPIO_M4")),
246 THUNDERBAY_PIN_DESC(24, "GPIO24",
247 THUNDERBAY_MUX(0X0, "SPI1_M0"),
248 THUNDERBAY_MUX(0X1, "TPIU_TRACE_M1"),
249 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
250 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
251 THUNDERBAY_MUX(0X4, "GPIO_M4")),
252 THUNDERBAY_PIN_DESC(25, "GPIO25",
253 THUNDERBAY_MUX(0X0, "SPI1_M0"),
254 THUNDERBAY_MUX(0X1, "TPIU_TRACE_M1"),
255 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
256 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
257 THUNDERBAY_MUX(0X4, "GPIO_M4")),
258 THUNDERBAY_PIN_DESC(26, "GPIO26",
259 THUNDERBAY_MUX(0X0, "ETHER0_M0"),
260 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
261 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
262 THUNDERBAY_MUX(0X3, "DEBUG_M3"),
263 THUNDERBAY_MUX(0X4, "GPIO_M4")),
264 THUNDERBAY_PIN_DESC(27, "GPIO27",
265 THUNDERBAY_MUX(0X0, "ETHER0_M0"),
266 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
267 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
268 THUNDERBAY_MUX(0X3, "DEBUG_M3"),
269 THUNDERBAY_MUX(0X4, "GPIO_M4")),
270 THUNDERBAY_PIN_DESC(28, "GPIO28",
271 THUNDERBAY_MUX(0X0, "ETHER0_M0"),
272 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
273 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
274 THUNDERBAY_MUX(0X3, "DEBUG_M3"),
275 THUNDERBAY_MUX(0X4, "GPIO_M4")),
276 THUNDERBAY_PIN_DESC(29, "GPIO29",
277 THUNDERBAY_MUX(0X0, "ETHER0_M0"),
278 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
279 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
280 THUNDERBAY_MUX(0X3, "DEBUG_M3"),
281 THUNDERBAY_MUX(0X4, "GPIO_M4")),
282 THUNDERBAY_PIN_DESC(30, "GPIO30",
283 THUNDERBAY_MUX(0X0, "ETHER0_M0"),
284 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
285 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
286 THUNDERBAY_MUX(0X3, "DEBUG_M3"),
287 THUNDERBAY_MUX(0X4, "GPIO_M4")),
288 THUNDERBAY_PIN_DESC(31, "GPIO31",
289 THUNDERBAY_MUX(0X0, "ETHER0_M0"),
290 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
291 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
292 THUNDERBAY_MUX(0X3, "DEBUG_M3"),
293 THUNDERBAY_MUX(0X4, "GPIO_M4")),
294 THUNDERBAY_PIN_DESC(32, "GPIO32",
295 THUNDERBAY_MUX(0X0, "ETHER0_M0"),
296 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
297 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
298 THUNDERBAY_MUX(0X3, "DEBUG_M3"),
299 THUNDERBAY_MUX(0X4, "GPIO_M4")),
300 THUNDERBAY_PIN_DESC(33, "GPIO33",
301 THUNDERBAY_MUX(0X0, "ETHER0_M0"),
302 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
303 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
304 THUNDERBAY_MUX(0X3, "DEBUG_M3"),
305 THUNDERBAY_MUX(0X4, "GPIO_M4")),
306 THUNDERBAY_PIN_DESC(34, "GPIO34",
307 THUNDERBAY_MUX(0X0, "ETHER0_M0"),
308 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
309 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
310 THUNDERBAY_MUX(0X3, "DIG_VIEW_0"),
311 THUNDERBAY_MUX(0X4, "GPIO_M4")),
312 THUNDERBAY_PIN_DESC(35, "GPIO35",
313 THUNDERBAY_MUX(0X0, "ETHER0_M0"),
314 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
315 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
316 THUNDERBAY_MUX(0X3, "DIG_VIEW_1"),
317 THUNDERBAY_MUX(0X4, "GPIO_M4")),
318 THUNDERBAY_PIN_DESC(36, "GPIO36",
319 THUNDERBAY_MUX(0X0, "ETHER0_M0"),
320 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
321 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
322 THUNDERBAY_MUX(0X3, "CPR_IO_OUT_CLK_0"),
323 THUNDERBAY_MUX(0X4, "GPIO_M4")),
324 THUNDERBAY_PIN_DESC(37, "GPIO37",
325 THUNDERBAY_MUX(0X0, "ETHER0_M0"),
326 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
327 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
328 THUNDERBAY_MUX(0X3, "CPR_IO_OUT_CLK_1"),
329 THUNDERBAY_MUX(0X4, "GPIO_M4")),
330 THUNDERBAY_PIN_DESC(38, "GPIO38",
331 THUNDERBAY_MUX(0X0, "ETHER0_M0"),
332 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
333 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
334 THUNDERBAY_MUX(0X3, "CPR_IO_OUT_CLK_2"),
335 THUNDERBAY_MUX(0X4, "GPIO_M4")),
336 THUNDERBAY_PIN_DESC(39, "GPIO39",
337 THUNDERBAY_MUX(0X0, "ETHER0_M0"),
338 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
339 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
340 THUNDERBAY_MUX(0X3, "CPR_IO_OUT_CLK_3"),
341 THUNDERBAY_MUX(0X4, "GPIO_M4")),
342 THUNDERBAY_PIN_DESC(40, "GPIO40",
343 THUNDERBAY_MUX(0X0, "ETHER0_M0"),
344 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
345 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
346 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
347 THUNDERBAY_MUX(0X4, "GPIO_M4")),
348 THUNDERBAY_PIN_DESC(41, "GPIO41",
349 THUNDERBAY_MUX(0X0, "POWER_INTERRUPT_MAX_PLATFORM_POWER_M0"),
350 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
351 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
352 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
353 THUNDERBAY_MUX(0X4, "GPIO_M4")),
354 THUNDERBAY_PIN_DESC(42, "GPIO42",
355 THUNDERBAY_MUX(0X0, "ETHER1_M0"),
356 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
357 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
358 THUNDERBAY_MUX(0X3, "DEBUG_M3"),
359 THUNDERBAY_MUX(0X4, "GPIO_M4")),
360 THUNDERBAY_PIN_DESC(43, "GPIO43",
361 THUNDERBAY_MUX(0X0, "ETHER1_M0"),
362 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
363 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
364 THUNDERBAY_MUX(0X3, "DEBUG_M3"),
365 THUNDERBAY_MUX(0X4, "GPIO_M4")),
366 THUNDERBAY_PIN_DESC(44, "GPIO44",
367 THUNDERBAY_MUX(0X0, "ETHER1_M0"),
368 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
369 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
370 THUNDERBAY_MUX(0X3, "DEBUG_M3"),
371 THUNDERBAY_MUX(0X4, "GPIO_M4")),
372 THUNDERBAY_PIN_DESC(45, "GPIO45",
373 THUNDERBAY_MUX(0X0, "ETHER1_M0"),
374 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
375 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
376 THUNDERBAY_MUX(0X3, "DEBUG_M3"),
377 THUNDERBAY_MUX(0X4, "GPIO_M4")),
378 THUNDERBAY_PIN_DESC(46, "GPIO46",
379 THUNDERBAY_MUX(0X0, "ETHER1_M0"),
380 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
381 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
382 THUNDERBAY_MUX(0X3, "DEBUG_M3"),
383 THUNDERBAY_MUX(0X4, "GPIO_M4")),
384 THUNDERBAY_PIN_DESC(47, "GPIO47",
385 THUNDERBAY_MUX(0X0, "ETHER1_M0"),
386 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
387 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
388 THUNDERBAY_MUX(0X3, "DEBUG_M3"),
389 THUNDERBAY_MUX(0X4, "GPIO_M4")),
390 THUNDERBAY_PIN_DESC(48, "GPIO48",
391 THUNDERBAY_MUX(0X0, "ETHER1_M0"),
392 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
393 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
394 THUNDERBAY_MUX(0X3, "DEBUG_M3"),
395 THUNDERBAY_MUX(0X4, "GPIO_M4")),
396 THUNDERBAY_PIN_DESC(49, "GPIO49",
397 THUNDERBAY_MUX(0X0, "ETHER1_M0"),
398 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
399 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
400 THUNDERBAY_MUX(0X3, "DEBUG_M3"),
401 THUNDERBAY_MUX(0X4, "GPIO_M4")),
402 THUNDERBAY_PIN_DESC(50, "GPIO50",
403 THUNDERBAY_MUX(0X0, "ETHER1_M0"),
404 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
405 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
406 THUNDERBAY_MUX(0X3, "DIG_VIEW_0"),
407 THUNDERBAY_MUX(0X4, "GPIO_M4")),
408 THUNDERBAY_PIN_DESC(51, "GPIO51",
409 THUNDERBAY_MUX(0X0, "ETHER1_M0"),
410 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
411 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
412 THUNDERBAY_MUX(0X3, "DIG_VIEW_1"),
413 THUNDERBAY_MUX(0X4, "GPIO_M4")),
414 THUNDERBAY_PIN_DESC(52, "GPIO52",
415 THUNDERBAY_MUX(0X0, "ETHER1_M0"),
416 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
417 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
418 THUNDERBAY_MUX(0X3, "CPR_IO_OUT_CLK_0"),
419 THUNDERBAY_MUX(0X4, "GPIO_M4")),
420 THUNDERBAY_PIN_DESC(53, "GPIO53",
421 THUNDERBAY_MUX(0X0, "ETHER1_M0"),
422 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
423 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
424 THUNDERBAY_MUX(0X3, "CPR_IO_OUT_CLK_1"),
425 THUNDERBAY_MUX(0X4, "GPIO_M4")),
426 THUNDERBAY_PIN_DESC(54, "GPIO54",
427 THUNDERBAY_MUX(0X0, "ETHER1_M0"),
428 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
429 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
430 THUNDERBAY_MUX(0X3, "CPR_IO_OUT_CLK_2"),
431 THUNDERBAY_MUX(0X4, "GPIO_M4")),
432 THUNDERBAY_PIN_DESC(55, "GPIO55",
433 THUNDERBAY_MUX(0X0, "ETHER1_M0"),
434 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
435 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
436 THUNDERBAY_MUX(0X3, "CPR_IO_OUT_CLK_3"),
437 THUNDERBAY_MUX(0X4, "GPIO_M4")),
438 THUNDERBAY_PIN_DESC(56, "GPIO56",
439 THUNDERBAY_MUX(0X0, "ETHER1_M0"),
440 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
441 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
442 THUNDERBAY_MUX(0X3, "POWER_INTERRUPT_ICCMAX_VDDD_M3"),
443 THUNDERBAY_MUX(0X4, "GPIO_M4")),
444 THUNDERBAY_PIN_DESC(57, "GPIO57",
445 THUNDERBAY_MUX(0X0, "POWER_INTERRUPT_ICCMAX_VPU_M0"),
446 THUNDERBAY_MUX(0X1, "TPIU_DATA_M1"),
447 THUNDERBAY_MUX(0X2, "TPIU_DATA_M2"),
448 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
449 THUNDERBAY_MUX(0X4, "GPIO_M4")),
450 THUNDERBAY_PIN_DESC(58, "GPIO58",
451 THUNDERBAY_MUX(0X0, "THERMTRIP_M0"),
452 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
453 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
454 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
455 THUNDERBAY_MUX(0X4, "GPIO_M4")),
456 THUNDERBAY_PIN_DESC(59, "GPIO59",
457 THUNDERBAY_MUX(0X0, "THERMTRIP_M0"),
458 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
459 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
460 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
461 THUNDERBAY_MUX(0X4, "GPIO_M4")),
462 THUNDERBAY_PIN_DESC(60, "GPIO60",
463 THUNDERBAY_MUX(0X0, "SMBUS_M0"),
464 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
465 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
466 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
467 THUNDERBAY_MUX(0X4, "GPIO_M4")),
468 THUNDERBAY_PIN_DESC(61, "GPIO61",
469 THUNDERBAY_MUX(0X0, "SMBUS_M0"),
470 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
471 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
472 THUNDERBAY_MUX(0X3, "POWER_INTERRUPT_ICCMAX_VDDD_M3"),
473 THUNDERBAY_MUX(0X4, "GPIO_M4")),
474 THUNDERBAY_PIN_DESC(62, "GPIO62",
475 THUNDERBAY_MUX(0X0, "PLATFORM_RESET_M0"),
476 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
477 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
478 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
479 THUNDERBAY_MUX(0X4, "GPIO_M4")),
480 THUNDERBAY_PIN_DESC(63, "GPIO63",
481 THUNDERBAY_MUX(0X0, "PLATFORM_RESET_M0"),
482 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
483 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
484 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
485 THUNDERBAY_MUX(0X4, "GPIO_M4")),
486 THUNDERBAY_PIN_DESC(64, "GPIO64",
487 THUNDERBAY_MUX(0X0, "PLATFORM_SHUTDOWN_M0"),
488 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
489 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
490 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
491 THUNDERBAY_MUX(0X4, "GPIO_M4")),
492 THUNDERBAY_PIN_DESC(65, "GPIO65",
493 THUNDERBAY_MUX(0X0, "PLATFORM_SHUTDOWN_M0"),
494 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
495 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
496 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
497 THUNDERBAY_MUX(0X4, "GPIO_M4")),
498 THUNDERBAY_PIN_DESC(66, "GPIO66",
499 THUNDERBAY_MUX(0X0, "POWER_INTERRUPT_ICCMAX_MEDIA_M0"),
500 THUNDERBAY_MUX(0X1, "EMPTY_M1"),
501 THUNDERBAY_MUX(0X2, "EMPTY_M2"),
502 THUNDERBAY_MUX(0X3, "EMPTY_M3"),
503 THUNDERBAY_MUX(0X4, "GPIO_M4")),
504};
505
506static const struct thunderbay_pin_soc thunderbay_data = {
507 .pins = thunderbay_pins,
508 .npins = ARRAY_SIZE(thunderbay_pins),
509};
510
511static u32 thb_gpio_read_reg(struct gpio_chip *chip, unsigned int pinnr)
512{
513 struct thunderbay_pinctrl *tpc = gpiochip_get_data(chip);
514
515 return readl(tpc->base0 + THB_GPIO_REG_OFFSET(pinnr));
516}
517
518static u32 thb_gpio_write_reg(struct gpio_chip *chip, unsigned int pinnr, u32 value)
519{
520 struct thunderbay_pinctrl *tpc = gpiochip_get_data(chip);
521
522 writel(value, (tpc->base0 + THB_GPIO_REG_OFFSET(pinnr)));
523 return 0;
524}
525
526static int thb_read_gpio_data(struct gpio_chip *chip, unsigned int offset, unsigned int pad_dir)
527{
528 int data_offset;
529 u32 data_reg;
530
531 /* as per GPIO Spec = pad_dir 0:input, 1:output */
532 data_offset = 0x2000u + (offset / 32);
533 if (!pad_dir)
534 data_offset += 4;
535 data_reg = thb_gpio_read_reg(chip, data_offset);
536
537 return data_reg & BIT(offset % 32);
538}
539
540static int thb_write_gpio_data(struct gpio_chip *chip, unsigned int offset, unsigned int value)
541{
542 int data_offset;
543 u32 data_reg;
544
545 data_offset = 0x2000u + (offset / 32);
546
547 data_reg = thb_gpio_read_reg(chip, data_offset);
548
549 if (value > 0)
550 data_reg |= BIT(offset % 32);
551 else
552 data_reg &= ~BIT(offset % 32);
553
554 return thb_gpio_write_reg(chip, data_offset, data_reg);
555}
556
557static int thunderbay_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
558{
559 u32 reg = thb_gpio_read_reg(chip, offset);
560
561 /* Return direction only if configured as GPIO else negative error */
562 if (reg & THB_GPIO_PORT_SELECT_MASK)
563 return !(reg & THB_GPIO_PAD_DIRECTION_MASK);
564 return -EINVAL;
565}
566
567static int thunderbay_gpio_set_direction_input(struct gpio_chip *chip, unsigned int offset)
568{
569 u32 reg = thb_gpio_read_reg(chip, offset);
570
571 /* set pin as input only if it is GPIO else error */
572 if (reg & THB_GPIO_PORT_SELECT_MASK) {
573 reg &= (~THB_GPIO_PAD_DIRECTION_MASK);
574 thb_gpio_write_reg(chip, offset, reg);
575 return 0;
576 }
577 return -EINVAL;
578}
579
580static void thunderbay_gpio_set_value(struct gpio_chip *chip, unsigned int offset, int value)
581{
582 u32 reg = thb_gpio_read_reg(chip, offset);
583
584 /* update pin value only if it is GPIO-output else error */
585 if ((reg & THB_GPIO_PORT_SELECT_MASK) && (reg & THB_GPIO_PAD_DIRECTION_MASK))
586 thb_write_gpio_data(chip, offset, value);
587}
588
589static int thunderbay_gpio_set_direction_output(struct gpio_chip *chip,
590 unsigned int offset, int value)
591{
592 u32 reg = thb_gpio_read_reg(chip, offset);
593
594 /* set pin as output only if it is GPIO else error */
595 if (reg & THB_GPIO_PORT_SELECT_MASK) {
596 reg |= THB_GPIO_PAD_DIRECTION_MASK;
597 thb_gpio_write_reg(chip, offset, reg);
598 thunderbay_gpio_set_value(chip, offset, value);
599 return 0;
600 }
601 return -EINVAL;
602}
603
604static int thunderbay_gpio_get_value(struct gpio_chip *chip, unsigned int offset)
605{
606 u32 reg = thb_gpio_read_reg(chip, offset);
607 int gpio_dir = 0;
608
609 /* Read pin value only if it is GPIO else error */
610 if (reg & THB_GPIO_PORT_SELECT_MASK) {
611 /* 0=in, 1=out */
612 gpio_dir = (reg & THB_GPIO_PAD_DIRECTION_MASK) > 0;
613
614 /* Returns negative value when pin is configured as PORT */
615 return thb_read_gpio_data(chip, offset, gpio_dir);
616 }
617 return -EINVAL;
618}
619
620static int thunderbay_gpiochip_probe(struct thunderbay_pinctrl *tpc)
621{
622 struct gpio_chip *chip = &tpc->chip;
623 int ret;
624
625 chip->label = dev_name(tpc->dev);
626 chip->parent = tpc->dev;
627 chip->request = gpiochip_generic_request;
628 chip->free = gpiochip_generic_free;
629 chip->get_direction = thunderbay_gpio_get_direction;
630 chip->direction_input = thunderbay_gpio_set_direction_input;
631 chip->direction_output = thunderbay_gpio_set_direction_output;
632 chip->get = thunderbay_gpio_get_value;
633 chip->set = thunderbay_gpio_set_value;
634 chip->set_config = gpiochip_generic_config;
635 /* identifies the first GPIO number handled by this chip; or,
636 * if negative during registration, requests dynamic ID allocation.
637 * Please pass -1 as base to let gpiolib select the chip base in all possible cases.
638 * We want to get rid of the static GPIO number space in the long run.
639 */
640 chip->base = -1;
641 /* Number of GPIOs handled by this controller; the last GPIO handled is (base + ngpio - 1)*/
642 chip->ngpio = THB_MAX_NPINS_SUPPORTED;
643
644 /* Register/add Thunder Bay GPIO chip with Linux framework */
645 ret = gpiochip_add_data(chip, tpc);
646 if (ret)
647 dev_err(tpc->dev, "Failed to add gpiochip\n");
648 return ret;
649}
650
651static int thunderbay_request_gpio(struct pinctrl_dev *pctldev,
652 struct pinctrl_gpio_range *range,
653 unsigned int pin)
654{
655 struct thunderbay_pinctrl *tpc = pinctrl_dev_get_drvdata(pctldev);
656 struct gpio_chip *chip = &tpc->chip;
657 u32 reg = 0;
658
659 if (thb_pinx_status[pin] == 0u) {
660 reg = thb_gpio_read_reg(chip, pin);
661 /* Updates PIN configuration as GPIO and sets GPIO to MODE-4*/
662 reg |= (THB_GPIO_PORT_SELECT_MASK | THB_GPIO_PINMUX_MODE_4);
663 thb_gpio_write_reg(chip, pin, reg);
664
665 /* update pin status as busy */
666 thb_pinx_status[pin] = 1u;
667
668 return 0;
669 }
670 return -EINVAL;
671}
672
673static void thunderbay_free_gpio(struct pinctrl_dev *pctldev,
674 struct pinctrl_gpio_range *range,
675 unsigned int pin)
676{
677 struct thunderbay_pinctrl *tpc = pinctrl_dev_get_drvdata(pctldev);
678 struct gpio_chip *chip = &tpc->chip;
679 u32 reg = 0;
680
681 if (thb_pinx_status[pin] == 1u) {
682 reg = thb_gpio_read_reg(chip, pin);
683
684 /* Updates PIN configuration from GPIO to PORT */
685 reg &= (~THB_GPIO_PORT_SELECT_MASK);
686
687 /* Change Port/gpio mode to default mode-0 */
688 reg &= (~THB_GPIO_PINMUX_MODE_4);
689
690 thb_gpio_write_reg(chip, pin, reg);
691
692 /* update pin status as free */
693 thb_pinx_status[pin] = 0u;
694 }
695}
696
697static int thb_pinctrl_set_mux(struct pinctrl_dev *pctldev,
698 unsigned int func_select, unsigned int group_select)
699{
700 struct thunderbay_pinctrl *tpc = pinctrl_dev_get_drvdata(pctldev);
701 struct gpio_chip *chip = &tpc->chip;
702 struct function_desc *function;
703 unsigned int i, pin_mode;
704 struct group_desc *group;
705 int ret = -EINVAL;
706 u32 reg = 0u;
707
708 group = pinctrl_generic_get_group(pctldev, group_select);
709 if (!group)
710 return -EINVAL;
711
712 function = pinmux_generic_get_function(pctldev, func_select);
713 if (!function)
714 return -EINVAL;
715
716 pin_mode = *(unsigned int *)(function->data);
717
718 /* Change modes for pins in the selected group */
719 for (i = 0; i < group->num_pins; i++) {
720 reg = thb_gpio_read_reg(chip, group->pins[i]);
721
722 switch (pin_mode) {
723 case 0u:
724 reg |= THB_GPIO_PINMUX_MODE_0;
725 break;
726 case 1u:
727 reg |= THB_GPIO_PINMUX_MODE_1;
728 break;
729 case 2u:
730 reg |= THB_GPIO_PINMUX_MODE_2;
731 break;
732 case 3u:
733 reg |= THB_GPIO_PINMUX_MODE_3;
734 break;
735 case 4u:
736 reg |= THB_GPIO_PINMUX_MODE_4;
737 break;
738 default:
739 return -EINVAL;
740 }
741
742 ret = thb_gpio_write_reg(chip, group->pins[i], reg);
743 if (~ret) {
744 /* update pin status as busy */
745 thb_pinx_status[group->pins[i]] = 1u;
746 }
747 }
748 return ret;
749}
750
751static int thunderbay_build_groups(struct thunderbay_pinctrl *tpc)
752{
753 struct group_desc *thunderbay_groups;
754 int i;
755
756 tpc->ngroups = tpc->soc->npins;
757 thunderbay_groups = devm_kcalloc(tpc->dev, tpc->ngroups,
758 sizeof(*thunderbay_groups), GFP_KERNEL);
759 if (!thunderbay_groups)
760 return -ENOMEM;
761
762 for (i = 0; i < tpc->ngroups; i++) {
763 struct group_desc *group = thunderbay_groups + i;
764 const struct pinctrl_pin_desc *pin_info = thunderbay_pins + i;
765
766 group->name = pin_info->name;
767 group->pins = (int *)&pin_info->number;
768 pinctrl_generic_add_group(tpc->pctrl, group->name,
769 group->pins, 1, NULL);
770 }
771 return 0;
772}
773
774static int thunderbay_add_functions(struct thunderbay_pinctrl *tpc, struct function_desc *funcs)
775{
776 struct function_desc *function = funcs;
777 int i;
778
779 /* Assign the groups for each function */
780 for (i = 0; i < tpc->soc->npins; i++) {
781 const struct pinctrl_pin_desc *pin_info = thunderbay_pins + i;
782 struct thunderbay_mux_desc *pin_mux = pin_info->drv_data;
783
784 while (pin_mux->name) {
785 const char **grp;
786 int j, grp_num, match = 0;
787 size_t grp_size;
788 struct function_desc *func;
789
790 for (j = 0; j < tpc->nfuncs; j++) {
791 if (!strcmp(pin_mux->name, function[j].name)) {
792 match = 1;
793 break;
794 }
795 }
796
797 if (!match)
798 return -EINVAL;
799
800 func = function + j;
801 grp_num = func->num_group_names;
802 grp_size = sizeof(*func->group_names);
803
804 if (!func->group_names) {
805 func->group_names = devm_kcalloc(tpc->dev,
806 grp_num,
807 grp_size,
808 GFP_KERNEL);
809 if (!func->group_names) {
810 kfree(func);
811 return -ENOMEM;
812 }
813 }
814
815 grp = func->group_names;
816 while (*grp)
817 grp++;
818
819 *grp = pin_info->name;
820 pin_mux++;
821 }
822 }
823
824 /* Add all functions */
825 for (i = 0; i < tpc->nfuncs; i++) {
826 pinmux_generic_add_function(tpc->pctrl,
827 function[i].name,
828 function[i].group_names,
829 function[i].num_group_names,
830 function[i].data);
831 }
832 kfree(function);
833 return 0;
834}
835
836static int thunderbay_build_functions(struct thunderbay_pinctrl *tpc)
837{
838 struct function_desc *thunderbay_funcs;
839 void *ptr;
840 int pin;
841
842 /* Total number of functions is unknown at this point. Allocate first. */
843 tpc->nfuncs = 0;
844 thunderbay_funcs = kcalloc(tpc->soc->npins * 8,
845 sizeof(*thunderbay_funcs), GFP_KERNEL);
846 if (!thunderbay_funcs)
847 return -ENOMEM;
848
849 /* Find total number of functions and each's properties */
850 for (pin = 0; pin < tpc->soc->npins; pin++) {
851 const struct pinctrl_pin_desc *pin_info = thunderbay_pins + pin;
852 struct thunderbay_mux_desc *pin_mux = pin_info->drv_data;
853
854 while (pin_mux->name) {
855 struct function_desc *func = thunderbay_funcs;
856
857 while (func->name) {
858 if (!strcmp(pin_mux->name, func->name)) {
859 func->num_group_names++;
860 break;
861 }
862 func++;
863 }
864
865 if (!func->name) {
866 func->name = pin_mux->name;
867 func->num_group_names = 1;
868 func->data = (int *)&pin_mux->mode;
869 tpc->nfuncs++;
870 }
871
872 pin_mux++;
873 }
874 }
875
876 /* Reallocate memory based on actual number of functions */
877 ptr = krealloc(thunderbay_funcs,
878 tpc->nfuncs * sizeof(*thunderbay_funcs), GFP_KERNEL);
879 if (!ptr)
880 return -ENOMEM;
881
882 thunderbay_funcs = ptr;
883 return thunderbay_add_functions(tpc, thunderbay_funcs);
884}
885
886static int thunderbay_pinconf_set_tristate(struct thunderbay_pinctrl *tpc,
887 unsigned int pin, u32 config)
888{
889 struct gpio_chip *chip = &tpc->chip;
890 u32 reg;
891
892 reg = thb_gpio_read_reg(chip, pin);
893 if (config > 0)
894 reg |= THB_GPIO_ENAQ_MASK;
895 else
896 reg &= ~THB_GPIO_ENAQ_MASK;
897
898 return thb_gpio_write_reg(chip, pin, reg);
899}
900
901static int thunderbay_pinconf_get_tristate(struct thunderbay_pinctrl *tpc,
902 unsigned int pin, u32 *config)
903{
904 struct gpio_chip *chip = &tpc->chip;
905 u32 reg;
906
907 reg = thb_gpio_read_reg(chip, pin);
908 *config = (reg & THB_GPIO_ENAQ_MASK) > 0;
909
910 return 0;
911}
912
913static int thunderbay_pinconf_set_pulldown(struct thunderbay_pinctrl *tpc,
914 unsigned int pin, u32 config)
915{
916 struct gpio_chip *chip = &tpc->chip;
917 u32 reg;
918
919 reg = thb_gpio_read_reg(chip, pin);
920 if (config > 0)
921 reg |= THB_GPIO_PULL_DOWN_MASK;
922 else
923 reg &= ~THB_GPIO_PULL_DOWN_MASK;
924
925 return thb_gpio_write_reg(chip, pin, reg);
926}
927
928static int thunderbay_pinconf_get_pulldown(struct thunderbay_pinctrl *tpc,
929 unsigned int pin, u32 *config)
930{
931 struct gpio_chip *chip = &tpc->chip;
932 u32 reg = 0;
933
934 reg = thb_gpio_read_reg(chip, pin);
935 *config = ((reg & THB_GPIO_PULL_DOWN_MASK) > 0) ? 1 : 0;
936
937 return 0;
938}
939
940static int thunderbay_pinconf_set_pullup(struct thunderbay_pinctrl *tpc,
941 unsigned int pin, u32 config)
942{
943 struct gpio_chip *chip = &tpc->chip;
944 u32 reg;
945
946 reg = thb_gpio_read_reg(chip, pin);
947 if (config > 0)
948 reg &= ~THB_GPIO_PULL_UP_MASK;
949 else
950 reg |= THB_GPIO_PULL_UP_MASK;
951
952 return thb_gpio_write_reg(chip, pin, reg);
953}
954
955static int thunderbay_pinconf_get_pullup(struct thunderbay_pinctrl *tpc,
956 unsigned int pin, u32 *config)
957{
958 struct gpio_chip *chip = &tpc->chip;
959 u32 reg;
960
961 reg = thb_gpio_read_reg(chip, pin);
962 *config = ((reg & THB_GPIO_PULL_UP_MASK) == 0) ? 1 : 0;
963
964 return 0;
965}
966
967static int thunderbay_pinconf_set_opendrain(struct thunderbay_pinctrl *tpc,
968 unsigned int pin, u32 config)
969{
970 struct gpio_chip *chip = &tpc->chip;
971 u32 reg;
972
973 reg = thb_gpio_read_reg(chip, pin);
974 if (config > 0)
975 reg &= ~THB_GPIO_PULL_ENABLE_MASK;
976 else
977 reg |= THB_GPIO_PULL_ENABLE_MASK;
978
979 return thb_gpio_write_reg(chip, pin, reg);
980}
981
982static int thunderbay_pinconf_get_opendrain(struct thunderbay_pinctrl *tpc,
983 unsigned int pin, u32 *config)
984{
985 struct gpio_chip *chip = &tpc->chip;
986 u32 reg;
987
988 reg = thb_gpio_read_reg(chip, pin);
989 *config = ((reg & THB_GPIO_PULL_ENABLE_MASK) == 0) ? 1 : 0;
990
991 return 0;
992}
993
994static int thunderbay_pinconf_set_pushpull(struct thunderbay_pinctrl *tpc,
995 unsigned int pin, u32 config)
996{
997 struct gpio_chip *chip = &tpc->chip;
998 u32 reg;
999
1000 reg = thb_gpio_read_reg(chip, pin);
1001 if (config > 0)
1002 reg |= THB_GPIO_PULL_ENABLE_MASK;
1003 else
1004 reg &= ~THB_GPIO_PULL_ENABLE_MASK;
1005
1006 return thb_gpio_write_reg(chip, pin, reg);
1007}
1008
1009static int thunderbay_pinconf_get_pushpull(struct thunderbay_pinctrl *tpc,
1010 unsigned int pin, u32 *config)
1011{
1012 struct gpio_chip *chip = &tpc->chip;
1013 u32 reg;
1014
1015 reg = thb_gpio_read_reg(chip, pin);
1016 *config = ((reg & THB_GPIO_PULL_ENABLE_MASK) > 0) ? 1 : 0;
1017
1018 return 0;
1019}
1020
1021static int thunderbay_pinconf_set_drivestrength(struct thunderbay_pinctrl *tpc,
1022 unsigned int pin, u32 config)
1023{
1024 struct gpio_chip *chip = &tpc->chip;
1025 u32 reg;
1026
1027 reg = thb_gpio_read_reg(chip, pin);
1028
1029 /* Drive Strength: 0x0 to 0xF */
1030 if (config <= 0xF) {
1031 reg = (reg | config);
1032 return thb_gpio_write_reg(chip, pin, reg);
1033 }
1034
1035 return -EINVAL;
1036}
1037
1038static int thunderbay_pinconf_get_drivestrength(struct thunderbay_pinctrl *tpc,
1039 unsigned int pin, u32 *config)
1040{
1041 struct gpio_chip *chip = &tpc->chip;
1042 u32 reg;
1043
1044 reg = thb_gpio_read_reg(chip, pin);
1045 reg = (reg & THB_GPIO_DRIVE_STRENGTH_MASK) >> 16;
1046 *config = (reg > 0) ? reg : 0;
1047
1048 return 0;
1049}
1050
1051static int thunderbay_pinconf_set_schmitt(struct thunderbay_pinctrl *tpc,
1052 unsigned int pin, u32 config)
1053{
1054 struct gpio_chip *chip = &tpc->chip;
1055 u32 reg;
1056
1057 reg = thb_gpio_read_reg(chip, pin);
1058 if (config > 0)
1059 reg |= THB_GPIO_SCHMITT_TRIGGER_MASK;
1060 else
1061 reg &= ~THB_GPIO_SCHMITT_TRIGGER_MASK;
1062
1063 return thb_gpio_write_reg(chip, pin, reg);
1064}
1065
1066static int thunderbay_pinconf_get_schmitt(struct thunderbay_pinctrl *tpc,
1067 unsigned int pin, u32 *config)
1068{
1069 struct gpio_chip *chip = &tpc->chip;
1070 u32 reg;
1071
1072 reg = thb_gpio_read_reg(chip, pin);
1073 *config = ((reg & THB_GPIO_SCHMITT_TRIGGER_MASK) > 0) ? 1 : 0;
1074
1075 return 0;
1076}
1077
1078static int thunderbay_pinconf_set_slew_rate(struct thunderbay_pinctrl *tpc,
1079 unsigned int pin, u32 config)
1080{
1081 struct gpio_chip *chip = &tpc->chip;
1082 u32 reg = 0;
1083
1084 reg = thb_gpio_read_reg(chip, pin);
1085 if (config > 0)
1086 reg |= THB_GPIO_SLEW_RATE_MASK;
1087 else
1088 reg &= ~THB_GPIO_SLEW_RATE_MASK;
1089
1090 return thb_gpio_write_reg(chip, pin, reg);
1091}
1092
1093static int thunderbay_pinconf_get_slew_rate(struct thunderbay_pinctrl *tpc,
1094 unsigned int pin, u32 *config)
1095{
1096 struct gpio_chip *chip = &tpc->chip;
1097 u32 reg;
1098
1099 reg = thb_gpio_read_reg(chip, pin);
1100 *config = ((reg & THB_GPIO_SLEW_RATE_MASK) > 0) ? 1 : 0;
1101
1102 return 0;
1103}
1104
1105static int thunderbay_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1106 unsigned long *config)
1107{
1108 struct thunderbay_pinctrl *tpc = pinctrl_dev_get_drvdata(pctldev);
1109 enum pin_config_param param = pinconf_to_config_param(*config);
1110 u32 arg;
1111 int ret;
1112
1113 switch (param) {
1114 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1115 ret = thunderbay_pinconf_get_tristate(tpc, pin, &arg);
1116 break;
1117
1118 case PIN_CONFIG_BIAS_PULL_DOWN:
1119 ret = thunderbay_pinconf_get_pulldown(tpc, pin, &arg);
1120 break;
1121
1122 case PIN_CONFIG_BIAS_PULL_UP:
1123 ret = thunderbay_pinconf_get_pullup(tpc, pin, &arg);
1124 break;
1125
1126 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1127 ret = thunderbay_pinconf_get_opendrain(tpc, pin, &arg);
1128 break;
1129
1130 case PIN_CONFIG_DRIVE_PUSH_PULL:
1131 ret = thunderbay_pinconf_get_pushpull(tpc, pin, &arg);
1132 break;
1133
1134 case PIN_CONFIG_DRIVE_STRENGTH:
1135 ret = thunderbay_pinconf_get_drivestrength(tpc, pin, &arg);
1136 break;
1137
1138 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1139 ret = thunderbay_pinconf_get_schmitt(tpc, pin, &arg);
1140 break;
1141
1142 case PIN_CONFIG_SLEW_RATE:
1143 ret = thunderbay_pinconf_get_slew_rate(tpc, pin, &arg);
1144 break;
1145
1146 default:
1147 return -ENOTSUPP;
1148 }
1149
1150 *config = pinconf_to_config_packed(param, arg);
1151
1152 return ret;
1153}
1154
1155static int thunderbay_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1156 unsigned long *configs, unsigned int num_configs)
1157{
1158 struct thunderbay_pinctrl *tpc = pinctrl_dev_get_drvdata(pctldev);
1159 enum pin_config_param param;
1160 unsigned int pinconf;
1161 int ret = 0;
1162 u32 arg;
1163
1164 for (pinconf = 0; pinconf < num_configs; pinconf++) {
1165 param = pinconf_to_config_param(configs[pinconf]);
1166 arg = pinconf_to_config_argument(configs[pinconf]);
1167
1168 switch (param) {
1169 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1170 ret = thunderbay_pinconf_set_tristate(tpc, pin, arg);
1171 break;
1172
1173 case PIN_CONFIG_BIAS_PULL_DOWN:
1174 ret = thunderbay_pinconf_set_pulldown(tpc, pin, arg);
1175 break;
1176
1177 case PIN_CONFIG_BIAS_PULL_UP:
1178 ret = thunderbay_pinconf_set_pullup(tpc, pin, arg);
1179 break;
1180
1181 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1182 ret = thunderbay_pinconf_set_opendrain(tpc, pin, arg);
1183 break;
1184
1185 case PIN_CONFIG_DRIVE_PUSH_PULL:
1186 ret = thunderbay_pinconf_set_pushpull(tpc, pin, arg);
1187 break;
1188
1189 case PIN_CONFIG_DRIVE_STRENGTH:
1190 ret = thunderbay_pinconf_set_drivestrength(tpc, pin, arg);
1191 break;
1192
1193 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1194 ret = thunderbay_pinconf_set_schmitt(tpc, pin, arg);
1195 break;
1196
1197 case PIN_CONFIG_SLEW_RATE:
1198 ret = thunderbay_pinconf_set_slew_rate(tpc, pin, arg);
1199 break;
1200
1201 default:
1202 return -ENOTSUPP;
1203 }
1204 }
1205 return ret;
1206}
1207
1208static const struct pinctrl_ops thunderbay_pctlops = {
1209 .get_groups_count = pinctrl_generic_get_group_count,
1210 .get_group_name = pinctrl_generic_get_group_name,
1211 .get_group_pins = pinctrl_generic_get_group_pins,
1212 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
1213 .dt_free_map = pinconf_generic_dt_free_map,
1214};
1215
1216static const struct pinmux_ops thunderbay_pmxops = {
1217 .get_functions_count = pinmux_generic_get_function_count,
1218 .get_function_name = pinmux_generic_get_function_name,
1219 .get_function_groups = pinmux_generic_get_function_groups,
1220 .set_mux = thb_pinctrl_set_mux,
1221 .gpio_request_enable = thunderbay_request_gpio,
1222 .gpio_disable_free = thunderbay_free_gpio,
1223};
1224
1225static const struct pinconf_ops thunderbay_confops = {
1226 .is_generic = true,
1227 .pin_config_get = thunderbay_pinconf_get,
1228 .pin_config_set = thunderbay_pinconf_set,
1229};
1230
1231static struct pinctrl_desc thunderbay_pinctrl_desc = {
1232 .name = "thunderbay-pinmux",
1233 .pctlops = &thunderbay_pctlops,
1234 .pmxops = &thunderbay_pmxops,
1235 .confops = &thunderbay_confops,
1236 .owner = THIS_MODULE,
1237};
1238
1239static const struct of_device_id thunderbay_pinctrl_match[] = {
1240 {
1241 .compatible = "intel,thunderbay-pinctrl",
1242 .data = &thunderbay_data
1243 },
1244 {}
1245};
1246
1247static int thunderbay_pinctrl_probe(struct platform_device *pdev)
1248{
1249 const struct of_device_id *of_id;
1250 struct device *dev = &pdev->dev;
1251 struct thunderbay_pinctrl *tpc;
1252 struct resource *iomem;
1253 int ret;
1254
1255 of_id = of_match_node(thunderbay_pinctrl_match, pdev->dev.of_node);
1256 if (!of_id)
1257 return -ENODEV;
1258
1259 tpc = devm_kzalloc(dev, sizeof(*tpc), GFP_KERNEL);
1260 if (!tpc)
1261 return -ENOMEM;
1262
1263 tpc->dev = dev;
1264 tpc->soc = of_id->data;
1265
1266 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1267 if (!iomem)
1268 return -ENXIO;
1269
1270 tpc->base0 = devm_ioremap_resource(dev, iomem);
1271 if (IS_ERR(tpc->base0))
1272 return PTR_ERR(tpc->base0);
1273
1274 thunderbay_pinctrl_desc.pins = tpc->soc->pins;
1275 thunderbay_pinctrl_desc.npins = tpc->soc->npins;
1276
1277 /* Register pinctrl */
1278 tpc->pctrl = devm_pinctrl_register(dev, &thunderbay_pinctrl_desc, tpc);
1279 if (IS_ERR(tpc->pctrl))
1280 return PTR_ERR(tpc->pctrl);
1281
1282 /* Setup pinmux groups */
1283 ret = thunderbay_build_groups(tpc);
1284 if (ret)
1285 return ret;
1286
1287 /* Setup pinmux functions */
1288 ret = thunderbay_build_functions(tpc);
1289 if (ret)
1290 return ret;
1291
1292 /* Setup GPIO */
1293 ret = thunderbay_gpiochip_probe(tpc);
1294 if (ret < 0)
1295 return ret;
1296
1297 platform_set_drvdata(pdev, tpc);
1298
1299 return 0;
1300}
1301
1302static int thunderbay_pinctrl_remove(struct platform_device *pdev)
1303{
1304 /* thunderbay_pinctrl_remove function to clear the assigned memory */
1305 return 0;
1306}
1307
1308static struct platform_driver thunderbay_pinctrl_driver = {
1309 .driver = {
1310 .name = "thunderbay-pinctrl",
1311 .of_match_table = thunderbay_pinctrl_match,
1312 },
1313 .probe = thunderbay_pinctrl_probe,
1314 .remove = thunderbay_pinctrl_remove,
1315};
1316
1317builtin_platform_driver(thunderbay_pinctrl_driver);
1318
1319MODULE_AUTHOR("Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>");
1320MODULE_AUTHOR("Kiran Kumar S <kiran.kumar1.s@intel.com>");
1321MODULE_DESCRIPTION("Intel Thunder Bay Pinctrl/GPIO Driver");
1322MODULE_LICENSE("GPL v2");