blob: 42214b4ff14a1372dcbf9822c8c192725366ed56 [file] [log] [blame]
Geert Uytterhoevencf18fd02018-07-16 17:30:52 +02001What: /sys/bus/i2c/devices/.../bd9571mwv-regulator.*.auto/backup_mode
2Date: Jul 2018
3KernelVersion: 4.19
4Contact: Geert Uytterhoeven <geert+renesas@glider.be>
5Description: Read/write the current state of DDR Backup Mode, which controls
6 if DDR power rails will be kept powered during system suspend.
7 ("on"/"1" = enabled, "off"/"0" = disabled).
8 Two types of power switches (or control signals) can be used:
Mauro Carvalho Chehab34433332020-10-30 08:40:39 +01009
Geert Uytterhoevencf18fd02018-07-16 17:30:52 +020010 A. With a momentary power switch (or pulse signal), DDR
11 Backup Mode is enabled by default when available, as the
12 PMIC will be configured only during system suspend.
13 B. With a toggle power switch (or level signal), the
14 following steps must be followed exactly:
Mauro Carvalho Chehab34433332020-10-30 08:40:39 +010015
Geert Uytterhoevencf18fd02018-07-16 17:30:52 +020016 1. Configure PMIC for backup mode, to change the role of
17 the accessory power switch from a power switch to a
18 wake-up switch,
19 2. Switch accessory power switch off, to prepare for
20 system suspend, which is a manual step not controlled
21 by software,
22 3. Suspend system,
23 4. Switch accessory power switch on, to resume the
24 system.
Mauro Carvalho Chehab34433332020-10-30 08:40:39 +010025
Geert Uytterhoevencf18fd02018-07-16 17:30:52 +020026 DDR Backup Mode must be explicitly enabled by the user,
27 to invoke step 1.
Mauro Carvalho Chehab34433332020-10-30 08:40:39 +010028
Geert Uytterhoevencf18fd02018-07-16 17:30:52 +020029 See also Documentation/devicetree/bindings/mfd/bd9571mwv.txt.
30Users: User space applications for embedded boards equipped with a
31 BD9571MWV PMIC.