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Thomas Gleixnerfcaf2032019-05-27 08:55:08 +02001// SPDX-License-Identifier: GPL-2.0-or-later
Robert Jarzmik209f4d72016-04-10 21:30:00 +02002/*
3 * Copyright (C) 2016 Robert Jarzmik <robert.jarzmik@free.fr>
Robert Jarzmik209f4d72016-04-10 21:30:00 +02004 */
5#include "pxa2xx.dtsi"
6#include "dt-bindings/clock/pxa-clock.h"
7
8/ {
9 model = "Marvell PXA25x family SoC";
10 compatible = "marvell,pxa250";
11
12 clocks {
13 /*
14 * The muxing of external clocks/internal dividers for osc* clock
15 * sources has been hidden under the carpet by now.
16 */
17 #address-cells = <1>;
18 #size-cells = <1>;
19 ranges;
20
21 clks: pxa2xx_clks@41300004 {
22 compatible = "marvell,pxa250-core-clocks";
23 #clock-cells = <1>;
24 status = "okay";
25 };
26
27 /* timer oscillator */
28 clktimer: oscillator {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <3686400>;
32 clock-output-names = "ostimer";
33 };
34 };
35
36 pxabus {
37 pdma: dma-controller@40000000 {
38 compatible = "marvell,pdma-1.0";
39 reg = <0x40000000 0x10000>;
40 interrupts = <25>;
41 #dma-channels = <16>;
42 #dma-cells = <2>;
43 #dma-requests = <40>;
44 status = "okay";
45 };
46
47 pxairq: interrupt-controller@40d00000 {
48 marvell,intc-priority;
49 marvell,intc-nr-irqs = <32>;
50 };
51
52 pinctrl: pinctrl@40e00000 {
53 reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4
54 0x40f00020 0x10>;
55 compatible = "marvell,pxa25x-pinctrl";
56 };
57
58 gpio: gpio@40e00000 {
59 compatible = "intel,pxa25x-gpio";
60 gpio-ranges = <&pinctrl 0 0 84>;
61 clocks = <&clks CLK_NONE>;
62 };
63
64 pwm0: pwm@40b00000 {
65 compatible = "marvell,pxa250-pwm";
66 reg = <0x40b00000 0x10>;
67 #pwm-cells = <1>;
68 clocks = <&clks CLK_PWM0>;
69 };
70
71 pwm1: pwm@40b00010 {
72 compatible = "marvell,pxa250-pwm";
73 reg = <0x40b00010 0x10>;
74 #pwm-cells = <1>;
75 clocks = <&clks CLK_PWM1>;
76 };
Robert Jarzmik24a610e2018-06-25 18:44:01 +020077
78 rtc@40900000 {
79 clocks = <&clks CLK_OSC32k768>;
80 };
Robert Jarzmik209f4d72016-04-10 21:30:00 +020081 };
82
83 timer@40a00000 {
84 compatible = "marvell,pxa-timer";
85 reg = <0x40a00000 0x20>;
86 interrupts = <26>;
87 clocks = <&clktimer>;
88 status = "okay";
89 };
Robert Jarzmik93ab7c82016-10-31 20:54:54 +010090
91 pxa250_opp_table: opp_table0 {
92 compatible = "operating-points-v2";
93
Viresh Kumara8702712017-04-20 16:25:08 +053094 opp-99532800 {
Robert Jarzmik93ab7c82016-10-31 20:54:54 +010095 opp-hz = /bits/ 64 <99532800>;
96 opp-microvolt = <1000000 950000 1650000>;
97 clock-latency-ns = <20>;
98 };
Viresh Kumara8702712017-04-20 16:25:08 +053099 opp-199065600 {
Robert Jarzmik93ab7c82016-10-31 20:54:54 +0100100 opp-hz = /bits/ 64 <199065600>;
101 opp-microvolt = <1000000 950000 1650000>;
102 clock-latency-ns = <20>;
103 };
Viresh Kumara8702712017-04-20 16:25:08 +0530104 opp-298598400 {
Robert Jarzmik93ab7c82016-10-31 20:54:54 +0100105 opp-hz = /bits/ 64 <298598400>;
106 opp-microvolt = <1100000 1045000 1650000>;
107 clock-latency-ns = <20>;
108 };
Viresh Kumara8702712017-04-20 16:25:08 +0530109 opp-398131200 {
Robert Jarzmik93ab7c82016-10-31 20:54:54 +0100110 opp-hz = /bits/ 64 <398131200>;
111 opp-microvolt = <1300000 1235000 1650000>;
112 clock-latency-ns = <20>;
113 };
114 };
Robert Jarzmik209f4d72016-04-10 21:30:00 +0200115};