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Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +01001// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2020 Collabora Ltd.
4 */
5#include <linux/clk.h>
Matthias Brugger123e8b42020-10-30 12:36:14 +01006#include <linux/clk-provider.h>
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +01007#include <linux/init.h>
8#include <linux/io.h>
9#include <linux/iopoll.h>
10#include <linux/mfd/syscon.h>
11#include <linux/of_clk.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14#include <linux/pm_domain.h>
15#include <linux/regmap.h>
Hsin-Yi Wang1b18c052021-01-29 18:12:07 +080016#include <linux/regulator/consumer.h>
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +010017#include <linux/soc/mediatek/infracfg.h>
18
Fabien Parent207f13b2020-12-09 14:32:37 +010019#include "mt8167-pm-domains.h"
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +010020#include "mt8173-pm-domains.h"
Matthias Bruggereb9fa762020-10-30 12:36:17 +010021#include "mt8183-pm-domains.h"
Weiyi Lua49d5e72020-10-30 12:36:22 +010022#include "mt8192-pm-domains.h"
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +010023
24#define MTK_POLL_DELAY_US 10
25#define MTK_POLL_TIMEOUT USEC_PER_SEC
26
27#define PWR_RST_B_BIT BIT(0)
28#define PWR_ISO_BIT BIT(1)
29#define PWR_ON_BIT BIT(2)
30#define PWR_ON_2ND_BIT BIT(3)
31#define PWR_CLK_DIS_BIT BIT(4)
Matthias Brugger58a17e32020-10-30 12:36:13 +010032#define PWR_SRAM_CLKISO_BIT BIT(5)
33#define PWR_SRAM_ISOINT_B_BIT BIT(6)
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +010034
35struct scpsys_domain {
36 struct generic_pm_domain genpd;
37 const struct scpsys_domain_data *data;
38 struct scpsys *scpsys;
39 int num_clks;
40 struct clk_bulk_data *clks;
Matthias Brugger123e8b42020-10-30 12:36:14 +010041 int num_subsys_clks;
42 struct clk_bulk_data *subsys_clks;
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +010043 struct regmap *infracfg;
Matthias Bruggerf4148542020-10-30 12:36:12 +010044 struct regmap *smi;
Hsin-Yi Wang1b18c052021-01-29 18:12:07 +080045 struct regulator *supply;
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +010046};
47
48struct scpsys {
49 struct device *dev;
50 struct regmap *base;
51 const struct scpsys_soc_data *soc_data;
52 struct genpd_onecell_data pd_data;
53 struct generic_pm_domain *domains[];
54};
55
56#define to_scpsys_domain(gpd) container_of(gpd, struct scpsys_domain, genpd)
57
58static bool scpsys_domain_is_on(struct scpsys_domain *pd)
59{
60 struct scpsys *scpsys = pd->scpsys;
61 u32 status, status2;
62
63 regmap_read(scpsys->base, scpsys->soc_data->pwr_sta_offs, &status);
64 status &= pd->data->sta_mask;
65
66 regmap_read(scpsys->base, scpsys->soc_data->pwr_sta2nd_offs, &status2);
67 status2 &= pd->data->sta_mask;
68
69 /* A domain is on when both status bits are set. */
70 return status && status2;
71}
72
73static int scpsys_sram_enable(struct scpsys_domain *pd)
74{
75 u32 pdn_ack = pd->data->sram_pdn_ack_bits;
76 struct scpsys *scpsys = pd->scpsys;
77 unsigned int tmp;
Matthias Brugger58a17e32020-10-30 12:36:13 +010078 int ret;
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +010079
80 regmap_clear_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bits);
81
82 /* Either wait until SRAM_PDN_ACK all 1 or 0 */
Matthias Brugger58a17e32020-10-30 12:36:13 +010083 ret = regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp,
84 (tmp & pdn_ack) == 0, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
85 if (ret < 0)
86 return ret;
87
88 if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) {
89 regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_ISOINT_B_BIT);
90 udelay(1);
91 regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_CLKISO_BIT);
92 }
93
94 return 0;
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +010095}
96
97static int scpsys_sram_disable(struct scpsys_domain *pd)
98{
99 u32 pdn_ack = pd->data->sram_pdn_ack_bits;
100 struct scpsys *scpsys = pd->scpsys;
101 unsigned int tmp;
102
Matthias Brugger58a17e32020-10-30 12:36:13 +0100103 if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) {
104 regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_CLKISO_BIT);
105 udelay(1);
106 regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_ISOINT_B_BIT);
107 }
108
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100109 regmap_set_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bits);
110
111 /* Either wait until SRAM_PDN_ACK all 1 or 0 */
112 return regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp,
113 (tmp & pdn_ack) == pdn_ack, MTK_POLL_DELAY_US,
114 MTK_POLL_TIMEOUT);
115}
116
Matthias Brugger928296e2020-10-30 12:36:11 +0100117static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, struct regmap *regmap)
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100118{
Matthias Brugger916d6d72020-10-30 12:36:10 +0100119 int i, ret;
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100120
Matthias Brugger916d6d72020-10-30 12:36:10 +0100121 for (i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) {
Matthias Brugger928296e2020-10-30 12:36:11 +0100122 u32 val, mask = bpd[i].bus_prot_mask;
123
124 if (!mask)
Matthias Brugger916d6d72020-10-30 12:36:10 +0100125 break;
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100126
Matthias Brugger928296e2020-10-30 12:36:11 +0100127 if (bpd[i].bus_prot_reg_update)
128 regmap_set_bits(regmap, bpd[i].bus_prot_set, mask);
129 else
Matthias Bruggerf4148542020-10-30 12:36:12 +0100130 regmap_write(regmap, bpd[i].bus_prot_set, mask);
Matthias Brugger928296e2020-10-30 12:36:11 +0100131
Matthias Bruggerf4148542020-10-30 12:36:12 +0100132 ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta,
Matthias Brugger928296e2020-10-30 12:36:11 +0100133 val, (val & mask) == mask,
134 MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
135 if (ret)
136 return ret;
137 }
138
139 return 0;
140}
141
142static int scpsys_bus_protect_enable(struct scpsys_domain *pd)
143{
144 int ret;
145
146 ret = _scpsys_bus_protect_enable(pd->data->bp_infracfg, pd->infracfg);
Matthias Bruggerf4148542020-10-30 12:36:12 +0100147 if (ret)
148 return ret;
Matthias Brugger928296e2020-10-30 12:36:11 +0100149
Matthias Bruggerf4148542020-10-30 12:36:12 +0100150 return _scpsys_bus_protect_enable(pd->data->bp_smi, pd->smi);
Matthias Brugger928296e2020-10-30 12:36:11 +0100151}
152
153static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd,
154 struct regmap *regmap)
155{
156 int i, ret;
157
158 for (i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) {
159 u32 val, mask = bpd[i].bus_prot_mask;
160
161 if (!mask)
162 continue;
163
164 if (bpd[i].bus_prot_reg_update)
165 regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask);
166 else
Matthias Bruggerf4148542020-10-30 12:36:12 +0100167 regmap_write(regmap, bpd[i].bus_prot_clr, mask);
Matthias Brugger928296e2020-10-30 12:36:11 +0100168
Matthias Brugger1d4597f2020-10-30 12:36:15 +0100169 if (bpd[i].ignore_clr_ack)
170 continue;
171
Matthias Bruggerf4148542020-10-30 12:36:12 +0100172 ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta,
Matthias Brugger928296e2020-10-30 12:36:11 +0100173 val, !(val & mask),
174 MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
Matthias Brugger916d6d72020-10-30 12:36:10 +0100175 if (ret)
176 return ret;
177 }
178
179 return 0;
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100180}
181
182static int scpsys_bus_protect_disable(struct scpsys_domain *pd)
183{
Matthias Brugger928296e2020-10-30 12:36:11 +0100184 int ret;
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100185
Matthias Bruggerf4148542020-10-30 12:36:12 +0100186 ret = _scpsys_bus_protect_disable(pd->data->bp_smi, pd->smi);
187 if (ret)
188 return ret;
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100189
Matthias Bruggerf4148542020-10-30 12:36:12 +0100190 return _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg);
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100191}
192
Hsin-Yi Wang1b18c052021-01-29 18:12:07 +0800193static int scpsys_regulator_enable(struct regulator *supply)
194{
195 return supply ? regulator_enable(supply) : 0;
196}
197
198static int scpsys_regulator_disable(struct regulator *supply)
199{
200 return supply ? regulator_disable(supply) : 0;
201}
202
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100203static int scpsys_power_on(struct generic_pm_domain *genpd)
204{
205 struct scpsys_domain *pd = container_of(genpd, struct scpsys_domain, genpd);
206 struct scpsys *scpsys = pd->scpsys;
207 bool tmp;
208 int ret;
209
Hsin-Yi Wang1b18c052021-01-29 18:12:07 +0800210 ret = scpsys_regulator_enable(pd->supply);
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100211 if (ret)
212 return ret;
213
Hsin-Yi Wang1b18c052021-01-29 18:12:07 +0800214 ret = clk_bulk_enable(pd->num_clks, pd->clks);
215 if (ret)
216 goto err_reg;
217
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100218 /* subsys power on */
219 regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT);
220 regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT);
221
222 /* wait until PWR_ACK = 1 */
223 ret = readx_poll_timeout(scpsys_domain_is_on, pd, tmp, tmp, MTK_POLL_DELAY_US,
224 MTK_POLL_TIMEOUT);
225 if (ret < 0)
226 goto err_pwr_ack;
227
228 regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT);
229 regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
230 regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
231
Matthias Brugger123e8b42020-10-30 12:36:14 +0100232 ret = clk_bulk_enable(pd->num_subsys_clks, pd->subsys_clks);
233 if (ret)
234 goto err_pwr_ack;
235
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100236 ret = scpsys_sram_enable(pd);
237 if (ret < 0)
Matthias Brugger123e8b42020-10-30 12:36:14 +0100238 goto err_disable_subsys_clks;
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100239
240 ret = scpsys_bus_protect_disable(pd);
241 if (ret < 0)
242 goto err_disable_sram;
243
244 return 0;
245
246err_disable_sram:
247 scpsys_sram_disable(pd);
Matthias Brugger123e8b42020-10-30 12:36:14 +0100248err_disable_subsys_clks:
249 clk_bulk_disable(pd->num_subsys_clks, pd->subsys_clks);
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100250err_pwr_ack:
251 clk_bulk_disable(pd->num_clks, pd->clks);
Hsin-Yi Wang1b18c052021-01-29 18:12:07 +0800252err_reg:
253 scpsys_regulator_disable(pd->supply);
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100254 return ret;
255}
256
257static int scpsys_power_off(struct generic_pm_domain *genpd)
258{
259 struct scpsys_domain *pd = container_of(genpd, struct scpsys_domain, genpd);
260 struct scpsys *scpsys = pd->scpsys;
261 bool tmp;
262 int ret;
263
264 ret = scpsys_bus_protect_enable(pd);
265 if (ret < 0)
266 return ret;
267
268 ret = scpsys_sram_disable(pd);
269 if (ret < 0)
270 return ret;
271
Matthias Brugger123e8b42020-10-30 12:36:14 +0100272 clk_bulk_disable(pd->num_subsys_clks, pd->subsys_clks);
273
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100274 /* subsys power off */
275 regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT);
276 regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT);
277 regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT);
278 regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT);
279 regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT);
280
281 /* wait until PWR_ACK = 0 */
282 ret = readx_poll_timeout(scpsys_domain_is_on, pd, tmp, !tmp, MTK_POLL_DELAY_US,
283 MTK_POLL_TIMEOUT);
284 if (ret < 0)
285 return ret;
286
287 clk_bulk_disable(pd->num_clks, pd->clks);
288
Hsin-Yi Wang1b18c052021-01-29 18:12:07 +0800289 scpsys_regulator_disable(pd->supply);
290
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100291 return 0;
292}
293
294static struct
295generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_node *node)
296{
297 const struct scpsys_domain_data *domain_data;
298 struct scpsys_domain *pd;
Hsin-Yi Wang1b18c052021-01-29 18:12:07 +0800299 struct device_node *root_node = scpsys->dev->of_node;
Matthias Brugger123e8b42020-10-30 12:36:14 +0100300 struct property *prop;
301 const char *clk_name;
302 int i, ret, num_clks;
303 struct clk *clk;
304 int clk_ind = 0;
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100305 u32 id;
306
307 ret = of_property_read_u32(node, "reg", &id);
308 if (ret) {
309 dev_err(scpsys->dev, "%pOF: failed to retrieve domain id from reg: %d\n",
310 node, ret);
311 return ERR_PTR(-EINVAL);
312 }
313
314 if (id >= scpsys->soc_data->num_domains) {
315 dev_err(scpsys->dev, "%pOF: invalid domain id %d\n", node, id);
316 return ERR_PTR(-EINVAL);
317 }
318
319 domain_data = &scpsys->soc_data->domains_data[id];
320 if (domain_data->sta_mask == 0) {
321 dev_err(scpsys->dev, "%pOF: undefined domain id %d\n", node, id);
322 return ERR_PTR(-EINVAL);
323 }
324
325 pd = devm_kzalloc(scpsys->dev, sizeof(*pd), GFP_KERNEL);
326 if (!pd)
327 return ERR_PTR(-ENOMEM);
328
329 pd->data = domain_data;
330 pd->scpsys = scpsys;
331
Hsin-Yi Wang1b18c052021-01-29 18:12:07 +0800332 if (MTK_SCPD_CAPS(pd, MTK_SCPD_DOMAIN_SUPPLY)) {
333 /*
334 * Find regulator in current power domain node.
335 * devm_regulator_get() finds regulator in a node and its child
336 * node, so set of_node to current power domain node then change
337 * back to original node after regulator is found for current
338 * power domain node.
339 */
340 scpsys->dev->of_node = node;
341 pd->supply = devm_regulator_get(scpsys->dev, "domain");
342 scpsys->dev->of_node = root_node;
343 if (IS_ERR(pd->supply)) {
344 dev_err_probe(scpsys->dev, PTR_ERR(pd->supply),
345 "%pOF: failed to get power supply.\n",
346 node);
347 return ERR_CAST(pd->supply);
348 }
349 }
350
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100351 pd->infracfg = syscon_regmap_lookup_by_phandle_optional(node, "mediatek,infracfg");
352 if (IS_ERR(pd->infracfg))
353 return ERR_CAST(pd->infracfg);
354
Matthias Bruggerf4148542020-10-30 12:36:12 +0100355 pd->smi = syscon_regmap_lookup_by_phandle_optional(node, "mediatek,smi");
356 if (IS_ERR(pd->smi))
357 return ERR_CAST(pd->smi);
358
Matthias Brugger123e8b42020-10-30 12:36:14 +0100359 num_clks = of_clk_get_parent_count(node);
360 if (num_clks > 0) {
361 /* Calculate number of subsys_clks */
362 of_property_for_each_string(node, "clock-names", prop, clk_name) {
363 char *subsys;
364
365 subsys = strchr(clk_name, '-');
366 if (subsys)
367 pd->num_subsys_clks++;
368 else
369 pd->num_clks++;
370 }
371
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100372 pd->clks = devm_kcalloc(scpsys->dev, pd->num_clks, sizeof(*pd->clks), GFP_KERNEL);
373 if (!pd->clks)
374 return ERR_PTR(-ENOMEM);
Matthias Brugger123e8b42020-10-30 12:36:14 +0100375
376 pd->subsys_clks = devm_kcalloc(scpsys->dev, pd->num_subsys_clks,
377 sizeof(*pd->subsys_clks), GFP_KERNEL);
378 if (!pd->subsys_clks)
379 return ERR_PTR(-ENOMEM);
380
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100381 }
382
383 for (i = 0; i < pd->num_clks; i++) {
Matthias Brugger123e8b42020-10-30 12:36:14 +0100384 clk = of_clk_get(node, i);
385 if (IS_ERR(clk)) {
386 ret = PTR_ERR(clk);
387 dev_err_probe(scpsys->dev, ret,
388 "%pOF: failed to get clk at index %d: %d\n", node, i, ret);
389 goto err_put_clocks;
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100390 }
Matthias Brugger123e8b42020-10-30 12:36:14 +0100391
392 pd->clks[clk_ind++].clk = clk;
393 }
394
395 for (i = 0; i < pd->num_subsys_clks; i++) {
396 clk = of_clk_get(node, i + clk_ind);
397 if (IS_ERR(clk)) {
398 ret = PTR_ERR(clk);
399 dev_err_probe(scpsys->dev, ret,
400 "%pOF: failed to get clk at index %d: %d\n", node,
401 i + clk_ind, ret);
402 goto err_put_subsys_clocks;
403 }
404
405 pd->subsys_clks[i].clk = clk;
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100406 }
407
408 ret = clk_bulk_prepare(pd->num_clks, pd->clks);
409 if (ret)
Matthias Brugger123e8b42020-10-30 12:36:14 +0100410 goto err_put_subsys_clocks;
411
412 ret = clk_bulk_prepare(pd->num_subsys_clks, pd->subsys_clks);
413 if (ret)
414 goto err_unprepare_clocks;
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100415
416 /*
417 * Initially turn on all domains to make the domains usable
418 * with !CONFIG_PM and to get the hardware in sync with the
419 * software. The unused domains will be switched off during
420 * late_init time.
421 */
Weiyi Luc1f31632020-10-30 12:36:21 +0100422 if (MTK_SCPD_CAPS(pd, MTK_SCPD_KEEP_DEFAULT_OFF)) {
423 if (scpsys_domain_is_on(pd))
424 dev_warn(scpsys->dev,
425 "%pOF: A default off power domain has been ON\n", node);
426 } else {
427 ret = scpsys_power_on(&pd->genpd);
428 if (ret < 0) {
429 dev_err(scpsys->dev, "%pOF: failed to power on domain: %d\n", node, ret);
430 goto err_unprepare_clocks;
431 }
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100432 }
433
434 if (scpsys->domains[id]) {
435 ret = -EINVAL;
436 dev_err(scpsys->dev,
437 "power domain with id %d already exists, check your device-tree\n", id);
Matthias Brugger123e8b42020-10-30 12:36:14 +0100438 goto err_unprepare_subsys_clocks;
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100439 }
440
Enric Balletbo i Serra022b02b2021-02-25 18:49:57 +0100441 if (!pd->data->name)
442 pd->genpd.name = node->name;
443 else
444 pd->genpd.name = pd->data->name;
445
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100446 pd->genpd.power_off = scpsys_power_off;
447 pd->genpd.power_on = scpsys_power_on;
448
Weiyi Luc1f31632020-10-30 12:36:21 +0100449 if (MTK_SCPD_CAPS(pd, MTK_SCPD_KEEP_DEFAULT_OFF))
450 pm_genpd_init(&pd->genpd, NULL, true);
451 else
452 pm_genpd_init(&pd->genpd, NULL, false);
453
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100454 scpsys->domains[id] = &pd->genpd;
455
456 return scpsys->pd_data.domains[id];
457
Matthias Brugger123e8b42020-10-30 12:36:14 +0100458err_unprepare_subsys_clocks:
459 clk_bulk_unprepare(pd->num_subsys_clks, pd->subsys_clks);
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100460err_unprepare_clocks:
461 clk_bulk_unprepare(pd->num_clks, pd->clks);
Matthias Brugger123e8b42020-10-30 12:36:14 +0100462err_put_subsys_clocks:
463 clk_bulk_put(pd->num_subsys_clks, pd->subsys_clks);
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100464err_put_clocks:
465 clk_bulk_put(pd->num_clks, pd->clks);
466 return ERR_PTR(ret);
467}
468
469static int scpsys_add_subdomain(struct scpsys *scpsys, struct device_node *parent)
470{
471 struct generic_pm_domain *child_pd, *parent_pd;
472 struct device_node *child;
473 int ret;
474
475 for_each_child_of_node(parent, child) {
476 u32 id;
477
478 ret = of_property_read_u32(parent, "reg", &id);
479 if (ret) {
480 dev_err(scpsys->dev, "%pOF: failed to get parent domain id\n", child);
481 goto err_put_node;
482 }
483
484 if (!scpsys->pd_data.domains[id]) {
485 ret = -EINVAL;
486 dev_err(scpsys->dev, "power domain with id %d does not exist\n", id);
487 goto err_put_node;
488 }
489
490 parent_pd = scpsys->pd_data.domains[id];
491
492 child_pd = scpsys_add_one_domain(scpsys, child);
493 if (IS_ERR(child_pd)) {
Enric Balletbo i Serra9950588a2021-03-03 10:10:54 +0100494 ret = PTR_ERR(child_pd);
495 dev_err_probe(scpsys->dev, ret, "%pOF: failed to get child domain id\n",
496 child);
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100497 goto err_put_node;
498 }
499
500 ret = pm_genpd_add_subdomain(parent_pd, child_pd);
501 if (ret) {
502 dev_err(scpsys->dev, "failed to add %s subdomain to parent %s\n",
503 child_pd->name, parent_pd->name);
504 goto err_put_node;
505 } else {
506 dev_dbg(scpsys->dev, "%s add subdomain: %s\n", parent_pd->name,
507 child_pd->name);
508 }
509
510 /* recursive call to add all subdomains */
511 ret = scpsys_add_subdomain(scpsys, child);
512 if (ret)
513 goto err_put_node;
514 }
515
516 return 0;
517
518err_put_node:
519 of_node_put(child);
520 return ret;
521}
522
523static void scpsys_remove_one_domain(struct scpsys_domain *pd)
524{
525 int ret;
526
Weiyi Luc1f31632020-10-30 12:36:21 +0100527 if (scpsys_domain_is_on(pd))
528 scpsys_power_off(&pd->genpd);
529
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100530 /*
531 * We're in the error cleanup already, so we only complain,
532 * but won't emit another error on top of the original one.
533 */
534 ret = pm_genpd_remove(&pd->genpd);
535 if (ret < 0)
536 dev_err(pd->scpsys->dev,
537 "failed to remove domain '%s' : %d - state may be inconsistent\n",
538 pd->genpd.name, ret);
539
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100540 clk_bulk_unprepare(pd->num_clks, pd->clks);
541 clk_bulk_put(pd->num_clks, pd->clks);
Matthias Brugger123e8b42020-10-30 12:36:14 +0100542
543 clk_bulk_unprepare(pd->num_subsys_clks, pd->subsys_clks);
544 clk_bulk_put(pd->num_subsys_clks, pd->subsys_clks);
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100545}
546
547static void scpsys_domain_cleanup(struct scpsys *scpsys)
548{
549 struct generic_pm_domain *genpd;
550 struct scpsys_domain *pd;
551 int i;
552
553 for (i = scpsys->pd_data.num_domains - 1; i >= 0; i--) {
554 genpd = scpsys->pd_data.domains[i];
555 if (genpd) {
556 pd = to_scpsys_domain(genpd);
557 scpsys_remove_one_domain(pd);
558 }
559 }
560}
561
562static const struct of_device_id scpsys_of_match[] = {
563 {
Fabien Parent207f13b2020-12-09 14:32:37 +0100564 .compatible = "mediatek,mt8167-power-controller",
565 .data = &mt8167_scpsys_data,
566 },
567 {
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100568 .compatible = "mediatek,mt8173-power-controller",
569 .data = &mt8173_scpsys_data,
570 },
Matthias Bruggereb9fa762020-10-30 12:36:17 +0100571 {
572 .compatible = "mediatek,mt8183-power-controller",
573 .data = &mt8183_scpsys_data,
574 },
Weiyi Lua49d5e72020-10-30 12:36:22 +0100575 {
576 .compatible = "mediatek,mt8192-power-controller",
577 .data = &mt8192_scpsys_data,
578 },
Enric Balletbo i Serra59b644b2020-10-30 12:36:08 +0100579 { }
580};
581
582static int scpsys_probe(struct platform_device *pdev)
583{
584 struct device *dev = &pdev->dev;
585 struct device_node *np = dev->of_node;
586 const struct scpsys_soc_data *soc;
587 struct device_node *node;
588 struct device *parent;
589 struct scpsys *scpsys;
590 int ret;
591
592 soc = of_device_get_match_data(&pdev->dev);
593 if (!soc) {
594 dev_err(&pdev->dev, "no power controller data\n");
595 return -EINVAL;
596 }
597
598 scpsys = devm_kzalloc(dev, struct_size(scpsys, domains, soc->num_domains), GFP_KERNEL);
599 if (!scpsys)
600 return -ENOMEM;
601
602 scpsys->dev = dev;
603 scpsys->soc_data = soc;
604
605 scpsys->pd_data.domains = scpsys->domains;
606 scpsys->pd_data.num_domains = soc->num_domains;
607
608 parent = dev->parent;
609 if (!parent) {
610 dev_err(dev, "no parent for syscon devices\n");
611 return -ENODEV;
612 }
613
614 scpsys->base = syscon_node_to_regmap(parent->of_node);
615 if (IS_ERR(scpsys->base)) {
616 dev_err(dev, "no regmap available\n");
617 return PTR_ERR(scpsys->base);
618 }
619
620 ret = -ENODEV;
621 for_each_available_child_of_node(np, node) {
622 struct generic_pm_domain *domain;
623
624 domain = scpsys_add_one_domain(scpsys, node);
625 if (IS_ERR(domain)) {
626 ret = PTR_ERR(domain);
627 of_node_put(node);
628 goto err_cleanup_domains;
629 }
630
631 ret = scpsys_add_subdomain(scpsys, node);
632 if (ret) {
633 of_node_put(node);
634 goto err_cleanup_domains;
635 }
636 }
637
638 if (ret) {
639 dev_dbg(dev, "no power domains present\n");
640 return ret;
641 }
642
643 ret = of_genpd_add_provider_onecell(np, &scpsys->pd_data);
644 if (ret) {
645 dev_err(dev, "failed to add provider: %d\n", ret);
646 goto err_cleanup_domains;
647 }
648
649 return 0;
650
651err_cleanup_domains:
652 scpsys_domain_cleanup(scpsys);
653 return ret;
654}
655
656static struct platform_driver scpsys_pm_domain_driver = {
657 .probe = scpsys_probe,
658 .driver = {
659 .name = "mtk-power-controller",
660 .suppress_bind_attrs = true,
661 .of_match_table = scpsys_of_match,
662 },
663};
664builtin_platform_driver(scpsys_pm_domain_driver);