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review.shift-gmbh.com / SHIFTPHONES / mainline / linux / fcaf20360a5992b88603271ab814a200e28d0088 / . / drivers / clk / imx / clk-imx7d.c
blob: 8f3aa994c8f7b07aa68a69742fc22621bfb41068 [file] [log] [blame]
Thomas Gleixnerfcaf2032019-05-27 08:55:08 +0200[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-or-later
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]2/*
3 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]4 */
5
6#include <dt-bindings/clock/imx7d-clock.h>
7#include <linux/clk.h>
8#include <linux/clkdev.h>
9#include <linux/err.h>
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/of.h>
13#include <linux/of_address.h>
14#include <linux/of_irq.h>
15#include <linux/types.h>
16
17#include "clk.h"
18
Fabio Estevam06981022016-08-12 15:26:56 -0300[diff] [blame]19static u32 share_count_sai1;
20static u32 share_count_sai2;
21static u32 share_count_sai3;
Stefan Agner22039d12017-06-08 15:34:47 -0700[diff] [blame]22static u32 share_count_nand;
Anson Huang9c7150d2018-05-18 09:01:05 +0800[diff] [blame]23static u32 share_count_enet1;
24static u32 share_count_enet2;
Fabio Estevam06981022016-08-12 15:26:56 -0300[diff] [blame]25
Arvind Yadavfdda6ee2017-08-28 10:58:52 +0530[diff] [blame]26static const struct clk_div_table test_div_table[] = {
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]27 { .val = 3, .div = 1, },
28 { .val = 2, .div = 1, },
29 { .val = 1, .div = 2, },
30 { .val = 0, .div = 4, },
31 { }
32};
33
Arvind Yadavfdda6ee2017-08-28 10:58:52 +0530[diff] [blame]34static const struct clk_div_table post_div_table[] = {
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]35 { .val = 3, .div = 4, },
36 { .val = 2, .div = 1, },
37 { .val = 1, .div = 2, },
38 { .val = 0, .div = 1, },
39 { }
40};
41
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]42static struct clk *clks[IMX7D_CLK_END];
43static const char *arm_a7_sel[] = { "osc", "pll_arm_main_clk",
44 "pll_enet_500m_clk", "pll_dram_main_clk",
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]45 "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_audio_post_div",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]46 "pll_usb_main_clk", };
47
48static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk",
49 "pll_enet_250m_clk", "pll_sys_pfd2_270m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]50 "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]51 "pll_usb_main_clk", };
52
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]53static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
54 "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]55 "pll_audio_post_div", "pll_video_post_div", "pll_sys_pfd7_clk", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]56
57static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
58 "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd6_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]59 "pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_post_div", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]60
61static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
62 "pll_dram_533m_clk", "pll_enet_250m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]63 "pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_post_div",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]64 "pll_sys_pfd4_clk", };
65
66static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
67 "pll_dram_533m_clk", "pll_sys_main_240m_clk",
68 "pll_sys_pfd2_135m_clk", "pll_sys_pfd6_clk", "pll_enet_250m_clk",
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]69 "pll_audio_post_div", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]70
Stefan Agner92a847e2016-04-28 14:07:03 -0700[diff] [blame]71static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]72 "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk",
Anson Huanga12ec8b2018-03-28 09:46:38 +0300[diff] [blame]73 "pll_enet_250m_clk", "pll_usb_main_clk", "pll_audio_post_div",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]74 "pll_video_post_div", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]75
76static const char *dram_phym_sel[] = { "pll_dram_main_clk",
77 "dram_phym_alt_clk", };
78
79static const char *dram_sel[] = { "pll_dram_main_clk",
Anson Huang7e797d92016-06-08 22:33:32 +0800[diff] [blame]80 "dram_alt_root_clk", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]81
82static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk",
83 "pll_sys_main_clk", "pll_enet_500m_clk",
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]84 "pll_usb_main_clk", "pll_sys_pfd7_clk", "pll_audio_post_div",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]85 "pll_video_post_div", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]86
87static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk",
88 "pll_sys_main_clk", "pll_enet_500m_clk",
89 "pll_enet_250m_clk", "pll_sys_pfd0_392m_clk",
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]90 "pll_audio_post_div", "pll_sys_pfd2_270m_clk", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]91
92static const char *usb_hsic_sel[] = { "osc", "pll_sys_main_clk",
93 "pll_usb_main_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk",
94 "pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", };
95
96static const char *pcie_ctrl_sel[] = { "osc", "pll_enet_250m_clk",
97 "pll_sys_main_240m_clk", "pll_sys_pfd2_270m_clk",
98 "pll_dram_533m_clk", "pll_enet_500m_clk",
99 "pll_sys_pfd1_332m_clk", "pll_sys_pfd6_clk", };
100
101static const char *pcie_phy_sel[] = { "osc", "pll_enet_100m_clk",
102 "pll_enet_500m_clk", "ext_clk_1", "ext_clk_2", "ext_clk_3",
103 "ext_clk_4", "pll_sys_pfd0_392m_clk", };
104
105static const char *epdc_pixel_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
106 "pll_dram_533m_clk", "pll_sys_main_clk", "pll_sys_pfd5_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]107 "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", "pll_video_post_div", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]108
109static const char *lcdif_pixel_sel[] = { "osc", "pll_sys_pfd5_clk",
110 "pll_dram_533m_clk", "ext_clk_3", "pll_sys_pfd4_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]111 "pll_sys_pfd2_270m_clk", "pll_video_post_div",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]112 "pll_usb_main_clk", };
113
114static const char *mipi_dsi_sel[] = { "osc", "pll_sys_pfd5_clk",
115 "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]116 "pll_dram_533m_clk", "pll_video_post_div", "pll_audio_post_div", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]117
118static const char *mipi_csi_sel[] = { "osc", "pll_sys_pfd4_clk",
119 "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]120 "pll_dram_533m_clk", "pll_video_post_div", "pll_audio_post_div", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]121
122static const char *mipi_dphy_sel[] = { "osc", "pll_sys_main_120m_clk",
123 "pll_dram_533m_clk", "pll_sys_pfd5_clk", "ref_1m_clk", "ext_clk_2",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]124 "pll_video_post_div", "ext_clk_3", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]125
126static const char *sai1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]127 "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]128 "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", };
129
130static const char *sai2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]131 "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]132 "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", };
133
134static const char *sai3_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]135 "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]136 "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_3", };
137
138static const char *spdif_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]139 "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_post_div",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]140 "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_3_clk", };
141
142static const char *enet1_ref_sel[] = { "osc", "pll_enet_125m_clk",
143 "pll_enet_50m_clk", "pll_enet_25m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]144 "pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_post_div",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]145 "ext_clk_4", };
146
147static const char *enet1_time_sel[] = { "osc", "pll_enet_100m_clk",
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]148 "pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]149 "ext_clk_4", "pll_video_post_div", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]150
151static const char *enet2_ref_sel[] = { "osc", "pll_enet_125m_clk",
152 "pll_enet_50m_clk", "pll_enet_25m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]153 "pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_post_div",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]154 "ext_clk_4", };
155
156static const char *enet2_time_sel[] = { "osc", "pll_enet_100m_clk",
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]157 "pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]158 "ext_clk_4", "pll_video_post_div", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]159
160static const char *enet_phy_ref_sel[] = { "osc", "pll_enet_25m_clk",
161 "pll_enet_50m_clk", "pll_enet_125m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]162 "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_post_div",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]163 "pll_sys_pfd3_clk", };
164
165static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
166 "pll_sys_main_120m_clk", "pll_dram_533m_clk",
167 "pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_enet_125m_clk",
168 "pll_usb_main_clk", };
169
170static const char *nand_sel[] = { "osc", "pll_sys_main_clk",
171 "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd3_clk",
172 "pll_enet_500m_clk", "pll_enet_250m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]173 "pll_video_post_div", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]174
175static const char *qspi_sel[] = { "osc", "pll_sys_pfd4_clk",
176 "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd3_clk",
177 "pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", };
178
179static const char *usdhc1_sel[] = { "osc", "pll_sys_pfd0_392m_clk",
180 "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd4_clk",
181 "pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", };
182
183static const char *usdhc2_sel[] = { "osc", "pll_sys_pfd0_392m_clk",
184 "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd4_clk",
185 "pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", };
186
187static const char *usdhc3_sel[] = { "osc", "pll_sys_pfd0_392m_clk",
188 "pll_dram_533m_clk", "pll_enet_500m_clk", "pll_sys_pfd4_clk",
189 "pll_sys_pfd2_270m_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", };
190
191static const char *can1_sel[] = { "osc", "pll_sys_main_120m_clk",
192 "pll_dram_533m_clk", "pll_sys_main_clk",
193 "pll_enet_40m_clk", "pll_usb_main_clk", "ext_clk_1",
194 "ext_clk_4", };
195
196static const char *can2_sel[] = { "osc", "pll_sys_main_120m_clk",
197 "pll_dram_533m_clk", "pll_sys_main_clk",
198 "pll_enet_40m_clk", "pll_usb_main_clk", "ext_clk_1",
199 "ext_clk_3", };
200
201static const char *i2c1_sel[] = { "osc", "pll_sys_main_120m_clk",
202 "pll_enet_50m_clk", "pll_dram_533m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]203 "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]204 "pll_sys_pfd2_135m_clk", };
205
206static const char *i2c2_sel[] = { "osc", "pll_sys_main_120m_clk",
207 "pll_enet_50m_clk", "pll_dram_533m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]208 "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]209 "pll_sys_pfd2_135m_clk", };
210
211static const char *i2c3_sel[] = { "osc", "pll_sys_main_120m_clk",
212 "pll_enet_50m_clk", "pll_dram_533m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]213 "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]214 "pll_sys_pfd2_135m_clk", };
215
216static const char *i2c4_sel[] = { "osc", "pll_sys_main_120m_clk",
217 "pll_enet_50m_clk", "pll_dram_533m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]218 "pll_audio_post_div", "pll_video_post_div", "pll_usb_main_clk",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]219 "pll_sys_pfd2_135m_clk", };
220
221static const char *uart1_sel[] = { "osc", "pll_sys_main_240m_clk",
222 "pll_enet_40m_clk", "pll_enet_100m_clk",
223 "pll_sys_main_clk", "ext_clk_2", "ext_clk_4",
224 "pll_usb_main_clk", };
225
226static const char *uart2_sel[] = { "osc", "pll_sys_main_240m_clk",
227 "pll_enet_40m_clk", "pll_enet_100m_clk",
228 "pll_sys_main_clk", "ext_clk_2", "ext_clk_3",
229 "pll_usb_main_clk", };
230
231static const char *uart3_sel[] = { "osc", "pll_sys_main_240m_clk",
232 "pll_enet_40m_clk", "pll_enet_100m_clk",
233 "pll_sys_main_clk", "ext_clk_2", "ext_clk_4",
234 "pll_usb_main_clk", };
235
236static const char *uart4_sel[] = { "osc", "pll_sys_main_240m_clk",
237 "pll_enet_40m_clk", "pll_enet_100m_clk",
238 "pll_sys_main_clk", "ext_clk_2", "ext_clk_3",
239 "pll_usb_main_clk", };
240
241static const char *uart5_sel[] = { "osc", "pll_sys_main_240m_clk",
242 "pll_enet_40m_clk", "pll_enet_100m_clk",
243 "pll_sys_main_clk", "ext_clk_2", "ext_clk_4",
244 "pll_usb_main_clk", };
245
246static const char *uart6_sel[] = { "osc", "pll_sys_main_240m_clk",
247 "pll_enet_40m_clk", "pll_enet_100m_clk",
248 "pll_sys_main_clk", "ext_clk_2", "ext_clk_3",
249 "pll_usb_main_clk", };
250
251static const char *uart7_sel[] = { "osc", "pll_sys_main_240m_clk",
252 "pll_enet_40m_clk", "pll_enet_100m_clk",
253 "pll_sys_main_clk", "ext_clk_2", "ext_clk_4",
254 "pll_usb_main_clk", };
255
256static const char *ecspi1_sel[] = { "osc", "pll_sys_main_240m_clk",
257 "pll_enet_40m_clk", "pll_sys_main_120m_clk",
258 "pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk",
259 "pll_usb_main_clk", };
260
261static const char *ecspi2_sel[] = { "osc", "pll_sys_main_240m_clk",
262 "pll_enet_40m_clk", "pll_sys_main_120m_clk",
263 "pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk",
264 "pll_usb_main_clk", };
265
266static const char *ecspi3_sel[] = { "osc", "pll_sys_main_240m_clk",
267 "pll_enet_40m_clk", "pll_sys_main_120m_clk",
268 "pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk",
269 "pll_usb_main_clk", };
270
271static const char *ecspi4_sel[] = { "osc", "pll_sys_main_240m_clk",
272 "pll_enet_40m_clk", "pll_sys_main_120m_clk",
273 "pll_sys_main_clk", "pll_sys_pfd4_clk", "pll_enet_250m_clk",
274 "pll_usb_main_clk", };
275
276static const char *pwm1_sel[] = { "osc", "pll_enet_100m_clk",
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]277 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]278 "ext_clk_1", "ref_1m_clk", "pll_video_post_div", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]279
280static const char *pwm2_sel[] = { "osc", "pll_enet_100m_clk",
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]281 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]282 "ext_clk_1", "ref_1m_clk", "pll_video_post_div", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]283
284static const char *pwm3_sel[] = { "osc", "pll_enet_100m_clk",
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]285 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]286 "ext_clk_2", "ref_1m_clk", "pll_video_post_div", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]287
288static const char *pwm4_sel[] = { "osc", "pll_enet_100m_clk",
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]289 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]290 "ext_clk_2", "ref_1m_clk", "pll_video_post_div", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]291
292static const char *flextimer1_sel[] = { "osc", "pll_enet_100m_clk",
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]293 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]294 "ext_clk_3", "ref_1m_clk", "pll_video_post_div", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]295
296static const char *flextimer2_sel[] = { "osc", "pll_enet_100m_clk",
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]297 "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]298 "ext_clk_3", "ref_1m_clk", "pll_video_post_div", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]299
300static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
301 "pll_sys_main_120m_clk", "pll_dram_533m_clk",
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]302 "pll_usb_main_clk", "pll_audio_post_div", "pll_enet_125m_clk",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]303 "pll_sys_pfd7_clk", };
304
305static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
306 "pll_sys_main_120m_clk", "pll_dram_533m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]307 "pll_usb_main_clk", "pll_video_post_div", "pll_enet_125m_clk",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]308 "pll_sys_pfd7_clk", };
309
310static const char *gpt1_sel[] = { "osc", "pll_enet_100m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]311 "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]312 "ref_1m_clk", "pll_audio_post_div", "ext_clk_1", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]313
314static const char *gpt2_sel[] = { "osc", "pll_enet_100m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]315 "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]316 "ref_1m_clk", "pll_audio_post_div", "ext_clk_2", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]317
318static const char *gpt3_sel[] = { "osc", "pll_enet_100m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]319 "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]320 "ref_1m_clk", "pll_audio_post_div", "ext_clk_3", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]321
322static const char *gpt4_sel[] = { "osc", "pll_enet_100m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]323 "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_post_div",
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]324 "ref_1m_clk", "pll_audio_post_div", "ext_clk_4", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]325
326static const char *trace_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
327 "pll_sys_main_120m_clk", "pll_dram_533m_clk",
328 "pll_enet_125m_clk", "pll_usb_main_clk", "ext_clk_2",
329 "ext_clk_3", };
330
331static const char *wdog_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
332 "pll_sys_main_120m_clk", "pll_dram_533m_clk",
333 "pll_enet_125m_clk", "pll_usb_main_clk", "ref_1m_clk",
334 "pll_sys_pfd1_166m_clk", };
335
336static const char *csi_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
337 "pll_sys_main_120m_clk", "pll_dram_533m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]338 "pll_enet_125m_clk", "pll_audio_post_div", "pll_video_post_div",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]339 "pll_usb_main_clk", };
340
341static const char *audio_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk",
342 "pll_sys_main_120m_clk", "pll_dram_533m_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]343 "pll_enet_125m_clk", "pll_audio_post_div", "pll_video_post_div",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]344 "pll_usb_main_clk", };
345
346static const char *wrclk_sel[] = { "osc", "pll_enet_40m_clk",
347 "pll_dram_533m_clk", "pll_usb_main_clk",
348 "pll_sys_main_240m_clk", "pll_sys_pfd2_270m_clk",
349 "pll_enet_500m_clk", "pll_sys_pfd7_clk", };
350
351static const char *clko1_sel[] = { "osc", "pll_sys_main_clk",
352 "pll_sys_main_240m_clk", "pll_sys_pfd0_196m_clk", "pll_sys_pfd3_clk",
353 "pll_enet_500m_clk", "pll_dram_533m_clk", "ref_1m_clk", };
354
355static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk",
356 "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_166m_clk", "pll_sys_pfd4_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]357 "pll_audio_post_div", "pll_video_post_div", "ckil", };
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]358
359static const char *lvds1_sel[] = { "pll_arm_main_clk",
360 "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk",
361 "pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk",
362 "pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk",
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]363 "pll_audio_post_div", "pll_video_post_div", "pll_enet_500m_clk",
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]364 "pll_enet_250m_clk", "pll_enet_125m_clk", "pll_enet_100m_clk",
365 "pll_enet_50m_clk", "pll_enet_40m_clk", "pll_enet_25m_clk",
366 "pll_dram_main_clk", };
367
368static const char *pll_bypass_src_sel[] = { "osc", "dummy", };
369static const char *pll_arm_bypass_sel[] = { "pll_arm_main", "pll_arm_main_src", };
370static const char *pll_dram_bypass_sel[] = { "pll_dram_main", "pll_dram_main_src", };
371static const char *pll_sys_bypass_sel[] = { "pll_sys_main", "pll_sys_main_src", };
372static const char *pll_enet_bypass_sel[] = { "pll_enet_main", "pll_enet_main_src", };
373static const char *pll_audio_bypass_sel[] = { "pll_audio_main", "pll_audio_main_src", };
374static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_src", };
375
376static struct clk_onecell_data clk_data;
377
Lucas Stach1b9af682015-09-21 18:54:04 +0200[diff] [blame]378static struct clk ** const uart_clks[] __initconst = {
379 &clks[IMX7D_UART1_ROOT_CLK],
380 &clks[IMX7D_UART2_ROOT_CLK],
381 &clks[IMX7D_UART3_ROOT_CLK],
382 &clks[IMX7D_UART4_ROOT_CLK],
383 &clks[IMX7D_UART5_ROOT_CLK],
384 &clks[IMX7D_UART6_ROOT_CLK],
385 &clks[IMX7D_UART7_ROOT_CLK],
386 NULL
387};
388
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]389static void __init imx7d_clocks_init(struct device_node *ccm_node)
390{
391 struct device_node *np;
392 void __iomem *base;
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]393
394 clks[IMX7D_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
395 clks[IMX7D_OSC_24M_CLK] = of_clk_get_by_name(ccm_node, "osc");
Gary Bisson4aba2752016-04-02 18:25:45 +0200[diff] [blame]396 clks[IMX7D_CKIL] = of_clk_get_by_name(ccm_node, "ckil");
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]397
398 np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-anatop");
399 base = of_iomap(np, 0);
400 WARN_ON(!base);
Yangtao Li5f8c1832018-12-26 08:57:16 -0500[diff] [blame]401 of_node_put(np);
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]402
403 clks[IMX7D_PLL_ARM_MAIN_SRC] = imx_clk_mux("pll_arm_main_src", base + 0x60, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
404 clks[IMX7D_PLL_DRAM_MAIN_SRC] = imx_clk_mux("pll_dram_main_src", base + 0x70, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
405 clks[IMX7D_PLL_SYS_MAIN_SRC] = imx_clk_mux("pll_sys_main_src", base + 0xb0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
406 clks[IMX7D_PLL_ENET_MAIN_SRC] = imx_clk_mux("pll_enet_main_src", base + 0xe0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
407 clks[IMX7D_PLL_AUDIO_MAIN_SRC] = imx_clk_mux("pll_audio_main_src", base + 0xf0, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
408 clks[IMX7D_PLL_VIDEO_MAIN_SRC] = imx_clk_mux("pll_video_main_src", base + 0x130, 14, 2, pll_bypass_src_sel, ARRAY_SIZE(pll_bypass_src_sel));
409
Dong Aishengf83d3162016-06-08 22:33:36 +0800[diff] [blame]410 clks[IMX7D_PLL_ARM_MAIN] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll_arm_main", "osc", base + 0x60, 0x7f);
Fabio Estevamad149722017-05-15 08:55:05 -0300[diff] [blame]411 clks[IMX7D_PLL_DRAM_MAIN] = imx_clk_pllv3(IMX_PLLV3_DDR_IMX7, "pll_dram_main", "osc", base + 0x70, 0x7f);
Dong Aishengf83d3162016-06-08 22:33:36 +0800[diff] [blame]412 clks[IMX7D_PLL_SYS_MAIN] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll_sys_main", "osc", base + 0xb0, 0x1);
413 clks[IMX7D_PLL_ENET_MAIN] = imx_clk_pllv3(IMX_PLLV3_ENET_IMX7, "pll_enet_main", "osc", base + 0xe0, 0x0);
Anson Huangb4a4cb52019-04-22 08:32:45 +0000[diff] [blame]414 clks[IMX7D_PLL_AUDIO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV_IMX7, "pll_audio_main", "osc", base + 0xf0, 0x7f);
415 clks[IMX7D_PLL_VIDEO_MAIN] = imx_clk_pllv3(IMX_PLLV3_AV_IMX7, "pll_video_main", "osc", base + 0x130, 0x7f);
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]416
417 clks[IMX7D_PLL_ARM_MAIN_BYPASS] = imx_clk_mux_flags("pll_arm_main_bypass", base + 0x60, 16, 1, pll_arm_bypass_sel, ARRAY_SIZE(pll_arm_bypass_sel), CLK_SET_RATE_PARENT);
418 clks[IMX7D_PLL_DRAM_MAIN_BYPASS] = imx_clk_mux_flags("pll_dram_main_bypass", base + 0x70, 16, 1, pll_dram_bypass_sel, ARRAY_SIZE(pll_dram_bypass_sel), CLK_SET_RATE_PARENT);
419 clks[IMX7D_PLL_SYS_MAIN_BYPASS] = imx_clk_mux_flags("pll_sys_main_bypass", base + 0xb0, 16, 1, pll_sys_bypass_sel, ARRAY_SIZE(pll_sys_bypass_sel), CLK_SET_RATE_PARENT);
420 clks[IMX7D_PLL_ENET_MAIN_BYPASS] = imx_clk_mux_flags("pll_enet_main_bypass", base + 0xe0, 16, 1, pll_enet_bypass_sel, ARRAY_SIZE(pll_enet_bypass_sel), CLK_SET_RATE_PARENT);
421 clks[IMX7D_PLL_AUDIO_MAIN_BYPASS] = imx_clk_mux_flags("pll_audio_main_bypass", base + 0xf0, 16, 1, pll_audio_bypass_sel, ARRAY_SIZE(pll_audio_bypass_sel), CLK_SET_RATE_PARENT);
422 clks[IMX7D_PLL_VIDEO_MAIN_BYPASS] = imx_clk_mux_flags("pll_video_main_bypass", base + 0x130, 16, 1, pll_video_bypass_sel, ARRAY_SIZE(pll_video_bypass_sel), CLK_SET_RATE_PARENT);
423
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]424 clks[IMX7D_PLL_ARM_MAIN_CLK] = imx_clk_gate("pll_arm_main_clk", "pll_arm_main_bypass", base + 0x60, 13);
Anson Huangafe7c082018-03-28 09:46:37 +0300[diff] [blame]425 clks[IMX7D_PLL_DRAM_MAIN_CLK] = imx_clk_gate("pll_dram_main_clk", "pll_dram_test_div", base + 0x70, 13);
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]426 clks[IMX7D_PLL_SYS_MAIN_CLK] = imx_clk_gate("pll_sys_main_clk", "pll_sys_main_bypass", base + 0xb0, 13);
427 clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13);
428 clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13);
429
Anson Huangafe7c082018-03-28 09:46:37 +0300[diff] [blame]430 clks[IMX7D_PLL_DRAM_TEST_DIV] = clk_register_divider_table(NULL, "pll_dram_test_div", "pll_dram_main_bypass",
431 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 21, 2, 0, test_div_table, &imx_ccm_lock);
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]432 clks[IMX7D_PLL_AUDIO_TEST_DIV] = clk_register_divider_table(NULL, "pll_audio_test_div", "pll_audio_main_clk",
433 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock);
434 clks[IMX7D_PLL_AUDIO_POST_DIV] = clk_register_divider_table(NULL, "pll_audio_post_div", "pll_audio_test_div",
435 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock);
Anson Huangb716aad2018-01-04 01:09:21 +0800[diff] [blame]436 clks[IMX7D_PLL_VIDEO_TEST_DIV] = clk_register_divider_table(NULL, "pll_video_test_div", "pll_video_main_clk",
437 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 19, 2, 0, test_div_table, &imx_ccm_lock);
438 clks[IMX7D_PLL_VIDEO_POST_DIV] = clk_register_divider_table(NULL, "pll_video_post_div", "pll_video_test_div",
439 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 22, 2, 0, post_div_table, &imx_ccm_lock);
Fabio Estevam54fe0792016-08-30 14:34:01 -0300[diff] [blame]440
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]441 clks[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main_clk", base + 0xc0, 0);
442 clks[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main_clk", base + 0xc0, 1);
443 clks[IMX7D_PLL_SYS_PFD2_270M_CLK] = imx_clk_pfd("pll_sys_pfd2_270m_clk", "pll_sys_main_clk", base + 0xc0, 2);
444
445 clks[IMX7D_PLL_SYS_PFD3_CLK] = imx_clk_pfd("pll_sys_pfd3_clk", "pll_sys_main_clk", base + 0xc0, 3);
446 clks[IMX7D_PLL_SYS_PFD4_CLK] = imx_clk_pfd("pll_sys_pfd4_clk", "pll_sys_main_clk", base + 0xd0, 0);
447 clks[IMX7D_PLL_SYS_PFD5_CLK] = imx_clk_pfd("pll_sys_pfd5_clk", "pll_sys_main_clk", base + 0xd0, 1);
448 clks[IMX7D_PLL_SYS_PFD6_CLK] = imx_clk_pfd("pll_sys_pfd6_clk", "pll_sys_main_clk", base + 0xd0, 2);
449 clks[IMX7D_PLL_SYS_PFD7_CLK] = imx_clk_pfd("pll_sys_pfd7_clk", "pll_sys_main_clk", base + 0xd0, 3);
450
451 clks[IMX7D_PLL_SYS_MAIN_480M] = imx_clk_fixed_factor("pll_sys_main_480m", "pll_sys_main_clk", 1, 1);
452 clks[IMX7D_PLL_SYS_MAIN_240M] = imx_clk_fixed_factor("pll_sys_main_240m", "pll_sys_main_clk", 1, 2);
453 clks[IMX7D_PLL_SYS_MAIN_120M] = imx_clk_fixed_factor("pll_sys_main_120m", "pll_sys_main_clk", 1, 4);
454 clks[IMX7D_PLL_DRAM_MAIN_533M] = imx_clk_fixed_factor("pll_dram_533m", "pll_dram_main_clk", 1, 2);
455
Anson Huangfebb6542018-08-08 12:39:27 +0800[diff] [blame]456 clks[IMX7D_PLL_SYS_MAIN_480M_CLK] = imx_clk_gate_dis_flags("pll_sys_main_480m_clk", "pll_sys_main_480m", base + 0xb0, 4, CLK_IS_CRITICAL);
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]457 clks[IMX7D_PLL_SYS_MAIN_240M_CLK] = imx_clk_gate_dis("pll_sys_main_240m_clk", "pll_sys_main_240m", base + 0xb0, 5);
458 clks[IMX7D_PLL_SYS_MAIN_120M_CLK] = imx_clk_gate_dis("pll_sys_main_120m_clk", "pll_sys_main_120m", base + 0xb0, 6);
459 clks[IMX7D_PLL_DRAM_MAIN_533M_CLK] = imx_clk_gate("pll_dram_533m_clk", "pll_dram_533m", base + 0x70, 12);
460
461 clks[IMX7D_PLL_SYS_PFD0_196M] = imx_clk_fixed_factor("pll_sys_pfd0_196m", "pll_sys_pfd0_392m_clk", 1, 2);
462 clks[IMX7D_PLL_SYS_PFD1_166M] = imx_clk_fixed_factor("pll_sys_pfd1_166m", "pll_sys_pfd1_332m_clk", 1, 2);
463 clks[IMX7D_PLL_SYS_PFD2_135M] = imx_clk_fixed_factor("pll_sys_pfd2_135m", "pll_sys_pfd2_270m_clk", 1, 2);
464
465 clks[IMX7D_PLL_SYS_PFD0_196M_CLK] = imx_clk_gate_dis("pll_sys_pfd0_196m_clk", "pll_sys_pfd0_196m", base + 0xb0, 26);
466 clks[IMX7D_PLL_SYS_PFD1_166M_CLK] = imx_clk_gate_dis("pll_sys_pfd1_166m_clk", "pll_sys_pfd1_166m", base + 0xb0, 27);
467 clks[IMX7D_PLL_SYS_PFD2_135M_CLK] = imx_clk_gate_dis("pll_sys_pfd2_135m_clk", "pll_sys_pfd2_135m", base + 0xb0, 28);
468
469 clks[IMX7D_PLL_ENET_MAIN_CLK] = imx_clk_fixed_factor("pll_enet_main_clk", "pll_enet_main_bypass", 1, 1);
470 clks[IMX7D_PLL_ENET_MAIN_500M] = imx_clk_fixed_factor("pll_enet_500m", "pll_enet_main_clk", 1, 2);
471 clks[IMX7D_PLL_ENET_MAIN_250M] = imx_clk_fixed_factor("pll_enet_250m", "pll_enet_main_clk", 1, 4);
472 clks[IMX7D_PLL_ENET_MAIN_125M] = imx_clk_fixed_factor("pll_enet_125m", "pll_enet_main_clk", 1, 8);
473 clks[IMX7D_PLL_ENET_MAIN_100M] = imx_clk_fixed_factor("pll_enet_100m", "pll_enet_main_clk", 1, 10);
474 clks[IMX7D_PLL_ENET_MAIN_50M] = imx_clk_fixed_factor("pll_enet_50m", "pll_enet_main_clk", 1, 20);
475 clks[IMX7D_PLL_ENET_MAIN_40M] = imx_clk_fixed_factor("pll_enet_40m", "pll_enet_main_clk", 1, 25);
476 clks[IMX7D_PLL_ENET_MAIN_25M] = imx_clk_fixed_factor("pll_enet_25m", "pll_enet_main_clk", 1, 40);
477
478 clks[IMX7D_PLL_ENET_MAIN_500M_CLK] = imx_clk_gate("pll_enet_500m_clk", "pll_enet_500m", base + 0xe0, 12);
479 clks[IMX7D_PLL_ENET_MAIN_250M_CLK] = imx_clk_gate("pll_enet_250m_clk", "pll_enet_250m", base + 0xe0, 11);
480 clks[IMX7D_PLL_ENET_MAIN_125M_CLK] = imx_clk_gate("pll_enet_125m_clk", "pll_enet_125m", base + 0xe0, 10);
481 clks[IMX7D_PLL_ENET_MAIN_100M_CLK] = imx_clk_gate("pll_enet_100m_clk", "pll_enet_100m", base + 0xe0, 9);
482 clks[IMX7D_PLL_ENET_MAIN_50M_CLK] = imx_clk_gate("pll_enet_50m_clk", "pll_enet_50m", base + 0xe0, 8);
483 clks[IMX7D_PLL_ENET_MAIN_40M_CLK] = imx_clk_gate("pll_enet_40m_clk", "pll_enet_40m", base + 0xe0, 7);
484 clks[IMX7D_PLL_ENET_MAIN_25M_CLK] = imx_clk_gate("pll_enet_25m_clk", "pll_enet_25m", base + 0xe0, 6);
485
486 clks[IMX7D_LVDS1_OUT_SEL] = imx_clk_mux("lvds1_sel", base + 0x170, 0, 5, lvds1_sel, ARRAY_SIZE(lvds1_sel));
487 clks[IMX7D_LVDS1_OUT_CLK] = imx_clk_gate_exclusive("lvds1_out", "lvds1_sel", base + 0x170, 5, BIT(6));
488
489 np = ccm_node;
490 base = of_iomap(np, 0);
491 WARN_ON(!base);
492
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]493 clks[IMX7D_ARM_A7_ROOT_SRC] = imx_clk_mux2("arm_a7_src", base + 0x8000, 24, 3, arm_a7_sel, ARRAY_SIZE(arm_a7_sel));
494 clks[IMX7D_ARM_M4_ROOT_SRC] = imx_clk_mux2("arm_m4_src", base + 0x8080, 24, 3, arm_m4_sel, ARRAY_SIZE(arm_m4_sel));
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]495 clks[IMX7D_MAIN_AXI_ROOT_SRC] = imx_clk_mux2("axi_src", base + 0x8800, 24, 3, axi_sel, ARRAY_SIZE(axi_sel));
496 clks[IMX7D_DISP_AXI_ROOT_SRC] = imx_clk_mux2("disp_axi_src", base + 0x8880, 24, 3, disp_axi_sel, ARRAY_SIZE(disp_axi_sel));
497 clks[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_mux2("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel));
498 clks[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_mux2("nand_usdhc_src", base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel));
499 clks[IMX7D_AHB_CHANNEL_ROOT_SRC] = imx_clk_mux2("ahb_src", base + 0x9000, 24, 3, ahb_channel_sel, ARRAY_SIZE(ahb_channel_sel));
500 clks[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_mux2("dram_phym_src", base + 0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel));
501 clks[IMX7D_DRAM_ROOT_SRC] = imx_clk_mux2("dram_src", base + 0x9880, 24, 1, dram_sel, ARRAY_SIZE(dram_sel));
502 clks[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_mux2("dram_phym_alt_src", base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel));
503 clks[IMX7D_DRAM_ALT_ROOT_SRC] = imx_clk_mux2("dram_alt_src", base + 0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel));
504 clks[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_mux2("usb_hsic_src", base + 0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel));
505 clks[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_mux2("pcie_ctrl_src", base + 0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel));
506 clks[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_mux2("pcie_phy_src", base + 0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel));
507 clks[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_mux2("epdc_pixel_src", base + 0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel));
508 clks[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_mux2("lcdif_pixel_src", base + 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel));
509 clks[IMX7D_MIPI_DSI_ROOT_SRC] = imx_clk_mux2("mipi_dsi_src", base + 0xa380, 24, 3, mipi_dsi_sel, ARRAY_SIZE(mipi_dsi_sel));
510 clks[IMX7D_MIPI_CSI_ROOT_SRC] = imx_clk_mux2("mipi_csi_src", base + 0xa400, 24, 3, mipi_csi_sel, ARRAY_SIZE(mipi_csi_sel));
511 clks[IMX7D_MIPI_DPHY_ROOT_SRC] = imx_clk_mux2("mipi_dphy_src", base + 0xa480, 24, 3, mipi_dphy_sel, ARRAY_SIZE(mipi_dphy_sel));
512 clks[IMX7D_SAI1_ROOT_SRC] = imx_clk_mux2("sai1_src", base + 0xa500, 24, 3, sai1_sel, ARRAY_SIZE(sai1_sel));
513 clks[IMX7D_SAI2_ROOT_SRC] = imx_clk_mux2("sai2_src", base + 0xa580, 24, 3, sai2_sel, ARRAY_SIZE(sai2_sel));
514 clks[IMX7D_SAI3_ROOT_SRC] = imx_clk_mux2("sai3_src", base + 0xa600, 24, 3, sai3_sel, ARRAY_SIZE(sai3_sel));
515 clks[IMX7D_SPDIF_ROOT_SRC] = imx_clk_mux2("spdif_src", base + 0xa680, 24, 3, spdif_sel, ARRAY_SIZE(spdif_sel));
516 clks[IMX7D_ENET1_REF_ROOT_SRC] = imx_clk_mux2("enet1_ref_src", base + 0xa700, 24, 3, enet1_ref_sel, ARRAY_SIZE(enet1_ref_sel));
517 clks[IMX7D_ENET1_TIME_ROOT_SRC] = imx_clk_mux2("enet1_time_src", base + 0xa780, 24, 3, enet1_time_sel, ARRAY_SIZE(enet1_time_sel));
518 clks[IMX7D_ENET2_REF_ROOT_SRC] = imx_clk_mux2("enet2_ref_src", base + 0xa800, 24, 3, enet2_ref_sel, ARRAY_SIZE(enet2_ref_sel));
519 clks[IMX7D_ENET2_TIME_ROOT_SRC] = imx_clk_mux2("enet2_time_src", base + 0xa880, 24, 3, enet2_time_sel, ARRAY_SIZE(enet2_time_sel));
520 clks[IMX7D_ENET_PHY_REF_ROOT_SRC] = imx_clk_mux2("enet_phy_ref_src", base + 0xa900, 24, 3, enet_phy_ref_sel, ARRAY_SIZE(enet_phy_ref_sel));
521 clks[IMX7D_EIM_ROOT_SRC] = imx_clk_mux2("eim_src", base + 0xa980, 24, 3, eim_sel, ARRAY_SIZE(eim_sel));
522 clks[IMX7D_NAND_ROOT_SRC] = imx_clk_mux2("nand_src", base + 0xaa00, 24, 3, nand_sel, ARRAY_SIZE(nand_sel));
523 clks[IMX7D_QSPI_ROOT_SRC] = imx_clk_mux2("qspi_src", base + 0xaa80, 24, 3, qspi_sel, ARRAY_SIZE(qspi_sel));
524 clks[IMX7D_USDHC1_ROOT_SRC] = imx_clk_mux2("usdhc1_src", base + 0xab00, 24, 3, usdhc1_sel, ARRAY_SIZE(usdhc1_sel));
525 clks[IMX7D_USDHC2_ROOT_SRC] = imx_clk_mux2("usdhc2_src", base + 0xab80, 24, 3, usdhc2_sel, ARRAY_SIZE(usdhc2_sel));
526 clks[IMX7D_USDHC3_ROOT_SRC] = imx_clk_mux2("usdhc3_src", base + 0xac00, 24, 3, usdhc3_sel, ARRAY_SIZE(usdhc3_sel));
527 clks[IMX7D_CAN1_ROOT_SRC] = imx_clk_mux2("can1_src", base + 0xac80, 24, 3, can1_sel, ARRAY_SIZE(can1_sel));
528 clks[IMX7D_CAN2_ROOT_SRC] = imx_clk_mux2("can2_src", base + 0xad00, 24, 3, can2_sel, ARRAY_SIZE(can2_sel));
529 clks[IMX7D_I2C1_ROOT_SRC] = imx_clk_mux2("i2c1_src", base + 0xad80, 24, 3, i2c1_sel, ARRAY_SIZE(i2c1_sel));
530 clks[IMX7D_I2C2_ROOT_SRC] = imx_clk_mux2("i2c2_src", base + 0xae00, 24, 3, i2c2_sel, ARRAY_SIZE(i2c2_sel));
531 clks[IMX7D_I2C3_ROOT_SRC] = imx_clk_mux2("i2c3_src", base + 0xae80, 24, 3, i2c3_sel, ARRAY_SIZE(i2c3_sel));
532 clks[IMX7D_I2C4_ROOT_SRC] = imx_clk_mux2("i2c4_src", base + 0xaf00, 24, 3, i2c4_sel, ARRAY_SIZE(i2c4_sel));
533 clks[IMX7D_UART1_ROOT_SRC] = imx_clk_mux2("uart1_src", base + 0xaf80, 24, 3, uart1_sel, ARRAY_SIZE(uart1_sel));
534 clks[IMX7D_UART2_ROOT_SRC] = imx_clk_mux2("uart2_src", base + 0xb000, 24, 3, uart2_sel, ARRAY_SIZE(uart2_sel));
535 clks[IMX7D_UART3_ROOT_SRC] = imx_clk_mux2("uart3_src", base + 0xb080, 24, 3, uart3_sel, ARRAY_SIZE(uart3_sel));
536 clks[IMX7D_UART4_ROOT_SRC] = imx_clk_mux2("uart4_src", base + 0xb100, 24, 3, uart4_sel, ARRAY_SIZE(uart4_sel));
537 clks[IMX7D_UART5_ROOT_SRC] = imx_clk_mux2("uart5_src", base + 0xb180, 24, 3, uart5_sel, ARRAY_SIZE(uart5_sel));
538 clks[IMX7D_UART6_ROOT_SRC] = imx_clk_mux2("uart6_src", base + 0xb200, 24, 3, uart6_sel, ARRAY_SIZE(uart6_sel));
539 clks[IMX7D_UART7_ROOT_SRC] = imx_clk_mux2("uart7_src", base + 0xb280, 24, 3, uart7_sel, ARRAY_SIZE(uart7_sel));
540 clks[IMX7D_ECSPI1_ROOT_SRC] = imx_clk_mux2("ecspi1_src", base + 0xb300, 24, 3, ecspi1_sel, ARRAY_SIZE(ecspi1_sel));
541 clks[IMX7D_ECSPI2_ROOT_SRC] = imx_clk_mux2("ecspi2_src", base + 0xb380, 24, 3, ecspi2_sel, ARRAY_SIZE(ecspi2_sel));
542 clks[IMX7D_ECSPI3_ROOT_SRC] = imx_clk_mux2("ecspi3_src", base + 0xb400, 24, 3, ecspi3_sel, ARRAY_SIZE(ecspi3_sel));
543 clks[IMX7D_ECSPI4_ROOT_SRC] = imx_clk_mux2("ecspi4_src", base + 0xb480, 24, 3, ecspi4_sel, ARRAY_SIZE(ecspi4_sel));
544 clks[IMX7D_PWM1_ROOT_SRC] = imx_clk_mux2("pwm1_src", base + 0xb500, 24, 3, pwm1_sel, ARRAY_SIZE(pwm1_sel));
545 clks[IMX7D_PWM2_ROOT_SRC] = imx_clk_mux2("pwm2_src", base + 0xb580, 24, 3, pwm2_sel, ARRAY_SIZE(pwm2_sel));
546 clks[IMX7D_PWM3_ROOT_SRC] = imx_clk_mux2("pwm3_src", base + 0xb600, 24, 3, pwm3_sel, ARRAY_SIZE(pwm3_sel));
547 clks[IMX7D_PWM4_ROOT_SRC] = imx_clk_mux2("pwm4_src", base + 0xb680, 24, 3, pwm4_sel, ARRAY_SIZE(pwm4_sel));
548 clks[IMX7D_FLEXTIMER1_ROOT_SRC] = imx_clk_mux2("flextimer1_src", base + 0xb700, 24, 3, flextimer1_sel, ARRAY_SIZE(flextimer1_sel));
549 clks[IMX7D_FLEXTIMER2_ROOT_SRC] = imx_clk_mux2("flextimer2_src", base + 0xb780, 24, 3, flextimer2_sel, ARRAY_SIZE(flextimer2_sel));
550 clks[IMX7D_SIM1_ROOT_SRC] = imx_clk_mux2("sim1_src", base + 0xb800, 24, 3, sim1_sel, ARRAY_SIZE(sim1_sel));
551 clks[IMX7D_SIM2_ROOT_SRC] = imx_clk_mux2("sim2_src", base + 0xb880, 24, 3, sim2_sel, ARRAY_SIZE(sim2_sel));
552 clks[IMX7D_GPT1_ROOT_SRC] = imx_clk_mux2("gpt1_src", base + 0xb900, 24, 3, gpt1_sel, ARRAY_SIZE(gpt1_sel));
553 clks[IMX7D_GPT2_ROOT_SRC] = imx_clk_mux2("gpt2_src", base + 0xb980, 24, 3, gpt2_sel, ARRAY_SIZE(gpt2_sel));
554 clks[IMX7D_GPT3_ROOT_SRC] = imx_clk_mux2("gpt3_src", base + 0xba00, 24, 3, gpt3_sel, ARRAY_SIZE(gpt3_sel));
555 clks[IMX7D_GPT4_ROOT_SRC] = imx_clk_mux2("gpt4_src", base + 0xba80, 24, 3, gpt4_sel, ARRAY_SIZE(gpt4_sel));
556 clks[IMX7D_TRACE_ROOT_SRC] = imx_clk_mux2("trace_src", base + 0xbb00, 24, 3, trace_sel, ARRAY_SIZE(trace_sel));
557 clks[IMX7D_WDOG_ROOT_SRC] = imx_clk_mux2("wdog_src", base + 0xbb80, 24, 3, wdog_sel, ARRAY_SIZE(wdog_sel));
558 clks[IMX7D_CSI_MCLK_ROOT_SRC] = imx_clk_mux2("csi_mclk_src", base + 0xbc00, 24, 3, csi_mclk_sel, ARRAY_SIZE(csi_mclk_sel));
559 clks[IMX7D_AUDIO_MCLK_ROOT_SRC] = imx_clk_mux2("audio_mclk_src", base + 0xbc80, 24, 3, audio_mclk_sel, ARRAY_SIZE(audio_mclk_sel));
560 clks[IMX7D_WRCLK_ROOT_SRC] = imx_clk_mux2("wrclk_src", base + 0xbd00, 24, 3, wrclk_sel, ARRAY_SIZE(wrclk_sel));
561 clks[IMX7D_CLKO1_ROOT_SRC] = imx_clk_mux2("clko1_src", base + 0xbd80, 24, 3, clko1_sel, ARRAY_SIZE(clko1_sel));
562 clks[IMX7D_CLKO2_ROOT_SRC] = imx_clk_mux2("clko2_src", base + 0xbe00, 24, 3, clko2_sel, ARRAY_SIZE(clko2_sel));
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]563
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]564 clks[IMX7D_ARM_A7_ROOT_CG] = imx_clk_gate3("arm_a7_cg", "arm_a7_src", base + 0x8000, 28);
565 clks[IMX7D_ARM_M4_ROOT_CG] = imx_clk_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28);
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]566 clks[IMX7D_MAIN_AXI_ROOT_CG] = imx_clk_gate3("axi_cg", "axi_src", base + 0x8800, 28);
567 clks[IMX7D_DISP_AXI_ROOT_CG] = imx_clk_gate3("disp_axi_cg", "disp_axi_src", base + 0x8880, 28);
568 clks[IMX7D_ENET_AXI_ROOT_CG] = imx_clk_gate3("enet_axi_cg", "enet_axi_src", base + 0x8900, 28);
569 clks[IMX7D_NAND_USDHC_BUS_ROOT_CG] = imx_clk_gate3("nand_usdhc_cg", "nand_usdhc_src", base + 0x8980, 28);
570 clks[IMX7D_AHB_CHANNEL_ROOT_CG] = imx_clk_gate3("ahb_cg", "ahb_src", base + 0x9000, 28);
571 clks[IMX7D_DRAM_PHYM_ROOT_CG] = imx_clk_gate3("dram_phym_cg", "dram_phym_src", base + 0x9800, 28);
572 clks[IMX7D_DRAM_ROOT_CG] = imx_clk_gate3("dram_cg", "dram_src", base + 0x9880, 28);
573 clks[IMX7D_DRAM_PHYM_ALT_ROOT_CG] = imx_clk_gate3("dram_phym_alt_cg", "dram_phym_alt_src", base + 0xa000, 28);
574 clks[IMX7D_DRAM_ALT_ROOT_CG] = imx_clk_gate3("dram_alt_cg", "dram_alt_src", base + 0xa080, 28);
575 clks[IMX7D_USB_HSIC_ROOT_CG] = imx_clk_gate3("usb_hsic_cg", "usb_hsic_src", base + 0xa100, 28);
576 clks[IMX7D_PCIE_CTRL_ROOT_CG] = imx_clk_gate3("pcie_ctrl_cg", "pcie_ctrl_src", base + 0xa180, 28);
577 clks[IMX7D_PCIE_PHY_ROOT_CG] = imx_clk_gate3("pcie_phy_cg", "pcie_phy_src", base + 0xa200, 28);
578 clks[IMX7D_EPDC_PIXEL_ROOT_CG] = imx_clk_gate3("epdc_pixel_cg", "epdc_pixel_src", base + 0xa280, 28);
579 clks[IMX7D_LCDIF_PIXEL_ROOT_CG] = imx_clk_gate3("lcdif_pixel_cg", "lcdif_pixel_src", base + 0xa300, 28);
580 clks[IMX7D_MIPI_DSI_ROOT_CG] = imx_clk_gate3("mipi_dsi_cg", "mipi_dsi_src", base + 0xa380, 28);
581 clks[IMX7D_MIPI_CSI_ROOT_CG] = imx_clk_gate3("mipi_csi_cg", "mipi_csi_src", base + 0xa400, 28);
582 clks[IMX7D_MIPI_DPHY_ROOT_CG] = imx_clk_gate3("mipi_dphy_cg", "mipi_dphy_src", base + 0xa480, 28);
583 clks[IMX7D_SAI1_ROOT_CG] = imx_clk_gate3("sai1_cg", "sai1_src", base + 0xa500, 28);
584 clks[IMX7D_SAI2_ROOT_CG] = imx_clk_gate3("sai2_cg", "sai2_src", base + 0xa580, 28);
585 clks[IMX7D_SAI3_ROOT_CG] = imx_clk_gate3("sai3_cg", "sai3_src", base + 0xa600, 28);
586 clks[IMX7D_SPDIF_ROOT_CG] = imx_clk_gate3("spdif_cg", "spdif_src", base + 0xa680, 28);
587 clks[IMX7D_ENET1_REF_ROOT_CG] = imx_clk_gate3("enet1_ref_cg", "enet1_ref_src", base + 0xa700, 28);
588 clks[IMX7D_ENET1_TIME_ROOT_CG] = imx_clk_gate3("enet1_time_cg", "enet1_time_src", base + 0xa780, 28);
589 clks[IMX7D_ENET2_REF_ROOT_CG] = imx_clk_gate3("enet2_ref_cg", "enet2_ref_src", base + 0xa800, 28);
590 clks[IMX7D_ENET2_TIME_ROOT_CG] = imx_clk_gate3("enet2_time_cg", "enet2_time_src", base + 0xa880, 28);
591 clks[IMX7D_ENET_PHY_REF_ROOT_CG] = imx_clk_gate3("enet_phy_ref_cg", "enet_phy_ref_src", base + 0xa900, 28);
592 clks[IMX7D_EIM_ROOT_CG] = imx_clk_gate3("eim_cg", "eim_src", base + 0xa980, 28);
593 clks[IMX7D_NAND_ROOT_CG] = imx_clk_gate3("nand_cg", "nand_src", base + 0xaa00, 28);
594 clks[IMX7D_QSPI_ROOT_CG] = imx_clk_gate3("qspi_cg", "qspi_src", base + 0xaa80, 28);
595 clks[IMX7D_USDHC1_ROOT_CG] = imx_clk_gate3("usdhc1_cg", "usdhc1_src", base + 0xab00, 28);
596 clks[IMX7D_USDHC2_ROOT_CG] = imx_clk_gate3("usdhc2_cg", "usdhc2_src", base + 0xab80, 28);
597 clks[IMX7D_USDHC3_ROOT_CG] = imx_clk_gate3("usdhc3_cg", "usdhc3_src", base + 0xac00, 28);
598 clks[IMX7D_CAN1_ROOT_CG] = imx_clk_gate3("can1_cg", "can1_src", base + 0xac80, 28);
599 clks[IMX7D_CAN2_ROOT_CG] = imx_clk_gate3("can2_cg", "can2_src", base + 0xad00, 28);
600 clks[IMX7D_I2C1_ROOT_CG] = imx_clk_gate3("i2c1_cg", "i2c1_src", base + 0xad80, 28);
601 clks[IMX7D_I2C2_ROOT_CG] = imx_clk_gate3("i2c2_cg", "i2c2_src", base + 0xae00, 28);
602 clks[IMX7D_I2C3_ROOT_CG] = imx_clk_gate3("i2c3_cg", "i2c3_src", base + 0xae80, 28);
603 clks[IMX7D_I2C4_ROOT_CG] = imx_clk_gate3("i2c4_cg", "i2c4_src", base + 0xaf00, 28);
604 clks[IMX7D_UART1_ROOT_CG] = imx_clk_gate3("uart1_cg", "uart1_src", base + 0xaf80, 28);
605 clks[IMX7D_UART2_ROOT_CG] = imx_clk_gate3("uart2_cg", "uart2_src", base + 0xb000, 28);
606 clks[IMX7D_UART3_ROOT_CG] = imx_clk_gate3("uart3_cg", "uart3_src", base + 0xb080, 28);
607 clks[IMX7D_UART4_ROOT_CG] = imx_clk_gate3("uart4_cg", "uart4_src", base + 0xb100, 28);
608 clks[IMX7D_UART5_ROOT_CG] = imx_clk_gate3("uart5_cg", "uart5_src", base + 0xb180, 28);
609 clks[IMX7D_UART6_ROOT_CG] = imx_clk_gate3("uart6_cg", "uart6_src", base + 0xb200, 28);
610 clks[IMX7D_UART7_ROOT_CG] = imx_clk_gate3("uart7_cg", "uart7_src", base + 0xb280, 28);
611 clks[IMX7D_ECSPI1_ROOT_CG] = imx_clk_gate3("ecspi1_cg", "ecspi1_src", base + 0xb300, 28);
612 clks[IMX7D_ECSPI2_ROOT_CG] = imx_clk_gate3("ecspi2_cg", "ecspi2_src", base + 0xb380, 28);
613 clks[IMX7D_ECSPI3_ROOT_CG] = imx_clk_gate3("ecspi3_cg", "ecspi3_src", base + 0xb400, 28);
614 clks[IMX7D_ECSPI4_ROOT_CG] = imx_clk_gate3("ecspi4_cg", "ecspi4_src", base + 0xb480, 28);
615 clks[IMX7D_PWM1_ROOT_CG] = imx_clk_gate3("pwm1_cg", "pwm1_src", base + 0xb500, 28);
616 clks[IMX7D_PWM2_ROOT_CG] = imx_clk_gate3("pwm2_cg", "pwm2_src", base + 0xb580, 28);
617 clks[IMX7D_PWM3_ROOT_CG] = imx_clk_gate3("pwm3_cg", "pwm3_src", base + 0xb600, 28);
618 clks[IMX7D_PWM4_ROOT_CG] = imx_clk_gate3("pwm4_cg", "pwm4_src", base + 0xb680, 28);
619 clks[IMX7D_FLEXTIMER1_ROOT_CG] = imx_clk_gate3("flextimer1_cg", "flextimer1_src", base + 0xb700, 28);
620 clks[IMX7D_FLEXTIMER2_ROOT_CG] = imx_clk_gate3("flextimer2_cg", "flextimer2_src", base + 0xb780, 28);
621 clks[IMX7D_SIM1_ROOT_CG] = imx_clk_gate3("sim1_cg", "sim1_src", base + 0xb800, 28);
622 clks[IMX7D_SIM2_ROOT_CG] = imx_clk_gate3("sim2_cg", "sim2_src", base + 0xb880, 28);
623 clks[IMX7D_GPT1_ROOT_CG] = imx_clk_gate3("gpt1_cg", "gpt1_src", base + 0xb900, 28);
624 clks[IMX7D_GPT2_ROOT_CG] = imx_clk_gate3("gpt2_cg", "gpt2_src", base + 0xb980, 28);
625 clks[IMX7D_GPT3_ROOT_CG] = imx_clk_gate3("gpt3_cg", "gpt3_src", base + 0xbA00, 28);
626 clks[IMX7D_GPT4_ROOT_CG] = imx_clk_gate3("gpt4_cg", "gpt4_src", base + 0xbA80, 28);
627 clks[IMX7D_TRACE_ROOT_CG] = imx_clk_gate3("trace_cg", "trace_src", base + 0xbb00, 28);
628 clks[IMX7D_WDOG_ROOT_CG] = imx_clk_gate3("wdog_cg", "wdog_src", base + 0xbb80, 28);
629 clks[IMX7D_CSI_MCLK_ROOT_CG] = imx_clk_gate3("csi_mclk_cg", "csi_mclk_src", base + 0xbc00, 28);
630 clks[IMX7D_AUDIO_MCLK_ROOT_CG] = imx_clk_gate3("audio_mclk_cg", "audio_mclk_src", base + 0xbc80, 28);
631 clks[IMX7D_WRCLK_ROOT_CG] = imx_clk_gate3("wrclk_cg", "wrclk_src", base + 0xbd00, 28);
632 clks[IMX7D_CLKO1_ROOT_CG] = imx_clk_gate3("clko1_cg", "clko1_src", base + 0xbd80, 28);
633 clks[IMX7D_CLKO2_ROOT_CG] = imx_clk_gate3("clko2_cg", "clko2_src", base + 0xbe00, 28);
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]634
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]635 clks[IMX7D_MAIN_AXI_ROOT_PRE_DIV] = imx_clk_divider2("axi_pre_div", "axi_cg", base + 0x8800, 16, 3);
636 clks[IMX7D_DISP_AXI_ROOT_PRE_DIV] = imx_clk_divider2("disp_axi_pre_div", "disp_axi_cg", base + 0x8880, 16, 3);
637 clks[IMX7D_ENET_AXI_ROOT_PRE_DIV] = imx_clk_divider2("enet_axi_pre_div", "enet_axi_cg", base + 0x8900, 16, 3);
638 clks[IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV] = imx_clk_divider2("nand_usdhc_pre_div", "nand_usdhc_cg", base + 0x8980, 16, 3);
639 clks[IMX7D_AHB_CHANNEL_ROOT_PRE_DIV] = imx_clk_divider2("ahb_pre_div", "ahb_cg", base + 0x9000, 16, 3);
640 clks[IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV] = imx_clk_divider2("dram_phym_alt_pre_div", "dram_phym_alt_cg", base + 0xa000, 16, 3);
641 clks[IMX7D_DRAM_ALT_ROOT_PRE_DIV] = imx_clk_divider2("dram_alt_pre_div", "dram_alt_cg", base + 0xa080, 16, 3);
642 clks[IMX7D_USB_HSIC_ROOT_PRE_DIV] = imx_clk_divider2("usb_hsic_pre_div", "usb_hsic_cg", base + 0xa100, 16, 3);
643 clks[IMX7D_PCIE_CTRL_ROOT_PRE_DIV] = imx_clk_divider2("pcie_ctrl_pre_div", "pcie_ctrl_cg", base + 0xa180, 16, 3);
644 clks[IMX7D_PCIE_PHY_ROOT_PRE_DIV] = imx_clk_divider2("pcie_phy_pre_div", "pcie_phy_cg", base + 0xa200, 16, 3);
645 clks[IMX7D_EPDC_PIXEL_ROOT_PRE_DIV] = imx_clk_divider2("epdc_pixel_pre_div", "epdc_pixel_cg", base + 0xa280, 16, 3);
646 clks[IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV] = imx_clk_divider2("lcdif_pixel_pre_div", "lcdif_pixel_cg", base + 0xa300, 16, 3);
647 clks[IMX7D_MIPI_DSI_ROOT_PRE_DIV] = imx_clk_divider2("mipi_dsi_pre_div", "mipi_dsi_cg", base + 0xa380, 16, 3);
648 clks[IMX7D_MIPI_CSI_ROOT_PRE_DIV] = imx_clk_divider2("mipi_csi_pre_div", "mipi_csi_cg", base + 0xa400, 16, 3);
649 clks[IMX7D_MIPI_DPHY_ROOT_PRE_DIV] = imx_clk_divider2("mipi_dphy_pre_div", "mipi_dphy_cg", base + 0xa480, 16, 3);
650 clks[IMX7D_SAI1_ROOT_PRE_DIV] = imx_clk_divider2("sai1_pre_div", "sai1_cg", base + 0xa500, 16, 3);
651 clks[IMX7D_SAI2_ROOT_PRE_DIV] = imx_clk_divider2("sai2_pre_div", "sai2_cg", base + 0xa580, 16, 3);
652 clks[IMX7D_SAI3_ROOT_PRE_DIV] = imx_clk_divider2("sai3_pre_div", "sai3_cg", base + 0xa600, 16, 3);
653 clks[IMX7D_SPDIF_ROOT_PRE_DIV] = imx_clk_divider2("spdif_pre_div", "spdif_cg", base + 0xa680, 16, 3);
654 clks[IMX7D_ENET1_REF_ROOT_PRE_DIV] = imx_clk_divider2("enet1_ref_pre_div", "enet1_ref_cg", base + 0xa700, 16, 3);
655 clks[IMX7D_ENET1_TIME_ROOT_PRE_DIV] = imx_clk_divider2("enet1_time_pre_div", "enet1_time_cg", base + 0xa780, 16, 3);
656 clks[IMX7D_ENET2_REF_ROOT_PRE_DIV] = imx_clk_divider2("enet2_ref_pre_div", "enet2_ref_cg", base + 0xa800, 16, 3);
657 clks[IMX7D_ENET2_TIME_ROOT_PRE_DIV] = imx_clk_divider2("enet2_time_pre_div", "enet2_time_cg", base + 0xa880, 16, 3);
658 clks[IMX7D_ENET_PHY_REF_ROOT_PRE_DIV] = imx_clk_divider2("enet_phy_ref_pre_div", "enet_phy_ref_cg", base + 0xa900, 16, 3);
659 clks[IMX7D_EIM_ROOT_PRE_DIV] = imx_clk_divider2("eim_pre_div", "eim_cg", base + 0xa980, 16, 3);
660 clks[IMX7D_NAND_ROOT_PRE_DIV] = imx_clk_divider2("nand_pre_div", "nand_cg", base + 0xaa00, 16, 3);
661 clks[IMX7D_QSPI_ROOT_PRE_DIV] = imx_clk_divider2("qspi_pre_div", "qspi_cg", base + 0xaa80, 16, 3);
662 clks[IMX7D_USDHC1_ROOT_PRE_DIV] = imx_clk_divider2("usdhc1_pre_div", "usdhc1_cg", base + 0xab00, 16, 3);
663 clks[IMX7D_USDHC2_ROOT_PRE_DIV] = imx_clk_divider2("usdhc2_pre_div", "usdhc2_cg", base + 0xab80, 16, 3);
664 clks[IMX7D_USDHC3_ROOT_PRE_DIV] = imx_clk_divider2("usdhc3_pre_div", "usdhc3_cg", base + 0xac00, 16, 3);
665 clks[IMX7D_CAN1_ROOT_PRE_DIV] = imx_clk_divider2("can1_pre_div", "can1_cg", base + 0xac80, 16, 3);
666 clks[IMX7D_CAN2_ROOT_PRE_DIV] = imx_clk_divider2("can2_pre_div", "can2_cg", base + 0xad00, 16, 3);
667 clks[IMX7D_I2C1_ROOT_PRE_DIV] = imx_clk_divider2("i2c1_pre_div", "i2c1_cg", base + 0xad80, 16, 3);
668 clks[IMX7D_I2C2_ROOT_PRE_DIV] = imx_clk_divider2("i2c2_pre_div", "i2c2_cg", base + 0xae00, 16, 3);
669 clks[IMX7D_I2C3_ROOT_PRE_DIV] = imx_clk_divider2("i2c3_pre_div", "i2c3_cg", base + 0xae80, 16, 3);
670 clks[IMX7D_I2C4_ROOT_PRE_DIV] = imx_clk_divider2("i2c4_pre_div", "i2c4_cg", base + 0xaf00, 16, 3);
671 clks[IMX7D_UART1_ROOT_PRE_DIV] = imx_clk_divider2("uart1_pre_div", "uart1_cg", base + 0xaf80, 16, 3);
672 clks[IMX7D_UART2_ROOT_PRE_DIV] = imx_clk_divider2("uart2_pre_div", "uart2_cg", base + 0xb000, 16, 3);
673 clks[IMX7D_UART3_ROOT_PRE_DIV] = imx_clk_divider2("uart3_pre_div", "uart3_cg", base + 0xb080, 16, 3);
674 clks[IMX7D_UART4_ROOT_PRE_DIV] = imx_clk_divider2("uart4_pre_div", "uart4_cg", base + 0xb100, 16, 3);
675 clks[IMX7D_UART5_ROOT_PRE_DIV] = imx_clk_divider2("uart5_pre_div", "uart5_cg", base + 0xb180, 16, 3);
676 clks[IMX7D_UART6_ROOT_PRE_DIV] = imx_clk_divider2("uart6_pre_div", "uart6_cg", base + 0xb200, 16, 3);
677 clks[IMX7D_UART7_ROOT_PRE_DIV] = imx_clk_divider2("uart7_pre_div", "uart7_cg", base + 0xb280, 16, 3);
678 clks[IMX7D_ECSPI1_ROOT_PRE_DIV] = imx_clk_divider2("ecspi1_pre_div", "ecspi1_cg", base + 0xb300, 16, 3);
679 clks[IMX7D_ECSPI2_ROOT_PRE_DIV] = imx_clk_divider2("ecspi2_pre_div", "ecspi2_cg", base + 0xb380, 16, 3);
680 clks[IMX7D_ECSPI3_ROOT_PRE_DIV] = imx_clk_divider2("ecspi3_pre_div", "ecspi3_cg", base + 0xb400, 16, 3);
681 clks[IMX7D_ECSPI4_ROOT_PRE_DIV] = imx_clk_divider2("ecspi4_pre_div", "ecspi4_cg", base + 0xb480, 16, 3);
682 clks[IMX7D_PWM1_ROOT_PRE_DIV] = imx_clk_divider2("pwm1_pre_div", "pwm1_cg", base + 0xb500, 16, 3);
683 clks[IMX7D_PWM2_ROOT_PRE_DIV] = imx_clk_divider2("pwm2_pre_div", "pwm2_cg", base + 0xb580, 16, 3);
684 clks[IMX7D_PWM3_ROOT_PRE_DIV] = imx_clk_divider2("pwm3_pre_div", "pwm3_cg", base + 0xb600, 16, 3);
685 clks[IMX7D_PWM4_ROOT_PRE_DIV] = imx_clk_divider2("pwm4_pre_div", "pwm4_cg", base + 0xb680, 16, 3);
686 clks[IMX7D_FLEXTIMER1_ROOT_PRE_DIV] = imx_clk_divider2("flextimer1_pre_div", "flextimer1_cg", base + 0xb700, 16, 3);
687 clks[IMX7D_FLEXTIMER2_ROOT_PRE_DIV] = imx_clk_divider2("flextimer2_pre_div", "flextimer2_cg", base + 0xb780, 16, 3);
688 clks[IMX7D_SIM1_ROOT_PRE_DIV] = imx_clk_divider2("sim1_pre_div", "sim1_cg", base + 0xb800, 16, 3);
689 clks[IMX7D_SIM2_ROOT_PRE_DIV] = imx_clk_divider2("sim2_pre_div", "sim2_cg", base + 0xb880, 16, 3);
690 clks[IMX7D_GPT1_ROOT_PRE_DIV] = imx_clk_divider2("gpt1_pre_div", "gpt1_cg", base + 0xb900, 16, 3);
691 clks[IMX7D_GPT2_ROOT_PRE_DIV] = imx_clk_divider2("gpt2_pre_div", "gpt2_cg", base + 0xb980, 16, 3);
692 clks[IMX7D_GPT3_ROOT_PRE_DIV] = imx_clk_divider2("gpt3_pre_div", "gpt3_cg", base + 0xba00, 16, 3);
693 clks[IMX7D_GPT4_ROOT_PRE_DIV] = imx_clk_divider2("gpt4_pre_div", "gpt4_cg", base + 0xba80, 16, 3);
694 clks[IMX7D_TRACE_ROOT_PRE_DIV] = imx_clk_divider2("trace_pre_div", "trace_cg", base + 0xbb00, 16, 3);
695 clks[IMX7D_WDOG_ROOT_PRE_DIV] = imx_clk_divider2("wdog_pre_div", "wdog_cg", base + 0xbb80, 16, 3);
696 clks[IMX7D_CSI_MCLK_ROOT_PRE_DIV] = imx_clk_divider2("csi_mclk_pre_div", "csi_mclk_cg", base + 0xbc00, 16, 3);
697 clks[IMX7D_AUDIO_MCLK_ROOT_PRE_DIV] = imx_clk_divider2("audio_mclk_pre_div", "audio_mclk_cg", base + 0xbc80, 16, 3);
698 clks[IMX7D_WRCLK_ROOT_PRE_DIV] = imx_clk_divider2("wrclk_pre_div", "wrclk_cg", base + 0xbd00, 16, 3);
699 clks[IMX7D_CLKO1_ROOT_PRE_DIV] = imx_clk_divider2("clko1_pre_div", "clko1_cg", base + 0xbd80, 16, 3);
700 clks[IMX7D_CLKO2_ROOT_PRE_DIV] = imx_clk_divider2("clko2_pre_div", "clko2_cg", base + 0xbe00, 16, 3);
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]701
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]702 clks[IMX7D_ARM_A7_ROOT_DIV] = imx_clk_divider2("arm_a7_div", "arm_a7_cg", base + 0x8000, 0, 3);
703 clks[IMX7D_ARM_M4_ROOT_DIV] = imx_clk_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3);
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]704 clks[IMX7D_MAIN_AXI_ROOT_DIV] = imx_clk_divider2("axi_post_div", "axi_pre_div", base + 0x8800, 0, 6);
705 clks[IMX7D_DISP_AXI_ROOT_DIV] = imx_clk_divider2("disp_axi_post_div", "disp_axi_pre_div", base + 0x8880, 0, 6);
706 clks[IMX7D_ENET_AXI_ROOT_DIV] = imx_clk_divider2("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6);
Stefan Agnere24f5282017-04-10 14:00:14 -0700[diff] [blame]707 clks[IMX7D_NAND_USDHC_BUS_ROOT_CLK] = imx_clk_divider2("nand_usdhc_root_clk", "nand_usdhc_pre_div", base + 0x8980, 0, 6);
Dong Aisheng9a6e9042017-04-11 10:37:48 +0800[diff] [blame]708 clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider2("ahb_root_clk", "ahb_pre_div", base + 0x9000, 0, 6);
Anson Huangfebb6542018-08-08 12:39:27 +0800[diff] [blame]709 clks[IMX7D_IPG_ROOT_CLK] = imx_clk_divider_flags("ipg_root_clk", "ahb_root_clk", base + 0x9080, 0, 2, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT);
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]710 clks[IMX7D_DRAM_ROOT_DIV] = imx_clk_divider2("dram_post_div", "dram_cg", base + 0x9880, 0, 3);
711 clks[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] = imx_clk_divider2("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3);
712 clks[IMX7D_DRAM_ALT_ROOT_DIV] = imx_clk_divider2("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3);
713 clks[IMX7D_USB_HSIC_ROOT_DIV] = imx_clk_divider2("usb_hsic_post_div", "usb_hsic_pre_div", base + 0xa100, 0, 6);
714 clks[IMX7D_PCIE_CTRL_ROOT_DIV] = imx_clk_divider2("pcie_ctrl_post_div", "pcie_ctrl_pre_div", base + 0xa180, 0, 6);
715 clks[IMX7D_PCIE_PHY_ROOT_DIV] = imx_clk_divider2("pcie_phy_post_div", "pcie_phy_pre_div", base + 0xa200, 0, 6);
716 clks[IMX7D_EPDC_PIXEL_ROOT_DIV] = imx_clk_divider2("epdc_pixel_post_div", "epdc_pixel_pre_div", base + 0xa280, 0, 6);
717 clks[IMX7D_LCDIF_PIXEL_ROOT_DIV] = imx_clk_divider2("lcdif_pixel_post_div", "lcdif_pixel_pre_div", base + 0xa300, 0, 6);
718 clks[IMX7D_MIPI_DSI_ROOT_DIV] = imx_clk_divider2("mipi_dsi_post_div", "mipi_dsi_pre_div", base + 0xa380, 0, 6);
719 clks[IMX7D_MIPI_CSI_ROOT_DIV] = imx_clk_divider2("mipi_csi_post_div", "mipi_csi_pre_div", base + 0xa400, 0, 6);
Rui Miguel Silva4dd5d5b2018-05-22 15:52:36 +0100[diff] [blame]720 clks[IMX7D_MIPI_DPHY_ROOT_DIV] = imx_clk_divider2("mipi_dphy_post_div", "mipi_dphy_pre_div", base + 0xa480, 0, 6);
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]721 clks[IMX7D_SAI1_ROOT_DIV] = imx_clk_divider2("sai1_post_div", "sai1_pre_div", base + 0xa500, 0, 6);
722 clks[IMX7D_SAI2_ROOT_DIV] = imx_clk_divider2("sai2_post_div", "sai2_pre_div", base + 0xa580, 0, 6);
723 clks[IMX7D_SAI3_ROOT_DIV] = imx_clk_divider2("sai3_post_div", "sai3_pre_div", base + 0xa600, 0, 6);
724 clks[IMX7D_SPDIF_ROOT_DIV] = imx_clk_divider2("spdif_post_div", "spdif_pre_div", base + 0xa680, 0, 6);
725 clks[IMX7D_ENET1_REF_ROOT_DIV] = imx_clk_divider2("enet1_ref_post_div", "enet1_ref_pre_div", base + 0xa700, 0, 6);
726 clks[IMX7D_ENET1_TIME_ROOT_DIV] = imx_clk_divider2("enet1_time_post_div", "enet1_time_pre_div", base + 0xa780, 0, 6);
727 clks[IMX7D_ENET2_REF_ROOT_DIV] = imx_clk_divider2("enet2_ref_post_div", "enet2_ref_pre_div", base + 0xa800, 0, 6);
728 clks[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_divider2("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6);
Anson Huangf93f2ed2018-05-18 09:01:04 +0800[diff] [blame]729 clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_divider2("enet_phy_ref_root_clk", "enet_phy_ref_pre_div", base + 0xa900, 0, 6);
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]730 clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider2("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6);
Stefan Agner22039d12017-06-08 15:34:47 -0700[diff] [blame]731 clks[IMX7D_NAND_ROOT_CLK] = imx_clk_divider2("nand_root_clk", "nand_pre_div", base + 0xaa00, 0, 6);
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]732 clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider2("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6);
733 clks[IMX7D_USDHC1_ROOT_DIV] = imx_clk_divider2("usdhc1_post_div", "usdhc1_pre_div", base + 0xab00, 0, 6);
734 clks[IMX7D_USDHC2_ROOT_DIV] = imx_clk_divider2("usdhc2_post_div", "usdhc2_pre_div", base + 0xab80, 0, 6);
735 clks[IMX7D_USDHC3_ROOT_DIV] = imx_clk_divider2("usdhc3_post_div", "usdhc3_pre_div", base + 0xac00, 0, 6);
736 clks[IMX7D_CAN1_ROOT_DIV] = imx_clk_divider2("can1_post_div", "can1_pre_div", base + 0xac80, 0, 6);
737 clks[IMX7D_CAN2_ROOT_DIV] = imx_clk_divider2("can2_post_div", "can2_pre_div", base + 0xad00, 0, 6);
738 clks[IMX7D_I2C1_ROOT_DIV] = imx_clk_divider2("i2c1_post_div", "i2c1_pre_div", base + 0xad80, 0, 6);
739 clks[IMX7D_I2C2_ROOT_DIV] = imx_clk_divider2("i2c2_post_div", "i2c2_pre_div", base + 0xae00, 0, 6);
740 clks[IMX7D_I2C3_ROOT_DIV] = imx_clk_divider2("i2c3_post_div", "i2c3_pre_div", base + 0xae80, 0, 6);
741 clks[IMX7D_I2C4_ROOT_DIV] = imx_clk_divider2("i2c4_post_div", "i2c4_pre_div", base + 0xaf00, 0, 6);
742 clks[IMX7D_UART1_ROOT_DIV] = imx_clk_divider2("uart1_post_div", "uart1_pre_div", base + 0xaf80, 0, 6);
743 clks[IMX7D_UART2_ROOT_DIV] = imx_clk_divider2("uart2_post_div", "uart2_pre_div", base + 0xb000, 0, 6);
744 clks[IMX7D_UART3_ROOT_DIV] = imx_clk_divider2("uart3_post_div", "uart3_pre_div", base + 0xb080, 0, 6);
745 clks[IMX7D_UART4_ROOT_DIV] = imx_clk_divider2("uart4_post_div", "uart4_pre_div", base + 0xb100, 0, 6);
746 clks[IMX7D_UART5_ROOT_DIV] = imx_clk_divider2("uart5_post_div", "uart5_pre_div", base + 0xb180, 0, 6);
747 clks[IMX7D_UART6_ROOT_DIV] = imx_clk_divider2("uart6_post_div", "uart6_pre_div", base + 0xb200, 0, 6);
748 clks[IMX7D_UART7_ROOT_DIV] = imx_clk_divider2("uart7_post_div", "uart7_pre_div", base + 0xb280, 0, 6);
749 clks[IMX7D_ECSPI1_ROOT_DIV] = imx_clk_divider2("ecspi1_post_div", "ecspi1_pre_div", base + 0xb300, 0, 6);
750 clks[IMX7D_ECSPI2_ROOT_DIV] = imx_clk_divider2("ecspi2_post_div", "ecspi2_pre_div", base + 0xb380, 0, 6);
751 clks[IMX7D_ECSPI3_ROOT_DIV] = imx_clk_divider2("ecspi3_post_div", "ecspi3_pre_div", base + 0xb400, 0, 6);
752 clks[IMX7D_ECSPI4_ROOT_DIV] = imx_clk_divider2("ecspi4_post_div", "ecspi4_pre_div", base + 0xb480, 0, 6);
753 clks[IMX7D_PWM1_ROOT_DIV] = imx_clk_divider2("pwm1_post_div", "pwm1_pre_div", base + 0xb500, 0, 6);
754 clks[IMX7D_PWM2_ROOT_DIV] = imx_clk_divider2("pwm2_post_div", "pwm2_pre_div", base + 0xb580, 0, 6);
755 clks[IMX7D_PWM3_ROOT_DIV] = imx_clk_divider2("pwm3_post_div", "pwm3_pre_div", base + 0xb600, 0, 6);
756 clks[IMX7D_PWM4_ROOT_DIV] = imx_clk_divider2("pwm4_post_div", "pwm4_pre_div", base + 0xb680, 0, 6);
757 clks[IMX7D_FLEXTIMER1_ROOT_DIV] = imx_clk_divider2("flextimer1_post_div", "flextimer1_pre_div", base + 0xb700, 0, 6);
758 clks[IMX7D_FLEXTIMER2_ROOT_DIV] = imx_clk_divider2("flextimer2_post_div", "flextimer2_pre_div", base + 0xb780, 0, 6);
759 clks[IMX7D_SIM1_ROOT_DIV] = imx_clk_divider2("sim1_post_div", "sim1_pre_div", base + 0xb800, 0, 6);
760 clks[IMX7D_SIM2_ROOT_DIV] = imx_clk_divider2("sim2_post_div", "sim2_pre_div", base + 0xb880, 0, 6);
761 clks[IMX7D_GPT1_ROOT_DIV] = imx_clk_divider2("gpt1_post_div", "gpt1_pre_div", base + 0xb900, 0, 6);
762 clks[IMX7D_GPT2_ROOT_DIV] = imx_clk_divider2("gpt2_post_div", "gpt2_pre_div", base + 0xb980, 0, 6);
763 clks[IMX7D_GPT3_ROOT_DIV] = imx_clk_divider2("gpt3_post_div", "gpt3_pre_div", base + 0xba00, 0, 6);
764 clks[IMX7D_GPT4_ROOT_DIV] = imx_clk_divider2("gpt4_post_div", "gpt4_pre_div", base + 0xba80, 0, 6);
765 clks[IMX7D_TRACE_ROOT_DIV] = imx_clk_divider2("trace_post_div", "trace_pre_div", base + 0xbb00, 0, 6);
766 clks[IMX7D_WDOG_ROOT_DIV] = imx_clk_divider2("wdog_post_div", "wdog_pre_div", base + 0xbb80, 0, 6);
767 clks[IMX7D_CSI_MCLK_ROOT_DIV] = imx_clk_divider2("csi_mclk_post_div", "csi_mclk_pre_div", base + 0xbc00, 0, 6);
768 clks[IMX7D_AUDIO_MCLK_ROOT_DIV] = imx_clk_divider2("audio_mclk_post_div", "audio_mclk_pre_div", base + 0xbc80, 0, 6);
769 clks[IMX7D_WRCLK_ROOT_DIV] = imx_clk_divider2("wrclk_post_div", "wrclk_pre_div", base + 0xbd00, 0, 6);
770 clks[IMX7D_CLKO1_ROOT_DIV] = imx_clk_divider2("clko1_post_div", "clko1_pre_div", base + 0xbd80, 0, 6);
771 clks[IMX7D_CLKO2_ROOT_DIV] = imx_clk_divider2("clko2_post_div", "clko2_pre_div", base + 0xbe00, 0, 6);
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]772
Anson Huang0d09e662018-10-17 06:12:04 +0000[diff] [blame]773 clks[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_gate2_flags("arm_a7_root_clk", "arm_a7_div", base + 0x4000, 0, CLK_OPS_PARENT_ENABLE);
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]774 clks[IMX7D_ARM_M4_ROOT_CLK] = imx_clk_gate4("arm_m4_root_clk", "arm_m4_div", base + 0x4010, 0);
Anson Huangfebb6542018-08-08 12:39:27 +0800[diff] [blame]775 clks[IMX7D_MAIN_AXI_ROOT_CLK] = imx_clk_gate2_flags("main_axi_root_clk", "axi_post_div", base + 0x4040, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]776 clks[IMX7D_DISP_AXI_ROOT_CLK] = imx_clk_gate4("disp_axi_root_clk", "disp_axi_post_div", base + 0x4050, 0);
777 clks[IMX7D_ENET_AXI_ROOT_CLK] = imx_clk_gate4("enet_axi_root_clk", "enet_axi_post_div", base + 0x4060, 0);
Adriana Reusedc5a8e2017-10-02 13:32:10 +0300[diff] [blame]778 clks[IMX7D_OCRAM_CLK] = imx_clk_gate4("ocram_clk", "main_axi_root_clk", base + 0x4110, 0);
Dong Aisheng9a6e9042017-04-11 10:37:48 +0800[diff] [blame]779 clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate4("ocram_s_clk", "ahb_root_clk", base + 0x4120, 0);
Anson Huangfebb6542018-08-08 12:39:27 +0800[diff] [blame]780 clks[IMX7D_DRAM_ROOT_CLK] = imx_clk_gate2_flags("dram_root_clk", "dram_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
781 clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate2_flags("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
782 clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate2_flags("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
783 clks[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_gate2_flags("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
Fabio Estevam6847c4c2017-01-18 15:53:56 -0200[diff] [blame]784 clks[IMX7D_OCOTP_CLK] = imx_clk_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0);
Anson Huangd931ba52018-01-09 17:52:05 +0800[diff] [blame]785 clks[IMX7D_SNVS_CLK] = imx_clk_gate4("snvs_clk", "ipg_root_clk", base + 0x4250, 0);
Oleksij Rempel30343892018-06-15 11:51:04 +0200[diff] [blame]786 clks[IMX7D_MU_ROOT_CLK] = imx_clk_gate4("mu_root_clk", "ipg_root_clk", base + 0x4270, 0);
Rui Miguel Silvabaf15cb2018-02-22 14:22:49 +0000[diff] [blame]787 clks[IMX7D_CAAM_CLK] = imx_clk_gate4("caam_clk", "ipg_root_clk", base + 0x4240, 0);
Peter Chen5fcb4c72018-03-28 09:46:35 +0300[diff] [blame]788 clks[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4690, 0);
Fabio Estevam96e9dff2016-08-12 15:26:54 -0300[diff] [blame]789 clks[IMX7D_SDMA_CORE_CLK] = imx_clk_gate4("sdma_root_clk", "ahb_root_clk", base + 0x4480, 0);
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]790 clks[IMX7D_PCIE_CTRL_ROOT_CLK] = imx_clk_gate4("pcie_ctrl_root_clk", "pcie_ctrl_post_div", base + 0x4600, 0);
791 clks[IMX7D_PCIE_PHY_ROOT_CLK] = imx_clk_gate4("pcie_phy_root_clk", "pcie_phy_post_div", base + 0x4600, 0);
792 clks[IMX7D_EPDC_PIXEL_ROOT_CLK] = imx_clk_gate4("epdc_pixel_root_clk", "epdc_pixel_post_div", base + 0x44a0, 0);
793 clks[IMX7D_LCDIF_PIXEL_ROOT_CLK] = imx_clk_gate4("lcdif_pixel_root_clk", "lcdif_pixel_post_div", base + 0x44b0, 0);
794 clks[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_gate4("mipi_dsi_root_clk", "mipi_dsi_post_div", base + 0x4650, 0);
795 clks[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_gate4("mipi_csi_root_clk", "mipi_csi_post_div", base + 0x4640, 0);
796 clks[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_gate4("mipi_dphy_root_clk", "mipi_dphy_post_div", base + 0x4660, 0);
Anson Huang9c7150d2018-05-18 09:01:05 +0800[diff] [blame]797 clks[IMX7D_ENET1_IPG_ROOT_CLK] = imx_clk_gate2_shared2("enet1_ipg_root_clk", "enet_axi_post_div", base + 0x4700, 0, &share_count_enet1);
798 clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate2_shared2("enet1_time_root_clk", "enet1_time_post_div", base + 0x4700, 0, &share_count_enet1);
799 clks[IMX7D_ENET2_IPG_ROOT_CLK] = imx_clk_gate2_shared2("enet2_ipg_root_clk", "enet_axi_post_div", base + 0x4710, 0, &share_count_enet2);
800 clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate2_shared2("enet2_time_root_clk", "enet2_time_post_div", base + 0x4710, 0, &share_count_enet2);
Fabio Estevam06981022016-08-12 15:26:56 -0300[diff] [blame]801 clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate2_shared2("sai1_root_clk", "sai1_post_div", base + 0x48c0, 0, &share_count_sai1);
802 clks[IMX7D_SAI1_IPG_CLK] = imx_clk_gate2_shared2("sai1_ipg_clk", "ipg_root_clk", base + 0x48c0, 0, &share_count_sai1);
803 clks[IMX7D_SAI2_ROOT_CLK] = imx_clk_gate2_shared2("sai2_root_clk", "sai2_post_div", base + 0x48d0, 0, &share_count_sai2);
804 clks[IMX7D_SAI2_IPG_CLK] = imx_clk_gate2_shared2("sai2_ipg_clk", "ipg_root_clk", base + 0x48d0, 0, &share_count_sai2);
805 clks[IMX7D_SAI3_ROOT_CLK] = imx_clk_gate2_shared2("sai3_root_clk", "sai3_post_div", base + 0x48e0, 0, &share_count_sai3);
806 clks[IMX7D_SAI3_IPG_CLK] = imx_clk_gate2_shared2("sai3_ipg_clk", "ipg_root_clk", base + 0x48e0, 0, &share_count_sai3);
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]807 clks[IMX7D_SPDIF_ROOT_CLK] = imx_clk_gate4("spdif_root_clk", "spdif_post_div", base + 0x44d0, 0);
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]808 clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0);
Stefan Agner22039d12017-06-08 15:34:47 -0700[diff] [blame]809 clks[IMX7D_NAND_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140, 0, &share_count_nand);
810 clks[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk", base + 0x4140, 0, &share_count_nand);
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]811 clks[IMX7D_QSPI_ROOT_CLK] = imx_clk_gate4("qspi_root_clk", "qspi_post_div", base + 0x4150, 0);
812 clks[IMX7D_USDHC1_ROOT_CLK] = imx_clk_gate4("usdhc1_root_clk", "usdhc1_post_div", base + 0x46c0, 0);
813 clks[IMX7D_USDHC2_ROOT_CLK] = imx_clk_gate4("usdhc2_root_clk", "usdhc2_post_div", base + 0x46d0, 0);
814 clks[IMX7D_USDHC3_ROOT_CLK] = imx_clk_gate4("usdhc3_root_clk", "usdhc3_post_div", base + 0x46e0, 0);
815 clks[IMX7D_CAN1_ROOT_CLK] = imx_clk_gate4("can1_root_clk", "can1_post_div", base + 0x4740, 0);
816 clks[IMX7D_CAN2_ROOT_CLK] = imx_clk_gate4("can2_root_clk", "can2_post_div", base + 0x4750, 0);
817 clks[IMX7D_I2C1_ROOT_CLK] = imx_clk_gate4("i2c1_root_clk", "i2c1_post_div", base + 0x4880, 0);
818 clks[IMX7D_I2C2_ROOT_CLK] = imx_clk_gate4("i2c2_root_clk", "i2c2_post_div", base + 0x4890, 0);
819 clks[IMX7D_I2C3_ROOT_CLK] = imx_clk_gate4("i2c3_root_clk", "i2c3_post_div", base + 0x48a0, 0);
820 clks[IMX7D_I2C4_ROOT_CLK] = imx_clk_gate4("i2c4_root_clk", "i2c4_post_div", base + 0x48b0, 0);
821 clks[IMX7D_UART1_ROOT_CLK] = imx_clk_gate4("uart1_root_clk", "uart1_post_div", base + 0x4940, 0);
822 clks[IMX7D_UART2_ROOT_CLK] = imx_clk_gate4("uart2_root_clk", "uart2_post_div", base + 0x4950, 0);
823 clks[IMX7D_UART3_ROOT_CLK] = imx_clk_gate4("uart3_root_clk", "uart3_post_div", base + 0x4960, 0);
824 clks[IMX7D_UART4_ROOT_CLK] = imx_clk_gate4("uart4_root_clk", "uart4_post_div", base + 0x4970, 0);
825 clks[IMX7D_UART5_ROOT_CLK] = imx_clk_gate4("uart5_root_clk", "uart5_post_div", base + 0x4980, 0);
826 clks[IMX7D_UART6_ROOT_CLK] = imx_clk_gate4("uart6_root_clk", "uart6_post_div", base + 0x4990, 0);
827 clks[IMX7D_UART7_ROOT_CLK] = imx_clk_gate4("uart7_root_clk", "uart7_post_div", base + 0x49a0, 0);
828 clks[IMX7D_ECSPI1_ROOT_CLK] = imx_clk_gate4("ecspi1_root_clk", "ecspi1_post_div", base + 0x4780, 0);
829 clks[IMX7D_ECSPI2_ROOT_CLK] = imx_clk_gate4("ecspi2_root_clk", "ecspi2_post_div", base + 0x4790, 0);
830 clks[IMX7D_ECSPI3_ROOT_CLK] = imx_clk_gate4("ecspi3_root_clk", "ecspi3_post_div", base + 0x47a0, 0);
831 clks[IMX7D_ECSPI4_ROOT_CLK] = imx_clk_gate4("ecspi4_root_clk", "ecspi4_post_div", base + 0x47b0, 0);
832 clks[IMX7D_PWM1_ROOT_CLK] = imx_clk_gate4("pwm1_root_clk", "pwm1_post_div", base + 0x4840, 0);
833 clks[IMX7D_PWM2_ROOT_CLK] = imx_clk_gate4("pwm2_root_clk", "pwm2_post_div", base + 0x4850, 0);
834 clks[IMX7D_PWM3_ROOT_CLK] = imx_clk_gate4("pwm3_root_clk", "pwm3_post_div", base + 0x4860, 0);
835 clks[IMX7D_PWM4_ROOT_CLK] = imx_clk_gate4("pwm4_root_clk", "pwm4_post_div", base + 0x4870, 0);
836 clks[IMX7D_FLEXTIMER1_ROOT_CLK] = imx_clk_gate4("flextimer1_root_clk", "flextimer1_post_div", base + 0x4800, 0);
837 clks[IMX7D_FLEXTIMER2_ROOT_CLK] = imx_clk_gate4("flextimer2_root_clk", "flextimer2_post_div", base + 0x4810, 0);
838 clks[IMX7D_SIM1_ROOT_CLK] = imx_clk_gate4("sim1_root_clk", "sim1_post_div", base + 0x4900, 0);
839 clks[IMX7D_SIM2_ROOT_CLK] = imx_clk_gate4("sim2_root_clk", "sim2_post_div", base + 0x4910, 0);
840 clks[IMX7D_GPT1_ROOT_CLK] = imx_clk_gate4("gpt1_root_clk", "gpt1_post_div", base + 0x47c0, 0);
841 clks[IMX7D_GPT2_ROOT_CLK] = imx_clk_gate4("gpt2_root_clk", "gpt2_post_div", base + 0x47d0, 0);
842 clks[IMX7D_GPT3_ROOT_CLK] = imx_clk_gate4("gpt3_root_clk", "gpt3_post_div", base + 0x47e0, 0);
843 clks[IMX7D_GPT4_ROOT_CLK] = imx_clk_gate4("gpt4_root_clk", "gpt4_post_div", base + 0x47f0, 0);
844 clks[IMX7D_TRACE_ROOT_CLK] = imx_clk_gate4("trace_root_clk", "trace_post_div", base + 0x4300, 0);
845 clks[IMX7D_WDOG1_ROOT_CLK] = imx_clk_gate4("wdog1_root_clk", "wdog_post_div", base + 0x49c0, 0);
846 clks[IMX7D_WDOG2_ROOT_CLK] = imx_clk_gate4("wdog2_root_clk", "wdog_post_div", base + 0x49d0, 0);
847 clks[IMX7D_WDOG3_ROOT_CLK] = imx_clk_gate4("wdog3_root_clk", "wdog_post_div", base + 0x49e0, 0);
848 clks[IMX7D_WDOG4_ROOT_CLK] = imx_clk_gate4("wdog4_root_clk", "wdog_post_div", base + 0x49f0, 0);
Stefan Agner1691cc32018-02-27 17:05:43 +0100[diff] [blame]849 clks[IMX7D_KPP_ROOT_CLK] = imx_clk_gate4("kpp_root_clk", "ipg_root_clk", base + 0x4aa0, 0);
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]850 clks[IMX7D_CSI_MCLK_ROOT_CLK] = imx_clk_gate4("csi_mclk_root_clk", "csi_mclk_post_div", base + 0x4490, 0);
851 clks[IMX7D_AUDIO_MCLK_ROOT_CLK] = imx_clk_gate4("audio_mclk_root_clk", "audio_mclk_post_div", base + 0x4790, 0);
852 clks[IMX7D_WRCLK_ROOT_CLK] = imx_clk_gate4("wrclk_root_clk", "wrclk_post_div", base + 0x47a0, 0);
Peter Chen5fcb4c72018-03-28 09:46:35 +0300[diff] [blame]853 clks[IMX7D_USB_CTRL_CLK] = imx_clk_gate4("usb_ctrl_clk", "ahb_root_clk", base + 0x4680, 0);
854 clks[IMX7D_USB_PHY1_CLK] = imx_clk_gate4("usb_phy1_clk", "pll_usb1_main_clk", base + 0x46a0, 0);
855 clks[IMX7D_USB_PHY2_CLK] = imx_clk_gate4("usb_phy2_clk", "pll_usb_main_clk", base + 0x46b0, 0);
Dong Aishengcbeac742016-06-30 17:31:17 +0800[diff] [blame]856 clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0);
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]857
858 clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
859
Bai Pingfdb868c2015-11-24 18:25:14 +0800[diff] [blame]860 clks[IMX7D_CLK_ARM] = imx_clk_cpu("arm", "arm_a7_root_clk",
861 clks[IMX7D_ARM_A7_ROOT_CLK],
862 clks[IMX7D_ARM_A7_ROOT_SRC],
863 clks[IMX7D_PLL_ARM_MAIN_CLK],
864 clks[IMX7D_PLL_SYS_MAIN_CLK]);
865
Bai Ping31cbb572015-11-26 10:18:43 +0800[diff] [blame]866 imx_check_clocks(clks, ARRAY_SIZE(clks));
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]867
868 clk_data.clks = clks;
869 clk_data.clk_num = ARRAY_SIZE(clks);
870 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
871
Dong Aisheng8d41e652018-03-28 09:46:39 +0300[diff] [blame]872 clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
873 clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
874 clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
875 clk_set_parent(clks[IMX7D_PLL_ENET_MAIN_BYPASS], clks[IMX7D_PLL_ENET_MAIN]);
876 clk_set_parent(clks[IMX7D_PLL_AUDIO_MAIN_BYPASS], clks[IMX7D_PLL_AUDIO_MAIN]);
877 clk_set_parent(clks[IMX7D_PLL_VIDEO_MAIN_BYPASS], clks[IMX7D_PLL_VIDEO_MAIN]);
878
Rui Miguel Silvab4f5e1f2018-05-22 15:52:37 +0100[diff] [blame]879 clk_set_parent(clks[IMX7D_MIPI_CSI_ROOT_SRC], clks[IMX7D_PLL_SYS_PFD3_CLK]);
880
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]881 /* use old gpt clk setting, gpt1 root clk must be twice as gpt counter freq */
882 clk_set_parent(clks[IMX7D_GPT1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]);
883
Peter Chen5fcb4c72018-03-28 09:46:35 +0300[diff] [blame]884 /* Set clock rate for USBPHY, the USB_PLL at CCM is from USBOTG2 */
885 clks[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb1_main_clk", "osc", 20, 1);
886 clks[IMX7D_USB_MAIN_480M_CLK] = imx_clk_fixed_factor("pll_usb_main_clk", "osc", 20, 1);
887
Lucas Stach1b9af682015-09-21 18:54:04 +0200[diff] [blame]888 imx_register_uart_clocks(uart_clks);
889
Frank Li8f6d8092015-05-19 02:45:03 +0800[diff] [blame]890}
891CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init);